JP4096872B2 - Semiconductor device and method for mounting semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a wafer level CSP type semiconductor device that realizes packaging of a semiconductor chip in a wafer state and a technique effective when applied to a manufacturing method thereof.

In recent years, electronic components used in these electronic devices are required to be small and highly functional as the electronic devices become lighter, thinner, smaller and have higher performance.
In response to these trends, a semiconductor device having a so-called CSP (Chip Size Package) structure in which the size of the semiconductor device is made as close as possible to the chip shape of an LSI (Large Scale Integrated Circuit) has been proposed. .
Among these, from the viewpoint of reducing manufacturing costs and improving productivity, any CSP (hereinafter referred to as a wafer level CSP) using a technique for packaging a semiconductor chip in a wafer state is now being put into practical use. Development is underway.
The wafer level CSP is a stage before cutting a plurality of semiconductor chips formed on a semiconductor wafer as individual semiconductor chips from the wafer, that is, in a wafer state, a wiring formation process of individual semiconductor chips and a formation process of external connection terminals, And semiconductor technology for packaging a semiconductor chip sealing process using an insulating resin.

In a conventional semiconductor device having a wafer level CSP structure, an area array type electrode arrangement by a rewiring process is adopted in the arrangement of LSI chip electrodes, thereby realizing a semiconductor device advantageous in increasing the number of pins.
As a conventional technique of a semiconductor device having a conventional wafer level CSP structure, for example, there is a technique disclosed in the following patent document.
JP 2002-280484 A JP 2002-280487A

However, in the case of such a conventional semiconductor device having a wafer level CSP structure, there is a large difference in thermal expansion coefficient between a mounting substrate on which the semiconductor device is mounted and a semiconductor wafer made of, for example, silicon constituting the semiconductor device. There has been a problem that a large stress (thermal stress) is generated between the mounting substrate and the semiconductor chip in a mounting process of the semiconductor device on the substrate, a use environment after mounting, and the like.
FIGS. 5A and 5B are diagrams for explaining the stress distribution when the temperature drops when the semiconductor device is mounted on a mounting substrate in a CSP-structured semiconductor device employing a conventional area electrode arrangement. FIG. 6 schematically shows the result of an actual simulation. A specific simulation condition is a simulation result when the temperature is changed from 125 ° C. to −40 ° C.

Here, FIG. 5A is a top view of the semiconductor device as viewed from the side where the external connection terminals are connected, and FIG. 5B is a cross-sectional view of the semiconductor device as viewed from the line XX ′ in FIG. It is sectional drawing which expanded and showed one place among them. In the enlarged view of FIG. 5B, the left side is the direction of the central portion 508 of the semiconductor device 500, and the right side is the direction of the outer peripheral portion 509 of the semiconductor device 500.
When the temperature is lowered, as shown in FIGS. 5A and 5B, a mother substrate 501 that is a mounting substrate, a semiconductor wafer 502, and a wiring electrically connected to the semiconductor element formed on the semiconductor wafer 502 503, a sealing body 504 that seals the semiconductor wafer 502 and the wiring 503, and a semiconductor device 500 that includes an external connection terminal 505 connected to the mother substrate 501, respectively. A stress 506 is generated from the outer peripheral portion 509 of the device 500 toward the central portion 508, that is, from the right side to the left side in FIG.

At this time, in the semiconductor device mounted on the mounting substrate, there is a large difference between the thermal expansion coefficient of the mounting substrate and the thermal expansion coefficient of the semiconductor device (thermal expansion coefficient of the semiconductor device (wafer) <thermal expansion coefficient of the mounting substrate). Therefore, a stress 506b larger than the stress 506a generated in the semiconductor device (semiconductor wafer) is generated on the mounting substrate 501. That is, a large stress difference is generated in the mounted semiconductor device.
As a result, due to the difference between these stresses 506, external connection terminals 505, such as solder, for connecting the mother substrate 501 and the semiconductor device 500 to each other in the mounting process of the semiconductor device on the mounting substrate, the use environment after mounting, and the like. There has been a problem that a great deal of stress is applied to the ball electrode. In particular, as shown in FIG. 5B, the stress is most applied to a portion 507 of the external connection terminal 505 connected to the semiconductor device 500 having a small thermal expansion coefficient and away from the direction of the central portion 508 to which the stress 506 is directed. However, there is a problem that the external connection terminal 505 is damaged.

That is, in the conventional semiconductor device, these different stresses are applied to the external connection terminal of the semiconductor device and the wiring to which the external connection terminal is connected, resulting in damage to the external connection terminal and disconnection of the wiring. It has caused a serious problem to reduce the reliability of.
Accordingly, the present invention provides a semiconductor device having a wafer level CSP structure that sufficiently relaxes the stress applied to the external connection terminal and the interface between the external connection terminal and the wiring, and causes damage to the external connection terminal and disconnection of the wiring. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device that can avoid a serious problem of reducing reliability.

In order to solve the above problems, according to a representative semiconductor device according to the present invention, a semiconductor chip having an electric circuit formed on the surface, and formed on the surface and electrically connected to the electric circuit. An electrode pad, a wiring electrically connected to the electrode pad, an insulating sealing body formed on the surface, covering the electrical circuit and the wiring and exposing a part of the wiring; and the wiring and the electrical And a plurality of recesses provided in a part of the wiring and spaced apart in a direction substantially the same as the direction in which the semiconductor chip expands and contracts due to thermal stress.
According to a representative method of manufacturing a semiconductor device according to the present invention, a semiconductor chip having an electric circuit formed on the surface, and an electrode pad formed on the surface and electrically connected to the electric circuit, A wiring electrically connected to the electrode pad; and an insulating sealing body formed on the surface, covering the electrical circuit and the wiring and exposing a part of the wiring; and being electrically connected to the wiring In the method of manufacturing a semiconductor device having external connection terminals, the direction in which the semiconductor chip expands and contracts due to thermal stress on a part of the surface of the wiring is formed before the step of forming the external connection terminals connected to the wiring. And a step of forming a plurality of recesses that are spaced apart in the same direction.
With these configurations, according to the present invention, a semiconductor device that can sufficiently relieve stress applied to the interface between the external connection terminal and the external connection terminal and the wiring, and a method for manufacturing the same are provided.

According to the present invention, at the interface between the external connection terminal and the wiring, the stress in the expansion / contraction direction in which the stress is most concentrated is arranged by disposing a plurality of concave portions spaced apart in substantially the same direction as the expansion / contraction direction due to thermal stress. Can be dispersed and the stress applied to the external connection terminals can be relaxed.
As a result, it is possible to make it difficult to cause a problem of reducing connection reliability, such as damage to the external connection terminals, caused by stress due to heat generated in the mounting process or the use environment after mounting. That is, the reliability of the semiconductor device itself can be improved.

  The best mode for carrying out the present invention will be described below.

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings of FIGS.
1A to 1F are process cross-sectional views illustrating a method for manufacturing a semiconductor device 100 according to the first embodiment of the present invention.
Prior to the process shown in FIG. 1A, a known wafer process is performed on the semiconductor wafer 101, and semiconductor elements arranged in a matrix are formed on the surface of the semiconductor wafer 101. The semiconductor element referred to here is an electric circuit on the wafer formed corresponding to one semiconductor device.
As shown in FIG. 1A, an electrode pad 102 electrically connected to the semiconductor element is formed on the surface of the wafer 101 on which the semiconductor element is formed. After the electrode pad 102 is formed, a resin material such as polyimide is applied onto the surface of the wafer 101 by spin coating. Of the applied polyimide, unnecessary polyimide is etched away by a known photolithography technique or the like. By these steps, a polyimide layer 103 which is an insulating layer is formed on the surface of the wafer 101 excluding a region corresponding to the electrode pad 102 and a region along the boundary line of the semiconductor element.
Next, as shown in FIG. 1B, an insulating bump 104 as an insulating stress relaxation layer (insulating column) is formed on the polyimide layer 103 adjacent to the electrode pad 102 at a position where the external connection terminal 109 is to be formed. Is formed.

This insulating bump 104 is formed by the following method, for example.
First, photosensitive polyimide resin is dropped on the wafer 101, and the polyimide resin is applied to the entire area of the wafer 101 by a spin coater. The applied polyimide resin is cured by subsequent curing, and a polyimide layer having a predetermined thickness is formed on the wafer 101. After forming the polyimide layer, a photomask is formed on the polyimide layer in the region where the insulating bumps 104 are to be formed. Next, the photosensitive polyimide resin exposed from the photomask is exposed, and the polyimide layer other than the region masked by the photomask is removed by etching. Through these steps, a cylindrical heat resistant insulating resin, for example, a stress relaxation layer (insulating support) made of polyimide resin is formed on the polyimide layer 103 adjacent to the electrode pad 102. Examples of the heat resistant insulating resin include polybenzoxazole in addition to polyimide resin.

In the manufacturing method of the present embodiment, curing is further performed on the stress relaxation layer (insulating support) made of a cylindrical polyimide resin formed on the wafer 101. As a result, the upper part of the columnar polyimide resin stress relaxation layer (insulating column) is shrunk, and the mesa-type insulating bump 104 is formed that spreads from the top to the bottom. Thereby, the contact area with the conductor on the insulating bump 104 to be formed later, that is, the wiring 106 can be improved, and the adhesion can be improved by the physical anchor effect.
When the mesa bump 104 having a height of 0.03 mm is formed by such a forming method, the amount of shrinkage in the curing process for forming the mesa bump 104 is taken into consideration, and the polyimide layer formed on the wafer 101 is The film thickness is desirably about 0.06 mm.
After the formation of the insulating bump 104 on the polyimide layer 103 adjacent to the electrode pad 102, as shown in FIG. 1C, the semiconductor device 100 expands and contracts due to thermal stress on the upper surface of the insulating bump 104, that is, the semiconductor. A plurality of recesses 105 are formed that are spaced apart in the same direction as the direction extending from the central portion 201 of the device 100 to the outer peripheral portion 202 of the semiconductor device 100. The recess 105 is formed on the upper surface of the insulating bump 104 by a known technique such as etching removal using photolithography.

Next, as shown in FIG. 1D, a barrier metal made of titanium tungsten (TiW) or the like is formed on the surface of the wafer 101 including the insulating bumps 104 having a plurality of recesses 105 on the upper surface by, for example, ion sputtering. It is formed. Thereafter, copper (Cu) is plated on the barrier metal, and the wiring 106 extending from the electrode pad 102 to the top of the insulating bump 104 is formed.
At this time, one end of each wiring 106 is electrically connected to the electrode pad 102 on the wafer 101, and the other end extends to a circular region covering the surface of the insulating bump 104. Further, the wiring 106 on the upper surface of the insulating bump 104 is a wiring having an uneven shape corresponding to the plurality of concave portions 105 formed on the upper surface of the bump.
After the wiring 106 is formed at a predetermined position on the surface of the wafer 101, a sealing resin for the package is supplied onto the wafer 101, and the semiconductor element formed on the surface of the wafer 101 and the wiring 106 are covered with the sealing resin. Is called. Thereafter, as shown in FIG. 1E, the sealing resin on the insulating bump 104 is removed, and the sealing body in which the opening 108 exposing the upper surface of the wiring 106 having the uneven shape on the bump is formed. 107 is provided on the wafer 101.
As a method for supplying the package resin, other known resin supply methods such as a spin coating method and a screen printing method can be employed.
Further, in removing the sealing resin on the insulating bump 104, in addition to etching removal using a photomask, grinding removal using a grinder or other grinding device may be used for the entire surface of the sealing resin.

Here, with reference to FIG. 2 and FIG. 3, the concave portion 105 formed in the interface between the wiring 106 and the external connection terminal 109 in the present embodiment will be described.
FIGS. 2A and 2B are views showing one of the semiconductor devices in the process shown in FIG.
2A is a top view of the semiconductor device of the present embodiment in FIG. 1E viewed from above, and FIG. 2B is viewed from the line XX ′ in FIG. It is sectional drawing which expanded and showed one insulating bump among sectional drawings. FIG. 3 is an enlarged view showing the upper surface of the wiring 106 exposed from one opening 108 in the semiconductor device, and shows another shape of the recess 105 applied to the semiconductor device of this embodiment. is there.
As shown in FIG. 2A, a plurality of openings 108 arranged in a matrix around the central portion 201 of the semiconductor device 100 are provided on the upper surface of the semiconductor device in the present embodiment. The wirings 106 exposed from the openings 108 are spaced apart from each other in the direction 203 that expands and contracts due to thermal stress, that is, the direction 203 that extends from the central portion 201 of the semiconductor device 100 to the outer peripheral portion 202 of the semiconductor device 100. A plurality of recesses 105 are formed.
The recess 105 formed on the upper surface of the insulating bump 104 has a plurality of linear grooves (slits) that are spaced apart from each other in the expansion and contraction direction and extend in the vertical direction as shown in FIG. It is also possible to adopt concentric annular grooves (slits) sharing one center 301 as shown in FIGS. 3 (a) and 3 (b).

Further, as shown in FIG. 2B, for example, when the thickness T of the copper thin film forming the wiring 106 in FIG. 1D is about 20 μm, the wiring formed on the upper surface of the insulating bump 104 In consideration of disconnection of the metal thin film and ease of processing, it is desirable that the unevenness depth D ₁ of 106 is about ½ of the film thickness T of the metal thin film forming the wiring 106, that is, about 10 μm. . Therefore, the depth D ₂ of the recess 105 on the upper surface of the insulating bump 104 formed in FIG. 1C takes into consideration the thickness T of the metal thin film forming the wiring 106 and the depth D ₁ of the unevenness of the wiring 106. It is preferable to be determined as appropriate above.
Thereafter, as shown in FIG. 1F, the external connection terminal 109 formed in another process is mounted on the opening 108, that is, on the wiring 106 on the upper surface of the insulating bump 104 exposed from the opening 108. Is done. Thereafter, reflow is performed on the wafer 101 on which the external connection terminal 109 is mounted, and the external connection terminal 109 is connected to the wiring 106.
Finally, as shown in FIG. 1F, a wafer 101 on which a plurality of semiconductor devices are formed is diced using a dicing saw 110 to obtain individually packaged semiconductor devices 112.

According to the semiconductor device of the present embodiment obtained by the above steps, the plurality of recesses 105 are separated from each other in the substantially same direction as the direction 205 that expands and contracts due to thermal stress at the interface between the external connection terminal 109 and the wiring 106. By disposing, the stress in the expansion / contraction direction where stress is most concentrated is dispersed, and the stress applied to the external connection terminal 109 can be relaxed.
As a result, it is possible to make it difficult to cause a problem of reducing connection reliability, such as damage to the external connection terminals, caused by stress due to heat generated in the mounting process or the use environment after mounting. That is, the reliability of the semiconductor device itself can be improved.
In particular, in the case of the semiconductor device of the present embodiment in which the external connection terminal 109 that is most affected by the stress is directly connected to the wiring 106 formed of a thin metal thin film, the interface between the wiring 106 and the external connection terminal 109 is used. According to the present invention, in which a plurality of recesses 105 are provided to relieve the applied stress, not only is the damage of the external connection terminal 109 where stress is most concentrated concentrated, but also the film thickness connected to the external connection terminal 109 is reduced. It is possible to prevent disconnection of the thin wiring 106.

In this embodiment, a ball electrode (solder ball) whose main material is Sn—Pb solder is used as the external connection terminal 109. However, the external connection terminal 109 according to the present invention is not limited to a ball electrode mainly composed of Sn—Pb solder, but is solder containing no lead (Pb) (Pb-free solder), for example, Sn—Ag—Bi. The present invention can also be applied to a ball electrode whose main material is a system solder.
In particular, in a ball electrode mainly composed of solder containing no Pb, the ball electrode itself is hard and brittle compared to a ball electrode mainly composed of solder containing Pb. Therefore, according to the present invention in which the plurality of recesses 105 that relieve stress are provided at the interface between the external connection terminal 109 and the wiring 106, the stress applied to the external connection terminal 109 can be concentrated on the interface. Furthermore, since the strength can be ensured by forming irregularities at the interface between the external connection terminal 109 and the wiring 106, the external connection terminal 109 is caused by stress generated between the mounting substrate and the semiconductor device. It becomes possible to prevent damage sufficiently.

In the case of a semiconductor device having a CSP structure having an insulating bump 104 formed of a highly hygroscopic material such as polyimide resin as in this embodiment, during storage until the semiconductor device is mounted on a mounting substrate, There is a risk that moisture may enter the insulating bumps 104 formed of polyimide resin from the air. When a heat treatment process such as reflow during mounting is performed on a semiconductor device in which moisture has entered, the intruded moisture is vaporized by the heat treatment, resulting in problems such as disconnection of wiring and detachment of insulating bumps 104. It will occur.
Therefore, in the case of a semiconductor device having a CSP structure having the insulating bumps 104 formed of a highly hygroscopic material, the insulating method is performed by sputtering or the like before the step of forming the insulating bumps 104 in the manufacturing method according to the present embodiment. A single layer or a composite layer of titanium (Ti), palladium (Pd), nickel (Ni), copper (Cu), gold (Au) or the like is formed in advance on a region on the semiconductor wafer 101 where the bumps 104 are formed. A metal barrier film may be formed, and then the insulating bumps 104 made of polyimide resin or the like may be formed in the above-described process.
With this configuration, the entire surface of the insulating bump 104 formed of a highly hygroscopic material is covered with a highly hygroscopic metal film, which prevents moisture from entering the air during storage. It becomes possible to prevent. As a result, problems such as disconnection of wiring and detachment of insulating bumps 104 due to heat treatment during mounting can be avoided, and stable substrate bonding can be realized.

Next, a semiconductor device according to a second embodiment of the present invention will be described. 4A to 4F are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the structure similar to 1st Embodiment mentioned above, and the detailed description is abbreviate | omitted.
In the semiconductor device according to the first embodiment described above, the wiring 106 is formed by the metal thin film extending from the electrode pad 102 to the top of the insulating bump 104. However, in the semiconductor device according to the second embodiment, FIG. 4 (f), one end is connected to the electrode pad 102, a rewiring 401 made of a metal thin film extending from the electrode pad 102, and one end is connected to the other end of the rewiring 401, The wiring 106 is configured by a conductive bump 402 made of, for example, copper (Cu), the other end of which is connected to the external connection terminal 109.

Also in the semiconductor device according to the second embodiment, the interface between the external connection terminal 109 and the wiring 106, that is, the upper surface of the conductive bump 402 is spaced apart in the substantially same direction as the direction of expansion and contraction due to thermal stress. A plurality of recesses 404 are formed.
Hereinafter, with reference to FIGS. 4A to 4F, a method of manufacturing the semiconductor device according to the present embodiment will be described.
Also in the semiconductor device of the second embodiment, a known wafer process is performed on the semiconductor wafer 101 prior to the process shown in FIG. 4A, and a plurality of semiconductor elements are formed on the surface of the semiconductor wafer 101. .
First, as shown in FIG. 4A, as in the case of the first embodiment, an electrode pad 102 electrically connected to each semiconductor element is formed on the surface of the wafer 101 on which the semiconductor element is formed. .
Thereafter, a resin material such as polyimide is applied onto the surface of the wafer 101 by spin coating or the like. Then, the polyimide resin in the region along the boundary line between the electrode pad 102 and the semiconductor element is removed, and a polyimide layer 103 that is an insulating layer is formed on the surface of the wafer 101.

Next, a pad electrode adhesion metal layer made of a metal material such as titanium (Ti) alloy or chromium (Cr) is formed on the entire surface of the semiconductor wafer 101 as a base metal thin film layer of a rewiring layer by sputtering or the like. At this time, the pad electrode bonding metal layer is a material that has good adhesion to the electrode pad 102 material, little metal interdiffusion, and good adhesion to the insulating layer 103 formed on the surface of the wafer 101. It is desirable to use
Thereafter, a plated feed layer metal film having a low electrical resistance and functioning as a plated feed layer of the rewiring layer is formed on the pad electrode adhesion metal layer by, for example, sputtering. The plating power supply layer metal film is made of a metal material such as Cu, for example. Then, a Cu plating layer is formed on the plating power supply layer metal film by using, for example, electrolytic plating.
Through the above steps, a rewiring 401 composed of a pad electrode adhesion metal layer, a plating power supply layer metal film, and a Cu plating layer as shown in FIG. 4B is formed.
Next, as shown in FIG. 4C, a Cu post 402 which is a conductive bump having a height of about 70 μm is formed on the rewiring 401 having one end connected to the electrode pad 102 by electroplating or the like. The Cu post 402 is electrically connected to the solder ball electrode of the external connection terminal 109 formed on the semiconductor wafer 101 in a later process.

Next, as shown in FIG. 4D, the sealing resin for the package is supplied to the main surface of the semiconductor wafer 101 on which the semiconductor elements are formed so that the entire surface of the electric circuit and the Cu post 402 is covered. . The supply of the sealing resin is performed by a transfer molding method, a potting method, a printing method, or the like.
Then, after the sealing resin is supplied onto the surface of the wafer 101, the surface of the sealing resin is ground with an abrasive until the upper surface of the Cu post 402 covered with the sealing resin is exposed. Thereby, the sealing body 107 having the opening 108 that exposes the upper surface of the Cu post 402 is formed.
Through the above steps, a wiring 403 is formed which is composed of the rewiring layer 401 and the Cu post 402 and is partially exposed from the opening 108 of the sealing body 107.
After such a step, as shown in FIG. 4E, the semiconductor device expands and contracts due to thermal stress on the exposed upper surface of the Cu post 402, that is, from the center of the semiconductor device to the outer periphery of the semiconductor device. A plurality of recesses 404 are formed so as to be spaced apart in the substantially same direction as the extending direction.
These concave portions 404 formed on the upper surface of the Cu post 402 are formed on the upper surface of the Cu post 402 by etching removal using photolithography or other known techniques, as in the case of the first embodiment described above. In addition, the shape of the recess 403 can be the same as that of the first embodiment.

Thereafter, as shown in FIG. 4F, external connection terminals formed in another process on the opening 108, that is, on the upper surface of the Cu post 402 that is a part of the wiring 403 exposed from the opening 108. 109 is mounted. Then, reflow is performed on the wafer 101 on which the external connection terminal 109 is mounted, and the external connection terminal 109 is fixed to the upper surface of the Cu post 402 and connected to the wiring 403.
Finally, using the dicing saw 110, the wafer 101 on which a plurality of semiconductor devices are formed is diced, and the individually packaged semiconductor device 400 is obtained.
According to the semiconductor device of the present embodiment obtained by the above steps, the plurality of recesses 105 are arranged at the interface between the external connection terminal 109 and the wiring 403 so as to be spaced apart in the substantially same direction as the direction of expansion and contraction due to thermal stress. As a result, the stress in the expansion / contraction direction where stress is concentrated most is dispersed, and the stress applied to the external connection terminal 109 can be relaxed.
As a result, it is possible to make it difficult to cause a problem of reducing connection reliability, such as damage to the external connection terminals, caused by stress due to heat generated in the mounting process or the use environment after mounting. That is, the reliability of the semiconductor device itself can be improved.

It is process sectional drawing which shows the manufacturing method of the semiconductor device in 1st Embodiment. It is a figure which shows the semiconductor device in 1st Embodiment. It is a figure which shows the other recessed part shape formed in the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device in 2nd Embodiment. It is a figure which shows the stress distribution at the time of the temperature fall in the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 Semiconductor wafer 102 Electrode pad 103 Insulating layer 104 Insulating bump 105 Recessed part 106 Wiring 107 Sealing body 108 Opening 109 External connection terminal 110 Dicing saw

Claims (13)

A semiconductor chip having an electric circuit formed on the surface;
An electrode pad formed on the surface and electrically connected to the electrical circuit;
A wiring electrically connected to the electrode pad;
An insulating sealing body formed on the surface, covering the electrical circuit and the wiring, and exposing a part of the wiring;
An external connection terminal electrically connected to the wiring at a part of the wiring;
A plurality of annular recesses provided in a part of the wiring and arranged concentrically spaced apart in the same first direction as the direction in which the semiconductor chip expands and contracts due to thermal stress;
In the annular shape, the width of the annular shape in the first direction passing through the center of the concentric circle is smaller than the width of the annular shape in the second direction orthogonal to the first direction and passing through the center of the concentric circle. A semiconductor device characterized by the above. A semiconductor chip having an electric circuit formed on the surface;
An electrode pad formed on the surface of the semiconductor chip and electrically connected to the electric circuit;
An insulating stress relaxation layer provided on the surface of the semiconductor chip and disposed at a position close to the electrode pad;
A wiring electrically connected to the electrode pad and formed from the electrode pad to the top of the insulating stress relaxation layer;
An insulating sealing body that is formed on the surface of the semiconductor chip, seals the electric circuit and the electrode pad, and exposes a part of the wiring formed on the top of the insulating stress relaxation layer;
A plurality of annular recesses provided in a part of the wiring and arranged concentrically spaced apart in the same first direction as the direction in which the semiconductor chip expands and contracts due to thermal stress;
In the annular shape, the width of the annular shape in the first direction passing through the center of the concentric circle is smaller than the width of the annular shape in the second direction orthogonal to the first direction and passing through the center of the concentric circle. A semiconductor device characterized by the above. The semiconductor device according to claim 2,
2. The semiconductor device according to claim 1, wherein the insulating stress relaxation layer is made of a heat resistant insulating resin. The semiconductor device according to claim 3.
A semiconductor device comprising a moisture barrier film provided on a surface of the semiconductor chip and in a lower portion of the insulating stress relaxation layer. The semiconductor device according to claim 2 or 3,
The semiconductor device, wherein the insulating stress relaxation layer has a mesa shape. The semiconductor device according to any one of claims 2 to 5,
A semiconductor device comprising a plurality of annular recesses on an upper surface of the insulating stress relaxation layer corresponding to a recess provided in a part of the wiring. A semiconductor chip having an electric circuit formed on the surface;
An electrode pad formed on the surface of the semiconductor chip and electrically connected to the electric circuit;
An insulating layer that exposes the electrode pads and covers the electrical circuit;
A conductive thin film formed on the insulating layer and electrically connected to the electrode pad;
A conductive post formed on the conductive thin film;
An insulating sealing body formed on the surface of the semiconductor chip and exposing a top portion of the conductive post;
An external connection terminal formed on the top of the conductive post;
A plurality of annular recesses provided on the top of the conductive post and arranged concentrically spaced apart in the same first direction as the direction in which the semiconductor chip expands and contracts due to thermal stress;
In the annular shape, the width of the annular shape in the first direction passing through the center of the concentric circle is smaller than the width of the annular shape in the second direction orthogonal to the first direction and passing through the center of the concentric circle. A semiconductor device characterized by the above. The semiconductor device according to claim 7.
The semiconductor device, wherein the conductive thin film and the conductive post are made of a material containing copper. A semiconductor chip having an electric circuit formed on the surface;
An electrode pad formed on the surface and electrically connected to the electrical circuit;
A wiring electrically connected to the electrode pad;
An insulating sealing body formed on the surface, covering the electrical circuit and the wiring, and exposing a part of the wiring;
An external connection terminal electrically connected to the wiring at a part of the wiring;
An annular recess provided in a part of the wiring, wherein the width of the annular shape in the first direction passing through the center of the annular shape is the same as the direction in which the semiconductor chip expands and contracts due to thermal stress. a recess narrow annular shape than a width in a second direction through the said center orthogonal to the first direction possess,
2. The semiconductor device according to claim 1, wherein the annular recess is formed of a plurality of annular recesses and is arranged concentrically and spaced apart from each other . The semiconductor device according to any one of claims 1 to 9,
The external connection terminal is made of a material that does not contain lead. The semiconductor device according to any one of claims 1 to 10 ,
The semiconductor device, wherein the external connection terminal is a solder ball. The semiconductor device according to any one of claims 1 to 11 ,
The depth of the recess is ½ of the film thickness of the wiring. Preparing a semiconductor chip having an electric circuit formed on a surface and having an electrode pad electrically connected to the electric circuit;
Forming a wiring electrically connected to the electrode pad on the surface;
Forming an insulating sealing body on the surface, covering the electrical circuit and the wiring and exposing a part of the wiring;
A plurality of annular recesses concentrically arranged on a part of the surface of the wiring and spaced apart in a first direction identical to a direction in which the semiconductor chip expands and contracts due to thermal stress, the concentric circles Forming a recess having a width of the annular shape in the first direction passing through a center perpendicular to the first direction and narrower than a width of the annular shape in a second direction passing through the center of the concentric circles;
A step of disposing an external connection terminal made of a material not containing lead on a part of the surface of the wiring in which the concave portion is formed, and electrically connecting the external connection terminal and the wiring;
After the step of electrically connecting the external connection terminals and the wiring, the external connection terminals are mounted on a mounting board, and the semiconductor chip is mounted on the mounting board by heating the external connection terminals and the mounting board. And a process for mounting the semiconductor device.

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