JP4097787B2 - Electronic endoscope device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic endoscope apparatus that performs signal processing on an output signal of a solid-state imaging device and reduces power consumption in a non-signal readout period.
[0002]
[Prior art]
In recent years, various electronic endoscope apparatuses using a solid-state imaging device such as a charge coupled device (CCD) have been proposed. The electronic endoscope apparatus includes an endoscope provided with a solid-state image pickup device that picks up an image of a subject in an elongated insertion portion, and supplies a drive signal to the fixed image pickup device and also connects an image pickup signal from the solid-state image pickup device to a cable. And a video processor for processing the imaged signal, and a video signal from the video processor is displayed on a monitor.
[0003]
As described above, various proposals have been made regarding the mounting around the solid-state imaging device, the output circuit of the imaging signal, and the transmission system in the electronic endoscope apparatus including the CCD. For example, the present applicant has proposed an electronic endoscope apparatus similar to that shown in FIG. 11 in Japanese Patent Application No. 9-71632.
[0004]
An electronic endoscope apparatus 1 ′ shown in FIG. 11 includes an electronic endoscope (also referred to as a scope) 2 having a CCD 10 as a solid-state imaging device, a light source apparatus 3 that supplies illumination light to illuminate a subject, and the CCD 10. While supplying a drive signal, a video processor 4 ′ that captures an imaging signal from the CCD 10 via a transmission cable 18 and processes the imaging signal, and a color monitor 5 that displays a video signal output from the video processor 4 ′. And.
[0005]
The electronic endoscope 2 has an elongated insertion portion 6, and a thick operation portion 8 is formed at the rear end of the insertion portion 6. A light guide 7 that transmits illumination light is inserted into the insertion portion 6, and the rear end of the light guide 7 is detachably connected to the light source device 3, and illumination light from the lamp 13 passes through the condenser lens 12. The lever is supplied to the rear end surface of the light guide 7. This illumination light is transmitted, and is further irradiated to the subject via the illumination lens 14 from the distal end surface attached to the distal end portion 31.
[0006]
An objective lens 9 is provided at the distal end portion 31 of the insertion portion 6 and connects the subject image to its focal plane. The CCD 10 is disposed on this focal plane. The subject image is optically color-separated by a color filter in front of the CCD chip of the CCD 10.
[0007]
It is photoelectrically converted by the CCD 10 and accumulated as charges corresponding to the subject image optically color-separated. In the CCD 10, accumulated charges are read out by applying a CCD drive signal from a CCD driver 16 provided in the video processor 4 ′ via a cable 17.
[0008]
The read signal (also referred to as an imaging signal) is amplified by an output amplifier 33 (see FIG. 12) which is an impedance reduction means provided inside the CCD 10 and then wired in the operation unit 8 and the insertion unit 6. Then, the signal is input to the preamplifier 20 inside the video processor 4 ′ connected to the terminal via the coaxial cable 18.
[0009]
The input terminal of the preamplifier 20, that is, the terminal end of the coaxial cable 18, is grounded via a resistor R1 and a switch S serving as a termination circuit constituting power consumption reduction means, and is grounded via a resistor R2. The switch S is ON / OFF controlled by the control circuit 22.
[0010]
The power supply terminal of the CCD 10 provided in the insertion portion 6 of the electronic endoscope 2 is connected to the cable 22 by a CCD power supply Vcc of about 15 [V] generated from a power supply circuit (not shown) inside the video processor 4 '. Is supplied through.
[0011]
As described above, the output amplifier 33 serving as the impedance reduction means is provided inside the CCD 10. The power supply Vcc inside the video processor 4 ′ is supplied via the cable 22 to the power supply terminal VDD of the output stage of the output amplifier 33.
[0012]
The output signal of the preamplifier 20 is extracted by the CDS circuit 23 from the baseband signal component from which reset noise and the like are removed, and is converted into a digital signal by the A / D converter 24. The digital signal is processed by the digital video processing circuit 25, converted to an analog video signal through a D / A converter 26, output to the color monitor 5, and an endoscopic image is displayed in the endoscopic image display area 5A. indicate. The control circuit 21 controls operations of the CDS circuit 23, the A / D converter 24, the digital video processing circuit 25, and the D / A converter 26.
[0013]
A CCD 10 employed in the electronic endoscope 2 is shown in FIG. The CCD 10 shown in FIG. 12 employs an interline transfer method, and the light receiving unit 40 is composed of photodiodes arranged on a matrix. Reference numeral 41 denotes a read gate, and a vertical transfer CCD 42 is provided on the read gate 41. The vertical transfer CCD 42 is provided on the horizontal transfer CCD 43.
[0014]
An output gate 44 is formed at one end of the horizontal transfer CCD 43. A read gate terminal LG is connected to the read gate 41. The vertical transfer CCD 42 can be supplied with vertical drive pulses φV1, φV2, φV3, and φV4. The horizontal transfer CCD 43 can be supplied with horizontal drive pulses φH1 and φH2.
[0015]
The output gate 44 is connected to the input terminal of the output amplifier 33. A power supply voltage of about 7 [V] is applied to the output gate 44 via the output gate terminal OG.
[0016]
The output amplifier 33 includes an amplifying transistor Q1 formed of a field effect transistor (FET), a transistor Q2 serving as a current source connected between the source electrode of the transistor Q1 and a ground line, a reset transistor Q3, and an amplifying transistor. A transistor Q4, a transistor Q5 serving as a current source connected between the source electrode of the transistor Q1 and the ground line, and a low impedance conversion transistor Q6 serving as an output stage.
[0017]
The output gate 44 is connected to the gate electrode of the transistor Q1 and the source electrode of the reset transistor Q3. The drain electrodes of the transistors Q1 and Q4 are connected to the power supply Vcc, and the drain electrode of the reset transistor Q3 is also connected to the power supply terminal Vcc via the terminal RD. A power supply voltage of about 15 [V] is applied to the power supply terminal Vcc.
[0018]
A reset pulse φR is applied to the gate electrode of the reset transistor Q3. In the transistor Q2, the gate electrode and the source electrode are connected in common and connected to the ground line, and the drain electrode is connected to the source electrode of the transistor Q1. The source electrode of transistor Q1 is connected to the gate electrode of transistor Q4.
[0019]
The source electrode of transistor Q4 is connected to the drain electrode of transistor Q5. The source electrode and gate electrode of the transistor Q5 are connected in common and connected to the earth line. The source electrode of the transistor Q4 is connected to the gate electrode of the transistor Q6, and the drain electrode of the transistor Q6 is connected to the power supply terminal VDD. The power supply terminal VDD is connected to the power supply terminal Vcc.
The source electrode of the transistor Q6 is connected to the output terminal Vout. The ground line is connected to the ground line of the video processor 4 'via a terminal GND.
[0020]
The transistors Q1 and Q2 constitute a first-stage source follower, the transistors Q4 and Q5 constitute a second-stage source follower, and the transistor Q6 constitutes an output source follower.
Charges generated by the photodiodes in each column are supplied to the vertical transfer CCD 42 via the read gate 41. A power supply voltage of about 3 [V] is applied to the read gate 41 via the read gate terminal LG, and the electric charge generated in the photodiode is read every frame or one field period.
[0021]
The vertical transfer CCD 42 is driven by applying four sets of clock signals of vertical drive pulses φV1, φV2, φV3, and φV4 through vertical drive pulse terminals φV1, φV2, φV3, and φV4, and are generated in the photodiode. The charged charges are read and transferred at a predetermined timing.
The charges transferred in the vertical transfer CCD 42 are supplied to the horizontal transfer CCD 43 for each scanning line. The horizontal transfer CCD 43 sends out charges supplied from the vertical transfer CCD 42 one scanning line at a time. The horizontal transfer CCD 43 is performed by applying a two-phase clock signal of horizontal drive pulse terminals φH1 and φH2. The signal charge output via the output gate 44 of the horizontal transfer CCD 43 is input to the gate electrode of the transistor Q1.
[0022]
In the reset transistor Q3, after the reset pulse φR is input at a predetermined timing, the image pickup signal of the photodiode of the light receiving unit 40 is output, and then the charge applied to the gate electrode of the transistor Q1 passes through the drain electrode. Are released toward the reset drain terminal RD.
[0023]
A power supply voltage of 0 [V] is applied through the P well terminal GND of the CCD 10. The imaging signal output from the output gate 44 is amplified by the first-stage source follower composed of the transistors Q1 and Q2, and the output signal from the first-stage source follower is further amplified by the second transistor Q3 and Q4. Amplified by the source follower at the second stage, the output signal from the second source follower is converted to low impedance by the output source follower constituted by the transistor Q6, and the video is output via the output terminal Vout and the coaxial cable 18. It is supplied to the termination circuit of the processor 4.
Thus, the output amplifier 33 is configured inside the CCD 10 using the MOS type field effect transistor.
[0024]
In this conventional example, an output amplifier 33 for converting to a low impedance is incorporated in the CCD 10, and the terminal portion of the coaxial cable 18 is not used during a period in which no signal is read in order to suppress or reduce heat generation in the CCD 10 due to the incorporation. The power consumption reducing means for suppressing the power consumption by turning off the switch S provided in the circuit is formed. The operation of reducing the power consumption by the conventional electronic endoscope apparatus 1 configured as described above will be described. 13A shows a monitor screen, FIG. 13B shows a horizontal synchronization signal, FIG. 13C shows a signal readout period in the horizontal period, and FIG. 13D shows an output period of the control signal in the horizontal period. Is shown.
[0025]
FIG. 13 (b ′) shows a vertical synchronization signal, FIG. 13 (c ′) shows a signal readout period in the vertical period, and FIG. 13 (d ′) shows a control signal output period in the vertical period.
As can be seen from FIG. 13, the control signal output from the control circuit 21 is output during the period of the endoscope image display area 5A, and is not output otherwise. More specifically, in the horizontal period, a control signal that becomes “H” is output in a period from the time when the time t1 has elapsed from the horizontal synchronization signal to the time t2.
[0026]
In the vertical period, a control signal that is “H” is output in a period from the time when the time T1 has elapsed from the vertical synchronization signal to the time T2 from the vertical synchronization signal.
That is, the control circuit 21 turns on the switch S by a control signal that becomes “H” shown in the signal readout period (see FIG. 13) in which the imaging signal from the CCD 10 is output, and non-signal readout that does not output the imaging signal. It becomes “L” during the period and is turned off.
[0027]
Thereby, it is possible to save power by reducing power consumption in the termination circuit.
That is, in FIG. 11, when the control signal is “H”, the DC termination resistance Ron viewed from the CCD 10 is
Ron = R1 / R2 / (R1 + R2)
It becomes.
[0028]
On the other hand, when the control signal is “L”, the DC termination resistance Roff viewed from the CCD 10 is
Roff = R2
It becomes.
Therefore, Roff> Ron
Thus, the power consumption can be reduced as compared with the case where the termination circuit is continuously driven with Ron as in the prior art.
[0029]
[Problems to be solved by the invention]
The CCD output signal in this case is as shown in FIG. 14, and a large DC level difference Vdc occurs between the signal readout period and the non-signal readout period.
When this large DC level difference Vdc occurs, the amplitude of the CCD output signal input to the preamplifier 20 is apparently increased, and the dynamic range of the preamplifier 20 and the subsequent signal processing system is made larger than in the normal case. I will have to.
[0030]
In order to increase this dynamic range, it is necessary to increase the power supply voltage of the signal processing system, change the circuit configuration to a more complicated one, etc., which increases the circuit scale or increases costs. Will occur.
[0031]
The present invention has been made in view of the above-described points, and even if power consumption is reduced, an electronic endoscope that can reduce the DC level difference caused by the reduction to such an extent that the dynamic range does not need to be expanded. The object is to provide a mirror device.
[0032]
[Means for Solving the Problems]
  The electronic endoscope apparatus of the present invention is
  Endoscope having a solid-state image sensor for imaging a subjectAnd supplying a drive signal to the solid-state image sensor and performing signal processing on an output signal output from the solid-state image sensorThe signal processor,Through the cableConnectedIn an electronic endoscope device,
  The solid-state imaging device isAmplifying the output signal from the solid-state image sensorHaving impedance reduction means for sending out to the cable;
  The signal processing unit
  An output signal from the impedance reduction unit is input, and a signal level holding unit that holds the level of the output signal;
  An output signal from the impedance reduction unit and an output signal from the signal level holding unit are input, and a signal switching unit that performs output by switching the input, and
  In a readout period in which signal readout from the solid-state imaging device is performed, a non-readout period in which the output signal from the impedance reduction unit is conducted to the signal switching unit and output is performed, and no signal readout is performed from the solid-state imaging device And a control means for conducting the output signal from the signal level holding means and outputting it,
  It is characterized by having.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
1 to 3 relate to the first embodiment of the present invention, FIG. 1 shows the overall configuration of the electronic endoscope apparatus of the first embodiment, and FIG. 2 shows the vicinity of the signal input section of the video processor. FIG. 3 shows an operation explanatory diagram.
[0034]
As shown in FIG. 1, the electronic endoscope apparatus 1 according to the first embodiment of the present invention includes a sample and hold circuit (in the video processor 4 ′ of the electronic endoscope apparatus 1 ′ shown in FIG. (S / H in FIG. 1) 51 and a changeover switch 52 are provided. A sample hold pulse is applied from the control circuit 21 to the sample hold circuit 51, and the changeover switch 52 is turned on by a control signal for turning on / off the switch S. The video processor 4 is provided with means for eliminating or reducing the DC level difference by performing switching control.
[0035]
More specifically, the electronic endoscope apparatus 1 according to the first embodiment of the present invention includes an electronic endoscope (also referred to as a scope) 2 including a CCD 10 as a solid-state imaging device, and illumination light that irradiates a subject. And a video processor 4 that supplies a drive signal to the CCD 10 and takes in an image signal from the CCD 10 via a transmission cable 18 and processes the image signal, and is output from the video processor 4. And a color monitor 5 for displaying a video signal.
[0036]
The electronic endoscope 2 has an elongated insertion portion 6, and a thick operation portion 8 is formed at the rear end of the insertion portion 6. A light guide 7 that transmits illumination light is inserted into the insertion portion 6, and the rear end of the light guide 7 is detachably connected to the light source device 3, and illumination light from the lamp 13 passes through the condenser lens 12. The lever is supplied to the rear end surface of the light guide 7. This illumination light is transmitted, and is further irradiated to a subject such as an affected part in the body cavity from the distal end surface attached to the distal end portion 31 via the illumination lens 14.
[0037]
An objective lens 9 is provided at the distal end portion 31 of the insertion portion 6 and connects the subject image to its focal plane. The CCD 10 is disposed on this focal plane. The subject image is optically color-separated by a color filter in front of the CCD chip of the CCD 10.
[0038]
It is photoelectrically converted by the CCD 10 and accumulated as charges corresponding to the subject image optically color-separated. In the CCD 10, accumulated charges are read out by applying a CCD drive signal from a CCD driver 16 provided in the video processor 4 via a cable 17.
[0039]
The read signal (also referred to as an imaging signal) is amplified by an output amplifier 33 (see FIG. 12) which is an impedance reduction means provided inside the CCD 10 and then wired in the operation unit 8 and the insertion unit 6. The signal is input to the preamplifier 20 through the coaxial cable 18 through the sample hold circuit 51 and the changeover switch 52 in the video processor 4 connected to the termination circuit portion of the coaxial cable 18.
[0040]
The input terminal of the preamplifier 20, that is, the terminal circuit portion of the coaxial cable 18, is grounded via a resistor R1 and a switch S constituting power consumption reduction means, and is grounded via a resistor R2. The switch S is turned on / off by a control signal from the control circuit 21. The control signal controls the changeover of the changeover switch 52.
[0041]
A sample hold pulse is applied from the control circuit 21 to the sample hold circuit 51, and the sampled signal value is held by the application of the sample hold pulse. During the non-signal period, the held value is pre-amplified via the changeover switch 52. The above-described DC level difference Vdc is eliminated by inputting it into the No. 20.
[0042]
FIG. 2 shows a more detailed configuration of the termination circuit portion of the coaxial cable 18 in the present embodiment.
[0043]
The end of the coaxial cable 18 is grounded via the resistor R1 and the collector-emitter of the switching transistor 53 constituting the switch S, and is grounded via the resistor R2.
[0044]
The base of the transistor 53 is grounded via a resistor R3, and is connected to a control signal input terminal to which a control signal is applied via a resistor R4 and a capacitor C1.
[0045]
The end of the coaxial cable 18 is connected to the contact a of the changeover switch 52 and the input end of the sample and hold circuit 51 through a DC blocking capacitor C2. The input end of the sample hold circuit 51 is grounded via a resistor R5, and the output end of the sample hold circuit 51 is connected to the contact b of the changeover switch 52.
[0046]
The changeover control terminal of the changeover switch 52 is connected to the control signal input terminal, and a sample hold pulse is applied from the control circuit 21 to the sample hold control terminal of the sample hold circuit 51.
[0047]
As shown in FIG. 3, this sample hold pulse is output during the OB portion reading period of the OB portion in the reading period, the sample hold circuit 51 holds the level of this OB portion, and the contact b of the changeover switch 52 during the non-reading period. Is switched to ON, and a signal of this level is input to the preamplifier 20.
[0048]
The impedances of the resistors R1, R2, R5, etc. connected to the terminal end of the coaxial cable 18 are made equal to the impedance of the terminal end of the coaxial cable 18, so that the transmitted signal is hardly reflected and applied to the preamplifier 20 at the terminal portion. It is supposed to be input.
[0049]
Further, the power supply terminal of the CCD 10 provided in the insertion portion 6 of the electronic endoscope 2 shown in FIG. 1 has a CCD power supply Vcc of about 15 [V] generated from a power supply circuit (not shown) inside the video processor 4. Is supplied via a cable 22.
[0050]
As described above, the output amplifier 33 (see FIG. 12), which is the impedance reduction means, is provided inside the CCD 10. The power supply Vcc in the video processor 4A is supplied via the cable 22 to the power supply terminal VDD of the output stage of the output amplifier 33.
The output signal of the preamplifier 20 is extracted by the CDS circuit 23 from the baseband signal component from which reset noise and the like are removed, and is converted into a digital signal by the A / D converter 24. The digital signal is processed by the digital video processing circuit 25, then converted to an analog video signal through the D / A converter 26, output to the monitor 5, and an endoscopic image is displayed in the endoscopic image display area 5A. To do. The control circuit 21 controls operations of the CDS circuit 23, the A / D converter 24, the digital video processing circuit 25, and the D / A converter 26.
[0051]
Next, the operation of the present embodiment will be described.
The illumination light generated from the lamp 13 of the light source device 3 is condensed on the rear end surface of the light guide 7 by the condenser lens 12. The illumination light is transmitted by the light guide 7, and is irradiated to the subject from the distal end surface that is the other end of the light guide 7 via the illumination lens 14.
[0052]
Reflected light from the subject forms a subject image on the CCD 10 by the objective lens 9. The formed subject image is photoelectrically converted by the CCD 10 and accumulated as a charge corresponding to the subject image.
[0053]
The CCD 10 receives the CCD drive signal from the CCD driver 16 provided in the video processor 4 via the cable 17, so that the accumulated charge is transferred from the horizontal transfer CCD 43 and the output gate 44 to the transistor Q 1 of the output amplifier 33. Is supplied to the gate electrode.
[0054]
The signal supplied to the gate electrode of the transistor Q1 is amplified by the transistors Q1 and Q4, reduced in impedance by the transistor Q6, and connected to the internal resistor R1 and switch S (more specifically, via the transmission cable 18). Specifically, the image signal is transmitted to a termination circuit including a transistor 53) to be switched, a resistor R2, a capacitor C2, a resistor R5, and the like, and the image signal transmitted to the termination circuit is passed through a sample hold circuit 51 and a switch 52 to be preprocessed 20 Is input.
[0055]
In the period in which the control circuit 21 reads out signals from the CCD 10, that is, in the signal readout period (simply abbreviated as the readout period in FIG. 3 and the like), the control signal is “H” as shown in FIG. The conductive switch is set in a conductive state and the contact a of the changeover switch 52 is turned on.
[0056]
Accordingly, the CCD output signal is input to the preamplifier 20 through the changeover switch 52, amplified, and then input to the CDS circuit 23.
[0057]
On the other hand, during a period in which no signal is read from the CCD 10, that is, a non-signal reading period (simply abbreviated as a non-reading period in FIG. 3 or the like), as shown in FIG. The transistor 53 is turned off to reduce the power consumption, and the contact b of the changeover switch 52 is turned on so that the signal held by the sample hold circuit 51 is input to the preamplifier 20. Like that.
[0058]
The transistor 53 is turned on during the signal reading period, and the transistor 53 is turned off during the non-signal reading period, so that the waveform of the CCD output signal at the input end of the sample hold circuit 51 or at point a in FIG. As shown in (B), the waveform includes an image portion and an OB portion (optical black portion), and a DC level difference Vdc is generated in a step shape between the signal reading period and the non-signal reading period. This waveform is the same as the waveform at point a in FIG.
[0059]
In the sample and hold circuit 51, as shown in FIG. 3C, the CCD output signal in the OB section is sampled by the sample and hold pulse applied in the signal reading period of the OB section on the termination side in the signal reading period. Therefore, the value of the CCD output signal of the OB section held by the sample hold circuit 51 is input to the preamplifier 20 during the non-signal reading period.
[0060]
That is, the preamplifier 20 receives the CCD output signal having the waveform at point a in FIG. 3B during the signal readout period, and receives the CCD output signal value of the OB section during the non-signal readout period.
[0061]
Therefore, a signal from which the DC level difference Vdc in FIG. 3B has been eliminated as shown in FIG. 3D is input to the input terminal of the preamplifier 20 (that is, the point b in FIG. 2).
[0062]
For this reason, the endoscope apparatus 1 with reduced power consumption can be realized without requiring expansion of the dynamic range on the preamplifier 20 and the subsequent stage side.
[0063]
Therefore, according to the present embodiment, the OB portion is sampled and held and the portion outside the signal readout period is replaced. Therefore, the replaced level becomes the same as the black level within the signal readout period, and the level difference can be eliminated.
[0064]
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 shows a circuit configuration in the vicinity of the signal input section of the video processor according to the second embodiment, and FIG. 5 shows an operation explanatory diagram.
[0065]
As shown in FIG. 4, in this embodiment, an integration circuit 56 for integrating the CCD output signal is provided in place of the sample hold circuit 51 in the first embodiment, and this integrated signal is output during the non-signal reading period by the control signal. It is something to replace with.
[0066]
That is, the connection point (point a) between the capacitor C2 and the resistor R5 is connected to one end of the resistor R6 that constitutes the integrating circuit 56, and the other end of the resistor R6 is grounded via the capacitor C3. Are connected to the contact b.
Other configurations are the same as those of the first embodiment.
[0067]
Next, the operation of the present embodiment will be described.
As described in the first embodiment, the control circuit 21 sets the control signal shown in FIG. 5A to “H” in the signal readout period to make the transistor 53 conductive, and the contact of the changeover switch 52. Set so that a turns on.
[0068]
Accordingly, the CCD output signal is input to the preamplifier 20 through the changeover switch 52, amplified, and then input to the CDS circuit 23.
[0069]
On the other hand, during the non-signal reading period, the control signal is set to “L”, the transistor 53 is turned off to reduce power consumption, and the contact b of the changeover switch 52 is switched to ON. The integration signal integrated by the integration circuit 56 is input.
[0070]
The transistor 53 is turned on during the signal readout period, and the transistor 53 is turned off during the non-signal readout period, so that the waveform of the CCD output signal at point a in FIG. 4 is a video as shown in FIG. The waveform includes the OB portion and the OB portion, and a DC level difference Vdc is generated in a stepped manner between the signal reading period and the non-signal reading period. This waveform is the same as the waveform at point a in FIG.
[0071]
Since the integrating circuit 56 outputs an integrated signal obtained by integrating the signal shown in FIG. 5B, the signal input to the preamplifier 20 is obtained by changing the DC level difference Vdc shown in FIG. 5B as shown in FIG. The waveform becomes smaller.
[0072]
The integrated signal that is integrated varies depending on the brightness level of the video portion, but is still within the allowable level of the integrated signal relative to the CCD output signal (that is, a level that does not require expansion of the dynamic range). It is substantially unnecessary to expand the dynamic range of the preamplifier 20 or the like.
[0073]
According to the present embodiment, by replacing the sample and hold circuit 51 of the first embodiment with the integration circuit 56, almost the same effect can be obtained at a low cost without requiring a sample and hold pulse. Further, the permissible level for the integrated signal is schematically shown in FIG. 5C, and the integral signal is sufficiently within the permissible level, so that it can be implemented practically.
[0074]
(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 shows a circuit configuration in the vicinity of the signal input unit of the video processor according to the third embodiment, and FIG. 7 shows an operation explanatory diagram.
[0075]
As shown in FIG. 6, in the present embodiment, a DC power source for generating a DC level is provided in place of the sample and hold circuit 51 in the first embodiment, and the changeover switch 52 is switched by a control signal and the non-signal reading period is set. It replaces with this direct current level.
[0076]
For example, one end and the other end of the variable resistor R7 are connected to the power supply Vcc and the ground, respectively, and the variable terminal is connected to the contact b of the changeover switch 52. The variable resistor R7 divides the power supply Vcc by resistance and switches the divided voltage. The voltage is applied to the contact b of the switch 52.
[0077]
A voltage having a certain DC level within the allowable DC level range is applied to the contact b. Other configurations are the same as those of the first embodiment.
Next, the operation of the present embodiment will be described.
[0078]
As described in the first embodiment, in the signal readout period, the control circuit 21 sets the control signal shown in FIG. Set so that a turns on.
[0079]
Accordingly, the CCD output signal is input to the preamplifier 20 through the changeover switch 52, amplified, and then input to the CDS circuit 23.
[0080]
On the other hand, during the non-signal reading period, the control signal is set to “L”, the transistor 53 is turned off to reduce power consumption, and the contact b of the changeover switch 52 is switched to ON. The DC level set from the DC power supply is input.
[0081]
In the signal readout period, the transistor 53 is turned on, and in the non-signal readout period, the transistor 53 is turned off, so that the waveform of the CCD output signal at point a in FIG. 6 is an image as shown in FIG. The waveform includes the OB portion and the OB portion, and a DC level difference Vdc is generated in a stepped manner between the signal reading period and the non-signal reading period. This waveform is the same as the waveform at point a in FIG.
[0082]
Since the DC level set from the DC power supply is input to the preamplifier 20 during the non-signal reading period, the signal input to the preamplifier 20 is as shown in FIG. The waveform is obtained by reducing the DC level difference Vdc.
[0083]
In the present embodiment, it is substantially unnecessary to expand the dynamic range of the preamplifier 20 and the like by setting the DC level applied to the preamplifier 20 by the variable resistor R7 within the allowable level range.
[0084]
According to the present embodiment, by replacing with a DC level application means instead of the sample hold circuit 51 of the first embodiment, a sample hold pulse is not required as in the second embodiment. The same effect can be obtained at low cost. In addition, the direct current level can be set within an allowable level that does not require expansion of the dynamic range, so that it is easy to implement at a low cost.
[0085]
Note that the DC level applied to the contact b of the changeover switch 52 by resistance division or the like may be set to a DC level equivalent to that of the OB portion described above, for example. Further, it may be set to the center value (median value) of the DC level variation of the OB portion.
[0086]
FIG. 8 is a block diagram of the PLL circuit 60 that synchronizes with an external composite synchronization signal. The configuration will be described below.
A composite synchronization signal from an external device is input to the horizontal synchronization separation circuit 61. The outputs of the horizontal synchronizing signal separation circuit 61 and the frequency dividing circuit 62 are input to the phase comparison circuit 63. The outputs J and K are input to the filter circuit 64. This output L is input as a control voltage for the VCO 65. The output of the VCO 65 is fed back as a clock input of the frequency dividing circuit 62.
[0087]
FIG. 9 shows a part of an internal block diagram of the phase comparison circuit 63 and an internal block diagram of the filter circuit 64.
In FIG. 9, VDD and VCC indicate the respective power supply voltages of 5V. Q11 and Q12 are MOS FETs, and Q13, Q14, and Q15 are NPN transistors. R11, R12, R13, and R14 are resistors, and C11 is a capacitor.
[0088]
Next, the operation will be described.
In FIG. 8, the phase of the output of the horizontal sync separator 61 and the output of the divider 62 is compared by the phase comparator 63.
[0089]
In the case where the output phase of the horizontal sync separating circuit 61 is advanced among the two phases, only the MOS FET Q12 in FIG. 9 is turned ON, and a current flows from right to left of K.
When the phase of the output of the frequency dividing circuit 62 is advanced, only the MOS FET Q11 is ON, and a current flows from the left to the right of J. When the phases match, both MOSFETs Q11 and Q12 are always OFF and no current flows.
[0090]
These currents are filtered by the filter circuit 64, and the output L is input to the VCO 65. This output is input to the frequency dividing circuit 62 to form a negative feedback loop.
[0091]
In FIG. 9, since the base-emitter voltage of the NPN transistor is generally about 0.6V, the base P potential of the transistor Q15 is 0.6V, the base N of the transistor Q14 is 1.2V, and the transistor Q13 Base M is 1.8V. For this reason, if the internal resistance when the MOSFETs Q11 and Q12 are ON is ignored, the current flowing through the resistor R11 when the MOSFET Q11 is ON is
5-1.8 / R11
In addition, the current flowing through the resistor R12 when the MOSFET Q12 is ON is
1.8 / R12
Therefore, for example, by setting R1 = 3.2 KΩ and R2 = 1.8 KΩ, each current value can be made the same (1 mA).
[0092]
In the modification shown in FIG. 10, the configuration of the filter circuit 64 is the same as that in FIG. Hereinafter, only the parts different from FIG. 9 will be described in detail.
[0093]
FIG. 10 shows a part of an internal block diagram of the phase comparator 63 and an internal block diagram of the filter circuit 64.
[0094]
In the phase comparator 63, CMOS digital buffers A1 and A2 are added in place of the MOSFETs Q11 and Q12 of FIG. These power supply terminals are connected to the power supply voltages VDD and GND and output high or low. Assume that this output is swung up to VDD or GND potential. In addition, silicon diodes D1 and D2 are newly added.
[0095]
Next, the operation will be described.
In FIG. 8, the phase of the output of the horizontal sync separator 61 and the output of the divider 62 is compared by the phase comparator 63.
In the case where the phase of the output of the horizontal sync separation circuit 61 is advanced among the two phases, both the digital buffers A1 and A2 in FIG. 10 become low outputs, and a current flows from right to left of K. When the phase of the output of the frequency dividing circuit 62 is advanced, both the digital buffers A1 and A2 become high outputs, and current flows from the left to the right of J. When the phases match, the digital buffer A1 is low and the digital buffer A2 is high output and no current flows.
[0096]
These currents are filtered by the filter circuit 64, and the output L is input to the VCO 65. This output is input to the frequency dividing circuit 62 to form a negative feedback loop.
[0097]
The silicon diodes D1 and D2 function to prevent current from flowing into the filter circuit 64 when the digital buffer A1 is at a low output and the digital buffer A2 is at a high output.
[0098]
Next, the operation will be briefly described.
Generally, the forward voltage drop of a silicon diode is about 0.6V. For this reason, if the internal resistances of the digital buffers A1 and A2 are ignored, the current flowing through the resistor R11 when the digital buffer A1 is high output is
5-1.8-0.6 / R11
It becomes.
[0099]
In addition, when the digital buffer A2 outputs low, the current flowing through the resistor R12 is
1.8-0.6 / R12
Therefore, for example, by setting R11 = 2.6 KΩ and R12 = 1.2 KΩ, each current value can be made the same (1 mA).
[0100]
As described above, the PLL circuit 60 having more ideal characteristics can be obtained by setting the resistance values of the resistors R11 and R12 to different values as described in FIG. 9 or FIG.
The MOSFETs Q11 and Q12 may be realized by a three-state buffer with a small leakage current.
[0101]
As described above, a PLL circuit having more ideal characteristics can be obtained by setting the resistance values of the resistors R11 and R12 to different values.
[0102]
In addition, a PLL circuit can be assembled using the output of a normal buffer instead of a special three-state buffer with little leakage current. For this reason, the phase comparison circuit can be incorporated into a 5V power supply FPGA having a normal buffer output. Further, since the amplifier in the filter circuit is not an operational amplifier but a transistor, the circuit scale can be reduced.
[0103]
[Appendix]
1. An endoscope provided with a solid-state imaging device for imaging a subject in an elongated insertion unit, and a video processor unit for supplying a drive signal to the solid-state imaging device and performing signal processing on an output signal output from the solid-state imaging device In an electronic endoscope apparatus in which and are separated via a cable,
The solid-state imaging device has an impedance reduction unit that amplifies the output signal and converts it to a low impedance and sends it to the cable.
The video processor unit reduces power consumption of the impedance reduction unit in a non-signal readout period in which an output signal is not read out with respect to a signal readout period in which an output signal photoelectrically converted from the solid-state imaging device is read out. Reduction means,
It is generated by the power consumption reducing means. An electronic endoscope apparatus comprising: means for reducing a direct current level difference between a read period and a non-read period of the output signal.
[0104]
2. In the supplementary note 1, the means for reducing the direct current level difference is characterized in that the OB portion in the readout period is sampled and held and replaced with a non-readout period for output.
3. In the supplementary note 1, the means for reducing the DC level difference is characterized in that the entire output signal is integrated and output after being replaced by a non-reading period.
[0105]
4). In the supplementary note 1, the means for reducing the direct current level difference is characterized in that a direct current level equivalent to the OB portion in the readout period is created by resistance division and replaced with a non-readout period for output. .
5. Appendix 4 is characterized in that the DC level value equivalent to that of the OB portion is the center of the variation in the DC level of the OB portion.
[0106]
6). A phase comparison circuit having two types of dedicated output signals, ie, a draw-in current output and a sweep-out current output, and one of the two types of dedicated output signals passes through the first resistor and the other passes through the second resistor. And a voltage-controlled oscillator whose frequency is controlled by the filter circuit output signal and whose output is directly or divided and input to the phase comparison circuit, the first and second A PLL circuit characterized in that the resistance values of the first resistor and the second resistor are set to different values so that respective current values when current flows through the resistors are equal.
7. In Appendix 6, the amplifier circuit in the filter circuit is composed of N (N is a natural number) stages of transistor circuits.
[0107]
(Background to appendices 6 and 7)
The present invention relates to a signal circuit of an endoscope image compression / decompression apparatus used in a hospital.
(Conventional technology)
2. Description of the Related Art In recent years, endoscope video signals are captured by an endoscope image compression / decompression apparatus and electronic filing is performed in hospitals. This is an extremely useful method without requiring manual work for handling a film or the like when an image is observed later.
[0108]
A device that receives such a video signal needs a PLL circuit that synchronizes a clock signal generated by an internal voltage controlled oscillator (hereinafter referred to as VCO) with a video synchronization signal input from the outside.
[0109]
In FIG. 2 and FIG. 4 in JP-A-1-296812, the input part of the filter circuit in this PLL circuit passes the charge / discharge currents having different directions to the capacitors to different resistors having the same resistance value. Examples have been disclosed.
Further, in FIG. 2 in Japanese Patent Laid-Open No. 6-177755, similarly, in the case where the filter input terminal voltage is half of the power supply voltage, as a conventional technique, the charge / discharge current flowing through each resistor is set to the same value. And its calculation formula is disclosed.
[0110]
However, in the above prior art circuits, an operational amplifier is used as an amplifier in the filter circuit, and the input terminal voltage is uniformly determined as in an amplifier simply by combining transistors at the subsequent stage. Nothing was said about the case where it was not halved.
[0111]
(Purpose of Supplementary Notes 6 and 7) Even when the filter input terminal voltage in the PLL circuit is not half of the power supply voltage, the charge / discharge current flowing through each resistor is made the same, and the PLL circuit with ideal characteristics can be used from the outside. An object is to provide a device capable of receiving a video synchronization signal.
[0112]
(Means and actions for solving the problems)
In a filter circuit in a PLL circuit used in an electronic filing device for an endoscopic image or the like, an incoming current output and a swept current output from a phase comparison circuit are input to the filter circuit via individual resistors.
The resistance values are set to different values in accordance with the power supply voltage and the filter input terminal voltage so that the currents flowing through the resistors become equal.
Therefore, it is possible to always operate the PLL circuit having ideal characteristics for any input terminal voltage of the filter circuit.
[0113]
【The invention's effect】
As described above, according to the present invention, an endoscope provided with a solid-state imaging device that images a subject in an elongated insertion portion, a drive signal is supplied to the solid-state imaging device, and output from the solid-state imaging device. In an electronic endoscope apparatus in which a video processor unit that performs signal processing on an output signal is separated via a cable,
The solid-state imaging device has an impedance reduction unit that amplifies the output signal and converts it to a low impedance and sends it to the cable.
The video processor unit reduces power consumption of the impedance reduction unit in a non-signal readout period in which an output signal is not read out with respect to a signal readout period in which an output signal photoelectrically converted from the solid-state imaging device is read out. Reduction means,
It is generated by the power consumption reducing means. Means for reducing the direct current level difference between the readout period and the non-readout period of the output signal is provided, so that even if power consumption is reduced, the dynamic level can be expanded by reducing the direct current level difference. It can be made as small as it is not necessary.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of an electronic endoscope apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a circuit configuration in the vicinity of a signal input unit of a video processor.
FIG. 3 is an explanatory diagram of operations in a signal readout period and a non-signal readout period.
FIG. 4 is a diagram showing a circuit configuration near a signal input unit of a video processor according to a second embodiment of the present invention.
FIG. 5 is an explanatory diagram of operations in a signal reading period and a non-signal reading period.
FIG. 6 is a diagram showing a circuit configuration in the vicinity of a signal input unit of a video processor according to a third embodiment of the present invention.
FIG. 7 is an explanatory diagram of operations in a signal reading period and a non-signal reading period.
FIG. 8 is a block diagram of a PLL circuit that synchronizes with a composite synchronization signal.
9 is a circuit diagram showing a part of the phase comparison circuit of FIG. 8 and an internal configuration of a filter circuit.
10 is a circuit diagram of a modification of FIG.
FIG. 11 is an overall configuration diagram of a conventional electronic endoscope apparatus.
FIG. 12 is a diagram showing an internal configuration of a CCD.
FIG. 13 is an operation explanatory diagram of a conventional example.
FIG. 14 is a diagram showing a CCD output waveform and the like input to a video processor in a conventional example.
[Explanation of symbols]
1. Electronic endoscope device
2 ... Electronic endoscope
3. Light source device
4 ... Video processor
5. Color monitor
10 ... CCD
16 ... CCD driver
18 ... Coaxial cable
20 ... Preamplifier
21 ... Control circuit
23 ... CDS circuit
51. Sample hold circuit
52 ... changeover switch
53 ... Transistor
R1-R5 ... resistance
C1, C2 ... Capacitors
S ... Switch

Claims (3)

An endoscope having a solid-state imaging device that images a subject, and a signal processing unit that supplies a drive signal to the solid-state imaging device and performs signal processing on an output signal output from the solid-state imaging device via a cable. In the connected electronic endoscope device,
The solid-state image sensor has an impedance reduction means for amplifying an output signal from the solid-state image sensor and sending it to the cable,
The signal processing unit
An output signal from the impedance reduction unit is input, and a signal level holding unit that holds the level of the output signal;
An output signal from the impedance reduction unit and an output signal from the signal level holding unit are input, and a signal switching unit that performs output by switching the input, and
In a readout period in which signal readout from the solid-state imaging device is performed, a non-readout period in which the output signal from the impedance reduction unit is conducted to the signal switching unit and output is performed, and no signal readout is performed from the solid-state imaging device And a control means for conducting the output signal from the signal level holding means and outputting it,
An electronic endoscope apparatus comprising: A termination circuit in which one end is connected to the cable and the other end is connected to the signal level holding means and the signal switching means, and transmits a signal so as to be equal to the impedance of the termination of the cable. The electronic endoscope apparatus according to claim 1, further comprising a unit. The control unit causes the signal level holding unit to hold the signal level of the optical black portion in the output signal from the solid-state imaging device in the readout period, and to the signal switching unit in the non-reading period. 3. The electronic endoscope apparatus according to claim 1, wherein the output is performed by conducting the signal level of the optical black portion.

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