JP4098460B2 - Mask for exposure - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an exposure mask used in the lithography process in the manufacture of semiconductor devices.
[0002]
[Prior art]
In recent years, with the high integration and high speed of semiconductor devices, the demand for dimensional control of device patterns has become increasingly severe. For this reason, there is a difference between the design dimension and the finished dimension due to the resolution limit in the wafer manufacturing process. As means for correcting this difference, various optical proximity correction methods (OPC = Optical Proximity Correction) have been proposed. OPC is a device geometry attributed to the wafer manufacturing process, such as by partially thickening the mask or placing a dummy pattern in consideration of the total wafer process or using optical simulation. It is intended to correct the change of.
[0003]
For example, FIG. 16 shows a pattern in which gate wirings are arranged. As shown in FIG. 16, since the corner of the gate wiring end portion is already at the resolution limit, the end portion of the finished gate wiring 32 becomes shorter than the designed mask pattern 31. This phenomenon is called shortening. This shortening becomes more prominent as the line width of the gate wiring 32 becomes narrower.
[0004]
Therefore, as shown in FIG. 17, a correction pattern 33 in which the length of the end portion of the mask pattern 31 is uniformly extended from the gate wiring 35 of a desired pattern by OPC, or a hammer head is attached to the end portion of the mask pattern 31. A correction pattern 34 has been created. As a result, shortening of the gate wiring 35 is suppressed.
[0005]
[Problems to be solved by the invention]
However, in the case of the above method, considering the case where the gate wirings are densely arranged, there is a limit value for the extension amount of the mask pattern end and the size of the hammer head, and there is a problem that the shortening cannot be sufficiently suppressed. It was.
[0006]
Therefore, it must be designed with a sufficient margin so that a sufficient extension amount or a hammer head can be attached to the interval between the mask pattern ends or between the mask patterns. However, a design with a margin will increase the chip area. Therefore, there has been a demand for an OPC technique that can suppress shortening even when the gate wirings are densely arranged.
[0007]
In an actual device, the surrounding environment varies depending on whether the gate wirings are densely arranged or sparsely arranged, and the amount of shortening varies depending on the environment. Therefore, a method for uniformly applying a necessary correction amount in consideration of an environment with the largest shortening amount is simple. However, a method for changing the correction amount according to the environment has been demanded in consideration of an increase in chip area.
[0008]
The present invention has been made to solve the above problems, it is an object without increasing the chip area, to provide an exposure mask which enables suppression of shortening in response to the environment It is in.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention uses the following means.
[0014]
The first exposure mask of the present invention comprises a plurality of first mask patterns provided with hammerheads on side surfaces of pattern ends, and a plurality of second mask patterns, wherein the second mask pattern, the first so that the pattern edge of the mask pattern and the pattern end portion of the second mask pattern is adjacent, the first direction and the ends facing the side portions Are alternately arranged in the second direction facing each other, and the pattern edge of the second mask pattern is closer to the second direction than the pattern edge of the first mask pattern adjacent to the first direction. The length has been extended .
[0015]
The second exposure mask of the present invention has a first mask pattern in which a plurality of first hammer heads are provided on the side surface of the pattern end, and a plurality of second hammer heads on the side surface of the pattern end. And the first hammer head and the second hammer head are provided at positions shifted so as not to overlap each other, and the first mask pattern and the second mask pattern are provided. the mask pattern, wherein as the first and second hammer head is not Mukaiawa each direction and ends opposite the side portions are arranged alternately in opposite directions, said first hammerhead Has a constant size and a constant spacing, and the second hammerhead has a size equal to and equal to the first hammerhead .
[0016]
In the second exposure mask, wherein the first, predetermined spacing of the second hammer head, the first, it is preferable that substantially equal to the constant magnitude of the second hammer head. Further, the constant interval between the first and second hammer heads may be larger than the constant size of the first and second hammer heads.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
[First embodiment]
In the first embodiment of the present invention, for example, a method for correcting an exposure mask pattern for forming a gate wiring of a transistor that intersects an element region will be described. In this mask pattern correction method, after a mask pattern having a line width equal to or smaller than a specified value is selected from mask patterns protruding from the element region, a distance to a pattern adjacent to the mask pattern is calculated, and this distance is calculated. Accordingly, the mask pattern is corrected accordingly.
[0020]
FIG. 1 shows a flowchart of mask pattern correction according to the first embodiment. The mask pattern correction method according to the first embodiment will be described below with reference to the flowchart shown in FIG.
[0021]
FIG. 2 shows an example in which a plurality of mask patterns for forming gate wirings are arranged crossing the element region. As shown in FIG. 2, first, second, and third mask patterns 12a, 12b, and 12c are arranged in parallel on the element region 11, and the first, second, and third mask patterns 12a, 12b, A fourth mask pattern 12d is arranged perpendicular to 12c.
[0022]
First, as shown in FIG. 3, in the first, second, and third mask patterns 12a, 12b, and 12c that overlap the element region 11, for example, a portion protruding from the element region 11 on the fourth mask pattern 12d side (hereinafter, referred to as the following) 13a and 13b are extracted (referred to as protruding portions) (ST1). Thereafter, as shown in FIG. 4, the line widths W1 and W2 of the protruding portions 13a and 13b are calculated (ST2).
[0023]
Next, it is determined whether or not the line widths W1 and W2 are smaller than the specified value a (a <W) (ST3). Here, for example, when the line width W1 of the protruding portion 13a of the first and second mask patterns 12a and 12b is the line width W1 <the specified value a, it is necessary to correct the first and second mask patterns 12a and 12b. Become. Further, for example, when the line width W2 of the protruding portion 13b of the third mask pattern 12c is equal to the line width W2 ≧ the specified value a, the correction process of the third mask pattern 12c is not performed and it is used as it is as a mask (ST4). As described above, whether or not the mask pattern is corrected is determined based on the line widths W1 and W2. A method for obtaining the specified value a will be described later.
[0024]
Next, as shown in FIG. 5, the distance from each side of the protruding portion 13a of the first and second mask patterns 12a and 12b to be corrected to the adjacent mask pattern (hereinafter, the distance between the adjacent patterns). S) is calculated (ST5).
[0025]
Next, a correction rule for the distance S between adjacent patterns is created (ST6). A detailed method for creating the correction rule will be described later.
[0026]
Next, as shown in FIG. 6, according to the correction rule, necessary correction is performed on each side of the protruding portion 13a, and a correction pattern 14 is created (ST7).
[0027]
Next, a method for obtaining the specified value a described above will be described. The specified value a defines a boundary as to whether or not a mask pattern correction process is necessary for which line width.
[0028]
First, as shown in FIG. 7, the line width W of the arranged test patterns 15 and the distance S between adjacent test patterns 15 are calculated. Next, the amount of shortening of the test pattern 15 with respect to the distance S is obtained by optical simulation or experiment. The result is shown in FIG.
[0029]
FIG. 8 shows the relationship between the distance S between adjacent test patterns 15 and the amount of shortening for various line widths W. In FIG. 8, line widths W = a, b, and c have a relationship of a>b> c, and the amount of shortening increases as the line width W decreases. Further, when the distance S between the adjacent test patterns 15 is S ′, the amount of shortening is maximized. Hereinafter, the case where the shortening amount is maximum is referred to as the worst case.
[0030]
Next, an allowable value of shortening is determined by design for the device to be applied. The allowable value of this shortening is determined by, for example, the alignment accuracy during exposure, dimensional variations, transistor operation, and the like.
[0031]
Next, the minimum line width at which the worst case shortening amount is less than or equal to the allowable value is determined. As a result, as shown in FIG. 8, for example, the line width a is determined as the specified value a. Here, when the line width is larger than the specified value a, the amount of shortening exceeds the allowable value, and thus a mask pattern correction process is required. Therefore, a correction pattern is created according to the correction rule by the above-described processing of ST5 to ST7.
[0032]
Next, a method for creating the correction rule described above will be described. First, as shown in FIG. 9, the line width W of the arranged test patterns 15 and the distance S between the adjacent test patterns 15 are calculated. Next, a hammer head 16 having a size of, for example, h is provided on the test pattern 15. Here, the size h of the hammer head 16 indicates the length of the portion protruding from the test pattern 15.
[0033]
Next, the line width W of the test pattern 15 is fixed, and the size h of the hammer head 16 is variously changed by optical simulation or experiment, and the shortening amount with respect to the distance S between the adjacent test patterns 15 is calculated. Here, although the magnitude | size of the hammer head 16 is changed by the integral multiple of the design grid, for example, it is not limited to this. In the same manner as described above, an allowable value of shortening is determined by design for the device to be applied, and the hammer head 16 is set so that the amount of shortening is less than the allowable value at all distances S with respect to the fixed line width W. The size h is changed. The line width W to be fixed is set to a line width that is equal to or less than the specified value a.
[0034]
FIG. 10 shows the relationship between the distance S between adjacent test patterns 15 and the shortening amount with respect to various sizes h of the hammer head 16. In FIG. 10, the sizes h = A, 2A, 3A of the hammer head 16 have a relationship of 3A>2A> A, and the shortening amount increases as the size h of the hammer head 16 decreases. Yes.
[0035]
As a result, as shown in FIG. 11, the size h of the hammer head 16 for each distance S between the test patterns 15 where the amount of shortening is equal to or less than an allowable value is obtained. Thus, as shown in FIG. 12, h = A when S <Sa or Sd ≦ S, h = 2A when Sa ≦ S <Sb or Sc ≦ S <Sd, and Sb ≦ S <Sc. A correction rule such that h = 3A can be created. Here, the distance S between the divided test patterns 15 is, for example, an integer multiple of the minimum grid of the design, but is not limited thereto.
[0036]
Note that a correction rule for a desired line width W can be created by acquiring data for various line widths W in the same manner as described above.
[0037]
According to the first embodiment, after a mask pattern having a line width equal to or less than a specified value is selected from the mask patterns protruding from the element region, a distance to a pattern adjacent to the mask pattern is calculated. The mask pattern is corrected according to the distance. For this reason, a desired mask pattern can be formed according to the surrounding environment. Therefore, the shortening phenomenon can be suppressed without increasing the chip area.
[0038]
[Second Embodiment]
In the second embodiment, exposure is performed by alternately arranging a first mask pattern having a hammer head at a pattern end and a second mask pattern having an extended pattern end in the left-right direction and the opposite direction. It is a mask for use. The pattern of the exposure mask in the second embodiment will be described below.
[0039]
First, as shown in FIG. 13, consider a layout in which the gate wirings 21 are densely arranged in the left-right direction and the opposite direction. In a mask pattern for finishing such a layout, if an attempt is made to attach a sufficient hammer head to the mask pattern to avoid shortening, the hammer heads of adjacent mask patterns will overlap. Further, when the end portions of the mask pattern are extended to finish according to the layout, the end portions of the mask patterns facing each other overlap.
[0040]
Therefore, in order to avoid the above problem, first, as shown in FIG. 14, the first mask pattern 22a and the second mask pattern 22b are divided in order to distinguish between the adjacent mask patterns and the mask patterns facing each other. Next, the first mask pattern 22a is subjected to a process of providing a hammer head 23 at the pattern end, and the second mask pattern is subjected to a process of extending the pattern end.
[0041]
According to the second embodiment, the first mask pattern 22a having the hammer head 23 at the pattern end and the second mask pattern 22b having the pattern end extended in the left-right direction and the opposing direction. They are arranged alternately. For this reason, it is possible to avoid the overlapping of the hammer heads of the adjacent mask patterns and the ends of the opposing mask patterns without increasing the chip area. Therefore, a mask pattern having a desired layout can be formed, and shortening can be sufficiently suppressed.
[0042]
It should be noted that the second embodiment can be used in combination with the first embodiment. In this case, a mask pattern having a desired layout can be formed, and shortening can be further suppressed.
[0043]
Further, as a method of dividing into the first mask pattern 22a and the second mask pattern 22b, it is possible to easily distinguish the patterns by using Levenson shifter arrangement conversion software.
[0044]
[Third embodiment]
In the third embodiment, a first mask pattern provided with a plurality of hammer heads having a constant size d and a constant interval d, and a position shifted by a half pitch from the hammer head of the first mask pattern. It is an exposure mask in which second mask patterns having a plurality of provided hammerheads are alternately arranged. The pattern of the exposure mask in the third embodiment will be described below.
[0045]
First, as shown in FIG. 15, as in the second embodiment, considering a layout in which the gate wirings 21 are densely arranged in the left-right direction and the opposite direction as shown in FIG. In order to distinguish, it divides into the 1st mask pattern 24a and the 2nd mask pattern 24b.
[0046]
Next, the 1st hammer head 25a whose length with respect to the longitudinal direction of the 1st mask pattern 24a is d is provided in the edge part of one side surface of the 1st mask pattern 24a. A second hammer head 25b having the same size as the first hammer head 25a is provided on one side surface of the first mask pattern 24a at a distance d from the first hammer head 25a. The third and fourth hammer heads 25c and 25d are provided on the other side surface of the first mask pattern 24a so as to be provided at the same positions as the first and second hammer heads 25a and 25b.
[0047]
Similarly, a fifth hammer head 25e having the same size as the first hammer head 25a is provided on one side surface on the inner side by a distance d from the end of the second mask pattern 24b. A sixth hammer head 25f having the same size as the fifth hammer head 25e is provided on one side surface of the second mask pattern 24b so as to be separated from the fifth hammer head 25e by a distance d. The seventh and eighth hammer heads 25g and 25h are provided on the other side surface of the second mask pattern 24b so as to be provided at the same position as the fifth and sixth hammer heads 25e and 25f.
[0048]
It should be noted that the interval between the hammer heads is preferably substantially equal to the size of the hammer head, but may be any interval that is not less than the size of the hammer head.
[0049]
According to the third embodiment, the first mask pattern 24a provided with a plurality of hammer heads having a constant size d and a constant interval d, and the hammer head and the half of the first mask pattern 24a. Second mask patterns 24b having a plurality of hammer heads provided at positions shifted in pitch are alternately arranged in the left-right direction and the opposing direction. For this reason, it is possible to avoid the overlapping of the hammer heads of the adjacent mask patterns and the ends of the opposing mask patterns without increasing the chip area. Therefore, a mask pattern having a desired layout can be formed, and shortening can be sufficiently suppressed.
[0050]
The third embodiment can also be used in combination with the first embodiment. In this case, a mask pattern having a desired layout can be formed, and shortening can be further suppressed.
[0051]
Further, as a method of dividing into the first mask pattern 24a and the second mask pattern 24b, it is possible to easily distinguish patterns by using Levenson shifter arrangement conversion software.
[0052]
In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.
[0053]
【The invention's effect】
According to the present invention described above, without increasing the chip area can be provided an exposure mask that enables suppression of shortening in response to the environment.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a mask pattern correction method according to a first embodiment of the present invention.
FIG. 2 is a plan view showing an example in which a plurality of mask patterns are arranged on an element region.
FIG. 3 is a plan view showing extraction (ST1) of a protruding portion of a mask pattern.
FIG. 4 is a plan view showing extraction (ST2, ST3) of a line width W of a protruding portion of a mask pattern.
FIG. 5 is a plan view showing calculation (ST5) of a distance S to a pattern adjacent to the protrusion portion of the mask pattern.
FIG. 6 is a plan view showing mask pattern creation (ST6, ST7) according to a correction rule.
FIG. 7 is a plan view showing a method for calculating a specified value a.
FIG. 8 is a diagram showing a relationship between a distance S between adjacent test patterns and a shortening amount with respect to various line widths W;
FIG. 9 is a plan view in which a hammer head is provided on a test pattern.
FIG. 10 is a diagram showing a relationship between a distance S between adjacent test patterns and a shortening amount with respect to various sizes h of the hammer head.
FIG. 11 is a diagram illustrating a distance at which the amount of shortening is less than or equal to an allowable value.
FIG. 12 is a table showing the relationship between the distance S between adjacent patterns and the size of the hammer head.
FIG. 13 is a plan view showing a layout in which gate wirings are densely arranged.
FIG. 14 is a plan view showing a mask pattern according to a second embodiment of the present invention.
FIG. 15 is a plan view showing a mask pattern according to a third embodiment of the present invention.
FIG. 16 is a plan view showing a mask pattern according to the prior art.
FIG. 17 is a plan view showing a mask pattern according to the prior art.
[Explanation of symbols]
11: Element region,
12a, 22a, 24a ... first mask pattern,
12b, 22b, 24b ... the second mask pattern,
12c ... a third mask pattern,
12d ... fourth mask pattern,
13a, 13b ... protruding portion,
14 ... correction pattern,
15 ... Test pattern,
16, 23, 25a, 25b, 25c, 25d, 25e, 25f, 25g, 25h ... hammer head,
21: Gate wiring.

Claims (4)

A plurality of first mask patterns provided with a hammer head on the side surface of the pattern end;
A plurality of second mask patterns;
And said second mask pattern and the first mask pattern, such that the pattern end of the said pattern end portions of the first mask pattern and the second mask pattern is adjacent, facing the side portions Alternately arranged in the first direction and the second direction where the ends face each other ,
The exposure is characterized in that the pattern end portion of the second mask pattern is longer in the second direction than the pattern end portion of the first mask pattern adjacent in the first direction. Mask. A first mask pattern in which a plurality of first hammerheads are provided on a side surface of the pattern end;
A plurality of second hammer heads and a second mask pattern provided on a side surface of the pattern end,
The first hammer head and the second hammer head are provided at positions shifted so as not to overlap,
The The said first mask pattern and the second mask pattern, wherein as the first and second hammer head is not Mukaiawa respectively, alternately arranged in the direction side portions face each other direction and the end portion face each other Has been
The first hammerhead has a constant size and a constant interval;
The exposure mask according to claim 1, wherein the second hammer head has the same size and the same interval as the first hammer head . 3. An exposure mask according to claim 2 , wherein the fixed interval between the first and second hammerheads is substantially equal to the fixed size of the first and second hammerheads. 3. The exposure mask according to claim 2 , wherein the constant interval between the first and second hammer heads is larger than the constant size of the first and second hammer heads.

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