JP4115264B2 - Delay device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a delay device, and more particularly, to a delay device that can add a new acoustic effect that has not existed before.
[0002]
[Prior art]
Conventionally, various sound effect devices for adding a sound effect to a musical tone signal such as an electronic musical instrument have been proposed. Among these devices, for example, there is a delay device. The delay device is a sound effect device for obtaining a delay signal of an input musical sound signal, and is called a so-called delay machine.
[0003]
  For example, in the performance of an electric guitar, there is a performance method in which a delay effect is added to a musical sound signal generated by string operation, and a repeated acoustic effect is added by superimposing the delayed musical sound on the performance. The delay device is used as an effect device when performing such a performance method. With this acoustic effect, a specific part of the performance can be emphasized or impressed.
[0004]
  As a conventional delay device, for example, delay means for delaying input data input in time series, and data input to the delay means are sequentially read from data with a small delay amount toward data with a large delay amount. There is a delay device provided with a reading means (Patent Document 1).
[0005]
  According to this delay device, the tone signal input to the delay means is read by the reading means from the tone signal having a small delay amount toward the tone signal having a large delay amount, that is, in the reverse order of the input order. It is. Therefore, for example, when “Dremi” is played by an electric guitar, when a predetermined delay time elapses after the performance, a musical sound that is opposite in time to “Miredo” is generated and repetitive. A sound effect can be obtained.
[0006]
  Also, it is disclosed that the output data is fed back to the input side of the delay means. In that case, when a predetermined delay time elapses, "Miredoremiredo ..." A forward sound is generated alternately, and a repetitive sound effect can be obtained.
[0007]
[Patent Document 1]
JP-A-6-332488 (paragraph [0005], FIG. 1 and the like)
[0008]
[Problems to be solved by the invention]
By the way, a performer who enjoys the performance of an electric guitar or the like uses the acoustic effect of the delay device to change the performance in order to perform as per the image or perform in a unique form not found elsewhere. Therefore, the aspect of the acoustic effect that can be added by such a delay device plays an important role not less than that of the tone that is pronounced in terms of musical interest, and other types of aspects can be used. It is requested.
[0009]
  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a delay device that can add a new acoustic effect that has not existed before.
[0010]
[Means for Solving the Problems]
In order to achieve this object, the delay device according to claim 1 comprises:From outsideInput signal input in time seriesA pre-stage unit that inputs and delays, and a post-stage unit that inputs and delays a signal delayed by the pre-stage unit.OutputThe front stage is theFirst delay means for delaying input signals and outputting in reverse order of input orderShi,The subsequent stage unit adds an output signal from the first delay unit and a signal output from the subsequent stage unit, and adds the signal added by the addition unit.Second delay means for delaying and outputting in the same order as the input order;The signal output from the second delay means is output to the outside.
  The delay device according to claim 2, comprising a front-stage unit for inputting and delaying an input signal input in time series from the outside, and a rear-stage unit for inputting and delaying a signal delayed by the front-stage unit, The signal delayed by the subsequent stage unit is output to the outside, and the previous stage unit adds the input signal and the signal output from the previous stage unit, and the signal added by the addition unit And a second delay means for delaying the signals output from the second delay means and outputting them in the reverse order of the input order. The signal output from the first delay means is output to the outside..
[0011]
  According to the delay device according to claim 1,OutsideInput signal from theFront partInput to the first delay means, and the input signal is delayed by the first delay means in the reverse order of the input order.First stageOutput from therearArranged in a rowLatter partIs input to the department.
[0012]
  In the rear stage, the signal output from the front stage and the feedback signal fed back from the rear stage are added. Added by the arithmetic means, and the added signal is sent by the second delay means.In the same order as the input order while being delayedLatter partIs output as an output signal from the unit to the outside.Further, the signal output from the subsequent stage is fed back to the adding means.
[0013]
  Here, for example, when the input signal from the outside to the preceding stage is the musical tone signal “Doremi”, the musical tone signal “Doremi” is delayed in the reverse order while being delayed by the first delay means.First stageOutput from theLatter partThe musical tone signal “Miredo” is input to the section.
[0014]
  Latter partWhen the music signal “Miredo” is input to theFirstWhile being delayed by the two delay means, the musical tone signal “Miredo” is output to the outside in the same order.
[0015]
  Furthermore,Latter partWhen the music signal “Miredo” is output from theIt is added to the signal output from the first delay unit by the adding means,The musical tone signal “Miredo” is output to the outside by the second delay means described above. as a result,Latter partThe musical tone signal “Miredomiredomired ...” is repeatedly output to the outside from the unit.
[0016]
  on the other hand,According to the delay device of claim 2, the outsideInput signal from theFirst, the input signal and the delayed and fed back signal are added by the adding means. next,The added signal is sent by the second delay means.LateThe output is output in the same order as the input order.The output signal is input to the subsequent stage and fed back to the adding means.
[0017]
  Latter partWhen the input signal is input to the unit, the first delay means delays the input signal and reverses the input order.OutsideIs output as an output signal to the unit.
[0018]
  Here, for example, from the outsideofIf the input signal is a musical tone signal “Doremi”,OutsideFrom the departmentFirst stageThe musical sound signal “doremi” input to the part is output in the same order while being delayed by the second delay means,Latter partThe musical sound signal “Doremi” is input to the section. Also,Latter partThe musical sound signal “Doremi” output from theThe signal is added to the signal input from the outside by the adding means and input to the second delay means.Therefore, the tone signal “Doremi” is transmitted by the second delay means described above.Latter partIt is output repeatedly to the part.
[0019]
  Latter partWhen the musical tone signal “Doremi” is input to the section, the musical tone signal “Doremi” is output to the outside in the reverse order as the musical tone signal “Miredo” while being delayed by the first delay means. as a result,Latter partThe musical tone signal “Miredomiredomired ...” is repeatedly output to the outside from the unit.
[0020]
  Claim3The delay device according to claim 1.Or 2In the delay device described above,First2 delay meansMultiplying means for multiplying the output signal output from the signal by a coefficient and outputting the multiplied signal to the adding means is provided.
[0021]
  Claim4The delay device described isFrom outsideThe input signal input in time series is delayed and output.Addition means for adding the feedback signal delayed and fed back and the input signal, storage means for sequentially storing the signals added by the addition means, and signals stored in the storage meansRead out in the reverse order of the input order.OutsideFirst reading means for outputting;Signal stored in the storage meansRead in the same order as the input orderSecond reading means for returning a signal as the feedback signal to the adding meansAnd.
[0022]
  This claim4According to the delay device described,The feedback signal read out by the second reading means described later and fed back and the input signal are added by the adding means, and the signals added by the adding means are sequentially stored in the storage means. The signal stored in the storage means is the firstIt is read in the reverse order of the input order by the reading means,OutsideIs output. Also,The second reading means stores Signal stored in the meansRead in the same order as the input orderThe signal is fed back to the adding means as a feedback signal.
[0023]
  Here, for example, from the outsideInput external input signalIs the musical tone signal “Doremi”, the musical tone signal “Doremi”The signal read by the second reading means is added by the adding means, and sequentially stored in the storage means. AndThe first reading means reads the data in the reverse order of the input order and outputs the musical sound signal “Miredo” to the outside. Furthermore,Stored in the storage meansThe tone signal “Doremi” is read by the second reading means in the same order as the input order, and added to the input signal input from the outside by the adding means.
[0024]
  AdditionThe musical tone signal “Doremi”Stored in the storage means again,By the first reading means described aboveRead out,It is output to the outside as a musical tone signal “Miredo”.SoAs a result, the musical tone signal “Miredomiredomired ...” is repeatedly output to the outside with delay.
[0025]
  Claim5The delay device as claimed in claim42. The delay device according to claim 1, wherein the second reading meansMultiplication means for multiplying the signal read from the coefficient by the coefficient and outputting the multiplied signal to the addition means.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a front view of a delay device 1 according to a first embodiment of the present invention.
[0027]
  The delay device 1 is a sound effect device that adds a delay effect to a musical sound signal such as an electronic musical instrument. In this embodiment, the input signal is delayed and output in the reverse order of the input order, and the output signal in the reverse order. Can be output repeatedly. As shown in FIG. 1, the delay device 1 is formed in a box-like body having a substantially rectangular shape when viewed from the front, and a plurality of knob operators 2 to 4 and a pedal operator 5 are respectively provided on the upper and lower portions thereof. The input and output jacks 6 and 7 are disposed on both side portions.
[0028]
  A knob operator (hereinafter referred to as “feedback setting knob”) 2 is an operator for setting a feedback parameter value, and a knob operator (hereinafter referred to as “delay time setting knob”) 3 is provided. This is a control for setting the parameter value of the delay time. These feedback and delay time setting knobs 2 and 3 are configured as variable resistors, and their resistance values are varied according to the amount of rotation operation.
[0029]
  That is, the parameter values of feedback and delay time are associated in advance with the magnitude of the resistance value of each variable resistor, and the CPU 12 (see FIG. 2) to be described later reads the resistance value indicated by each variable resistance value. Each parameter value is calculated based on the read resistance value. The CPU 12 transmits the calculated parameter value to a DSP 14 (see FIG. 2), which will be described later, and the DSP 14 performs digital signal processing such as delay on the musical sound signal in accordance with the received parameter value. Details of this signal processing will be described later.
[0030]
  Here, the feedback setting knob 2 of the present embodiment is configured so that the feedback parameter value can be set in the range of “0 to 120” by the rotation operation from the MIN display position to the MAX display position shown in FIG. The minimum unit that can be set is “0.25”. This parameter value represents the feedback amount to the input (feedback amount). For example, if the parameter value is “50”, the output is reduced to a level of 50% and fed back to the input, and if “110”, the output is amplified to a level of 110% and fed back to the input.
[0031]
  The parameter value “0” means that the feedback amount is 0%, and feedback to the input is not performed (no feedback). The parameter value “100” means that the feedback amount is 100%, and the output is fed back to the input with the level unchanged.
[0032]
  On the other hand, the delay time setting knob 3 of the present embodiment is configured so that the parameter value of the delay time can be set in the range of “0 to 5000” by the rotation operation from the MIN display position to the MAX display position shown in FIG. The smallest settable unit is “1”. This parameter value represents a so-called delay time. For example, if the parameter value is “500”, it means that the delay time is 500 ms, and the same sound is output 500 ms after a predetermined sound is input.
[0033]
  A knob operator (hereinafter referred to as “mode setting knob”) 4 is an operator for setting the operation mode of the delay device 1. This mode setting knob 4 is constituted by a so-called changeover switch of a two-position selection type, and the operation mode of the delay device 1 can be switched between the normal mode and the reverse mode according to the operation position.
[0034]
  The normal mode is a mode in which the input signals input to the delay device 1 are delayed and output in the same order as the input order, and the output signals in the same order are repeatedly output. For example, when the musical tone signal “Doremi” is input, the musical tone signal “Doremi” is repeatedly delayed and output after the delay time set by the delay time setting knob 3 described above has elapsed.
[0035]
  On the other hand, the reverse mode is a mode in which the input signals input to the delay device 1 are delayed and output in the reverse order of the input order, and the output signals in the reverse order are repeatedly output. For example, when a musical sound signal “Doremi” is input, these input signals are repeated in the reverse order, and are delayed and output as a musical sound signal “Mired Milled Milled ...”.
[0036]
  The musical tone signal “Miredo Mired Mired...” Is output while its output level gradually decreases (or increases) in accordance with the feedback amount set by the feedback setting knob 2 described above.
[0037]
  Here, the normal mode can be achieved by a known configuration. Therefore, in the following description, the description regarding the configuration in the normal mode is omitted, and the reverse mode will be mainly described.
[0038]
  The pedal operator 5 is an operator for switching whether to input an input signal from the outside (input jack 6 described later) to a delay line 23 (see FIG. 3) described later in the reverse mode. Each time the part is pressed, the on / off state can be switched alternately. That is, when the pedal operator 5 is turned “on”, input to the delay line 23 is permitted. When the pedal operator 5 is turned off, input to the delay line 23 is prohibited.
[0039]
  The prohibition of input to the delay line 23 here means that the acoustic effect in the reverse mode is not added to the input signal. Therefore, even when the pedal operator 5 is “off”, the input signal input from the input jack 6 is output as it is from an output jack 7 described later without adding an acoustic effect. .
[0040]
  The pedal operator 5 also plays a role of resetting a temporal start position when an acoustic effect is added to the input signal. That is, in the reverse mode, the addition of the acoustic effect to the input signal is started based on the timing at which the pedal operator 5 is operated from “off” to “on”.
[0041]
  The input jack 6 is a connection part for inputting an input signal to the delay device 1, and is connected to a plug of a cable extending from an electronic musical instrument or the like as an input signal source. The output jack 7 is a connection unit for outputting an output signal from the delay device 1, and the cable connected to the output jack 7 is connected to a speaker device or the like as an output signal destination.
[0042]
  The input jack 6 also serves as a power switch for the delay device 1. That is, when a plug is connected to the input jack 6, the delay device 1 is powered on, and execution of various processes by the CPU 12 and the like is started (see FIGS. 5 and 6). On the other hand, when the plug is removed from the input jack 6, the power supply of the delay device 1 is cut off.
[0043]
  Next, the electrical configuration of the delay device 1 will be described with reference to FIG. FIG. 2 is a block diagram showing an electrical configuration of the delay device 1.
[0044]
  The delay device 1 mainly includes a UI 11 as a user interface unit, a CPU 12 as an arithmetic unit, a DSP 14 as a digital signal processing unit, and a RAM 15 that stores various data in a rewritable manner when executing the processing of the DSP 14. It is installed.
[0045]
  The UI 11 is provided with the knob operators 2 to 4 and the pedal operator 5 described above, and various parameter values and operation mode setting operations are performed by the operator. As shown in FIG. 2, the UI 11 is connected to the CPU 12, and when the various operators 2 to 5 of the UI 11 are operated, the operation state is detected by the CPU 12.
[0046]
  The CPU 12 is an arithmetic device for controlling the operation of the entire delay device 1. The CPU 12 is connected to the UI 11 and the DSP 14, respectively, acquires parameter values and operation modes set by the UI 11, and executes processing such as controlling the operation of the DSP 14 based on the acquired contents.
[0047]
  The CPU 12 includes a ROM that stores the control program of the flowchart shown in FIG. 5 and a RAM that stores various data in a rewritable manner when the control program is executed. However, the ROM and RAM may be provided outside the CPU 12.
[0048]
  The ADC 13 is an analog-digital converter for sampling an analog signal and converting it into a digital signal. The ADC 13 converts the analog signal input from the above-described input jack 6 ("IN" display side in FIG. 2) into a digital signal. Output to the DSP 14. In this embodiment, the sampling frequency is 44.1 kHz.
[0049]
  The DSP 14 is a digital signal processor for adding an acoustic effect (signal processing) to the digital signal input from the ADC 13 based on an instruction from the CPU 12. The DSP 14 converts the digital signal (musical sound signal) input from the ADC 13. A sound effect such as delay or reverse delay is added and output to the DAC 16 described later.
[0050]
  The DSP 14 includes a ROM that stores the control program of the flowchart shown in FIG. 6 and a RAM that stores various data in a rewritable manner when the control program is executed. However, the ROM and RAM may be provided outside the DSP 14. For example, instead of the RAM here, a RAM 15 described later may be used.
[0051]
  As shown in FIG. 2, a RAM 15 is connected to the DSP 14. The RAM 15 is a memory that stores a digital signal in a rewritable manner. The DSP 14 writes the digital signal input from the ADC 13 into the RAM 15 and reads out the written digital signal from the RAM 15 to perform signal processing on the digital signal and add an acoustic effect.
[0052]
  Note that the digital signal is written to the RAM 15 at an address indicated by the write pointer W, and the digital signal is read from the RAM 15 from an address indicated by two types of read pointers RP1 and RP2 that travel in opposite directions. (See FIG. 4). Details of the digital signal writing / reading method will be described later.
[0053]
  The DAC 16 is a digital-analog converter for converting a digital signal into an analog signal, converts the digital signal input from the DSP 14 into an analog signal, and outputs the output jack 7 (see “OUT” display side in FIG. 2). ). This output signal is emitted to the outside as a musical sound signal through an external amplifier and a speaker (not shown).
[0054]
  FIG. 3 is a flowchart showing the flow of signal processing in the DSP 14 and the RAM 15.
[0055]
  The adders 21a and 21b are arithmetic units that add and output a plurality of input signals. The adders 21a and 21b output the upstream side (FIG. 3 “IN” display side) and the downstream side (FIG. 3 “ OUT ”display side), respectively.
[0056]
  That is, the adder 21 a adds an input signal from the input jack 6 (“IN” display side in FIG. 3) and a feedback signal from a multiplier 22 described later, and outputs the result to the delay line 23. On the other hand, the adder 21b adds the input signal from the delay line 23 and the input signal directly input from the input jack 6 ("IN" display side in FIG. 3) to output the output jack 7 ("OUT" in FIG. 3). Output to the display side).
[0057]
  The multiplier 22 is an arithmetic unit that multiplies an input signal by a predetermined multiplication coefficient (feedback coefficient) and outputs the result, and multiplies an input signal from a delay line 23 described later by a feedback coefficient and outputs the result to the adder 21a. . Here, the feedback coefficient means a parameter value (“0 to 120”) set by the above-described feedback setting knob 2 (see FIG. 1). For example, if the set parameter value (feedback coefficient) is “50”, the input signal from the delay line 23 is reduced to a level of 50% and output to the adder 21a.
[0058]
  The delay line 23 is a buffer in which an area is secured in the above-described RAM 15 (see FIG. 2), and an input signal from the adder 21a is sequentially written at an address position indicated by the write pointer W (see FIG. 4).
[0059]
  As will be described later, the delay line 23 is provided with two types of read pointers, a reverse read pointer RP1 and a normal read pointer RP2, and a signal read from the address position indicated by the reverse read pointer RP1. Is output to the adder 21b, and a signal read from the address position indicated by the normal read pointer RP2 is output to the multiplier 22. Here, a detailed configuration of the delay line 23 will be described with reference to FIG.
[0060]
  FIG. 4 is a schematic diagram schematically showing the configuration of the delay line 23. In FIG. 4, arrow A represents the traveling direction of the reverse read pointer RP1, and arrow B represents the traveling direction of the normal read pointer RP2 and the write pointer W.
[0061]
  The address START represents the head address that is the start position of the delay line 23, and the address END represents the end address that is the end position of the delay line 23. Note that the delay line 23 of this embodiment is configured as a so-called ring buffer in which an address START and an address END are connected.
[0062]
  Therefore, for example, when the write pointer W is advanced from the address END by the address “1” in the direction of arrow B, the write pointer W points to the address START, and for example, the reverse read pointer RP1 is changed from the address START. When the head is advanced in the direction of arrow A by “1” addresses, the reverse read pointer RP1 points to the address END.
[0063]
  Since the concept of the ring buffer is a well-known matter, the description thereof will be omitted in the description of flowcharts (FIGS. 5 and 6) described later.
[0064]
  The write pointer W is a write pointer for indicating a write address position when writing an input signal to the delay line 23. The DSP 14 (see FIG. 2) advances the write pointer W in the direction of arrow B by “1” address every sampling period (44.1 kHz in this embodiment), and delays from the adder 21a (see FIG. 3). The input signal input to the line 23 is sequentially written in each address position indicated by the write pointer W.
[0065]
  The reverse read pointer RP1 and the normal read pointer RP2 are read pointers for indicating an address position when a signal is read from the delay line 23.
[0066]
  The reverse read pointer RP1 is advanced in the direction of arrow A by “1” address every sampling period, that is, in the direction opposite to the direction of writing the input signal by the write pointer W (direction of arrow B), and the DSP 14 (FIG. 2). (See) sequentially reads out signals from each address position indicated by the reverse read pointer RP1, and outputs the read signals to the adder 21b (see FIG. 3).
[0067]
  The read position by the reverse read pointer RP1 is reset to the latest write position by the write pointer W every time the delay time set by the delay time setting knob 3 (see FIG. 1) described above elapses. The process proceeds in the direction of arrow A until the next reset.
[0068]
  Therefore, from the position indicated by the reverse read pointer RP1, the signals written by the write pointer W are read out in the reverse order of the writing order. As a result, the delay line 23 sends the signal to the adder 21b (see FIG. 3). An output signal that is reverse in time to the input order of the input signals input to the delay line 23 is repeatedly output for each delay time.
[0069]
  On the other hand, the normal read pointer RP2 is advanced by “1” addresses every sampling period in the same direction as the direction of writing of the input signal by the write pointer W (arrow B direction), and the DSP 14 (see FIG. 2) Signals are sequentially read from each address position indicated by the read pointer RP2, and the read signals are output to the multiplier 22 (see FIG. 3).
[0070]
  Here, the converted delay time value DT shown in FIG. 4 is written to the delay line 23 by the write pointer W until the delay time set by the delay time setting knob 3 (see FIG. 1) described above elapses. This means an address converted value of the area occupied by the signal. As shown in FIG. 4, the normal read pointer RP2 is an address position behind (in the direction of the arrow B) behind the write pointer W by this delay time converted value DT. Pointing.
[0071]
  Therefore, the signal after the “delay time” has elapsed since writing by the write pointer W is read from the address position indicated by the normal read pointer RP2, and as a result, the multiplier 22 (see FIG. 3) is read from the delay line 23. ), The input signal input to the delay line 23 is output after being delayed by the “delay time”.
[0072]
  Next, processing executed by the delay device 1 configured as described above will be described with reference to the flowcharts of FIGS. 5 and 6. In the description of each flowchart, the description will be given with reference to FIGS. 1 to 4 as appropriate.
[0073]
  Here, in the above description, “W (write pointer)” and “RP1, RP2 (reverse and normal read pointer)” are used as symbols representing the pointers themselves. In the following description, these symbols are used. Is also used as a symbol representing a register. Each register is provided in both the CPU 12 and the DSP 14 and stores an address value indicated by each pointer.
[0074]
  Similarly, DT (delay time conversion value) and START (address) are also used as symbols representing registers. Each register stores the address conversion value and the head address value of the delay line 23 described above.
[0075]
  Further, a turn register TRN is provided as a register in the CPU 12 and the DSP 14. The turn register TRN is a register for storing a read end address position (that is, an address position serving as a reference for resetting) when resetting the reverse read pointer RP1 that is reset every delay time. When the value of the turn register TRN and the value of the reverse read pointer RP1 are compared and a certain condition is satisfied, the reverse read pointer RP1 is reset (that is, the value of the register is rewritten).
[0076]
  Further, in the explanation of each flowchart shown in FIG. 5 and FIG. 6, the address of the delay line 23 (see FIG. 4) is set to “0, 1, 2,. "Address" is represented by an integer value of "0 to n". Therefore, an integer value of “0 to n” is stored in each register.
[0077]
  FIG. 5 is a flowchart showing main processing executed by the CPU 12. This process is started when the delay device 1 is turned on, and is repeatedly executed by the CPU 12 while the power is turned on, and the parameter values set by the feedback and delay time setting knobs 2 and 3 described above. Is mainly performed, and is transmitted to the DSP 14.
[0078]
  Regarding the main process, the CPU 12 first executes an initialization process to initialize each value of the built-in RAM, registers, input / output ports, etc., and further the RAM 15 in which a delay line area is secured (S1). The initial value of the write pointer W is set to the value of the start address (address START) that is the start position of the delay line 23 (W = START), and the initial value of the reverse read pointer RP1 is set to the write pointer W. The value of the address is set to be “1” smaller than (the direction of arrow A in FIG. 4) (RP1 = W−1).
[0079]
  After executing the initialization process, the CPU 12 detects each operation state of the feedback and delay time setting knobs 2 and 3 (see FIG. 1), and each of the feedback and delay times set by the setting knobs 2 and 3 is detected. Read the parameter value. Then, the read parameter values are transmitted to the DSP 14 (S2). The DSP 14 performs digital signal processing such as delay on the musical tone signal based on the transferred parameter values (for example, S24 in FIG. 6).
[0080]
  Next, the CPU 12 determines whether or not this process is the first process after activation (S3). If it is the first process (S3: Yes), the values of the normal read pointer RP2 and the turn register TRN are determined. Are set, and each set value is transmitted to the DSP 14 (S4).
[0081]
  Specifically, as described above, the address position to which the value of the normal read pointer RP2 should point is more than the address position pointed to by the write pointer W by the delay time set by the delay time setting knob 3 (see FIG. 1). Since it must be a time delayed value (see FIG. 4), the value of the normal read pointer RP2 is a value obtained by converting the time delay (delay time) into an address amount, that is, a delay time converted value DT. A value obtained by subtracting the value of か ら from the value of the write pointer W is set (RP2 = W−DT).
[0082]
  Further, the value of the normal read pointer RP2 is set as the value of the turn register TRN (TRN = RP2). As described above, the value of the turn register TRN is an address value serving as a reference when resetting the reverse read pointer RP1, and more specifically, the reverse read pointer RP1 is obtained from the address value indicated by the value of the turn register TRN. Is also reset after proceeding to the address position smaller by “1” (arrow A direction side in FIG. 4) (see S27 and S28 in FIG. 6).
[0083]
  As a result, the time during which the signal input to the delay line 23 is read out and output in reverse order from the address position indicated by the value of the reverse read pointer RP1 during reset, and the address indicated by the value of the normal read pointer RP2 described above. It is possible to make the time from reading from the position to delaying the output to be approximately equal.
[0084]
  Thus, in the present embodiment, the reset interval of the reverse read pointer RP1 and the delay time of the normal read pointer RP2 can be set simultaneously by operating one delay time setting knob 3 (see FIG. 1). As a result, since both can be varied with a correlation between them (reset interval and delay time), an effective presentation can be achieved in terms of musical interest.
[0085]
  However, it is naturally possible to set both (reset interval and delay time) independently of each other. In this case, two independent setting knobs are provided, and in the process of S4, the value of the normal read pointer RP2 is set based on the parameter value set by one setting knob, and based on the other parameter value. The value of the turn register TRN may be set. Thereby, the variation of the acoustic effect by the delay apparatus 1 can be expanded more.
[0086]
  In the process of S3, when this process is not the first process after activation (S3: No), the process of S4 has already been executed, and the setting of the values of the normal read pointer RP2 and the turn register TRN is completed. Therefore, the process of S4 is skipped and the process proceeds to S5.
[0087]
  In the processing after S5, the CPU 12 first detects the operation state of the mode setting knob 4 (see FIG. 1) and reads the currently set operation mode (S5). Then, it is determined whether or not the read operation mode is the reverse mode (S6).
[0088]
  As a result, when it is determined that the currently set operation mode is not the reverse mode, that is, the currently set operation mode is the normal mode (S6: No), the processing after S7 is executed. Instead, the process proceeds to S2. Although omitted in FIG. 5, in this case, the normal mode process is executed before the process shifts to S2.
[0089]
  On the other hand, when it is determined that the currently set operation mode is the reverse mode (S6: Yes), the operating state of the pedal operator 5 (see FIG. 1) is detected, and the pedal operator 5 It is determined whether or not the switch has been switched from "off" to "on" (S7).
[0090]
  As described above, the pedal operator 5 switches whether or not an input signal from the outside (input jack 6) is input to the delay line 23 (see FIG. 3), and at the time of adding an acoustic effect to the input signal. It also plays the role of resetting the time starting position.
[0091]
  Therefore, in the process of S7, when it is determined that the pedal operator 5 has been switched from "off" to "on" (S7: Yes), first, in order to reset the temporal start position of the acoustic effect, The values of the reverse read pointer RP1 and the turn register TRN are set, and the set values are transmitted to the DSP 14 (S8). Next, in order to input the input signal to the delay line 23, the input signal from the outside is input. After permitting (S9), the process proceeds to S2.
[0092]
  Specifically, in the process of S8, the reverse read pointer RP1 is set to an address value (one in the direction of arrow A in FIG. 4) smaller than the write pointer W (RP1 = W-1), and the turn The value of the normal read pointer RP2 at this time is set in the register TRN (TRN = RP2).
[0093]
  As a result, the reverse read pointer RP1 as a pointer (see FIG. 4) is input to the delay line 23 for each delay time set by the delay time setting knob 3 from the timing when the pedal operator 5 is “ON”. The operation of reading the input signals to the address position indicated by the value of the turn register TRN in the reverse order of the input order (in the direction of arrow A in FIG. 4) is repeatedly executed.
[0094]
  On the other hand, if it is determined in step S7 that the pedal operator 5 has not been switched from “OFF” to “ON” (S7: No), the pedal operator 5 then “ It is determined whether or not “ON” is switched to “OFF” (S10). As a result of the determination, if it is determined that the pedal operator 5 is switched from “ON” to “OFF” (S10: Yes), the pedal operator 5 blocks the input signal input to the delay line 23. Therefore, input of an input signal from the outside to the delay line 23 is prohibited (S11), and the process proceeds to S2.
[0095]
  As a result, no input signal is input to the delay line 23, and generation of a new musical sound signal to which an acoustic effect such as a delay is added is interrupted. However, since the signal processing by the DSP 14 is continuously executed for the input signal input to the delay line 23 until the pedal operator 5 is turned off (see FIG. 6), the pedal operator 5 Is switched from “on” to “off”, the output of the tone signal to which the sound effect such as the delay is added is not interrupted suddenly.
[0096]
  On the other hand, as a result of the determination in the process of S10, when it is determined that the pedal operator 5 has not been switched from "ON" to "OFF" (S10: No), the pedal operator 5 is not operated. Since the “ON” or “OFF” state is maintained, the process proceeds to the process of S2 without performing the process of switching the input state to the delay line 23 (S9, S11).
[0097]
  FIG. 6 is a flowchart showing signal write / read processing with respect to the delay line 23 executed by the DSP 14. This process is started when the delay device 1 is turned on, and is repeatedly executed by the DSP 14 every sampling period (44.1 kHz in this embodiment) while the power is turned on. Based on the various parameter values and the like, processing for performing signal processing such as delay on the input signal input to the delay line 23 is performed.
[0098]
  Regarding this processing, the DSP 14 first writes an input signal at the address position indicated by the value of the write pointer W (S21), and then adds “1” to the value of the write pointer W (W = W + 1, S22). As a result, the write pointer W as a pointer is advanced by “1” addresses in the direction of arrow B (see FIG. 4).
[0099]
  The input signal written by the write pointer W is multiplied by the output signal from the adder 21a (see FIG. 3), that is, the signal input to the adder 21a from the input jack 6 (“IN” side in FIG. 3). This is a signal obtained by adding the signal input from the device 22 to the adder 21a (see FIG. 3).
[0100]
  In the process of S23, the DSP 14 first reads the input signal written at the address position indicated by the value of the normal read pointer RP2 from the delay line 23, and outputs the read signal to the multiplier 22 (see FIG. 3). After that (S23), the value of the normal read pointer RP2 is updated (S24). The signal output from the delay line 23 to the multiplier 22 is multiplied by the feedback parameter value (feedback coefficient) set by the feedback setting knob 2 by the multiplier 22, and then output to the adder 21a. (See FIG. 3).
[0101]
  The value of the normal read pointer RP2 is updated by subtracting the delay time converted value DT from the value of the write pointer W (RP2 = W−DT). As a result, the normal read pointer RP2 as a pointer is disposed at an address position (on the opposite arrow B side in FIG. 4) that is smaller than the write pointer W by the delay time converted value DT (see FIG. 4), and the delay time. Even when the setting knob 3 is operated during performance and the delay time is changed, the delay output reflecting the changed delay time can be performed.
[0102]
  In the process of S25, the DSP 14 first reads the input signal written at the address position indicated by the value of the reverse read pointer RP1 from the delay line 23, and outputs the read signal to the adder 21b (see FIG. 3). After that, the value of the reverse read pointer RP1 is updated (S26). The signal output from the delay line 23 to the adder 21b is added to the signal input directly from the input jack 6 ("IN" side in FIG. 3) in the adder 21b, and the signal after the addition is sent to the outside. Is output from the output jack 7 ("OUT" side in FIG. 3) (see FIG. 3).
[0103]
  The value of the reverse read pointer RP1 is updated by subtracting “1” from the value of the reverse read pointer RP1 (RP1 = RP1-1). As a result, the reverse read pointer RP1 as a pointer is advanced by the amount of “1” address in the direction of arrow A, that is, in the direction opposite to the direction of writing the input signal by the write pointer W (direction of arrow B). (See FIG. 4).
[0104]
  After updating the value of the reverse read pointer RP1 (S27), the DSP 14 determines whether or not the updated value of the reverse read pointer RP1 is smaller than the value of the turn register TRN (S27).
[0105]
  As described above, the value of the normal read pointer RP2 immediately after power-on or the value of the normal read pointer RP2 at the time of resetting the value of the reverse read pointer RP1 is stored in the value of the turn register TRN (FIG. 5). Of S4 and S8).
[0106]
  Therefore, in the process of S27, when it is determined that the value of the reverse read pointer RP1 is smaller than the value of the turn register TRN (S27: Yes), the reverse read pointer RP1 as a pointer is set by the delay time setting knob 3. Since the progress in the arrow A direction (see FIG. 4) by the set delay time has been completed, the values of the reverse read pointer RP1 and the turn register TRN are reset in order to reset the values of the reverse read pointer RP1. Is updated (S28), and this process is terminated.
[0107]
  Specifically, in the process of S28, the reverse read pointer RP1 is set with an address value (RP1 = W-1) smaller than the write pointer W by “1” (arrow A direction side in FIG. 4), and the turn The value of the normal read pointer RP2 at this time is set in the register TRN (TRN = RP2).
[0108]
  As a result, the reverse read pointer RP1 as a pointer is reset, and the reverse read pointer RP1 advances in the direction of arrow A (see FIG. 4) during the delay time set by the delay time setting knob 3. Is updated (ie, the value of the turn register TRN).
[0109]
  On the other hand, if it is determined in S27 that the value of the reverse read pointer RP1 is greater than or equal to the value of the turn register TRN (S27: No), the reverse read pointer RP1 as a pointer is a delay time setting knob. This means that the progress in the arrow A direction (see FIG. 4) by the delay time set by 3 has not yet been completed, so there is no need to reset the reverse read pointer RP1. Therefore, in this case (S27: No), this process is terminated without executing the process of S28.
[0110]
  Thus, according to the delay device 1 of the first embodiment, the delay time setting knob 3 outputs the output signal read from the reverse read pointer RP1 in the reverse order of the input order inputted to the delay line 23. Can be repeatedly output to the adder 21b every time the delay time set by the above has elapsed, and the input signals input to the delay line 23 are read from the normal read pointer RP2 in the same order as the input order. The output signal can be delayed and output to the multiplier 22 after the delay time set by the delay time setting knob 3 has elapsed (see FIG. 3).
[0111]
  As shown in FIG. 3, the signal output from the delay line 23 (normal read pointer RP2) to the multiplier 22 is output to the adder 21a after being multiplied by the feedback coefficient described above. The adder 21 a adds the input signal from the outside and then feeds back to the input of the delay line 23. On the other hand, the signal output from the delay line 23 (reverse read pointer RP1) to the adder 21b is added to the signal directly input from the outside in the adder 21b as shown in FIG. It is output to the outside as a signal.
[0112]
  As a result, the input signals input to the delay device 1 are directly output to the outside, read out in the reverse order of the input order, output to the outside, and further read out in the same order as the input order. Since only the signal is delayed and fed back to the input, the delay device 1 delays and outputs the input signal in the reverse order of the input order, and repeatedly outputs the output signal in the reverse order.
[0113]
  Thus, for example, when the musical sound signal “Doremi” is sequentially input to the delay device 1, the musical sound signal “Mired Milled Mired ...” that is in the reverse direction in time is followed by the musical sound signal “Doremi” that is output directly. "Is repeatedly output in a delayed manner, so that it is possible to produce an unprecedented new sound effect, and as a result, it is possible to improve the musical interest.
[0114]
  In the flowchart of FIG.4As the storage means described,Delay line 23 isThe process of S25 corresponds to the first reading means, and the process of S23 corresponds to the second reading means.
[0115]
  Next, the second and third embodiments will be described with reference to FIGS. 7 (a) and 7 (b). In the first embodiment, the delay device 1 is constituted by one delay line 23. However, the delay devices 101 and 201 of the second and third embodiments have two delays of a reverse delay line 111 and a normal delay line 112. It is configured by combining lines. In addition, the same code | symbol is attached | subjected to the part same as the above-mentioned 1st Example, and the description is abbreviate | omitted.
[0116]
  First, the delay device 101 of the second embodiment will be described with reference to FIG. The delay device 101 according to the second embodiment is configured such that the reverse delay line 111 is arranged at a front stage where an external input signal is inputted, and the normal delay line 112 is arranged at a rear stage which outputs an output signal to the outside. Yes.
[0117]
  FIG. 7A is a flowchart showing a signal processing flow executed by the DSP 14 and the RAM 15 in the second embodiment.
[0118]
  The reverse delay line 111 is a buffer in which an area is secured in the RAM 15 (see FIG. 2), and is provided with a write pointer and a reverse read pointer. The write pointer is a pointer that advances by incrementing the address by “1” every sampling period (44.1 kHz in the present embodiment).
[0119]
  On the other hand, the reverse read pointer is a pointer that advances by decreasing the address by “1” for each sampling period, and similarly to the reverse read pointer RP1 in the first embodiment described above, the delay time setting knob 3 (see FIG. 1). ) Is reset to the address position where the latest input signal is written by the write pointer at every delay time set by (1).
[0120]
  The reverse delay line 111 writes an input signal from the input jack 6 ("IN" display side in FIG. 7A) to an address position indicated by the write pointer, and an address position indicated by the reverse read pointer. And output to adders 121a and 121b described later. As a result, in the reverse delay line 111, the input signals are read out in the reverse order of the input order and delayed for each delay time.
[0121]
  Note that the reverse delay line 111 corresponds to the preceding stage described in claim 1, and the “delay and output the input signals in the reverse order of the input order” described here corresponds to the first delay means.
[0122]
  The normal delay line 112 is a buffer in which an area is secured in the RAM 15 (see FIG. 2), and is provided with a write pointer and a normal read pointer. Like the reverse delay line 111, the write pointer is a pointer that advances by incrementing the address by “1” for each sampling period.
[0123]
  As with the write pointer, the normal read pointer is a pointer that progresses by incrementing the address by “1” every sampling period. Like the normal read pointer RP2 in the first embodiment described above, the delay time setting knob 3 The area that is occupied by the signal written by the write pointer until the delay time set by (see FIG. 1) elapses is arranged on the rear side in the traveling direction of the write pointer (that is, the address value is smaller). The
[0124]
  The normal delay line 112 writes an input signal from an adder 121a, which will be described later, into an address position indicated by the write pointer, and reads the written input signal from an address position indicated by the normal read pointer, and sends it to an adder 121b, which will be described later. Output. As a result, in the normal delay line 112, after the delay time elapses, the input signals are read out in the same order as the input order and are delayed and output.
[0125]
  The second delay means described in claim 1 corresponds to the processing described herein “reading input signals in the same order as the input order and outputting them in a delayed manner”.
[0126]
  The reverse delay line 111 and the normal delay line 112 are configured as so-called ring buffers, like the delay line 23 in the first embodiment. The adders 121a, 121b, and 221a to 221c have the same configuration as the adders 21a and 21b in the first embodiment, and a description thereof is omitted.
[0127]
  According to the delay device 101 configured as described above, as shown in FIG. 7A, an input signal input from the input jack 6 (FIG. 7A “IN” display side) is input to the adder 121b. Via the output jack 7 ("OUT" side in Fig. 7 (a)), and is input to the reverse delay line 111 and output in the reverse order of the input order.
[0128]
  The output signal output from the reverse delay line 111 is output from the output jack 7 (“OUT” side in FIG. 7 (a)) via the adder 121b to the outside, and the adder 121a performs multiplication described later. The signal is added to the output signal output from the device 22 and input to the normal delay line 112, where it is delayed and output in the same order as the input order.
[0129]
[0130]
  The output signal output from the normal delay line 112 is input to the adder 121b from the input jack 6 ("IN" display side in FIG. 7A) and the output output from the reverse delay line 111. The signal is added to the signal and output from the output jack 7 (“OUT” side in FIG. 7A) to the outside and output to the multiplier 22.
[0131]
  The output signal output from the normal delay line 112 to the multiplier 22 is multiplied by the feedback parameter value (feedback coefficient) set by the feedback setting knob 2 (see FIG. 1), and then output to the adder 121a. . The adder 121 a adds the output signal from the reverse delay line 111 and then feeds back to the input of the normal delay line 112.
[0132]
  In addition, claim 1Latter partas,UpThe adder 121a and the normal delay line 112 described above are applicable.The adding means according to claim 1 corresponds to the adder 121a.
[0133]
  As a result, the input signal input to the delay device 101 is directly output to the outside, read out in the reverse order to the input order, and output to the outside from the reverse delay line 111, and further reverse to the input order. Therefore, the delay device 101 delays and outputs the input signal in the reverse order of the input order, and the output signal in the reverse order is output from the delay device 101. Output repeatedly.
[0134]
  Therefore, for example, when the musical sound signal “Doremi” is sequentially input to the delay device 101, the musical sound in the reverse direction in time follows the musical sound signal “Doremi” that is directly output, as in the first embodiment. Since the signal “Miredo Mired Mired...” Is repeatedly output in a delayed manner, it is possible to produce a new acoustic effect that has never existed before, and as a result, it is possible to improve musical interest.
[0135]
  Next, the delay device 201 of the third embodiment will be described with reference to FIG. The delay device 201 of the third embodiment is configured such that the normal delay line 112 is arranged at a front stage where an external input signal is inputted and the reverse delay line 111 is arranged at a rear stage which outputs an output signal to the outside. Yes.
[0136]
  FIG. 7B is a flowchart showing the flow of signal processing executed by the DSP 14 and the RAM 15 in the third embodiment. In addition, the same code | symbol is attached | subjected to the part same as above-mentioned 2nd Example, and the description is abbreviate | omitted.
[0137]
  According to the delay device 201, the input signal input from the input jack 6 (FIG. 7B “IN” display side) is directly input via the adder 221 c to the output jack 7 (FIG. 7B “ OUT ”side) and is input to the reverse delay line 111 via the adder 221b, and is delayed and output in the reverse order of the input order. Further, the input signal from the input jack 6 is input to the normal delay line 112 via the adder 221a, and delayed and output in the same order as the input order.
[0138]
[0139]
  The output signal output from the normal delay line 112 is output to the multiplier 22 and is added to the input signal from the input jack 6 (“IN” display side in FIG. 7B) in the adder 221b. And output to the reverse delay line 111.
[0140]
  The output signal output from the normal delay line 112 to the multiplier 22 is multiplied by the feedback parameter value (feedback coefficient) set by the feedback setting knob 2 (see FIG. 1), and then output to the adder 221a. . In the adder 221a, the signal is added to the input signal from the input jack 6 ("IN" display side in FIG. 7B) and then fed back to the input of the normal delay line 112.
[0141]
  Claims2DescribedFirst stageAs part,AdditionApplicable to calculator 221a, normal delay line 112, etc.The subsequent stage corresponds to the reverse delay line 111 or the like that executes a process of reading and delaying in the reverse order of the input order.
[0142]
  The output signal output from the reverse delay line 111 is added by the adder 221c with the input signal from the above-described input jack 6 (FIG. 7 (b) “IN” display side) and output jack 7 (FIG. 7 ( b) Output to the outside from the “OUT” side).
[0143]
  As a result, the input signal input to the delay device 201 is directly output to the outside, read out in the same order as the input order, repeatedly output to the reverse delay line 111, and the output is read out in the reverse order. Therefore, the delay device 201 delays and outputs the input signals in the reverse order of the input order, and repeatedly outputs the output signals in the reverse order.
[0144]
  Therefore, for example, when the musical tone signal “Doremi” is sequentially input to the delay device 201, the musical tone of the reverse direction is temporally subsequent to the directly outputted musical tone signal “Doremi”, as in the first embodiment. Since the signal “Miredo Mired Mired...” Is repeatedly output in a delayed manner, it is possible to produce a new acoustic effect that has never existed before, and as a result, it is possible to improve musical interest.
[0145]
  The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be easily made without departing from the spirit of the present invention. It can be guessed.
[0146]
  For example, in the delay devices 1, 101, and 201 in each of the above embodiments, when power is turned on, signal reading by the reverse and normal read pointers (reverse and normal read pointers RP1 and RP2) is executed immediately after that. Instead of this, the reverse and normal read pointers (reverse and normal read pointers) are used until the first cycle of the delay time set by the delay time setting knob 3 elapses after the power is turned on. The DSP 14 may be configured to perform a mute process such as stopping reading of signals by the read pointers RP1 and RP2) or stopping (or masking) output of the read signals.
[0147]
  As a result, it is possible to suppress the occurrence of unnecessary noise (noise) caused by reading a signal from an area where no signal is written by the write pointer (write pointer W).
[0148]
  In addition, the delay devices 1, 101, and 201 in the above embodiments receive the input signal input from the input jack 6 (FIG. 3 and FIG. 7 "IN" display side) and output jack 7 ((FIGS. 3 and 7). A route (hereinafter referred to as “direct line”) for direct output from the “OUT” display side) is provided.This direct line always functions effectively in each of the above embodiments. Although configured, switching means for invalidating the function of the direct line may be provided.
[0149]
  For example, when a switch of “on / off” switching type is arranged on the UI 11 (see FIG. 2) as the user interface unit and this switch is “on” by the operator, the direct line is activated, As in the above-described embodiments, the input signal input from the input jack 6 is directly output to the outside from the output jack 7, while the direct line is invalidated when the switch is turned off by the operator. Thus, the direct output to the outside is prohibited. Thereby, the variation of the acoustic effect by delay device 1,101,201 can be expanded more.
[0150]
  In the delay device 1 in the first embodiment, the value of the normal read pointer RP2 at the time when the reverse read pointer RP1 is reset is stored in the turn register TRN (see S8 in FIG. 5 and S28 in FIG. 6). The determination as to whether or not to reset the reverse read pointer RP1 is made based on the value of the turn register TRN (see S27 in FIG. 6), but the determination is not necessarily limited to this. Of course, it is possible to adopt other methods.
[0151]
  For example, when the reverse read pointer RP1 is reset, the value of the write pointer W at that time (that is, the time S8 in FIG. 5 and the time S28 in FIG. 6) is stored in the register W0 ( (W0 = W), the determination in S27 of FIG. 6 (that is, determination of whether or not to reset the reverse read pointer RP1) is a value obtained by subtracting the delay time converted value DT from the value of the register W0 (W0−DT). You may comprise so that it may perform as a reference | standard.
[0152]
  Accordingly, whether or not to reset the reverse read pointer RP1 is determined based on the set value (delay time) by the delay time setting knob 3 for each sampling period in which the flowchart of FIG. 6 is executed. Therefore, for example, even when the delay time setting knob 3 is operated during performance and the set value (delay time) is changed, the changed set value (delay time) is more accurately and quickly set in the reverse read pointer RP1. This can be reflected in the reset process (S27 in FIG. 6).
[0153]
  In the delay devices 1, 101, and 201 in the above-described embodiment, when the reverse read pointer RP1 is reset when the pedal operator 5 is "ON" or when the delay time elapses, the reset reverse read pointer RP1 is reset. The DSP 14 is configured to output all the signals read out in accordance with the above, that is, to output the signals read out immediately after the reset. However, the present invention is not necessarily limited to this. The DSP 14 may be configured to execute the mute process only.
[0154]
  Specifically, when the reverse read pointer RP1 is reset, reading of the signal by the reverse read pointer RP1 is stopped or read only for a predetermined time (for example, approximately 1/441 seconds) including the reset time. The DSP 14 is configured to stop (or mask) the output of the received signal.
[0155]
  As a result, even if the read position changes suddenly or the continuity of the read signal is interrupted due to the reset of the reverse read pointer RP1, the problem caused by the mute processing for a certain period is alleviated and unnecessary. Generation of noise or the like can be suppressed in advance.
[0156]
  Further, in the delay devices 1, 101, and 201 in each of the above-described embodiments, a normal delay effect (normally) in which a musical tone signal “Dremidremidemi ...” is repeatedly output to the outside with respect to an input signal of the musical tone signal “Doremi”. Mode) and the reverse delay effect (reverse mode) that repeatedly outputs to the outside as a tone signal “Miredo Mired mired ...” can be switched by the mode setting knob 4, but in addition to this, other The effect (mode) may be switched.
[0157]
  For example, the reverse delay effect disclosed in Patent Document 1 described above, that is, a delay effect (first effect) in which a tone signal “Miredo Remi Mired ...” is repeatedly output to the outside in response to an input signal of a tone signal “Dremi” (first). (Mode 3) may be switchable. Thereby, the variation of the acoustic effect by delay device 1,101,201 can be expanded more, and the improvement of musical interest can be aimed at.
[0158]
【The invention's effect】
According to the delay device of claim 1,First stageDepartmentFrom outsideA first delay means for delaying the input signal and outputting it in the reverse order of the input order;Latter partDepartmentOutput from the first delay meansSignal andThe signal output from the subsequent stage is added by the adding means and input to the second delay means. The second delay means delays the signal and outputs it in the same order as the input order. The signal output from the second delay means is output to the outside and fed back to the adding means. Therefore,There is an effect that the inputted input signals can be output in the reverse order of the input order, and the output can be repeated.
  According to the delay device of the second aspect, the pre-stage unit adds the input signal and the signal output from the pre-stage unit, and delays the signal added by the addition unit to make the input order the same. Second delay means for outputting in order, and the latter stage section has first delay means for delaying the signals output from the second delay means and outputting them in the reverse order of the input order, and output from the first delay means. The signal is output to the outside. Therefore, there is an effect that the input signals inputted in the same manner as in the first aspect can be outputted in the reverse order of the input order and the output can be repeated.
[0159]
  For example, when the input signal is a tone signal “Doremi”, the input signal can be repeatedly delayed and output to the outside as a tone signal “Miredo Milled Milled ...” that is reverse in time. A new acoustic effect can be added to the performance and the like, and as a result, the musical interest can be improved.
[0160]
  Claim3According to the described delay device, claim 1.Or 2In addition to the effect of the described delay device,Multiplier means for multiplying the signal output from the second delay means by a coefficient and outputting the multiplied signal to the adder means.Therefore, there is an effect that an output signal obtained by reversing the input signal in terms of time can be repeatedly delayed and output while gradually decreasing (or increasing) its output level. The variation of the acoustic effect by the apparatus can be further expanded.
[0161]
  Claim4According to the delay device described,The feedback signal read and fed back by the second reading means described later and the input signal are added by the adding means, and the signals added by the adding means are sequentially stored in the storage means. The signal stored in the storage means is the firstIt is read in the reverse order of the input order by the reading means,OutsideIs output. Also,The second reading means is a signal stored in the storage means.Read in the same order as the input orderThe read signal is fed back to the adding means as a feedback signal. Therefore,There is an effect that the inputted input signals can be output in the reverse order of the input order, and the output can be repeated.
[0162]
  For example, when the input signal is a tone signal “Doremi”, the input signal can be repeatedly delayed and output to the outside as a tone signal “Miredo Milled Milled ...” that is reverse in time. A new acoustic effect can be added to the performance and the like, and as a result, the musical interest can be improved.
[0163]
  Claim5According to the described delay device, the claim4In addition to the effect of the described delay device,Multiplying means for multiplying the signal read by the second reading means by a coefficient and outputting the multiplied signal to the adding meansTherefore, there is an effect that an output signal obtained by reversing the input signal in terms of time can be repeatedly delayed and output while gradually decreasing (or increasing) its output level. The variation of the acoustic effect by the apparatus can be further expanded.
[Brief description of the drawings]
FIG. 1 is a front view of a delay device according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing an electrical configuration of the delay device.
FIG. 3 is a flowchart showing a flow of signal processing in a DSP and a RAM.
FIG. 4 is a schematic diagram schematically showing a configuration of a delay line.
FIG. 5 is a flowchart showing main processing executed by a CPU.
FIG. 6 is a flowchart showing signal write / read processing for a delay line executed by the DSP;
7A is a flowchart showing the flow of signal processing executed by the DSP and RAM in the second embodiment, and FIG. 7B is a flow chart of signal processing executed by the DSP and RAM in the third embodiment. It is a flowchart showing a flow.
[Explanation of symbols]
1,101,201 delay device
2 Feedback setting knob
3 Delay time setting knob
4 Mode setting knob
5 Pedal operator
6 Input jack
7 Output jack
21a,121a,221a Adder (Addition means)
22 Multiplier (Multiplication means)
23 Delay line (Memorymeans)
111 Reverse delay line (first delay means)
112 Normal delay line (second delay means)
RP1 Reverse read pointer (part of the first reading means)
RP2 normal read pointer (part of second reading means)
W Light pointer

Claims (5)

A front-stage unit that inputs and delays an input signal that is input in time series from the outside, and a rear-stage unit that inputs and delays a signal delayed by the front-stage unit. In the delay device that outputs to the outside ,
The front portion may have a first delay means for outputting the reverse input order delaying the input signal,
The subsequent stage unit adds an output signal from the first delay unit and a signal output from the subsequent stage unit, delays the signal added by the addition unit, and outputs the delayed signal in the input order. And a second delay means for outputting the signal output from the second delay means to the outside . A front-stage unit that inputs and delays an input signal that is input in time series from the outside, and a rear-stage unit that inputs and delays a signal delayed by the front-stage unit. In the delay device that outputs to the outside,
The preceding stage has an adding means for adding the input signal and the signal output from the preceding stage, and a second delay means for delaying the signal added by the adding means and outputting the same in the input order. And
The latter stage section includes first delay means for delaying the signal output from the second delay means and outputting the signal in the reverse order of the input order, and outputting the signal output from the first delay means to the outside. Feature delay device. 3. The delay device according to claim 1 , further comprising a multiplying unit that multiplies the signal output from the second delay unit by a coefficient and outputs the multiplied signal to the adding unit . In a delay device that delays and outputs an input signal input in time series from the outside ,
An adding means for adding the feedback signal delayed and fed back to the input signal;
Storage means for sequentially storing signals added by the addition means;
First reading means for reading the signals stored in the storage means in the reverse order of the input order and outputting them to the outside ;
A delay device comprising: second reading means for reading the signals stored in the storage means in the same order as the input order, and feeding the signals back to the adding means as the feedback signal . 5. The delay device according to claim 4 , further comprising a multiplying unit that multiplies the signal read from the second reading unit by a coefficient and outputs the multiplied signal to the adding unit .

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