JP4120280B2 - Circuit synthesis apparatus and circuit synthesis method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit synthesis device and a circuit synthesis method having a plurality of radio signal processing circuits having a radio signal transmission / reception function, and in particular, to a circuit synthesis device that synthesizes a plurality of radio signal processing circuits and executes data processing, and The present invention relates to a circuit synthesis method.
[0002]
[Prior art]
Recently, with the increase in scale and capacity of LSIs (large scale integrated circuits) and the increase in data processing speed, the number of LSI lead pins has increased, and the interval between lead frames has become extremely narrow inside LSIs. The connection technology with the lead frame, etc., requires an extremely advanced technology.
[0003]
For this reason, conventionally, a semiconductor device capable of configuring an LSI with an extremely small number of terminals and reducing the manufacturing cost and miniaturization of the LSI has been disclosed in Japanese Patent Application Laid-Open No. 2000-60130 (hereinafter, a conventional example). 1).
[0004]
In the semiconductor device described in the conventional example 1, an antenna and a wireless transmission / reception function circuit are mounted on the semiconductor element unit, and between the semiconductor element unit such as a CPU (central processing unit) and the semiconductor element unit such as a memory and each controller. Communication or information exchange is performed wirelessly by radio waves, and each semiconductor element portion can be identified from each other by providing an identification bit (address) at the beginning of the signal or by providing an individual frequency. it can. As a result, the lead frame of the signal terminal of the semiconductor element portion can be eliminated, and the structure can be configured with an extremely small number of terminals.
[0005]
By the way, in a manufactured LSI, there is a case where it is desired to reconfigure a circuit depending on the processing contents. An example of such an LSI is an FPGA (Field Programmable Gate Array). The FPGA is an rewritable integrated circuit after wiring (after completion of the product). For example, the circuit design is changed by a designer and reconfigured depending on a product trial stage of a mobile phone or the like, or a use application of the product. It is possible.
[0006]
[Problems to be solved by the invention]
However, in the case of a reconfigurable device using a wired LSI such as an FPGA, it is necessary to calculate the amount of delay by the designer when reconfiguring the LSI, and to design in consideration of this. Yes, it is difficult to reconfigure the LSI alone. Furthermore, in the FPGA, when a circuit is reconstructed, a new function cannot be newly added, and there is a problem that the circuit design must be performed using only an integrated circuit having a predetermined function.
[0007]
Further, in the technique described in the above-described conventional example 1, the exchange of data between the semiconductor elements is exchanged by wireless signals instead of wired, and the whole semiconductor system can be simplified and reduced in size. Is assigned a predetermined frequency in advance or a predetermined address is assigned, and transmits / receives data having the determined frequency or address to perform the determined process. There is a problem that it is difficult to add a new function and reconfigure an LSI once configured.
[0008]
The present invention has been proposed in view of such a conventional situation, and a circuit synthesizer capable of easily adding a circuit having a new function and automatically reconfiguring a plurality of circuits as required. An object of the present invention is to provide a circuit synthesis method.
[0009]
[Means for Solving the Problems]
In order to achieve the above-described object, a circuit synthesis device according to the present invention has a plurality of radio signal processing circuits arranged in a shielded space and provided with a radio signal transmission / reception means, and the radio signal processing circuit includes: A first wireless signal processing circuit having a means for communicating with the outside of the space, and a plurality of second wireless signal processing circuits controlled by the first wireless signal processing circuit. The signal processing circuit includes the plurality of second radio signal processing circuits. Processing of the second radio signal processing circuit by sending a command signal to the mobile station and returning the circuit content of the second radio signal processing circuit Based on the detection means for detecting the function and the program supplied from the outside via the communication means based on the detection result of the detection means The above for executing the program Control means for individually controlling a plurality of second radio signal processing circuits The plurality of second radio signal processing circuits execute processing in accordance with an instruction included in a control signal transmitted by the first radio signal processing circuit according to the program. It is characterized by that.
[0010]
In the present invention, since the first wireless signal processing circuit detects and controls the function of the second wireless signal processing circuit, the second wireless signal is automatically generated when a program supplied from the outside is processed. A processing circuit is synthesized. Further, the functions of all the second radio signal processing circuits in which the first radio signal processing circuits are arranged in the shield space can be grasped, and even when the second radio signal processing circuit is newly added, the function can be quickly obtained. The function can be grasped.
[0011]
The control means of the first radio signal processing circuit is configured to execute a function of the second radio signal processing circuit for executing the program based on a function detection result of the second radio signal processing circuit; It is possible to control transmission / reception of signals between the first radio signal processing circuit and the second radio signal processing circuit and between the second radio signal processing circuits, thereby supplying a new program. Each time, the first radio signal processing circuit can automatically recombine and synthesize the circuit composed of the second radio signal processing circuit group.
[0012]
Further, the plurality of second radio signal processing circuits receive a control signal from the first radio signal processing circuit via the transmission / reception means, and execute the program based on the control signal. Can do.
[0013]
Furthermore, the control signal can individually set an input frequency for reception and an output frequency for transmission with respect to the second radio signal processing circuit. Since the exchange of data is performed by radio signals of individually set frequencies, the processing order processed by the second radio signal processing circuit can be freely changed by changing the frequency set by the first radio signal processing circuit. Can be changed.
[0014]
The first radio signal processing circuit can transmit a control signal having a preset frequency that can be received by all the plurality of second radio signal processing circuits at all times. Reconstruction is possible.
[0015]
Further, the control means can assign one or more input and output frequencies to each of the second radio signal processing circuits, and can transmit an internal code for executing processing for each input frequency or output frequency. A plurality of processes can be executed by one second radio frequency processing circuit due to the difference in input frequency.
[0016]
The circuit synthesis method according to the present invention includes a plurality of radio signal processing circuits arranged in a shielded space and provided with radio signal transmission / reception means, and a first radio signal having communication means with the outside of the space. A wireless signal processing circuit combining method for combining the plurality of wireless signal processing circuits comprising a processing circuit and a plurality of second wireless signal processing circuits controlled by the first wireless signal processing circuit, The first radio signal processing circuit is the plurality of second radio signal processing circuits. Processing of the second radio signal processing circuit by sending a command signal to the mobile station and returning the circuit content of the second radio signal processing circuit In accordance with a detection step for detecting a function, and a program supplied from the outside by the first wireless signal processing circuit using the function detection result of the second wireless signal processing circuit via the communication means For executing the program A control step for individually controlling the plurality of second radio signal processing circuits. The plurality of second radio signal processing circuits execute processing in accordance with an instruction included in a control signal transmitted by the first radio signal processing circuit according to the program. It is characterized by that.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. This embodiment is applied to a circuit synthesizing apparatus in which a plurality of circuits are synthesized by a command by a radio signal and a given problem can be solved.
[0018]
As shown in FIG. 1, in the circuit synthesis device 1 according to the present embodiment, a plurality of integrated circuits having a radio signal transmission / reception function are installed on a substrate (not shown) in a space 3 shielded by a housing 2. It has been done. The housing 2 is made of, for example, metal or the like, and is formed so that radio waves in the housing 2 that is the shield space 3 do not leak outside the housing, and radio waves outside the housing 2 do not enter the housing. . The plurality of integrated circuits include a host integrated circuit (first wireless signal processing circuit) ICA capable of communicating with the outside, and a plurality of integrated circuits (second wireless signal processing) controlled by the host integrated circuit ICA. Circuit) ICBn (ICB1 to ICBn).
[0019]
Such a circuit synthesis device 1 is formed by housing an integrated circuit ICA and an integrated circuit ICBn having a wireless transmission / reception function (communication means) in a housing 2 having a shielded space 3 that does not leak radio waves to the outside. Is done. In the present embodiment, only one host integrated circuit ICA is prepared. The host integrated circuit ICA uses the detection means (not shown) for detecting the function of the integrated circuit ICBn and the integrated circuit ICBn according to a program supplied from the outside via the communication means using the detection result of the detection means. Control means (not shown) for individually controlling are provided. The control means controls the function of the integrated circuit ICBn for executing the program and the transmission / reception of signals between the host integrated circuit ICA and the integrated circuit ICBn and between the integrated circuits ICBn based on the function detection result of the detecting means. To do.
[0020]
Further, the integrated circuit ICBn has processing functions different from each other such as a function having an addition, multiplication, or division function, or a function combining these functions. The host integrated circuit ICA controls the function of the integrated circuit ICBn so that the integrated circuit ICBn performs a predetermined process according to the program, and controls the transmission / reception of the integrated circuit ICBn so that data is transmitted to the predetermined integrated circuit. The program is controlled to be transmitted to ICBn, and the program is executed.
[0021]
Communication between each integrated circuit between the host integrated circuit ICA and the integrated circuit ICBn or between the integrated circuits ICBn is performed by radio signals having different frequencies, for example. Due to the difference in frequency, communication can be performed without interfering with other integrated circuits. It is also possible to set addresses individually in the integrated circuit ICBn and exchange them by radio signals to which this address information is added.
[0022]
The detection means of the host integrated circuit ICA detects the functions of all the integrated circuits ICBn existing in the shield space 3 by broadcasting, and creates a list of usable integrated circuits ICBn.
[0023]
Further, when a problem (program) to be solved is supplied via the communication means, the control means of the host integrated circuit ICA uses a usable integrated circuit ICBn group detected by the detection means to solve the problem. Compile and convert to internal code. That is, the host integrated circuit ICA self-creates a procedure and method for solving a given problem by using the available integrated circuit ICBn group. Specifically, the contents of processing performed in each integrated circuit ICBn are individually determined, and in accordance with the input order of data processed in each integrated circuit ICBn so that the processing is performed according to the created internal code, An input frequency and an output frequency are individually set for each integrated circuit ICBn. Here, the input frequency and output frequency set in each integrated circuit ICBn are not limited to one, and a plurality of input frequencies and output frequencies can be set. The integrated circuit ICBn in which a plurality of frequencies are set is different in input frequency or output frequency. Depending on the difference, the processing performed in the integrated circuit ICBn can be varied. The host integrated circuit ICA transmits the internal code and input / output frequency information as control signals to each integrated circuit ICBn.
[0024]
When the host integrated circuit ICA transmits a control signal to the integrated circuit ICBn, identification information such as a preset address that identifies each integrated circuit ICBn is added to the control signal, and each of the integrated circuits ICB1 to ICBn is added. Control signals can be individually transmitted. The frequency for transmitting the control signal is preferably a frequency that can be received by all the integrated circuits ICBn for the control signal, and is transmitted using the frequency for the control signal. Further, instead of an address, an input frequency may be designated in advance for each integrated circuit ICBn. In this case, a control signal can be individually transmitted to each integrated circuit ICBn by an input frequency serving as an address. .
[0025]
Further, when synthesizing the problem solving method, optimization may be performed by determining the frequency based on the amount of information flowing through the communication circuit.
[0026]
Each integrated circuit ICBn executes a problem according to an internal code (instruction) included in the control signal. That is, since an input / output frequency is set for each integrated circuit ICBn, a radio signal having a specific frequency is received only by the specific integrated circuit ICB. The specific integrated circuit ICB performs predetermined processing on the received radio signal in accordance with the internal code, converts the processed data into an output frequency set by the control signal, and outputs the result. The output frequency is received by the integrated circuit ICB set as the input frequency, and the program is executed by repeating the same processing.
[0027]
FIG. 2 is a block diagram showing an integrated circuit ICBn provided in the shield space in the wireless circuit synthesis device of the present embodiment. As shown in FIG. 2, the integrated circuit ICBn includes a wireless transmission / reception unit 11 that can transmit and receive a plurality of frequencies, a command storage memory 12 that stores control signals (commands) from the host integrated circuit ICA, and data that processes data. And a processing unit 13. The radio transmission / reception unit 11 processes the radio signal received at the set input frequency by the antenna unit 14 for transmitting / receiving a radio signal by the data processing unit 13 and then converts the radio signal to the output frequency set by the control signal. Frequency conversion means (not shown). A plurality of such integrated circuits ICBn are prepared in the shield space.
[0028]
The host integrated circuit ICA has means for communicating with the outside in addition to the configuration shown in FIG. The instruction storage memory stores a program supplied via communication means with the outside, and the data processing unit performs a conversion process (compile) for converting the program supplied from the outside into an internal code.
[0029]
Next, the operation of the present embodiment will be described. FIG. 3 is a flowchart showing the operation of the present embodiment. First, the host integrated circuit ICA confirms the presence of the integrated circuit ICBn in the shield space 3 and diagnoses what function these integrated circuits ICBn have. Diagnosis is performed by transmitting a radio signal of a predetermined frequency used exclusively by the host integrated circuit ICA and returning the circuit contents from each integrated circuit ICBn. The host integrated circuit ICA transmits a command signal, receives a radio signal sent back from the integrated circuit ICBn, and repeatedly grasps the circuit contents, thereby obtaining information on all the integrated circuits ICBn in the shield space 3. it can.
[0030]
Next, as shown in FIG. 3, an instruction code (program code) is input to the host integrated circuit ICA from a user or an external device connected to the host integrated circuit ICA (step S1). Then, the host integrated circuit ICA uses each integrated circuit ICBn existing in its own shield space 3 which is self-diagnosed and grasped in advance by the host integrated circuit ICA using the method described above. Compile into internal code that can be solved (step S2). Then, the internal code as a compilation result is transmitted from the host integrated circuit ICA to each integrated circuit ICBn as a control signal, for example, by a radio signal having a frequency dedicated to the instruction, and the instruction is assigned to each integrated circuit ICBn (step S3). ). As shown in FIG. 4, the control signal supplied from the host integrated circuit ICA to each integrated circuit ICBn includes the input frequency, the output frequency, and the processing contents in the data processing unit 13 of each integrated circuit ICBn. Each integrated circuit ICBn receives this control signal and stores it in the instruction storage memory 12. Each integrated circuit ICBn always detects a radio signal having an input frequency set by a control signal from the host integrated circuit ICA, and immediately performs a specified process when there is an input, at a specified output frequency. Output (step S4). Then, the program is executed by repeating a series of operations.
[0031]
According to the present embodiment, since the host integrated circuit ICA has a function of detecting the function of the integrated circuit ICBn, each function of the integrated circuit ICBn arranged in the space 3 can be grasped, and from the outside. When the program is supplied, it can be compiled into internal code so that the program can be executed using the functions of the integrated circuit ICBn, and based on this, a control signal can be transmitted to the integrated circuit ICBn. That is, each time a control signal is transmitted, the circuit group composed of each integrated circuit ICBn can be automatically reconstructed. Further, since the integrated circuits ICA and ICBn communicate with each other by radio signals, it is possible to execute processing without worrying about delay and timing due to communication. In addition, since all the integrated circuits ICBn are configured to be capable of parallel operation, processing is performed in a pipeline manner, so that the processing speed is increased.
[0032]
When there are a plurality of instructions to each integrated circuit ICBn, the host integrated circuit ICA shall monitor a plurality of frequencies. Furthermore, when it is desired to improve the processing speed, an integrated circuit similar to the integrated circuit ICBn is newly added in the shield space 3, the self-diagnosis result by the host integrated circuit ICA is updated, and then compiled, Pipeline processing is performed, and the performance of the wireless circuit synthesis device is improved.
[0033]
Further, if the function is insufficient only by the integrated circuit ICBn provided in the space 3 in order to execute the supplied program, the function that the host integrated circuit ICA lacks for the user or the like May be requested. Even when there is such a request or when it is desired to add a new function, there is no need to wire between the integrated circuits ICA and ICBn because they communicate wirelessly, and there is no need to place a new circuit in the shield space. Reconstruction is possible. The new integrated circuit ICB may have its own address in advance, or the host integrated circuit ICA may set an address for the new integrated circuit ICB or set a predetermined input frequency. It may be.
[0034]
Next, a specific example of this embodiment will be described. Here, as a problem to be solved to the host integrated circuit ICA of the wireless circuit synthesis device in the present embodiment,
(A + B) × C ÷ D + E
The case where the formula shown in FIG.
[0035]
In this specific example, it is assumed that at least an integrated circuit ICBn that functions as an adder, a multiplier, and a divider is disposed in the shield space 3.
[0036]
First, the host integrated circuit ICA grasps the function of each integrated circuit ICBn by using a command frequency for each integrated circuit ICBn in the shield space 3. Then, when the equation shown by (A + B) × C ÷ D + E is given by the user or the like, the integrated circuits ICB1 to ICB3 functioning as an adder, a multiplier, and a divider are extracted in order to solve this problem. . Next, compilation is performed so that the above problem can be solved by the integrated circuits ICB1 to ICB3 functioning as an adder, a multiplier, and a divider, and the result of the compilation is given to each of the integrated circuits ICB1 to ICB3 as a control signal. An example of a control signal (command) given in this specific example is shown in FIG. As described above, each of the integrated circuits ICB1 to ICB3 has identification information such as an address for identifying the integrated circuits ICB1 to ICB3, and receives a control signal having its own identification information.
[0037]
FIGS. 5A to 5C show instructions given to the integrated circuits ICB1 to ICB3, which are an adder, a multiplier, and a divider, respectively, and each row shows an input frequency, an output frequency, and a processing content. In this specific example, for the adder, there are two commands whose input frequencies are frequencies 01 and 02.
[0038]
FIG. 6 is a flowchart showing the operation of the adder when the command shown in FIG. As shown in FIG. 6, the integrated circuit functioning as an adder is in a standby state until it receives radio signals (commands) of frequencies 01 and 04 (step S10). When an instruction with frequencies 01 and 04 is received, an addition operation is started and data after conversion is returned at a specified frequency.
[0039]
Specifically, first, it is determined whether or not the received command is a radio signal having a frequency 01 (step S11). If the received command is the frequency 01, the first data is added to the 0th data. Is rewritten to 0th (step S12). Next, according to the command shown in FIG. 5, that is, according to the command that the signal input at frequency 01 is output at frequency 02, the data rewritten at step S12 is output as a radio signal at output frequency 02 (step S13).
[0040]
On the other hand, if the command received in step S11 is not frequency 01, it is determined whether or not it is frequency 04 (step S14). If the frequency is 04, a value obtained by adding the fourth data to the zeroth data is rewritten to the zeroth (step S15). Next, according to the command shown in FIG. 5, that is, according to the command that the signal input at frequency 04 is output at frequency 05, the data rewritten at step S15 is output as a radio signal at output frequency 05 (step S16).
[0041]
FIG. 7 is a diagram schematically showing the flow of data processed by the wireless circuit synthesis device of this example. The host integrated circuit ICA to which the program code is given by the user compiles the program code into internal code that can be processed by the adder ICB1, the multiplier ICB2, and the divider ICB3 as described above, and the compiled result is the adder ICB1. After the notification to the multiplier ICB2 and the divider ICB3, the host integrated circuit ICA transmits data (A | B | C | D | E) d1 having the frequency 01 to the adder ICB1. Here, the data (A | B | C | D | E) d1 input to the adder ICB1 at the frequency 01 is converted into the 0th input data (A) by the command from the host integrated circuit ICA shown in FIG. The first input data (B) is added, and the 0th overwrite process is performed. The data d1 is assigned with the input frequency as the frequency 01 and is received by the adder ICB1 in the reception waiting state. The instruction when the input frequency is 01, that is, as described above, adds the 0th and 1st data. The 0th overwrite process is executed. Then, the processed data is transmitted as data d2 having an output frequency 02. The data d2 is a data string represented by (A + B) | B | C | D | E.
[0042]
The data d2 of frequency 02 is received by the multiplier ICB2 in the reception waiting state. The multiplier ICB2 is instructed to multiply the second data (C) by the zeroth data (A + B) of the data d2 received at the frequency 02, and transmits the multiplied data d3 at the frequency 03. The data d3 is a data string represented by (A + B) × C | B | C | D | E.
[0043]
The data d3 of frequency 03 is received by the divider ICB3 in the reception waiting state. The divider ICB3 is instructed to divide the third data (D) by the 0th data ((A + B) × C) of the data d3 received at the frequency 03, and the divided data d4 at the frequency 04. Send. The data d4 is a data string represented by (A + B) × C ÷ D | B | C | D | E.
[0044]
The data d4 of frequency 04 is received again by the adder ICB1 in the reception waiting state. The adder ICB1 is instructed to add the fourth data (E) to the zeroth data ((A + B) × C ÷ D) of the data d4 received at the frequency 04, and uses the added data d5 as the frequency. Send in 05. The data d5 is a data string represented by (A + B) × C ÷ D + E | B | C | D | E.
[0045]
The final output (data d5 of frequency 05) obtained in this way is received by the host integrated circuit ICA, and the processing is completed. Note that the adder ICB1 may transmit only the 0th data, that is, only (A + B) × C ÷ D + E to the host ICA.
[0046]
【The invention's effect】
As described above in detail, the circuit synthesis device according to the present invention has a plurality of radio signal processing circuits arranged in a shielded space and provided with radio signal transmitting / receiving means, and the radio signal processing circuit is The first radio signal processing circuit includes a first radio signal processing circuit having communication means with the outside of the space and a plurality of second radio signal processing circuits controlled by the first radio signal processing circuit. The circuit is configured to detect the functions of the plurality of second radio signal processing circuits, and based on a program supplied from the outside via the communication unit using a detection result of the detection unit. Since the control means for individually controlling the second radio signal processing circuit is provided, the second radio signal processing circuit detects all functions of the second radio signal processing circuit and is arranged in the shield space. Wireless signal processing times The detection result can be used to compose a second wireless signal processing circuit group each time a program supplied from the outside is processed, thereby forming a synthesis circuit. Even when a second radio signal processing circuit is newly added, its function can be quickly grasped, and the first radio signal processing circuit can freely configure a circuit composed of the second radio signal processing circuit group. Can be automatically reconfigured.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing a circuit synthesis device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an integrated circuit constituting the circuit synthesis device according to the embodiment of the present invention.
FIG. 3 is a flowchart showing an operation of the circuit synthesis device according to the embodiment of the present invention.
FIG. 4 is a diagram illustrating a command signal output from a host integrated circuit of the circuit synthesis device according to the embodiment of the present invention.
FIG. 5 is a diagram showing a command signal of the circuit synthesis device in a specific example of the embodiment of the present invention.
FIG. 6 is a flowchart showing an operation of an adder constituting a part of the circuit synthesis device in a specific example of the embodiment of the present invention.
FIG. 7 is a schematic diagram showing the operation of the circuit synthesis device in the specific example of the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Composition circuit apparatus, 2 housing | casing, 3 shield space, 11 wireless transmission / reception part, 12 command memory, 13 data processing part, 14 antenna part, ICA host integrated circuit, ICB integrated circuit, ICB1 adder, ICB2 multiplier, ICB3 Divider

Claims (11)

A plurality of radio signal processing circuits arranged in a shielded space and provided with means for transmitting and receiving radio signals;
The wireless signal processing circuit includes a first wireless signal processing circuit having communication means with the outside of the space, and a plurality of second wireless signal processing circuits controlled by the first wireless signal processing circuit. ,
The first radio signal processing circuit sends a command signal to the plurality of second radio signal processing circuits to return the circuit contents of the second radio signal processing circuit, thereby returning the second radio signal processing circuit. And a plurality of second radio signal processing circuits for executing the program according to a program supplied from the outside via the communication unit based on a detection result of the detection unit the have a control means for controlling individually,
The circuit synthesizing apparatus, wherein the plurality of second radio signal processing circuits execute processing in accordance with an instruction included in a control signal transmitted by the first radio signal processing circuit according to the program . The control means of the first radio signal processing circuit includes a function of the second radio signal processing circuit for executing the program based on a function detection result of the second radio signal processing circuit, and the 2. The circuit synthesis apparatus according to claim 1, wherein transmission / reception of signals between the first radio signal processing circuit and the second radio signal processing circuit and between the second radio signal processing circuits is controlled. The plurality of second radio signal processing circuits receive a control signal from the first radio signal processing circuit via the transmission / reception means, and execute the program based on the control signal. The circuit synthesis device according to claim 1. 4. The circuit synthesis apparatus according to claim 3, wherein the second radio signal processing circuit has an input frequency for reception and an output frequency for transmission set individually by the control signal. 2. The circuit composition according to claim 1, wherein the first radio signal processing circuit transmits a control signal having a preset frequency that can be always received by all the plurality of second radio signal processing circuits. apparatus. The control means of the first radio signal processing circuit uses the detected function of the second radio signal processing circuit to convert the program into an internal code executable by the second radio signal processing circuit. Control signal generation for assigning the input frequency and output frequency individually to each of the conversion means for conversion and the second radio signal processing circuit, and generating a control signal including the assigned input frequency and output frequency and the internal code The circuit synthesis apparatus according to claim 4, further comprising: means and execution means for causing the second radio signal processing circuit to execute the program. The second radio signal processing circuit includes a storage unit that stores the control signal received via the transmission / reception unit, a processing unit that processes a radio signal having the input frequency based on the control signal, and the processing unit. The circuit synthesis device according to claim 4, further comprising: conversion means for converting data output from the wireless signal having the output frequency. The control means allocates one or more input frequencies and output frequencies for each of the second radio signal processing circuits, and transmits an internal code for executing processing for each of the input frequencies or output frequencies. The circuit synthesis apparatus according to claim 4. A first wireless signal processing circuit which is arranged in a shielded space and has a plurality of wireless signal processing circuits provided with wireless signal transmitting and receiving means, and which has means for communicating with the outside of the space; A wireless signal processing circuit combining method for combining the plurality of wireless signal processing circuits comprising a plurality of second wireless signal processing circuits controlled by the signal processing circuit,
The first radio signal processing circuit sends a command signal to the plurality of second radio signal processing circuits to send back the circuit contents of the second radio signal processing circuit, whereby the second radio signal processing circuit a detection step of detecting a processing function,
The plurality of second radio signals for causing the first radio signal processing circuit to execute the program according to a program supplied from the outside via the communication means using the function detection result of the second radio signal processing circuit It has a control step for individually controlling the radio signal processing circuit,
The circuit synthesizing method, wherein the plurality of second radio signal processing circuits execute processing according to an instruction included in a control signal transmitted by the first radio signal processing circuit according to the program . A plurality of radio signal processing circuits arranged in a shielded space and provided with means for transmitting and receiving radio signals;
The plurality of radio signal processing circuits include a first radio signal processing circuit and another second radio signal processing circuit controlled by the first radio signal processing circuit,
The first radio signal processing circuit stores a predetermined program for controlling the second radio signal processing circuit, and the plurality of second radio signals for executing the program according to the stored predetermined program. have a control means for controlling the second radio signal processing circuit,
The circuit synthesizing apparatus, wherein the plurality of second radio signal processing circuits execute processing in accordance with an instruction included in a control signal transmitted by the first radio signal processing circuit according to the program . A plurality of radio signal processing circuits arranged in a shielded space and provided with a radio signal transmitting and receiving means; a first radio signal processing circuit; and another first controlled by the first radio signal processing circuit A wireless signal processing circuit combining method for combining the plurality of wireless signal processing circuits comprising two wireless signal processing circuits,
The first radio signal processing circuit controls the plurality of second radio signal processing circuits for executing the program according to a predetermined program for controlling the second radio signal processing circuit stored in the storage means. have a control process,
The circuit synthesizing method, wherein the plurality of second radio signal processing circuits execute processing according to an instruction included in a control signal transmitted by the first radio signal processing circuit according to the program .

Images