JP4121263B2 - Compound semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a compound semiconductor device, and more particularly to a compound semiconductor device used in a high frequency band of 2.4 GHz band or higher.
[0002]
[Prior art]
In mobile communication devices such as cellular phones, microwaves in the GHz band are often used, and switching elements for switching these high-frequency signals are used in antenna switching circuits and transmission / reception switching circuits. In many cases (for example, JP-A-9-181642). As the element, a field effect transistor (hereinafter referred to as FET) using gallium arsenide (GaAs) is often used because it handles high frequency, and accordingly, the monolithic microwave integration in which the switch circuit itself is integrated. A circuit (MMIC) is being developed.
[0003]
A compound semiconductor device using GaAsFET will be described below by taking a switch circuit device as an example.
[0004]
FIG. 9A shows a cross-sectional view of a GaAs FET. An N-type channel region 2 is formed by doping an N-type impurity on the surface portion of the non-doped GaAs substrate 1, a gate electrode 3 in Schottky contact is disposed on the surface of the channel region 2, and both sides of the gate electrode 3 are disposed. The source / drain electrodes 4 and 5 are placed in ohmic contact with the GaAs surface. In this transistor, a depletion layer is formed in the channel region 2 immediately below by the potential of the gate electrode 3, thereby controlling the channel current between the source electrode 4 and the drain electrode 5.
[0005]
FIG. 9B shows an example of a principle circuit diagram of a compound semiconductor device called SPDT (Single Pole Double Throw) using GaAs FETs.
[0006]
The sources (or drains) of the first and second FET1 and FET2 are connected to the common input terminal IN, and the gates of the FET1 and FET2 are connected to the first and second control terminals Ctl-1, R1 and R2, respectively. This is connected to Ctl-2, and the drain (or source) of each FET is connected to the first and second output terminals OUT1 and OUT2. The signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET to which the H level signal is applied is turned ON, and the signal applied to the input terminal IN is selected. The signal is transmitted to one of the output terminals. The resistors R1 and R2 are arranged for the purpose of preventing leakage of a high-frequency signal through the gate electrode with respect to the DC potential of the control terminals Ctl-1 and Ctl-2 that are AC grounded.
[0007]
An equivalent circuit diagram of such a compound semiconductor device is shown in FIG. In the microwave, the characteristic impedance is 50Ω, and the impedance of each terminal is represented by R1 = R2 = R3 = 50Ω resistance. Further, assuming that the potential of each terminal is V1, V2, and V3, insertion loss and isolation are expressed by the following equations.
[0008]
Insertion Loss = 20log (V2 / V1) [dB]
This is an insertion loss when a signal is transmitted from the common input terminal IN to the output terminal OUT1,
Isolation = 20 log (V3 / V1) [dB]
This is an isolation between the common input terminal IN and the output terminal OUT2. In a compound semiconductor device, it is required to reduce the above insertion loss (Insertion Loss) as much as possible to improve isolation, and it is important to design an FET inserted in series in a signal path. The reason for using a GaAs FET as this FET is that GaAs has a higher electron mobility than Si, so that the resistance is low and the loss can be reduced. Since GaAs is a semi-insulating substrate, high isolation between signal paths is achieved. It is because it is suitable. On the other hand, the GaAs substrate is more expensive than Si, and if an equivalent such as a PIN diode can be made of Si, it will be lost in cost competition.
[0009]
FIG. 11 is a circuit diagram of a compound semiconductor device that has been put into practical use. In this circuit, shunt FET3 and FET4 are connected between the output terminals OUT1 and OUT2 of FET1 and FET2 to be switched and the ground, and control terminals Ctl-2 and Ctl- to FET2 and FET1 are connected to the gates of the shunt FET3 and FET4. 1 complementary signal is applied. As a result, when FET1 is ON, shunt FET4 is ON, and FET2 and shunt FET3 are OFF.
[0010]
In this circuit, when the signal path from the common input terminal IN to the output terminal OUT1 is turned on and the signal path from the common input terminal IN to the output terminal OUT2 is turned off, the shunt FET 4 is turned on, so that the input to the output terminal OUT2 Signal leakage escapes to ground through the grounded capacitor C, and isolation can be improved.
[0011]
FIG. 12 shows an example of a compound semiconductor chip in which such compound semiconductor devices are integrated.
[0012]
FET 1 and FET 2 for switching on the GaAs substrate are arranged in the left and right central portions, shunt FET 3 and shunt FET 4 are arranged in the vicinity of the left and right lower corners, and resistors R1, R2, R3, and R4 are connected to the gate electrodes of each FET. ing. Also, pads corresponding to the common input terminal IN, the output terminals OUT1 and OUT2, the control terminals Ctl-1, Ctl-2, and the ground terminal GND are provided around the substrate. Further, the source electrodes of the shunt FET 3 and the shunt FET 4 are connected to each other and connected to the ground terminal GND through a capacitor C for grounding. Note that the second-layer wiring indicated by the dotted line is a gate metal layer (Ti / Pt / Au) formed simultaneously with the formation of the gate electrode of each FET, and the third-layer wiring indicated by the solid line is each element. Is a pad metal layer (Ti / Pt / Au) for connection and pad formation. The ohmic metal layer (AuGe / Ni / Au) that comes into ohmic contact with the first layer substrate forms the source electrode, gate electrode, and extraction electrodes at both ends of each FET. In FIG. Not shown to overlap the layer.
[0013]
FIG. 13A shows an enlarged plan view of the portion of the FET 1 shown in FIG. In this figure, a rectangular region surrounded by a one-dot chain line is a channel region 12 formed on the substrate 11. Comb-like four third pad metal layers 30 extending from the left side are source electrodes 13 (or drain electrodes) connected to the output terminal OUT1, and below this are the first ohmic metal layers 10 There is a source electrode 14 (or drain electrode) formed. Further, four comb-like third pad metal layers 30 extending from the right side are drain electrodes 15 (or source electrodes) connected to the common input terminal IN, and below this are the first layer ohmic metals. There is a drain electrode 16 (or source electrode) formed of layer 10. Both electrodes are arranged in a shape in which comb teeth are engaged, and a gate electrode 17 formed of the second gate metal layer 20 is arranged in a comb shape on the channel region 12 between them.
[0014]
FIG. 13B shows a cross-sectional view of a part of this FET. The substrate 11 is provided with an n-type channel region 12 and n + -type high concentration regions for forming a source region 18 and a drain region 19 on both sides thereof. The channel region 12 is provided with a gate electrode 17, Are provided with a drain electrode 14 and a source electrode 16 formed of the first ohmic metal layer 10. Further, as described above, the drain electrode 13 and the source electrode 15 formed of the third pad metal layer 30 are provided thereon, and wiring of each element is performed.
[0015]
In the compound semiconductor device described above, a design technique has been adopted in which the gate width Wg is increased to reduce the on-resistance of the FET in order to minimize the insertion loss of the FET1 and FET2. For this reason, due to the increase in the gate width Wg, the size of the FET1 and FET2 has increased, and development has progressed in the direction of increasing the chip size.
[0016]
Further, in such a compound semiconductor device, a GaAs substrate which is a semi-insulating substrate is used, and a pad for thermocompression bonding of a wiring or a bonding wire directly serving as a conductive path is provided thereon. However, since a signal to be handled is a high frequency in the GHz band, it is necessary to provide a separation distance of 20 μm or more in order to ensure isolation between adjacent wirings. The isolation required for the compound semiconductor device is 20 dB or more, and a separation distance of 20 μm or more is necessary to experimentally secure isolation of 20 dB or more.
[0017]
Although this theoretical support is scarce, until now, the semi-insulating GaAs substrate has been considered to be infinite in voltage because of the idea that it is an insulating substrate. However, when actually measured, it was found that the withstand voltage was finite. For this reason, the depletion layer extends in the semi-insulating GaAs substrate, and when the depletion layer reaches the adjacent electrode due to the change of the depletion layer distance according to the high frequency signal, it is considered that the leakage of the high frequency signal occurs there. . Therefore, it was determined that a separation distance of 20 μm or more is necessary to ensure isolation of 20 dB or more.
[0018]
As is apparent from FIG. 12, in the conventional compound semiconductor device, pads corresponding to the common input terminal IN, the output terminals OUT1, OUT2, the control terminals Ctl-1, Ctl-2, and the ground terminal GND are provided around the substrate. ing. Forming a wiring layer at a distance of at least 20 μm from the pad further increases the chip size.
[0019]
[Problems to be solved by the invention]
In the above compound semiconductor device, the gate width Wg is increased in order to reduce the insertion loss (Insertion Loss) of the FET 1 and FET 2 as much as possible, and the size of each FET is increased due to the design method for reducing the on-resistance of the FET. In addition, a separation distance of 20 μm is required for the design that ensures the isolation between the pad and the wiring layer.
[0020]
For this reason, in the conventional compound semiconductor device, the chip size is increasingly increased, and as long as a GaAs substrate, which is more expensive than the silicon substrate, is used, the compound semiconductor device is replaced with an inexpensive silicon chip and loses the market. Invited the result.
[0021]
[Means for Solving the Problems]
The present invention has been made in view of the various circumstances described above, and by reducing the gate size by reducing the FET size, the distance between the pad and the wiring layer or other pattern is also reduced to reduce the chip size. It is characterized by realizing a reduced compound semiconductor device.
[0022]
That is, the semiconductor device includes a compound semiconductor substrate, a pad provided on the compound semiconductor substrate, and a bonding wire fixed to the pad, and the pad is directly disposed on the substrate and activated on the substrate surface under the pad. A region is provided, and the impurity region is characterized in that the expansion of the depletion layer under the pad is regulated.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a compound semiconductor device of the present invention will be described below with reference to FIGS. 1 to 8 by taking a compound semiconductor switch circuit device using GaAsFET as an example.
[0024]
FIG. 1 is a circuit diagram showing a compound semiconductor device of the present invention. The source electrodes (or drain electrodes) of the first FET 1 and the second FET 2 are connected to the common input terminal IN, and the gate electrodes of the FET 1 and FET 2 are respectively connected to the first and second control terminals Ctl via resistors R1 and R2. -1, Ctl-2, and the drain electrodes (or source electrodes) of FET1 and FET2 are connected to the first and second output terminals OUT1 and OUT2. The control signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET on the side to which the H level signal is applied is turned on and applied to the common input terminal IN. The input signal is transmitted to one of the output terminals. The resistors R1 and R2 are arranged for the purpose of preventing leakage of a high-frequency signal through the gate electrode with respect to the DC potential of the control terminals Ctl-1 and Ctl-2 that are AC grounded.
[0025]
The circuit shown in FIG. 1 has substantially the same circuit configuration as the principle circuit of a compound semiconductor device called SPDT (Single Pole Double Throw) using GaAs FETs shown in FIG. In addition, the gate width Wg of the gate electrode of the FET 2 is designed to be 700 μm or less, and the distance between the pad and the wiring layer is greatly reduced.
[0026]
Decreasing the gate width Wg compared to the conventional one means increasing the on-resistance of the FET, and the gate electrode area (Lg × Wg) is reduced to reduce the Schottky between the gate electrode and the channel region. This means that the parasitic capacitance due to the junction is reduced, and there is a large difference in circuit operation.
[0027]
Further, greatly reducing the separation distance between the pad and the wiring layer greatly contributes to reducing the size of the compound semiconductor chip.
[0028]
  2 and 3 show an example of a compound semiconductor chip in which the compound semiconductor device of the present invention is integrated. In any case, an activated impurity region 40 (indicated by a two-dot chain line) is provided under each pad electrode, and the spread of a depletion layer under the pad electrode can be suppressed by this region. Here, the activated impurity region 40 is a region having a good crystal structure and conductivity, specifically, an epitaxial layer having conductivity and an impurity diffusion region by ion implantation.Also, spread the depletion layerIn order to suppress, the impurity concentration is 1 × 10¹⁶cm^-3The above is necessary. The activated impurity region 40 is simply referred to as the impurity region 40 in the following description.
[0029]
FIGS. 2 and 3 are both compound semiconductor devices using GaAsFETs. The components are the same, but only the shape and arrangement of the impurity regions 40 are different. In FIG. 2, an impurity region 40 is provided on the entire lower surface of each pad electrode. In FIG. 3, the pad electrode and the wiring layer are provided only at the peripheral edge of each pad electrode in the adjacent portion. 2 and 3, the pad electrode is provided so as to protrude from the substrate contact portion.
[0030]
Further, an impurity region 40 is provided under the wiring layer 42. In this case, although detailed illustration is omitted, the entire surface under the wiring layer 42 may be provided, or the wiring layer 42 may be provided only at the peripheral end portion.
[0031]
As shown in FIGS. 2 and 3, FETs 1 and 2 for switching on a GaAs substrate are arranged in the center, and resistors R1 and R2 are connected to the gate electrodes of the FETs. Pads corresponding to the common input terminal IN, the output terminals OUT1 and OUT2, and the control terminals Ctl-1 and Ctl-2 are provided around the substrate. The second layer wiring indicated by the dotted line is a gate metal layer (Ti / Pt / Au) 20 formed simultaneously with the formation of the gate electrode of each FET, and the third layer wiring indicated by the solid line is each A pad metal layer (Ti / Pt / Au) 30 for connecting elements and forming pads. The ohmic metal layer (AuGe / Ni / Au) 10 that is in ohmic contact with the first layer substrate forms the source electrode, drain electrode, and extraction electrodes at both ends of each resistor, as shown in FIGS. However, it is not shown because it overlaps the pad metal layer.
[0032]
As is apparent from FIGS. 2 and 3, the components are only pads corresponding to FET1, FET2, resistors R1, R2, common input terminal IN, output terminals OUT1, OUT2, and control terminals Ctl-1, Ctl-2. Compared with the conventional compound semiconductor device shown in FIG.
[0033]
Further, in the present invention, FET1 (FET2 is the same) is formed with a gate width of 700 μm or less and less than half that of the conventional one, so that FET1 can also be half the size of the conventional one. That is, the FET 1 shown in FIGS. 2 and 3 is formed in a rectangular channel region 12 surrounded by a one-dot chain line. Comb-like three third-layer pad metal layers 30 extending from the lower side are the source electrode 13 (or drain electrode) connected to the output terminal OUT1, and the first-layer ohmic metal layer 10 is below this. There is a source electrode 14 (or drain electrode) formed by Further, three comb-shaped third pad metal layers 30 extending from the upper side are drain electrodes 15 (or source electrodes) connected to the common input terminal IN, and below this are the first layer ohmic metals. There is a drain electrode 14 (or source electrode) formed of layer 10. Both electrodes are arranged in a shape in which comb teeth are engaged, and a gate electrode 17 formed of the second gate metal layer 20 is arranged in the shape of four comb teeth on the channel region. Note that the middle comb-tooth drain electrode 13 (or source electrode) extending from the upper side is shared by the FET 1 and the FET 2, which further contributes to miniaturization. Here, the meaning that the gate width is 700 μm or less means that the total gate width of the comb-like gate electrode 17 of each FET is 700 μm or less.
[0034]
The cross-sectional structure of FET1 and FET2 is shown in FIG. The substrate 11 is provided with an n-type channel region 12 and n + -type high concentration regions for forming a source region 18 and a drain region 19 on both sides of the n-type channel region 12, and the channel region 12 includes a second gate metal layer 20. A gate electrode 17 to be formed is provided, and a drain electrode 14 and a source electrode 16 formed of the first ohmic metal layer 10 are provided in the high concentration region. Further, as described above, the drain electrode 13 and the source electrode 15 formed of the third pad metal layer 30 are provided thereon, and wiring of each element is performed. The FET shown in the figure can be finely patterned by using an I-line stepper in its manufacturing method. For example, in the gate electrode, the gate length Lg can be easily reduced.
[0035]
Next, a description will be given of whether it is possible to design a design that ensures isolation by omitting the shunt FET in a high frequency band of 2.4 GHz or higher.
[0036]
FIG. 5 shows the relationship of gate width Wg−insertion loss when the gate length Lg of the FET is 0.5 μm.
[0037]
When the input signal is 1 GHz, if the gate width Wg is reduced from 1000 μm to 600 μm, the insertion loss (Insertion Loss) of 0.35 dB to 0.55 dB and 0.2 dB is deteriorated. However, when the input signal is 2.4 GHz, if the gate width Wg is reduced from 1000 μm to 600 μm, an insertion loss of only 0.6 dB from 0.60 dB to 0.65 dB is sufficient. This is because insertion loss (Insertion Loss) is greatly affected by the on-resistance of the FET when the input signal is 1 GHz, but insertion loss (Insertion Loss) is affected by the on-resistance of the FET when the input signal is 2.4 GHz. I knew that I would n’t receive much
[0038]
This is because a 2.4 GHz input signal has a higher frequency than 1 GHz, so that it is considered that the influence of the capacitance component due to the gate electrode of the FET is greater than the on-resistance of the FET. For this reason, when the high frequency of 2.4 GHz or more, if the capacitance component has a greater influence on the insertion loss than the on-resistance of the FET, it is better to design by focusing on reducing the capacitance component rather than the on-resistance. In other words, the idea of completely reversing the conventional design was necessary.
[0039]
On the other hand, FIG. 6 shows the relationship of gate width Wg-isolation when the gate length Lg of the FET is 0.5 μm.
[0040]
When the input signal is 1 GHz, if the gate width Wg is reduced from 1000 μm to 600 μm, the isolation of 19.5 dB to 23.5 dB and 4.0 dB is improved. Similarly, in the case of a 2.4 GHz input signal, if the gate width Wg is reduced from 1000 μm to 600 μm, the isolation of 14 dB to 18 dB and 4.0 dB is improved. That is, it can be seen that the isolation is improved depending on the parasitic capacitance of the OFF-side FET caused by the gate electrode.
[0041]
Therefore, in view of the fact that insertion loss (Insertion Loss) is only slightly worsened in the high frequency band of 2.4 GHz or higher, as shown in FIG. 5, the isolation shown in FIG. 6 is given priority. Thus, the size of the compound semiconductor chip can be reduced by designing. That is, when the input signal is 2.4 GHz, if the gate width Wg is 700 μm or less, 16.5 dB or more of isolation can be secured, and if the gate width Wg is 600 μm or less, 18 dB or more can be secured. Isolation can be ensured.
[0042]
Specifically, in the compound semiconductor device of the present invention whose actual pattern is shown in FIG. 2 and FIG. 3, FET 1 and FET 2 having a gate length Lg of 0.5 μm and a gate width Wg of 600 μm are designed, and insertion loss (Insertion Loss) is 0.65 dB, and isolation is 18 dB. This characteristic includes 2.4 GHz band ISM Band (Industrial Scientific) including Bluetooth (mobile phone, notebook PC, personal digital assistant, digital camera, and other peripheral devices wirelessly interconnected to improve the mobile environment and business environment). and medical frequency band) as a communication switch in the application field of spread spectrum communication.
[0043]
Next, using FIG. 2, FIG. 3, and FIG. 7, it will be described how to significantly reduce the distance between the pad and the wiring layer.
[0044]
  FIG. 7 shows a structure of pads and wirings of the compound semiconductor device of the present invention. 7A shows a bonding pad portion, and FIG. 7B shows a cross-sectional view of the wiring layer portion. As shown in FIG. 2, five pads of a common input terminal IN, output terminals OUT1 and OUT2, and control terminals Ctl-1 and Ctl-2 are arranged around the substrate. Further, as shown in FIG. 7, each pad has an n + -type impurity region 40 (indicated by a two-dot chain line in FIG. 2) provided on the substrate 11 along the entire lower surface thereof, and most of the pads on the substrate 11. The gate metal layer 20 is provided on the gate metal layer 20 and the pad metal layer 30 is superimposed on the gate metal layer 20. Further, the impurity region 40 is provided on the entire lower surface (FIG. 7B) below the wiring layer 42. In this case, the impurity region 40 is a diffusion region formed simultaneously in the ion implantation process for forming the source region and the drain region. Accordingly, the gold bonding wire 41 is ball bonded onto the pad metal layer 30 of the pad. Here, as described above, the impurity region 40 may be an epitaxial layer having an impurity concentration capable of suppressing a depletion layer. If the uppermost layer of the GaAs substrate is an n-type epitaxial layer, a diffusion region by ion implantation may not be provided. Can be implementedThe
[0045]
Thereby, the impurity region 40 is provided on the surface of the substrate 11 under the pad and the wiring layer. Therefore, the substrate 11 not doped with impurities (semi-insulating, but the substrate resistance value is 1 × 10⁷Unlike the (Ω · cm) surface, the impurity concentration is high (ion species 29Si⁺And the concentration is 1-5x10¹⁸cm^-3Therefore, since the depletion layer under the pad or the wiring layer does not extend, the distance between the pad and the wiring layer or another pattern adjacent to each other can be reduced to a limit that can secure isolation of 20 μm to 20 dB. Specifically, it has been determined that a separation distance of 4 μm is sufficient to ensure isolation of 20 dB or more. Also, in the electromagnetic field simulation, it is known that isolation can be obtained as much as 40 dB at 2.4 GHz if a separation distance of about 4 μm is provided.
[0046]
Here, as shown in FIG. 3, the impurity region 40 may be provided only at the peripheral edge of the pad and the wiring layer. That is, the impurity input region 40 is provided along the three sides except for the upper side of the pad of the common input terminal IN, and the pads of the output terminals OUT1 and OUT2 are formed in a C shape along the four sides, leaving a corner portion of the GaAs substrate. Impurity region 40 is provided, and the pads of control terminals Ctl-1 and Ctl-2 are C-shaped impurities along the four sides of the irregular pentagon except for the corner portion of the GaAs substrate and the portion connected to resistors R1 and R2. Region 40 is provided. The portion where the impurity region 40 is not provided is a portion facing the peripheral edge of the GaAs substrate, and even if the depletion layer spreads, there is a sufficient separation distance from adjacent pads and wirings, and leakage is not a problem.
[0047]
Therefore, since five pads occupy nearly half of the semiconductor chip, the wiring layer can be arranged to the vicinity of the pads if the pad structure of the present invention is employed. Specifically, since the impurity region 40 is also provided under the wiring layer, the pad electrodes are adjacent to each other, the pad electrodes are separated from the wiring layer, the wiring layer, and other patterns such as resistance and capacitance. The distance can be as close as 4 μm, which can greatly contribute to the reduction of the semiconductor chip.
[0048]
As a result, the size of the compound semiconductor chip of the present invention is 0.37 × 0.30 mm.²I was able to pay. This means that the conventional compound semiconductor chip size can actually be reduced to 20%.
[0049]
Further, when the present invention is applied to a compound semiconductor switch circuit device, a number of circuit characteristics can be improved. First, a voltage standing-wave ratio VSWR (Voltage Standing-Wave Ratio) representing reflection at a switch with respect to high-frequency input power is 1.1 to 1.2. VSWR represents the ratio of the maximum value and the minimum value of the voltage standing wave generated between the reflected wave generated at the discontinuous portion in the high-frequency transmission line and the input wave. In an ideal state, VSWR = 1 means reflection 0. . In a conventional compound semiconductor switch circuit device having a shunt FET, VSWR is about 1.4, and in the present invention, the voltage standing wave ratio can be greatly improved. This is because the compound semiconductor switch circuit device of the present invention has only FETs 1 and 2 for switching in the high-frequency transmission line, and there are only FETs that are simple in terms of circuit and extremely small in size. .
[0050]
Second, the linearity characteristic indicating the distortion level of the output signal with respect to the high-frequency input signal is P_IN30 dBm is realized as 1 dB. FIG. 8 shows the linearity characteristics of the input / output power. The input / output power ratio is ideally 1, but since there is insertion loss, the output power is reduced accordingly. Since the output power becomes distorted as the input power increases, the point that the output power decreases by 1 dB relative to the input power is P_INExpressed as 1 dB. In compound semiconductor switch circuit devices with shunt FETs, P_INAlthough 1 dB is 26 dBm, the compound semiconductor switch circuit device of the present invention without a shunt FET is 30 dBm, and an improvement of about 4 dB or more can be achieved. The reason for this is that, in the case of the present invention without a shunt FET, only the FET for the switch that is turned off is synergistically affected by the pinch-off voltage of the off switch and the shunt FET with the shunt FET. Because it is only an influence.
[0051]
Here, in the embodiment of the present invention, the compound semiconductor switch circuit device has been described as an example. However, the present invention is similarly applied to a compound semiconductor device such as an MMIC (for example, an amplifier and a mixer), a diode, and an FET other than the switch circuit device. it can.
[0052]
【The invention's effect】
As described above in detail, according to the present invention, the following effects can be obtained.
[0053]
First, by providing an impurity region under the pad and the wiring layer that occupies almost half of the semiconductor chip size or under the peripheral edge portion, the distance from the adjacent pad, wiring layer, or other pattern can be reduced to 4 μm. Since they can be arranged close to each other, coupling of high-frequency signals and securing of a withstand voltage of 10 V can be achieved in a small space, and there is an advantage that significant shrinking is possible.
[0054]
Second, focusing on the design that ensures isolation by omitting shunt FETs in the high frequency band of 2.4 GHz or higher, the reciprocal idea that considers the reduction of on-resistance of FETs so far. The gate width Wg of the gate electrodes of FET1 and FET2 used for the switch is designed to be 700 μm or less. As a result, it is possible to reduce the size of the FET 1 and FET 2 used for the switch, to suppress the insertion loss (Insertion Loss), and to secure the isolation.
[0055]
Third, since the compound semiconductor device of the present invention can be designed without the shunt FET, the components are FET1, FET2, resistors R1, R2, common input terminal IN, output terminals OUT1, OUT2, and control terminal Ctl−. Only the pads corresponding to 1 and Ctl-2 have an advantage that they can be configured with the minimum components compared to the conventional compound semiconductor device.
[0056]
Fourth, as described above, the reduction in the separation distance between the minimum component parts, the pad, and the wiring layer enables the semiconductor chip size to be reduced to 20% as compared with a conventional compound semiconductor device. Competitiveness can be greatly improved. Since the chip size can be reduced, it is mounted on a smaller package (SMCP6 size 1.6 mm x 1.6 mm x 0.75 mm) than the conventional small package (MCP6 size 2.1 mm x 2.0 mm x 0.9 mm). Can now.
[0057]
Fifth, since the insertion loss does not increase so much even when the frequency becomes 2.4 GHz or higher, it is possible to design an isolation that can eliminate the shunt FET. For example, even with a 3 GHz input signal and a gate width of 300 μm, sufficient isolation can be secured without a shunt FET.
[0058]
Sixth, in the compound semiconductor device of the present invention, the voltage standing wave ratio VSWR (Voltage Standing-Wave Ratio) representing the reflection at the switch with respect to the high frequency input power can be realized to 1.1 to 1.2, and the reflection is small. Can provide a switch.
[0059]
Seventh, in the compound semiconductor device of the present invention, the linearity characteristic P representing the distortion level of the output signal with respect to the high frequency input signal._IN1 dB can be improved to 30 dBm, and the linearity characteristics of the switch can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram for explaining the present invention.
FIG. 2 is a plan view for explaining the present invention.
FIG. 3 is a plan view for explaining the present invention.
FIG. 4 is a cross-sectional view for explaining the present invention.
FIG. 5 is a characteristic diagram for explaining the present invention.
FIG. 6 is a characteristic diagram for explaining the present invention.
FIG. 7 is a cross-sectional view for explaining the present invention.
FIG. 8 is a characteristic diagram for explaining the present invention.
9A is a cross-sectional view for explaining a conventional example, and FIG. 9B is a circuit diagram.
FIG. 10 is an equivalent circuit diagram for explaining a conventional example.
FIG. 11 is a circuit diagram for explaining a conventional example.
FIG. 12 is a plan view for explaining a conventional example.
13A is a plan view and FIG. 13B is a cross-sectional view for explaining a conventional example.

Claims (17)

A non-doped compound semiconductor substrate;
A pad provided on the compound semiconductor substrate;
A bonding wire fixed to the pad,
The pad is directly disposed on the substrate, an activated n-type impurity region is provided on the surface of the substrate under the pad, and the expansion of a depletion layer under the pad is regulated by the impurity region. A compound semiconductor device.   The compound semiconductor device according to claim 1, wherein the impurity region is an epitaxial layer.   The compound semiconductor device according to claim 1, wherein the impurity region is a diffusion region formed by ion implantation.   The compound semiconductor device according to claim 1, wherein the impurity region is provided so as to protrude from the substrate contact portion of the pad. 2. The compound semiconductor device according to claim 1, wherein a distance between adjacent pads is 20 μm or less and is narrowed to a limit where a predetermined isolation can be secured. A non-doped compound semiconductor substrate;
A pad provided on the compound semiconductor substrate;
A bonding wire fixed to the pad;
An FET having an n-type channel layer provided on the compound semiconductor substrate;
The pad is directly disposed on the substrate, an activated n-type impurity region is provided on the surface of the substrate under the pad, and the expansion of a depletion layer under the pad is regulated by the impurity region. A compound semiconductor device.   The compound semiconductor device according to claim 6, wherein the impurity region is an epitaxial layer.   The compound semiconductor device according to claim 6, wherein the impurity region is a diffusion region formed by ion implantation.   The compound semiconductor device according to claim 6, wherein the impurity region is provided so as to protrude from the substrate contact portion of the pad. The compound semiconductor device according to claim 6, wherein a distance between the pads adjacent to each other is reduced to a limit of 20 μm or less so that a predetermined isolation can be secured. An n-type channel layer is provided on a non-doped compound semiconductor substrate, and first and second FETs having a source electrode, a gate electrode and a drain electrode provided on the surface of the channel layer are formed. A common input terminal is used as first and second output terminals connected to the drain electrode or source electrode of both FETs, and a control signal is applied to a control terminal connected to the gate electrodes of both FETs to either one of the FETs. In a compound semiconductor device in which a signal path is formed with the common input terminal and one of the first and second output terminals by conducting an electric current,
The common input terminal, the first and second output terminals, and the pad serving as the control terminal are directly disposed on the substrate, and an activated n-type impurity region is provided under the pad to provide semi-insulating properties. A compound semiconductor device characterized in that a distance from another pattern of the compound semiconductor device directly provided on the substrate is 20 μm or less.   The compound semiconductor device according to claim 11, wherein the impurity region is an epitaxial layer.   The compound semiconductor device according to claim 11, wherein the impurity region is a diffusion region formed by ion implantation.   12. The compound semiconductor device according to claim 11, wherein the impurity region is provided so as to protrude from the substrate contact portion of the pad. 12. The compound semiconductor device according to claim 11, wherein a separation distance between the pad adjacent to each other and the other pattern is narrowed to a limit where a predetermined isolation can be ensured.   The compound semiconductor device according to claim 11, wherein a diffusion region having the same impurity concentration as that of the source region and the drain region is used as the impurity region.   12. The compound semiconductor device according to claim 11, wherein the first and second FETs include a gate electrode that is in Schottky contact with the channel layer, and a source and drain electrode that are in ohmic contact with the channel layer.

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