JP4123022B2 - Operation synchronization circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a multiprocessor system in which a plurality of processors operate in parallel, connects electrical signals for communication between processors, converts electrical characteristics of electrical signals, connects them, or connects to optical fibers. The ports that convert optical signals and electrical signals to each other and these ports are connected to each other, and the electrical or optical signals are uniquely determined by the ports indicated by the signals themselves or by the connection method between the ports. The present invention relates to a circuit for synchronizing operations of processors in a system including a fabric that transmits and receives signals between ports.
[0002]
[Prior art]
In a multiprocessor system, since each processor operates in parallel, special consideration is required for debugging of hardware or software in system development and synchronization between operating processors.
In a configuration in which processors are connected to a common bus as a conventional multiprocessor system, a mechanism for time synchronization is added to the common bus (see, for example, Patent Document 1). In the configuration in which the processor is connected to the network, a network for newly providing a trigger signal to the processor is added (for example, see Patent Document 2).
[0003]
[Patent Document 1]
JP 2000-348007 A (6th page, FIG. 1)
[Patent Document 2]
Japanese Patent Laid-Open No. 5-165792 (page 5, FIG. 1)
[0004]
[Problems to be solved by the invention]
In a conventional multiprocessor system, the time of a plurality of processors is set in order to grasp the operation state of a plurality of processors. Operation trace information that records the state of register information and the like is acquired, and software that operates on a plurality of processors in the system can operate in a coordinated manner. In order to achieve this time synchronization, time synchronization information and originally unnecessary debug information are communicated via a common bus or fabric. For this reason, time synchronization information must be interrupted in communication gaps between processors that perform large amounts of data transmission and reception, and delays in transmission processing and reception processing are not constant for each processor, so strict time synchronization cannot be performed. . In addition, by performing time synchronization ignoring the dependency between the internal state of the software executed by the processor and the data transmission / reception, for example, the processor that has completed the transmission process of a certain data and the data before the reception process of the data Operation trace information is collected with the processor. At this time, transmission of the data is completed on the one hand, but not received on the other hand, and correct operation trace information cannot be collected, such as a problem that it cannot be distinguished from the case where data transmission / reception is not performed correctly. In addition, communication of time synchronization information hinders the occurrence of defects during software development, and the reproducibility of the defects is impaired, or the communication time of the entire system increases due to the increase in communication time of time synchronization information, which degrades the system processing performance There is a problem of letting you.
[0005]
The present invention has been made to solve the above-described problems, and an object thereof is to realize operation synchronization without interfering with inter-processor communication.
[0006]
[Means for Solving the Problems]
The operation synchronization circuit according to the present invention includes: It is an operation synchronization circuit that is set as a master or slave, A card internal bus, a data communication converter connected to the card internal bus and performing conversion for transmitting an electrical signal on the card internal bus to the fabric, and a port connecting the data communication converter and the fabric To synchronize operation with the internal bus of the card A synchronization signal driven by a pulse, a data signal indicating a sign necessary for system synchronization, and a status signal indicating an internal state of another operation synchronization signal transceiver An operation synchronization signal transceiver for connecting to an operation synchronization bus In the master-set operation synchronization circuit, the operation-synchronization signal transmitter / receiver drives the synchronization signal and the data signal, reads the status signal, and transmits and receives the operation-synchronization signal in the slave-set operation synchronization circuit. Reads the synchronization signal and the data signal and drives the status signal Is.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration of an operation synchronization circuit in the multiprocessor system according to the first embodiment. The multiprocessor system shown in the figure is a system including two or more processors of the same or different types. The IEEE802.3 standard compliant with the IEEE802.3 standard installed in the multiprocessor system, the FiberChannel (ANSI X3. 230: 1994), InfiniBand (InfiniBand Trade Association), RACEway (ANSI / VITA 5-1994), RapidIO (RapioIO Trade Association), Hyper Transport (Hyper Transport Consortium), STARFABRIC (StarFabric Trade Association), PCI Express (Peripheral Com onent Interconnect Special Interest Group), an upward compatible standard of the above-mentioned standard, or a combination of connections that communicate one-to-one between devices using electrical or optical signals compliant with other standards. This is a system in which processors mounted on two or more processor cards communicate with each other via a fabric 6, which is a connection network that can exchange data. As shown in the processor card (1) 2, the processor card (2) 11, and the processor card (n) 13, each of the two or more processor cards constituting the multiprocessor system transmits the fabric 6 and the inside of the fabric. The signal to be converted is converted into an electrical signal on the processor card and connected by a port 5 for connection. In the processor card (1) 2, the processor card (2) 11, and the processor card (n) 13, the processor (1) 1, the processor (2) 10, and the processor (n) 12 that perform main arithmetic processing operate in parallel. Each processor card has a card internal bus 3 that electrically connects the processor and other electronic circuits. The card internal bus 3 converts the electrical signal for connection with the port 5 and the electrical signal on the card internal bus 3 to each other while maintaining the data contents and the respective transmission methods and electrical characteristics. A data communication converter 4 that can detect and correct transmission of erroneous data that is predicted to occur on the fabric 6 is connected. Data transmitted and received by the processor (1) 1, the processor (2) 10, and the processor (n) 12 are transmitted to each other via the card internal bus 3, the data communication converter 4, the port 5, and the fabric 6. The Regarding the internal connection method of the fabric 6, there are a point-to-point connection such as a crossbar switch or a method of directly connecting the ports of the processor card in a ring shape, but the details of the structure are omitted.
[0008]
The processor card (1) 2 is connected to an operation synchronization signal transmitter / receiver 20a connected to the card internal bus 3. The operation synchronization signal transmitter / receiver 20a is a device for controlling and observing signals constituting the operation synchronization bus 21 by connecting to the card internal bus 3. The operation synchronization signal transmitter / receiver 20a can drive the synchronization signal 23 and the data signal 24 constituting the operation synchronization bus 21 shown in FIG. 2 and read the status signal 25 at any time according to an instruction from the processor (1) 1. Similarly, the processor card (2) 11 and the processor card (n) 13 are connected to operation synchronization signal transmitters / receivers 20b and 20c, and these processor cards are operation synchronization buses in which an operation synchronization bus 21 is electrically mounted. It is mechanically fixed to the back panel 27 and electrically connected to the operation synchronization bus 21. In this bus connection configuration, since the operation synchronization signal transmitter / receiver has the same electrical characteristics, it can be connected to the common operation synchronization bus 21. Therefore, the processor (1) 1, the other processor (2) 10, the processor (n ) Even if 12 are of different types, or the card internal bus 3 can be connected to a different type of bus for each processor card. In the operation synchronization signal transmitter / receiver connected to the operation synchronization bus 21, only one operation synchronization signal transmitter / receiver 20a operates as a master, and all other operation synchronization signal transmitters / receivers 20b and 20c operate as slaves. . The master-set operation synchronization signal transmitter / receiver 20 a can drive the synchronization signal 23 and the data signal 24 among the signals of the operation synchronization bus 21 and read the status signal 25. On the other hand, the operation synchronization signal transmitters / receivers 20b and 20c set as slaves can read the synchronization signal 23 and the data signal 24 and can drive the status signal 25. The master or slave operation setting may be a master-specific operation synchronization signal transmitter / receiver and a slave-specific operation synchronization signal transmitter / receiver, or an operation synchronization signal designed for both the master and slave. A master / slave setting signal 22 may be set for each processor card in order to determine the internal operation of the transceiver. In this case, the master / slave setting signal 22 supplies an electric signal for instructing the master setting to only one processor card (1) 2, and the other processor card (2) 11, processor card (n ) 13 is supplied with an electrical signal instructing slave setting. Even if the processor cards have the same configuration, only one processor card (1) 2 operates as an operation synchronization signal transmitter / receiver 20a set as a master, and the other processor cards (2) 11, (n) 13 The operation synchronization bus / back panel 27 supplies the master / slave setting signal 22 as a master setting or a signal for instructing the slave setting depending on the position where the card is fixed so that it can operate as the slave setting operation synchronizing signal transmitter / receiver 20b, 20c. To do. With this configuration, it is possible to save the trouble of setting the master setting and the slave setting for each card, and all the operation synchronization signal transmitters / receivers connected to the operation synchronization bus 21 are set as slaves, or two or more are simultaneously set. The master setting can be prevented. In another configuration, instead of using the master / slave setting signal 22, a configuration in which the processor instructs the operation synchronization signal transmitter / receiver via the card internal bus 3 to perform master setting or slave setting by software.
[0009]
Details of the operation synchronization bus 21 will be described with reference to FIG. Unlike a VME (Versa Module Europe) standard bus or a CompactPCI (Compact-Peripheral Component Interconnect) standard bus, one synchronization signal 23 and one or more data signals 24 for notifying operation status and time, It consists of one or more status signals 25 for sharing the internal state of each operation synchronization signal transceiver. Further, a timer / register circuit 26 is included in the operation synchronization signal transceivers 20a, 20b, and 20c. The timer / register circuit 26 is a circuit that can be controlled by the processor via the card internal bus 3. When the processor requests the start of a timer operation, the timer register circuit 26 operates a circuit prepared for timekeeping, calculates the time internally every time a fixed time elapses, and holds the time It has the function to do. The processor can read the time calculated and held in the timer / register circuit 26 at any time, and can acquire the time elapsed since the timer operation start was requested. Further, the operation synchronization signal transmitter / receiver 20a set as a master can output to the data signal 24 the time calculated by the timer / register circuit 26 at regular intervals based on an instruction from the processor. The slave-set operation synchronization signal transceivers 20b and 20c can read the time output from the master-set operation synchronization signal transmitter / receiver 20a via the data signal 24 and store it in the timer / register circuit 26. it can. This time can be read by the processor (2) 10 and the processor (n) 12 via the card internal bus 3. Alternatively, the operation synchronization code designated by the processor is written to the timer / register circuit 26 of the operation synchronization signal transmitter / receiver 20a set as the master, and when the processor requests transmission of the code, the operation synchronization code is output to the data signal 24. To do. The slave-set operation synchronization signal transmitters / receivers 20 b and 20 c read the operation synchronization code from the data signal 24 and hold it in the timer / register circuit 26. This operation synchronization code can be read by the processor (2) 10 and the processor (n) 12 via the card internal bus 3.
[0010]
Among the processor cards, the processor card (1) 2 that is set as the only master by the master setting instruction of the master / slave setting signal 22 has the authority to manage the operation synchronization bus 21 in this multiprocessor system. In each processor card set as a slave, the status is written in the timer register circuit 26 in order to notify the processor (2) 10 and the processor (n) 12 that the operation can be started when the preparation for the system operation is completed. . In response to this, the slave-set operation synchronization signal transceivers 20 b and 20 c output a status signal 25 to the operation synchronization bus 21. The status signal 25 is received by the operation synchronization signal transmitter / receiver 20a of the processor card (1) 2 set as the master, and held in the timer / register circuit 26.
[0011]
The processor (1) 1 can read the status signal 25 from the timer / register circuit 26 at any time via the card internal bus 3. By this reading, it is possible to grasp the operation state of the processor cards (2) 11, (n) 13 on which the operation synchronization signal transceivers 20b, 20c set as slaves are mounted. The processor (1) 1 prepares for system operation of all the processor cards by monitoring the status of the status signal 25 obtained from the timer / register circuit 26 even when the activation times of the respective processor cards are different. I can wait until I can. With this mechanism, a processor that has completed booting quickly starts communication via the fabric 6 in a state where a processor that is not ready for booting is connected, and communication with the processor prior to booting completion cannot be established. Can be prevented.
[0012]
Since the processor (1) 1 starts the system operation, the system operation can be started at an arbitrary time thereafter by completion of its own startup preparation and completion of startup preparation of another processor obtained by the mechanism. At the start of the system operation, the processor (1) 1 sends to the timer / register circuit 26 of the operation synchronization signal transmitter / receiver 20a set as a master the code previously indicated to notify the operation start as the synchronization start time or the code indicating the time zero. Set. The master-set operation synchronization signal transmitter / receiver 20a outputs this code to the data signal 24 and drives the synchronization signal 23 in pulses. The slave-set operation synchronization signal transmitters / receivers 20b and 20c connected to the operation synchronization bus 21 receive an edge of the synchronization signal 23 that transitions from logic L to logic H or, depending on the configuration, from logic H to logic L. The synchronization is completely synchronized within the range of the difference in each processor card in the total time of the signal transmission delay time of the synchronization signal and the physical response delay time of the element parts that transmit and receive this signal. Therefore, the accuracy of synchronization does not depend on the pulse width of the synchronization signal 23 or the transmission delay of the data signal 24.
[0013]
After starting the operation synchronization, the processor starts high-speed data transmission / reception via the data communication converter 4, the port 5, and the fabric 6 of each processor card. When the processor (1) 1 does not need to perform the operation synchronization management of the multiprocessor system, the processor (1) 1 controls the timer / register circuit 26 included in the operation synchronization signal transceiver 20a to perform the timer operation. By instructing, it is defined for the slave-set operation synchronization signal transceivers 20b and 20c on the other processor card (2) 11 and processor card (n) 13 regardless of the software operation of the processor (1) 1. Time data is output to the data signal 24 at time intervals, and the synchronization signal 23 is pulse-driven. With the above operation, time synchronization can be performed for the other processors (2) 10 and the processor (n) 12. Furthermore, since the processor (1) 1 can also refer to the time information by referring to the timer / register circuit 26, time synchronization can be performed. Also, the interrupt input for instructing the interrupt processing of the program operation included in each processor is connected to the operation synchronization signal transmitters / receivers 20a, 20b, and 20c by the interrupt signal line 33, and the interrupt signal is notified simultaneously with the generation of the synchronization signal 23 pulse. Thus, the occurrence of time synchronization may be notified regardless of the contents of the software processing.
[0014]
When the processor (1) 1 performs synchronization management of the multiprocessor system, an appropriate operation synchronization code is written in the timer / register circuit 26 included in the operation synchronization signal transmitter / receiver 20a set as the master. By this writing operation, the operation synchronization signal transmitter / receiver 20a outputs the code designated by the data signal 24 and pulse-drives the synchronization signal 23.
The operation synchronization signal transmitters / receivers 20b and 20c set as slaves fetch the code of the data signal 24 every time the synchronization signal 23 is received and hold it in the timer / register circuit 26. From time to time, the processor reads the timer / register circuit 26 from the card internal bus 3 to obtain a code for operation synchronization from the processor (1) 1 and can perform operation synchronization. In another configuration, every time the synchronization signal 23 is received, the operation synchronization signal transceivers 20b and 20c set as slaves connect the interrupt signal line 33 to the interrupt input provided in the processor, and the software processing contents of the processor Instead, the processor may be notified of the reception of the operation synchronization signal.
[0015]
The timing of each signal on the operation synchronization bus 21 will be described with reference to FIG. The synchronization signal 23 is an effective signal at the edge portion of the waveform on the pulse, and for example, synchronization is assumed at the time of transition from logic L to logic H as shown in FIG. In another configuration, synchronization may be established at the time of transition from logic H to logic L. This signal is output by the operation synchronization signal transmitter / receiver 20a set by the master / slave setting signal 22. The data signal 24 is composed of one or more signal lines, and is composed of the number of signal lines sufficient to represent a code necessary for system operation synchronization. The sign of this signal is fixed at the time when the signal of the synchronization signal 23 transitions from logic L to logic H, or depending on the configuration, from logic H to logic L, and is output from the master-set operation synchronization signal transceiver 20a. The slave-set operation synchronization signal transceivers 20b and 20c read the data. The status signal 25 is output from the slave-set operation synchronization signal transmitters / receivers 20b and 20c, and is set from logic L to logic H or logic H to logic L depending on the configuration when each processor becomes operable. In order to read the status signals of a plurality of processors at the same time, the number of lines corresponding to the number of processors may be configured, or one signal may be shared by two or more processors.
[0016]
Embodiment 2. FIG.
FIG. 4 shows the configuration of the operation synchronization circuit in the multiprocessor system according to the second embodiment. The multiprocessor system shown in the figure is supported by a robust structure of a common bus back panel 32 such as a VME standard bus, a PCI standard, or a Compact PCI standard bus that is widely available on the market, and is a back panel that is allowed by the standard. In this configuration, the operation synchronization bus 21 is arranged in each empty signal line.
[0017]
The processor card (1) 2, the processor card (2) 11, and the processor card (n) 13 are inserted into the common bus / back panel 32. The common bus 31 is a bus in which address lines, data lines, and control signals are connected based on the common standard, such as a VME standard, PCI standard, Compact PCI standard bus, and the like. It is connected to the card internal bus 3 via a common bus converter 30 that mutually converts electrical characteristics and data exchange procedures with the electrical signal and performs data transfer.
Here, in the minimum configuration, the operation synchronization bus 21 can be configured from one signal line for each of the synchronization signal 23, the data signal 24, and the status signal 25, and an empty signal line of the common bus 31 can be easily used. it can. In addition, in comparison with the common bus 31 that takes a complicated procedure in terms of the characteristics of the electrical signal, it is possible to perform operation synchronization by the edge of the pulse signal of the synchronization signal 23. Also depends only on the propagation delay of the electrical signal on that signal line. For this reason, the time transmitted to each operation synchronization signal transmitter / receiver is sufficiently accurate compared with the operation of the processor.
The master / slave setting signal 22 is set to only one master setting signal and another slave setting signal in accordance with the position where the card is inserted into the common bus / back panel 32. With this configuration, it is possible to save the trouble of setting the master setting and the slave setting for each card, all the operation synchronization signal transmitters / receivers connected to the operation synchronization bus 21 are set as slaves, or two or more are simultaneously set. The master setting can be prevented. In another configuration, instead of using the master / slave setting signal 22, a configuration in which the processor instructs the operation synchronization signal transmitter / receiver via the card internal bus 3 to perform master setting or slave setting by software.
[0018]
Embodiment 3 FIG.
FIG. 5 shows the configuration of the operation synchronization circuit in the multiprocessor system of the third embodiment. The multiprocessor system shown in the figure has a configuration in which operation synchronization can be performed between processor cards connected to a common fabric 6 connected to different common bus / back panels 32.
[0019]
A connector 28, which is a connection device for connecting the synchronization signal 23, the data signal 24, and the status signal 25 constituting the operation synchronization bus 21, is connected between the different common bus / back panel 32, and the synchronization signal 23, data signal 24. The back panels are connected by a cable 29 which is a wiring for electrically connecting the status signal 25. Normally, it is difficult to apply such a configuration to, for example, the common bus 31 from the viewpoint of electrical characteristics. However, since the operation synchronous bus 21 is slower than the operation of the common bus 31, its electrical Since the characteristics are extremely simple, extension by the cable 29 is easy. Further, even if the common bus 31 is of different types of standards, the operation synchronization bus 21 can be made common, and the operation synchronization can be easily performed.
[0020]
Embodiment 4 FIG.
FIG. 6 shows the configuration of the operation synchronization circuit in the multiprocessor system of the fourth embodiment. The multiprocessor system shown in the figure is a card that does not have a direct connection with the fabric 6, and performs reading and writing with a memory via a common bus, and controls signal input from external devices and external devices. The input / output card 15 for outputting the signal is connected to the common bus 31.
[0021]
The card internal bus 3 on the input / output card 15 converts and holds the electrical characteristics of the input signal from the external device, outputs a signal according to the electrical characteristics required by the external device, or An input / output controller 14 that generates an output signal by analog-to-digital conversion or vice versa is connected to perform input / output control with an external device (not shown). The card internal bus 3 may be the same bus as the processor card (1) 2 and the other card internal bus 3, or may be a dedicated bus specialized for the input / output card 15 or a collection of simple control lines and data lines. . When an input signal from an external device is processed by a multiprocessor system, it is important to know when the input signal is. When the input / output controller 14 reads the time information and the operation synchronization information transmitted from the processor card (1) 2 via the operation synchronization bus 21 via the card internal bus 3, the input signal and its acquisition time are read. Alternatively, the internal state of the processor (1) 1 can be associated. Thus, by exchanging information in which the input signal is associated with the time via the common bus 31, for example, the processor (1) 1 can execute necessary arithmetic processing, and the system configuration can be flexibly performed. There is.
[0022]
Further, by changing the configuration of the master / slave setting signal 22 set by the common bus / back panel 32, the operation synchronization signal transmitter / receiver 20b on the input / output card 15 is operated as a master setting, and the processor card (1) 2 may be configured to operate as the slave setting. In this case, the input / output controller 14 instructs the timer / register circuit 26 included in the master-set operation synchronization signal transmitter / receiver 20b to perform timer operation, and converts the input signal from the external device at regular intervals. In addition, time synchronization can be performed.
[0023]
【The invention's effect】
Since the present invention is configured as described above, operation synchronization can be realized without interfering with inter-processor communication.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an operation synchronization circuit in a multiprocessor system showing Embodiment 1 of the present invention;
FIG. 2 is a diagram for explaining details of an operation synchronization bus according to the first embodiment of the present invention;
FIG. 3 is a diagram for explaining signal timing of an operation synchronous bus according to the first embodiment of the present invention.
FIG. 4 is a diagram for explaining an operation synchronization circuit in a multiprocessor system showing Embodiment 2 of the present invention;
FIG. 5 is a diagram for explaining an operation synchronization circuit in a multiprocessor system showing Embodiment 3 of the present invention;
FIG. 6 is a diagram for explaining an operation synchronization circuit in a multiprocessor system showing Embodiment 4 of the present invention;
[Explanation of symbols]
1 processor (1)
2 processor cards (1)
3 Card internal bus
4 Data communication converter
5 ports
6 Fabric
10 processors (2)
11 Processor card (2)
12 processors (n)
13 Processor card (n)
14 I / O controller
15 I / O card
20a Operation setting signal transmitter / receiver for master setting
20b Operation setting signal transmitter / receiver of slave setting
20c Slave-set operation synchronization signal transmitter / receiver
21 Operation synchronous bus
22 Master / slave setting signal
23 Sync signal
24 data signals
25 Status signal
26 Timer / Register Circuit
27 Operation Synchronized Bus / Back Panel
28 Connector
29 Cable
30 Common bus converter
31 Common bus
32 Common bus and back panel
33 Interrupt signal line

Claims (3)

It is an operation synchronization circuit that is set as a master or slave,
A card internal bus,
A data communication converter connected to the card internal bus and performing a conversion to transmit an electrical signal on the card internal bus onto the fabric;
A port connecting the data communication converter and the fabric;
An operation composed of a pulse-driven synchronization signal, a data signal indicating a code required for system synchronization, and a status signal indicating the internal state of another operation synchronization signal transmitter / receiver in order to synchronize operation with the card internal bus An operation synchronization signal transceiver for connecting the synchronization bus;
Equipped with a,
In the master-set operation synchronization circuit, the operation synchronization signal transmitter / receiver drives the synchronization signal and the data signal, reads the status signal,
In the slave-set operation synchronization circuit, the operation synchronization signal transceiver reads the synchronization signal and the data signal, and drives the status signal.
An operation synchronization circuit characterized by the above . A common bus,
A common bus converter that is connected to the card internal bus and converts electrical signals of the card internal bus to data of the common bus;
The operation synchronization circuit according to claim 1. The operation synchronization circuit according to claim 2, wherein there are a plurality of the common buses.

Images