JP4123537B2 - Electronic equipment - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The invention disclosed in this specification relates to an electronic device having a non-light-emitting display such as a liquid crystal display in which an active matrix circuit is formed using a thin film transistor (hereinafter referred to as TFT) on a substrate. In particular, the active matrix circuit according to the present invention relates to an electronic device which is controlled by a drive circuit (peripheral circuit) using TFTs which are also formed on the same substrate.
[0002]
[Prior art]
In recent years, it has come to be used as a display for various portable electronic devices (for example, personal computers, word processors, electronic notebooks) by utilizing the thin and light liquid crystal display. Among liquid crystal displays, a so-called active matrix type liquid crystal display in which pixels are controlled one by one using TFTs has excellent display characteristics and is being used in more electronic devices.
[0003]
There are several types of active matrix liquid crystal displays. In the first type, only an active matrix circuit is formed by TFTs, and a circuit for driving the active matrix circuit is configured by an external single crystal semiconductor integrated circuit chip. In this case, it is necessary to connect a semiconductor chip or a semiconductor package around the glass substrate by means of the TAB method or the like, and the apparatus becomes relatively large. Further, the wiring extending from the active matrix circuit is thinned in order to improve the aperture ratio, and the total number of the wiring exceeds 1000, so that there is a technical problem in the connection.
[0004]
In addition, a considerable area is required for this connecting portion, and the alignment accuracy is at most 60 μm due to the difference in thermal expansion coefficient between the wiring on the glass substrate and the wiring of the external chip or the tape in the case of the TAB method. It could not be applied to a high-definition display with a pixel pitch smaller than that. This has become an obstacle to miniaturization of the apparatus. In this type of TFT, a TFT using amorphous silicon that can be manufactured even at a low temperature is used as a TFT instead of obtaining a very high characteristic.
[0005]
The second one is not only an active matrix circuit but also a gate line driver circuit and a source line driver circuit for driving the thin film integrated circuit using TFTs formed on the same substrate. (Hereinafter referred to as a monolithic active matrix display). The gate line and source line driver circuits have circuits such as a shift register, a buffer, or a decoder.
[0006]
This type of device does not use an external semiconductor chip as described above, so that the device is relatively small. Further, since it is not necessary to connect a large number of wirings, this is also advantageous for downsizing the apparatus. In this type, a crystalline silicon TFT having better characteristics has to be used for a drive circuit (driver circuit).
Thus, the second method (monolithic active matrix display) is advantageous for promoting the downsizing of the apparatus.
[0007]
However, with the expansion of demand, further miniaturization, lightening, and thinning have been required. Taking a personal computer as an example, in addition to the display, various semiconductor chips such as a central processing circuit (CPU), main memory, image signal processing device, and image memory are mounted on a main board (main board) other than the liquid crystal display. And at least two substrates of a liquid crystal display and a main board are required.
[0008]
Even in an electronic device having a lower function, downsizing of the entire device is effective. For example, in recent years, in a car navigation system and an electronic notebook, a communication device and a storage device are indispensable in addition to a display. Therefore, conventionally, the communication device and the storage device consisted of two parts, a display and a main body. In order to make the device smaller, thinner and lighter, it is necessary to integrate the display and the main body.
[0009]
That is, it is an apparatus in which various semiconductor circuits are mounted on a single substrate. In order to meet such a demand, several techniques have been proposed. For example, in Japanese Patent Application Laid-Open No. 7-209672, as shown in the block diagram of FIG. A technique for mounting by the on-glass method is disclosed.
[0010]
Here, gate line and source line driver circuits on the substrate and an active matrix circuit 4 (each pixel has a switching transistor 1, a pixel electrode 2, and an auxiliary capacitor 3) are formed by TFTs. In some cases, a signal processing circuit (a circuit that converts a general video signal into a signal used in a display) may also be constituted by a TFT. On the other hand, the CPU, memory, correction memory, and input port are constituted by semiconductor chips. (Figure 3)
[0011]
The input port is a circuit that reads an externally input signal and converts it into an image signal. The correction memory is a memory unique to the panel for correcting an input signal or the like in accordance with the characteristics of the active matrix panel. In particular, this correction memory has information specific to each pixel as a non-volatile memory, and is used for individual correction. That is, if a pixel of the electro-optical device has a point defect, a signal corrected accordingly is sent to the pixels around the point to cover the point defect and make the defect inconspicuous.
[0012]
Alternatively, when the pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so that the brightness is the same as that of the surrounding pixels. Since the pixel defect information varies from panel to panel, the information stored in the correction memory varies from panel to panel.
The CPU and the memory have the same functions as those of a normal computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. In addition to this, various chips may be attached as necessary.
[0013]
When the wire bonding method is employed, the cross-sectional shape shown in FIG. 4 is obtained. That is, the chip 22 is mounted on the glass substrate 20 on which the circuit 21 is formed with the terminal portion facing upward, and the terminal electrode 21 of the circuit and the terminal portion 23 of the chip are connected by the metal bonding wire 24. Then, by sealing this portion with the resin 25, the connecting portion is protected from external impact. In order to keep terminal contact / adhesion stability, the surface of the terminal 21 is preferably a metal such as aluminum.
[0014]
In the case of the wire bonding method, since the resin swells at the terminal connection portion in this way, there is a disadvantage that it becomes thick. On the other hand, in the FCOG method, as shown in FIG. 6, the chip 42 is mounted on the glass substrate 40 on which the circuit 41 is formed with the terminal portion facing downward, and the terminal electrode 41 of the circuit and the terminal portion 43 of the chip are bumped. They are connected by (conductive protrusions) 44 (FIG. 6A) or metal particles 46 (FIG. 6B). The chip is fixed on the substrate 40 by sealing this portion with the resin 45.
[0015]
In the case of the FCOG method, since the thickness of the terminal connection portion is substantially the thickness of the chip, the thickness can be reduced. In the FCOG method, a terminal other than aluminum can be used for the terminal on the glass substrate side. For example, a transparent conductive oxide film (ITO or the like) can also be used. In general, when an active matrix circuit for a liquid crystal display is formed on a glass substrate, the uppermost wiring is often configured using a transparent conductive film, and therefore the FCOG method is particularly preferable in this respect.
[0016]
The appearance of the device manufactured by the FCOG method is as shown in FIG. A substrate 29 is provided so as to face the substrate 30, and a liquid crystal is sandwiched therebetween. The substrate 30 includes an active matrix circuit 31 and peripheral drive circuits 32, 33, and 34 for driving the active matrix circuit 31 using TFTs. Then, a main memory chip 36, an MPU (micro arithmetic circuit) 37, and a correction memory 38 were bonded to the surface on which these circuits were formed, and each chip was connected to a circuit on the substrate 30.
[0017]
On the substrate 30, a wiring terminal portion (wiring connection pad) of ITO (indium tin oxide) as shown in 39 of FIG. 5 (corresponding to 41 of FIG. 6) is formed in the fixed portion 35.
On the other hand, as shown in FIG. 10, a method of forming a CPU and various memories on an active matrix substrate simultaneously with peripheral circuits and matrix circuits using TFTs (hereinafter referred to as a complete monolithic display) has also been proposed. (Japanese Patent Laid-Open No. 7-135327, FIG. 10)
[0018]
[Problems to be solved by the invention]
These conventional techniques have the following problems. First, in the technique of attaching a chip on a glass substrate (the wire bonding method and the FCOG method as described above are collectively referred to as a COG (chip on glass) method), the chip mounting cost is high, There is a problem that the thickness cannot be ignored.
[0019]
In addition, with respect to a fully monolithic display, the characteristics of the transistors required for the CPU are so high that the characteristics required for the switching transistors of the active matrix circuit are incomparable, and the element design rules are different. Therefore, it is not easy to form simultaneously on the same substrate. In addition, since a semiconductor circuit is formed separately, the area other than the display portion increases.
The present invention has been made in view of the above problems, and proposes an electronic device having a non-light emitting display with a new structure.
[0020]
[Means for Solving the Problems]
The present invention solves the above problem by paying attention to a counter substrate (a substrate having a counter electrode, which corresponds to the substrate 29 in FIG. 5) that has not been considered in the conventional method. A conventional counter substrate is provided with only a counter electrode. On the other hand, in the present invention, a semiconductor integrated circuit using TFTs is also provided on the counter substrate, and this semiconductor integrated circuit is a substrate provided with an active matrix circuit (referred to as a TFT side substrate or a matrix substrate). The gate line driver circuit and the source line driver circuit (peripheral circuit region) are provided as much as possible.
[0021]
The semiconductor integrated circuit formed on the counter substrate is designed so that at least 70% of its area overlaps with the peripheral circuit region of the matrix substrate. This is the same as stacking semiconductor integrated circuits in two stages, and is effective in reducing the area other than the display portion as much as possible.
[0022]
For example, as shown in FIG. 1, circuits such as a CPU and a memory are formed on the counter substrate 6. On the other hand, the matrix substrate 5 is provided with an active matrix circuit, a gate line and a source line driver circuit, and other circuits (for example, a signal processing circuit) as necessary. However, for the purpose of reducing the area other than the display portion, providing only the active matrix circuit, the gate line, and the source line driver circuit has a great effect. The circuit of the electronic device of FIG. 1 is substantially the same as that shown in FIG. 3 or FIG. (Figure 1)
[0023]
The connection between the substrates may be a method of connecting terminals provided on each substrate by wiring as in the prior art. However, as shown in FIG. 2, the substrates may be connected by conductive projection-like terminals (interconnections, bumps) 7. FIG. 2 is a schematic cross-sectional view of an electronic device having a liquid crystal display according to one embodiment of the present invention. A brief description will be given with reference to FIG. The matrix substrate 5 is provided with a peripheral drive circuit region 9 and a matrix region 10.
[0024]
The counter substrate 6 is provided with a TFT semiconductor integrated circuit region 8 in addition to the counter electrode 11. For the purpose of protecting the circuit and enhancing the insulation, the semiconductor integrated circuit region 8 is formed of an organic resin (for example, polyimide, polyamide, polyimide amide, acrylic, epoxy, etc.) or an inorganic material (silicon oxide, silicon nitride, silicon oxynitride). (Oxynitride) or the like) and an opening may be formed only in the portion where the bump is provided.
[0025]
Bumps 7 are provided on the counter substrate 6 by a conductive material such as gold (Au), the counter substrate 6 and the matrix substrate 5 are overlapped, and liquid crystal 14 is injected. Crimp to the terminal provided in 9. Finally, the sealant 13 prevents the liquid crystal 14 from leaking. Actually, a spacer is also enclosed for the purpose of keeping the thickness between the substrates constant.
[0026]
In general, in the conventional method, the sealant is often provided inside the peripheral drive circuit. However, for the purpose of reducing the area other than the display portion, as shown in FIG. Sealing agent outside the circuit (for example, Japanese Patent Laid-Open No. 8-220560), or as shown in FIG. 2B, overlaps all or part of the peripheral drive circuit (for example, Japanese Patent Laid-Open No. 4-324826). May be provided. (Figure 2)
[0027]
In the present invention, the characteristics, fabrication process, fabrication conditions, structure, material, and the like of the TFT of the counter substrate and the TFT of the matrix substrate are different from each other, so that characteristics that cannot be implemented only by the respective semiconductor integrated circuits can be obtained. It can be complemented and a greater effect can be obtained. Although details will be described in the embodiments, it is generally preferable that the semiconductor integrated circuit on the counter substrate is a circuit that requires a higher speed operation than the peripheral drive circuit on the matrix substrate, and that the TFT has characteristics and structure corresponding to the circuit.
[0028]
In the conventional complete monolithic active matrix display (FIG. 10), it is difficult to obtain TFTs having different characteristics because it is necessary to simultaneously produce TFTs on the matrix substrate. Since TFTs can be manufactured separately on the substrate, the TFT characteristics can be different. For example, it is effective to change the design rule, doping amount (dose amount), process maximum temperature, gate insulating film thickness, and the like between the counter substrate and the matrix substrate.
[0029]
In the present invention, the TFT manufacturing method is not particularly limited, and a known SOI (silicon on insulator) technique may be used. For example, a TFT semiconductor integrated circuit formed on another substrate as disclosed in JP-A-8-153777, JP-A-8-250745, JP Salemo et al. (SID International Symposium, DIgest of Technical Papers, May 1992, pp63-66), etc. A method of peeling and transferring to another substrate may be used.
Of course, it is needless to say that a synergistic effect may be obtained by combining a TFT having a specific structure and manufacturing method with the present invention. An example is shown below.
[0030]
【Example】
[Example 1]
The display of this embodiment will be described with reference to FIGS. This display consists of two substrates 5 and 6. The substrate 5 is a so-called matrix substrate, and has an active matrix and gate line and source line driver circuits for driving the active matrix. Here, the gate line driver circuit includes a shift register, a buffer, and the like, and the source line driver circuit includes a sample and hold circuit in addition to them.
[0031]
In the above driver circuit, the shift register may be replaced with a counter and a decoder having equivalent functions. In this embodiment, the source line driver circuit is constituted by two systems of shift registers (shift registers 1 and 2) and is driven with a phase difference of a half cycle.
[0032]
On the other hand, the substrate 6 has a signal processing circuit in addition to the counter electrode, processes the input video signal, and outputs three clock pulses and a four-divided video signal. The clock pulse is sent to the matrix substrate by three interconnections 7a, and the video signal is sent by four interconnections 7b.
[0033]
Further, the signal processing device supplies a potential to the counter electrode. In this electronic apparatus, a circuit corresponding to a so-called CPU is not mounted because it is complicated and unnecessary for explaining the basic idea of the present invention. It can also be installed.
The video input terminal and the power supply terminal are provided on the matrix substrate 5, and they are sent to the counter substrate 6 through the interconnection 7c. (Fig. 7)
[0034]
The reason why the video signal is divided as described above in the display of this embodiment is mainly to reduce the operation speed of the source line driver circuit and reduce the burden. For example, in a display with 50,000 pixels, in order to process 30 frames of image information per second, the processing speed of the source line driver circuit is:
50,000 (pixels) x 30 (frames / second) = 1.5 MHz
If it is.
[0035]
This can also be processed in a known TFT (for example, Japanese Patent Publication Nos. 5-9794 and 2-61032) using polysilicon having a design rule of about 10 μm. However, as the number of pixels increases, processing cannot catch up. For example, on a VGA display, the number of pixels is
640 (columns) × 480 (rows) × 3 (primary colors) = 921600 (pixels)
The processing speed of the source line driver circuit is as high as 28 MHz.
[0036]
A first method for solving this is a method of providing a plurality of shift registers. For example, two shift registers are provided in parallel, and each of them transmits a pulse whose phase is shifted by a half cycle. By doing so, the processing speed of the source line driver circuit can be halved.
The second method is a method in which a video signal is divided and a plurality of signals are simultaneously output from a source line driver circuit and processed. For example, the operation speed can be reduced to ¼ by dividing the video signal into four and sampling it with one shift register.
[0037]
In this display, since the video signal is divided into four and has two shift registers, the operation speed can be reduced to 1/8.
Since these techniques are known techniques, they will not be described in detail any more. However, if an appropriate signal is input by the above method, the burden on the source line driver circuit can be sufficiently reduced. However, when a video signal processing circuit is also built in, a circuit for processing at the above speed is absolutely necessary in a circuit for processing a signal input to the source line driver circuit. That is, the signal processing circuit is a circuit that requires high-speed operation. The source line driver circuit is a circuit that operates at a lower speed. In general, the gate line driver circuit operates at a lower speed than the source line driver circuit.
[0038]
According to the present invention, the circuit provided on the counter substrate among the two substrates constituting the display can exhibit an effect by providing a circuit that requires higher speed operation than that of the matrix substrate. In this display, the signal processing circuit on the counter substrate needs to operate at a speed eight times faster than that of the matrix substrate. One countermeasure is to change the design rule of the signal processing circuit to 0.35 or less of the matrix substrate. In this display, the design rule of the signal processing circuit is 2 μm, and the design rule of the matrix substrate is 8 μm.
[0039]
In the circuit of the matrix substrate, it is necessary to form a pattern in an area equivalent to the expansion of the active matrix, and it is difficult to engrave the circuit with a design rule of 2 μm. However, the counter substrate circuit has few such restrictions, and it is easy to form a circuit with a design rule of 2 μm in a very limited area.
[0040]
FIG. 8 shows an outline of the arrangement of each circuit of the display. In the matrix substrate 5 (bottom of FIG. 8), an active matrix region 10 is provided at the center, and a peripheral circuit region 9 is provided on the left and above the active matrix region 10. Here, a source line driver circuit and a gate line driver circuit are provided. Further, a plug-in type terminal 15 for connecting to the outside is provided at the left end of the substrate 5. For this purpose, the matrix substrate 5 is longer than the counter substrate 6 by x.
[0041]
On the other hand, the counter substrate 11 (upper in FIG. 8) is provided with a counter electrode 11 in a region corresponding to the active matrix region of the matrix substrate. Further, a semiconductor integrated circuit region 8 is provided in the upper left portion so as to overlap with the peripheral circuit of the matrix substrate. A signal processing circuit is provided here. Thus, since the semiconductor integrated circuit region 8 has a limited area compared to the active matrix region 10, it is not difficult to form a circuit with a small design rule only in this portion.
[0042]
In this display, a sealing region 13 is provided outside the peripheral circuit region 9 and the active matrix region 10. Further, the interconnection 7 (corresponding to 7a, 7b and 7c in FIG. 7) is formed at the upper left of the active matrix region 10. However, it is provided so as not to overlap with the peripheral circuit 9 and the semiconductor integrated circuit 8. This is because a large pressure is applied around the interconnection, thereby preventing the circuit from being destroyed.
[0043]
In this embodiment, the TFT is manufactured using a technique using polysilicon by a known thermal solid phase growth method, and a TFT manufacturing process formed on the matrix substrate 5 and a TFT formed on the counter substrate 6 are manufactured. The process is the same.
In the display of FIG. 8, connection terminals (video terminals, power supply terminals, etc.) 15 to the outside may be provided on the counter substrate side. As is apparent from the circuit block diagram of FIG. 7, the number of interconnection terminals can be reduced by one.
[0044]
Further, the interconnection 7 may be provided in the sealing region 13. Since the interconnection is a mechanical connection, it is unstable. In the sealing region, since it is fixed by the sealant, it becomes more stable.
FIG. 9 shows an example in which the connection terminal 15 to the outside is provided on the counter substrate side and the interconnection 7 is provided in the sealing region.
[0045]
[Example 2]
In FIG. 11, the schematic diagram of the cross section of the display of a present Example is shown. The circuit configuration of this display is the same as that shown in FIGS. 7 and 8, but in this embodiment, the TFT manufacturing process is different between the matrix substrate and the counter substrate, and other parameters are set accordingly. To change.
[0046]
FIG. 11 will be described. A semiconductor circuit including an N-channel TFT 53 and a P-channel TFT 54 is configured on the matrix substrate 5, and a semiconductor circuit including an N-channel TFT 51 and a P-channel TFT 52 is configured on the counter substrate 6. Has been. The semiconductor circuits on both the substrates face each other and are electrically connected by the interconnection 7.
[0047]
The interconnection is a gold bump, and a contact can be stably formed by using conductive oxide films 55 and 56 such as indium tin oxide film (ITO) at the terminal portion.
In this display, the matrix substrate uses a known low-temperature polysilicon TFT technology. In this method, an inexpensive alkali-free glass substrate is used as the substrate, and the maximum process temperature is set to about 600 ° C. Amorphous silicon is crystallized by a thermal solid phase growth method at about 600 ° C. In order to promote crystallization, a catalyst material that promotes crystallization, such as nickel, may be used (for example, JP-A-6-296020).
[0048]
However, it is impossible to form a gate insulating film by a thermal oxidation method used in a normal semiconductor process. For this reason, the gate insulating film uses a film deposited by a vapor deposition method. The insulating film formed by the vapor deposition method has many defects, and a thickness of 1000 mm or more is necessary in order to improve the pressure resistance. In this embodiment, it is 1000 mm.
[0049]
On the other hand, a known high-temperature polysilicon TFT technology is used for the counter substrate. In this method, an expensive quartz substrate is used as the substrate, and the maximum process temperature is set to 600 ° C. or higher, for example, 1000 ° C. Therefore, it is possible to crystallize amorphous silicon and to form a gate insulating film by a thermal oxidation method. A silicon oxide film obtained by a thermal oxidation method has excellent electrical characteristics. In this embodiment, the thickness is 500 mm. Thus, since the gate insulating film can be thinned, a TFT capable of high speed operation can be obtained.
[0050]
Regarding the design rule, the matrix substrate is 8 μm and the counter substrate is 2 μm. As is apparent from the figure, the gate width of the matrix substrate is larger than that of the counter substrate, and thus the latter design rule is smaller than the former. Also, regarding the thickness of the gate insulating film, the former is thicker than the latter. (Fig. 11)
[0051]
As the design rule is reduced, the scaling rule may require increasing the doping concentration or lowering the power supply voltage. Also in this regard, in the present invention, since the semiconductor circuits of the matrix substrate and the counter substrate are independently manufactured, there is no obstacle. Also in this embodiment, the dose amount of the counter substrate may be higher than that of the matrix substrate. Further, the power supply voltage of the counter substrate may be lower than that of the matrix substrate.
[0052]
Example 3
The structure and manufacturing process of the display of this embodiment will be described with reference to FIGS. The circuit configuration of this display is the same as that of the first embodiment, and is shown in FIGS. In this display, the TFT circuit on the matrix substrate side is formed by using low-temperature polysilicon technology, while the TFT circuit on the counter substrate is a semiconductor circuit formed on a single crystal silicon wafer and peeled off and transferred onto a glass substrate. It is.
[0053]
In this example, alkali-free glass was used for both the matrix substrate and the counter substrate. A glass substrate is less expensive than a quartz substrate, but its heat resistance is inferior, and there is a great difficulty in manufacturing a high-performance TFT. However, as disclosed in JP-A-8-153777, JP-A-8-250745, JP Salemo et al. (SID International Symposium, DIgest of Technical Papers, May 1992, pp63-66), etc., special SOI technology, that is, other substrates. In the method of peeling the semiconductor integrated circuit of the TFT formed in this way and transferring it to another substrate, the restrictions on the substrate to which the TFT is transferred are remarkably reduced.
[0054]
The cross section of the counter substrate near the semiconductor circuit of this display is as shown in FIG. FIG. 12A is a view at a relatively small magnification. The left side of the drawing is a portion 107 (corresponding to 8 in FIG. 2) provided with a semiconductor integrated circuit, and the right side is a terminal portion provided with an interconnection (corresponding to 7 in FIG. 2). A pattern of electrical wiring 104 made of a material such as a conductive oxide is formed on the substrate 101, and further, protrusions (bumps) 106 are provided with a material such as gold. This is for fixing the semiconductor integrated circuit 102 to the counter substrate 101.
[0055]
On the other hand, the semiconductor integrated circuit 102 has substantially the same thickness as that of the TFT. For this purpose, the surface of the connection portion is made of a material such as a conductive oxide whose contact resistance does not fluctuate due to oxidation. 105 is provided and brought into contact with the bump 106. Then, a resin 103 is sealed between the semiconductor integrated circuit 102 and the substrate 101 for mechanical fixation. (Fig. 12 (A))
[0056]
FIG. 12B is an enlarged view of the contact portion surrounded by the dotted line in FIG. Reference numerals indicate the same as those in FIG. Further, FIG. 12C is an enlarged view of a portion surrounded by a dotted line in FIG. That is, the semiconductor integrated circuit has a structure in which an N-channel TFT (112) and a P-channel TFT (113) are sandwiched between a base insulating film 111, an interlayer insulator 114, or a passivation film 115 such as silicon nitride. . (FIGS. 12B and 12C)
[0057]
Usually, silicon oxide is used as the base film 111 when forming a semiconductor integrated circuit. However, since it alone is inferior in moisture resistance and the like, a passivation film must be separately provided thereon. As shown in FIG. 13, the semiconductor circuit 102 is required to have a thickness enough to enter a gap between the matrix substrate and the counter substrate (although it varies depending on the liquid crystal material, it is approximately several μm to 10 several μm). Usually, it is 0.5-5 micrometers, and the conditions are satisfied.
[0058]
If a liquid crystal sealing (sealing) process is performed with a sealing agent 13 such as an epoxy resin on or outside the semiconductor integrated circuit portion 8 as shown in FIG. 2A or FIG. 2B, Since the liquid crystal material 14 is filled between the substrates 5 and 6, no movable ions or the like enter from the outside, and it is not necessary to provide a special passivation film.
[0059]
As for the contact portion, in addition to the method using bumps, as shown in FIG. 12D, conductive particles such as gold grains 108 are diffused into the adhesion portion, thereby making electrical contact. You may make it obtain. The diameter of the particles may be slightly larger than the distance between the semiconductor integrated circuit 102 and the substrate 101. (Fig. 12D)
[0060]
FIG. 13 shows a state in which the counter substrate having the TFT semiconductor integrated circuit shown in FIG. A substrate 101 (corresponding to 6 in FIG. 2) on the upper side of the figure is a counter substrate, which is provided with a semiconductor integrated circuit 102, a terminal portion 104 on which an interconnection 7 is provided, and a counter electrode 11. If the terminal portion is formed of a transparent conductive film (for example, indium tin oxide), the pixel electrode 11 and the terminal portion 104 can be formed simultaneously.
[0061]
On the other hand, the peripheral circuit region 116 and the active matrix region 10 are provided on the matrix substrate 5. These TFT circuits are formed by the low-temperature polysilicon technique shown in the second embodiment. Further, the terminal portion 117 of the interconnection 7 is formed of a material such as a conductive oxide. Then, an interconnection 7 is formed between the terminal portions 104 and 117. (Fig. 13)
[0062]
Hereinafter, a process of forming a semiconductor integrated circuit on the counter substrate and obtaining the counter substrate as shown in FIG. 12 will be described with reference to FIGS. FIG. 14 shows an outline of a process for forming a semiconductor integrated circuit on a single crystal silicon wafer. FIG. 15 shows an outline of a process for transferring and mounting the semiconductor integrated circuit obtained above on a substrate of a liquid crystal display.
[0063]
First, a silicon oxide layer 122 having a thickness of 2000 to 5 μm is provided on a single crystal silicon wafer (thickness 0.3 μm) 121, and further a crystalline silicon layer is formed. The thickness of the silicon layer greatly affects the required characteristics of the semiconductor circuit, but in general, a thinner one is preferred. In this embodiment, it is 400 to 600 mm.
[0064]
As a process up to this point, a silicon layer may be deposited on the silicon oxide layer 122, but for example, a SIMOX (Separation by implanted oxygen) substrate may be used. A SIMOX substrate is a substrate in which oxygen ions are implanted at a certain acceleration on a single crystal silicon wafer, and a silicon oxide layer is formed thereunder while leaving a single crystal silicon layer on the surface. The SIMOX substrate is advantageous because a TFT can be formed using a single crystal silicon layer.
[0065]
In order to obtain crystalline silicon by a deposition method, a method of irradiating amorphous silicon with intense light such as a laser (laser annealing method) or a method of solid phase growth by thermal annealing (solid phase growth method) is used. It is done. Even in the case of adopting the solid phase growth method, a method (seed growth method) in which a single crystal is grown using a contact portion with a single crystal silicon wafer as a seed (seed crystal) by moving the heated portion with a strip heater is used. May be.
[0066]
Further, when using the solid phase growth method, as disclosed in JP-A-6-244104, when a catalyst element such as nickel is added to silicon, the crystallization temperature can be lowered and the annealing time can be shortened. Further, as described in JP-A-6-318701, silicon crystallized once by the solid phase growth method may be laser-annealed. Which method should be adopted may be determined depending on the required characteristics of the semiconductor circuit, the heat resistance of the substrate, and the like.
[0067]
The silicon layer thus formed is etched to form island-like silicon regions 123 and 124.
Thereafter, a silicon oxide gate insulating film 125 having a thickness of 1200 mm is deposited by plasma CVD method or thermal CVD method, and further subjected to heat treatment in an oxidizing atmosphere at 950 to 1050 ° C. to thereby provide an interface between the insulating film and the silicon layer. Improve properties.
[0068]
Next, gate electrodes and wirings 126 and 127 are formed of crystalline silicon having a thickness of 5000 mm. The gate wiring may be a metal such as aluminum, tungsten, or titanium, or a silicide thereof.
Further, when forming a metal gate electrode, as disclosed in JP-A-5-267667 or 6-338612, the upper surface or side surface thereof may be coated with an anodic oxide. What kind of material the gate electrode is made of may be determined depending on required characteristics of the semiconductor circuit, heat resistance of the substrate, and the like. (Fig. 14 (A))
[0069]
Thereafter, N-type and P-type impurities are introduced into the island-like silicon region by means of ion doping or the like in a self-aligned manner to form the N-type region 128 and the P-type region 129. Then, an interlayer insulator (a silicon oxide film having a thickness of 5000 mm) 130 is deposited by a known means. And a contact hole is opened in this, and the aluminum alloy wiring 131-133 is formed. (Fig. 14B)
[0070]
Further, a silicon nitride film 134 having a thickness of 2000 mm is deposited thereon as a passivation film by a plasma CVD method, and a contact hole leading to the output terminal wiring 133 is formed therein. Then, an electrode 105 having an indium tin oxide film (ITO, thickness of 1000 mm) is formed by sputtering.
Thereafter, a gold bump 106 having a diameter of about 10 μm and a height of about 1 μm is formed on the ITO electrode 105. In this way, a semiconductor integrated circuit is obtained on a single crystal silicon wafer. (Figure 14 (C))
[0071]
On the other hand, the electrode 104 is also formed on the counter substrate 101 with ITO having a thickness of 1000 mm. Although not shown in the figure, a counter electrode is also formed simultaneously with ITO. In this embodiment, Corning 7059 having a thickness of 1.1 mm is used as the counter substrate. In addition, alkali-free or low-alkali glass such as Corning 1737, NH Techno Glass NA45, 35, and Nippon Electric Glass OA2 are used. Then, a single crystal silicon wafer substrate 121 on which a semiconductor integrated circuit is formed is bonded to the substrate 101 by applying pressure. At this time, the electrode 104 and the electrode 105 are electrically connected by the bump 106. (Fig. 15 (A))
[0072]
Next, an adhesive 103 mixed with a thermosetting organic resin is injected into the gap between the single crystal silicon wafer substrate 121 and the counter substrate 101. Note that the adhesive may be applied to either surface before the two substrates are pressure-bonded.
Then, the electrical connection and mechanical bonding between the substrates 101 and 121 were completed by treating the substrate in a nitrogen atmosphere at 120 ° C. for 15 minutes. It should be noted that a method of performing this bonding may be employed after testing whether or not the electrical connection is insufficient before complete bonding by the method disclosed in Japanese Patent Laid-Open No. 7-14880. (Fig. 15 (B))
[0073]
Next, the silicon wafer substrate 121 is thinned. The process may be mechanical polishing or chemical mechanical polishing, but chemical etching is preferable in order to reduce damage to the device. For example, halogen fluoride (such as chlorine trifluoride) is preferable for the above purpose because it has the selectivity of etching silicon but not oxides such as silicon oxide and ITO.
[0074]
Specifically, the silicon wafer substrate 121 is polished to a thickness of 10 to 100 μm to make a thin piece, which is then subjected to halogen fluoride atmosphere (for example, fluorine trichloride (ClF _Three ) And nitrogen mixed gas stream. The flow rates of fluorine trichloride and nitrogen are both 500 sccm. The reaction pressure is 1 to 10 Torr. The silicon wafer is etched by placing it at room temperature. (Figure 15 (C))
[0075]
Etching with halogen fluoride has a feature that it proceeds more on the surface irradiated with light (ultraviolet light or laser light), so that light is applied to the back surface (surface on which no TFT is formed) of the single crystal silicon wafer substrate 121. May be irradiated. Similar effects can be obtained by irradiating ions or electron beams.
Further, after the lapse, the peeling layer is completely etched, and the bottom surface of the underlying silicon oxide layer 122 is exposed. In the etching with halogen fluoride, the etching stops at the bottom surface of the underlying silicon oxide layer, so that the bottom surface is extremely flat. (Fig. 15D)
[0076]
In this way, the formation of the semiconductor integrated circuit on the counter substrate 101 is completed. Such a circuit transfer technique is difficult in a large area, but can be relatively easily performed in a limited area. In the present invention, the area of the semiconductor integrated circuit on the counter substrate is much smaller than the area of the active matrix, and a large characteristic can be enjoyed with a small risk.
[0077]
【The invention's effect】
As described above, the area of the display portion can be improved by forming a semiconductor integrated circuit on the counter substrate so as to overlap with a peripheral circuit of the matrix substrate. Such a display or an electronic device having a display is advantageous in downsizing, and is expected to meet industrial demand. Thus, the present invention is industrially beneficial.
[0078]
Note that in this specification, the TFT manufacturing process or structure is not particularly referred to, but this is because the present invention is not an invention having an effect only on a TFT having a specific structure. The present invention is effective in TFTs having various structures, and in particular, has an advantage that the TFTs of the matrix substrate and the counter substrate can be compensated for each other by making the structure, manufacturing process, size and the like different from each other. Will be apparent from the description of the examples.
[Brief description of the drawings]
FIG. 1 illustrates an example of a structure of an electronic device of the invention.
FIG. 2 illustrates an example of a cross-sectional structure of an electronic device of the invention.
FIG. 3 illustrates a configuration of a conventional electronic device.
FIG. 4 is a diagram illustrating a configuration of a conventional electronic device.
FIG. 5 illustrates a structure of a conventional electronic device.
FIG. 6 is a diagram illustrating a configuration of a conventional electronic device.
FIG. 7 is a diagram illustrating a configuration of a display according to an embodiment.
FIG. 8 is a diagram illustrating a configuration of a display according to an embodiment.
FIG. 9 is a diagram illustrating a configuration of a display according to an embodiment.
FIG. 10 illustrates a structure of a conventional electronic device.
FIG. 11 is a diagram showing a cross section of a display according to an embodiment.
FIG. 12 is a diagram showing a cross-sectional state of the counter substrate of the display of the example.
FIG. 13 is a diagram showing a cross section of a display according to an embodiment.
14A and 14B illustrate a cross-sectional view of a manufacturing process of a semiconductor integrated circuit on a counter substrate of a display according to an embodiment.
FIG. 15 is a diagram illustrating a cross-section of a mounting process of a semiconductor integrated circuit on a counter substrate of a display according to an embodiment.
[Explanation of symbols]
1 Switching transistor
2 Pixel electrode
3 Auxiliary capacity
4 Active matrix area
5 Matrix substrate
6 Counter substrate
7 Bump
8 Semiconductor integrated circuit area
9 Peripheral drive circuit area
10 Active matrix area
11 Counter electrode
12 Protective insulating film
13 Sealant
14 Liquid crystal materials
20, 40 Glass substrate (matrix substrate)
21, 41 TFT circuit wiring terminals
22, 42 Semiconductor chip (IC chip)
23, 43 Semiconductor chip terminal
24 Bonding wire
25, 45 resin
29 Counter substrate
30 Matrix substrate
31 Active matrix circuit area
32-34 Peripheral drive circuit area
35 Chip bonding area
36 Main memory
37 MPU
38 Auxiliary memory
39 Wiring connection pads
44 Bump
46 metal particles

Claims (4)

A first substrate having a semiconductor integrated circuit associated with the active matrix circuit and before Symbol active matrix circuit,
A second substrate having a counter electrode,
A semiconductor integrated circuit using TFT is formed on the second substrate,
The semiconductor integrated circuit formed on the first substrate and the semiconductor integrated circuit formed on the second substrate are electrically connected by a conductive material,
Wherein the conductive material is a bus amplifier or conductive particles,
The conductive material in the sealing material for sealing the first substrate and the second substrate, formed in said semiconductor integrated circuit is formed on the second substrate and the first substrate provided so as not to overlap with the semiconductor integrated circuit,
Wherein said semiconductor integrated circuit formed on a second substrate, an electronic device, characterized in that overlaps the formed on the first substrate the semiconductor integrated circuit. A first substrate having a semiconductor integrated circuit associated with the active matrix circuit and before Symbol active matrix circuit,
A second substrate having a counter electrode,
A semiconductor integrated circuit using TFT is formed on the second substrate,
The semiconductor integrated circuit formed on the first substrate and the semiconductor integrated circuit formed on the second substrate are electrically connected by a conductive material,
Wherein the conductive material is a bus amplifier or conductive particles,
The conductive material in the sealing material for sealing the first substrate and the second substrate, formed in said semiconductor integrated circuit is formed on the second substrate and the first substrate provided so as not to overlap with the semiconductor integrated circuit,
Wherein said semiconductor integrated circuit formed on the second substrate overlaps with the formed first substrate the semiconductor integrated circuit,
The electronic device, wherein the semiconductor integrated circuit formed on the second substrate is formed by transfer. In claim 1 or claim 2,
Wherein said semiconductor integrated circuit formed on a second substrate, an electronic device, characterized in that overlap with the semiconductor integrated circuit in which at least 70% is formed on the first substrate of the area. In any one of Claims 1 thru | or 3,
The semiconductor integrated circuit formed on the first substrate includes a TFT,
The electronic device, wherein the TFT and the TFT used for the semiconductor integrated circuit formed over the second substrate are different in any of characteristics, structures, and materials.

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