JP4125933B2 - Processor system with common memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a processor system configured to access one common memory from a plurality of processors, and in particular, a common that can make sure that the time required for accessing the common memory is smaller than a predetermined maximum time. The present invention relates to a processor system having a memory.
[0002]
[Prior art]
As a processor system having a common memory for accessing a common memory by a plurality of processors, a system using a ring bus as described in, for example, Japanese Patent Laid-Open No. 11-13412 has been proposed. In this method, the processor that wants to access the common memory first sends a request signal as a broadcast signal so that it does not interfere with access from other processors and is not disturbed by access from other processors. After confirming the above, it is possible to actually access the common memory.
[0003]
[Problems to be solved by the invention]
However, in the processor system having the conventional common memory described above, when the ring bus is used for access from another processor when it is desired to access the common memory, a waiting time is required until the ring bus becomes free. . Especially in situations where many processors request access at the same time, this waiting time becomes large and the time required to access the common memory cannot be accurately estimated, and in some cases, the access must be given up. There was a problem that the situation was possible.
The present invention has been made in consideration of the above points, and an object of the present invention is to provide a processor system having a common memory that can make the time required for accessing the common memory smaller than a predetermined maximum time. To do.
[0004]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a common memory for reading and writing from a plurality of processors, a signal ring bus for transmitting an access signal between the common memory and the processor, and a timing ring bus for transmitting a timing signal. A timing generator that transmits the timing signal having a finite timing value to the timing ring bus, a plurality of processors including a bus controller, and a signal between the signal ring bus and the common memory. A memory control unit that mediates between the processor, the processor core, a dual-port memory that can be read and written independently from the processor core side and the bus control unit side, a distinction between writing and reading, a common memory address And common memory access instructions consisting of dual-port memory addresses A request register for storing; a response register for storing a common memory read instruction including a common memory address and a dual port memory address; a request flag that is set and reset in accordance with writing to and reading from the request register; A FIFO structure having a response flag that is set and reset in accordance with writing to and reading from the response register, and wherein the bus control unit stores the content of the common memory access instruction to which an end bit capable of random writing is added If the request flag is set, the contents of the common memory access instruction stored in the request register are stored and then the request flag is reset. If the response flag is reset A request queue for setting the response flag after generating the common memory read instruction content and storing it in the response register, a timing memory for storing a predetermined access timing value capable of transmitting or receiving an access signal, and the request While reading the common memory access instruction content stored in the queue and generating an access signal based on this, the access timing value is obtained from the timing memory, and the timing value of the timing ring bus is the same as the access timing value. When matched, a transmission control unit that transmits the access signal to the signal ring bus, and an access timing value from the timing memory, and when the timing value of the timing ring bus matches the access timing value, Access from the signal ring bus A reception control unit that receives the access signal, extracts a memory read result, stores it in a corresponding address of the dual port memory, and sets a corresponding end bit of the request queue, and the memory control unit The access signal input from the signal ring bus is passed to the common memory, and when the access signal means reading , the memory read result from the common memory is output to the signal ring bus as an access signal to the corresponding processor. and, if the access signal wherein the input means writing, which is constituted as and writes the data into the common memory.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a first embodiment of a processor system having a common memory according to the present invention. FIG. 1 shows a case in which one common memory is accessed by five processors. In FIG. 1, 111, 112, 113, 114, 115 are processors, 121, 122, 123, 124, 125 are bus control units, 13 is a timing generation unit, 14 is a signal ring bus, 15 is a timing ring bus, Reference numeral 16 is a memory control unit, and 17 is a common memory.
[0006]
The timing generator 13 generates a timing signal including a cyclic timing value and transmits the timing signal to the timing ring bus 15. Here, for example, it is assumed that the timing value takes a cyclic value such that it increases by 1 from 0 to 7 and then returns to 0.
[0007]
As an example, the access operation to the common memory 17 will be described using the processor 111 and the bus control unit 121 as an example. The processor 111 instructs the bus control unit 121 to transmit an access signal when writing to or reading from the common memory 17 is desired. The bus control unit 121 receives an instruction from the processor 111, generates an access signal, and accesses the signal ring bus 14 when the timing value of the timing ring bus 15 reaches a predetermined access timing value. Send a signal. Here, it is assumed that 0, 1, 2, 3, 4, and 5 are set for the bus control units 121, 122, 123, 124, and 125, respectively, as access timing values. Therefore, the bus control unit 121 transmits an access signal to the signal ring bus 14 when the timing value of the timing ring bus 15 is 0. The access signal includes information such as distinction between writing and reading, a transmission source address corresponding to the processor 111, a common memory address, and writing data in the case of writing.
[0008]
The memory control unit 16 constantly monitors the signal ring bus 14 and receives it when an access signal is received. If the received access signal means writing, the common memory address and write data are extracted, and the write data is written to the common memory address of the common memory 17. On the other hand, if the received access signal means reading, the source address and the common memory address are extracted, and reading is performed from the common memory address of the common memory 17.
[0009]
In the case of the read process, the read result is output from the common memory 17 generally with a time delay. The memory control unit 16 generates an access signal from the read result, and the timing value of the timing ring bus 15 is 0 because the access timing value predetermined for the transmission source address corresponding to the processor 111 is 0. At this time, an access signal is transmitted to the signal ring bus 14.
[0010]
The bus control unit 121 receives an access signal when the timing value of the timing ring bus 15 is zero. Then, the reading result is extracted from the access signal and passed to the processor 111, whereby the processor 111 completes the reading process from the common memory. In this example, only one value is assumed as the access timing value, but a plurality of values can be set. That is, for example, since the timing values 6 and 7 are unassigned, if they are assigned to the bus control unit 121, the common memory access efficiency from the bus control unit 121, that is, the common memory access efficiency from the processor 111. Can be improved.
[0011]
FIG. 2 is a block diagram showing a configuration example of the processor and the bus control unit in the processor system of the present invention. In FIG. 2, 21 is a processor, 22 is a bus control unit, 211 is a processor core, 212 is a dual port memory (hereinafter abbreviated as DP memory), 213 is a response register, 214 is a request register, 215 is a response flag, 216 Is a request flag, 221 is a request queue, 222 is a timing memory, 223 is a transmission control unit, and 224 is a reception control unit. Similar to the above description, the processor 111 and the bus control unit 121 in FIG. 1 will be described as an example.
[0012]
When the processor 111 (corresponding to the processor 21 in FIG. 2) wants to write to or read from the common memory 17, the processor core 211 checks the state of the request flag 216. The request flag 216 is a 1-bit flag having two states of set and reset, and is set when there is a common memory access request, and is reset when there is no common memory access request. If the request flag 216 is reset, the processor core 211 stores, in the request register 214, the distinction between writing and reading, the common memory address, and in the case of writing, the DP memory address where the write data is stored. The request flag 216 is set. If the request flag 216 is set, the preceding common memory access request has not yet been processed, and the processor core 211 must wait for processing.
[0013]
The bus control unit 121 (corresponding to the bus control unit 22 in FIG. 2) monitors the request flag 216, and when it is set, reads the contents of the request register 214 and stores the contents in the request queue 221. The request flag 216 is reset. The request queue 221 is a memory having an irregular FIFO structure to which an end bit that can be written randomly is added, and contents other than the end bit can be sequentially read from the previously stored contents.
[0014]
The timing memory 222 stores an access timing value that permits predetermined transmission or reception to the bus control unit 121. The access timing value for the bus control unit 121 is assumed to be zero.
[0015]
The transmission control unit 223 reads the content written first from the request queue 221 and generates an access signal based on this. The access signal includes information such as distinction between writing and reading, a transmission source address corresponding to the processor 111, a common memory address, and write data obtained from the DP memory address of the DP memory in the case of writing. On the other hand, the transmission control unit 223 knows the access timing value 0 from the timing memory 222 and transmits an access signal to the signal ring bus 14 when the timing value of the timing ring bus 15 is 0. In addition, the transmission control unit 223 sets a corresponding end bit of the request queue 221 in the case of a read process. If there is no content to be read in the request queue 221, it waits for the content to be read to be stored.
[0016]
The memory control unit 16 constantly monitors the signal ring bus 14 and receives it when an access signal is received. If the received access signal means writing, the common memory address and write data are extracted, and the write data is written to the common memory address of the common memory 17. On the other hand, if the received access signal means reading, the source address and the common memory address are extracted, and reading is performed from the common memory address of the common memory 17.
[0017]
In the case of the read process, the read result is output from the common memory 17 generally with a time delay. The memory control unit 16 generates an access signal from the read result, and the timing value of the timing ring bus 15 is 0 because the access timing value predetermined for the transmission source address corresponding to the processor 111 is 0. At this time, an access signal is transmitted to the signal ring bus 14.
[0018]
In the bus control unit 121 (corresponding to the bus control unit 22 in FIG. 2), the reception control unit 224 receives an access signal when the timing value of the timing ring bus 15 is 0. Then, the read result and the DP memory address are extracted from the access signal, the read result is written to the DP memory address of the DP memory 212, and then the corresponding end bit of the request queue 221 is set. In general, the DP memory 212 cannot perform writing from the reception control unit 224 and reading from the transmission control unit 223 at the same time. However, when the access signal is generated for the writing process in the transmission control unit 223, it is considered that there is little problem in particular because reading from the DP memory 212 is performed prior to transmission.
[0019]
The request queue 221 checks the end bit in order, and if it is set, checks the status of the response flag 215. The response flag 215 is a 1-bit flag having two states, set and reset, and is set when there is a common memory read result, and is reset when there is no common memory read result. If the response flag 215 is reset, the request queue 221 stores the common memory address and the DP memory address in the response register 213, and then sets the response flag 215. If the response flag 215 is set, the request queue 221 has to wait for processing because the preceding common memory read result has not yet been processed.
[0020]
In the processor 112 (corresponding to the processor 21 in FIG. 2), the processor core 211 examines the state of the response flag 215, and if it is set, reads the contents of the response register 213 and reads the DP memory 212 of the DP memory 212. -Read the read result of the common memory from the address. Thereafter, the processor core 211 can perform necessary processing after resetting the response flag 215.
[0021]
First, since the processor 21 in FIG. 2 uses the DP memory 212 to store the transmitted and received data, writing from the reception control unit 224 and reading to the transmission control unit 223 cannot be performed simultaneously. I mentioned that it doesn't usually matter. However, when a plurality of consecutive access timing values are assigned to a specific processor, reading from the DP memory 212 for transmission of an access signal at a later access timing value in the transmission control unit 223 is reception control. It may happen that the writing to the DP memory 212 by reception at the front access timing value in the unit 224 coincides. In such a case, it is possible to perform writing and reading in the DP memory 212 at the same time by providing a DP memory dedicated to transmission and reception, or providing a dedicated circuit capable of transmitting and receiving simultaneously instead of the DP memory. It is also possible to solve this problem.
[0022]
FIG. 3 is a block diagram showing a second embodiment of the processor system of the present invention. FIG. 3 shows a case where one common memory is accessed by five processors, as in FIG. In FIG. 3, 31 is a transfer circuit, and the same components as those in FIG.
[0023]
The transfer circuit 31 is a circuit that mediates communication with the memory control unit 16 after assigning priorities to access signals transmitted through the signal ring bus 14. Since the access signal from each bus control unit corresponding to each processor arrives at the transfer circuit at a unique timing value, the priority processing can be performed using only the timing value of the timing ring bus 15. With such a configuration, it is possible to reliably perform a common memory access from a processor that needs to preferentially access the common memory.
[0024]
FIG. 4 is a block diagram showing a configuration example of the transfer circuit of the present invention. In FIG. 4, reference numeral 41 is an upstream receiving unit, 42 is an upstream priority queue, 43 is an upstream general queue, 44 is an upstream transmitting unit, 45 is a downstream receiving unit, 46 is a downstream queue, and 47 is a downstream transmitting unit. The upstream priority queue 42, the upstream general queue 43, and the downstream queue 46 are each composed of a FIFO memory.
[0025]
The upstream receiving unit 41 receives the access signal from the signal ring bus 14, selects the upstream priority queue 42 or the upstream general queue 43 according to the timing value of the timing ring bus 15, and stores the access signal. The upstream transmission unit 44 first reads from the upstream priority queue 42, reads from the upstream general queue 43 only when the upstream priority queue 42 is empty, and passes the read access signal to the memory control unit. If the upstream priority queue 42 and the upstream general queue 43 are empty, the upstream transmission unit 44 waits for processing.
[0026]
The downlink receiving unit 45 receives an access signal including a common memory read result from the memory control unit and stores it in the downlink queue 46. The downlink transmission unit 47 reads the access signal from the downlink queue 46, checks the access timing value for the transmission source address in the access signal, and when the timing value of the timing ring bus 15 matches the access timing value, An access signal is transmitted to the ring bus.
[0027]
FIG. 5 is a block diagram showing a third embodiment of the processor system of the present invention. FIG. 5 shows an example in which one common memory is accessed by a total of seven processors. In FIG. 5, 511 and 512 are processors, 521 and 522 are bus control units, 53 is a first signal ring bus, 54 is a first timing ring bus, 55 is a second signal ring bus, and 56 is This is a second timing ring bus, and the same components as those in FIGS. 1 and 3 are denoted by the same reference numerals.
[0028]
In FIG. 5, two signal ring buses 53 and 55 and timing ring buses 54 and 56 are provided, respectively, and these are connected by a transfer circuit 31. Also, the bus controllers 121, 122, 123, 124, and 125 corresponding to the five processors 111, 112, 113, 114, and 115 are connected to the first signal ring bus 53 and the first timing ring bus 54, respectively. The bus controllers 521 and 522 corresponding to the other two processors 511 and 512, and the memory controller 16 and the common memory 17 connected thereto are the second signal ring bus 55 and the second timing ring bus. 56. With this configuration, the common memory access from the two processors connected to the second signal ring bus 55 is performed with the highest priority, and further connected to the first signal ring bus 53. By giving priority rankings among the five processors, it is possible to perform detailed priority processing for common memory access.
[0029]
Although the processor system for accessing the common memory has been described above, the present invention is not limited to the above-described embodiment, and various modifications may be made without departing from the spirit of the present invention. Of course, it is possible.
【The invention's effect】
As described above in detail, according to the present invention, since the common memory access from each processor can be controlled on the condition of the timing value of the predetermined timing ring bus, the common memory is accessed at a preset speed. Therefore, it is possible to provide a processor system including a common memory that can always make the time required for accessing the common memory smaller than a predetermined maximum time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a processor system having a common memory according to the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a processor and a bus control unit in a processor system including a common memory according to the present invention.
FIG. 3 is a block diagram showing a second embodiment of a processor system having a common memory according to the present invention.
FIG. 4 is a block diagram illustrating a configuration example of a transfer circuit according to the present invention.
FIG. 5 is a block diagram showing a third embodiment of a processor system having a common memory according to the present invention.
[Explanation of symbols]
111, 112, 113, 114, 115: processor, 121, 122, 123, 124, 125: bus control unit, 13: timing generation unit, 14: signal ring bus, 15: timing ring bus, 16: memory control Unit: 17: common memory, 21: processor, 22: bus control unit, 211: processor core, 212: dual port memory, 213: response register, 214: request register, 215: response flag, 216: request flag, 221 : Request queue, 222: timing memory, 223: transmission control unit, 224: reception control unit, 31: transfer circuit, 41: uplink reception unit, 42: uplink priority queue, 43: uplink general queue, 44: uplink transmission unit, 45: Downlink reception unit, 46: Downstream queue, 47: Downstream transmission unit, 511, 512: Processor, 52 , 522: bus control unit, 53: first signal ring bus, 54: first timing ring bus, 55: second signal ring bus, 56: second timing ring bus.

Claims (3)

A common memory for reading and writing from a plurality of processors, a signal ring bus for transmitting an access signal between the common memory and the processor, a timing ring bus for transmitting a timing signal, and a timing ring bus A timing generation unit that transmits the timing signal including a timing value; a plurality of processors including a bus control unit; and a memory control unit that mediates a signal between the signal ring bus and the common memory. And
The processor includes a processor core, a dual port memory that can be read / written independently from the processor core side and the bus control unit side, a distinction between writing and reading, a common memory access instruction comprising a common memory address and a dual port memory address A request register for storing contents, a response register for storing common memory read instruction contents including a common memory address and a dual port memory address, and a request flag that is set and reset in accordance with writing to and reading from the request register And a response flag that is set and reset in accordance with writing to and reading from the response register,
The bus control unit
If the request flag is set, the common memory access instruction content stored in the request register is stored if the request flag is set. The request flag is reset and then the end bits are sequentially checked and set, and if the response flag is reset, the common memory read instruction content is generated and stored in the response register. A request queue that sets the response flag;
A timing memory for storing a predetermined access timing value capable of transmitting or receiving an access signal;
The contents of the common memory access instruction stored in the request queue are read and an access signal is generated based on the read instruction, while the access timing value is known from the timing memory, and the timing value of the timing ring bus is the access timing. A transmission control unit that transmits the access signal to the signal ring bus when the value matches,
Knowing the access timing value from the timing memory, when the timing ring bus timing value coincides with the access timing value, the access signal is received from the signal ring bus and the memory read result is extracted to obtain the dual port memory And a reception control unit that sets a corresponding end bit of the request queue.
The memory control unit passes the access signal input from the signal ring bus to the common memory, and when the access signal means reading, the memory reading result from the common memory is used as an access signal to the corresponding processor. A processor system comprising a common memory, wherein the processor system outputs data to the signal ring bus, and writes data to the common memory when the input access signal signifies writing. A common memory you read and write from a plurality of processors, concluding part of the plurality of processors, and a ring bus for the first signal to be transmitted access signals between said common memory, said plurality of processors A second signal ring bus for transmitting an access signal to and from the common memory, and a first signal for transmitting a timing signal in parallel with the first signal ring bus. A timing ring bus, a second timing ring bus for transmitting timing signals in parallel with the second signal ring bus, and a timing signal having a finite timing value are transmitted to the first timing ring bus. A timing generator, a bus controller provided in each of the plurality of processors, the first signal ring bus, and the second signal. A transfer circuit that mediates the access signal to and from the first timing ring bus and the timing signal between the first timing ring bus and the second timing ring bus; and the second signal A memory controller that mediates signals between the ring bus for use and the common memory,
Each of the bus control units inputs or outputs the access signal to the signal ring bus when a timing signal of the timing ring bus reaches a predetermined value,
The transfer circuit performs a mediation process by assigning priorities to the access signals from the processors connected to the first signal ring bus,
The memory control unit passes the access signal input from the signal ring bus to the common memory, and when the access signal means reading, the memory reading result from the common memory is used as an access signal to the corresponding processor. A processor system comprising a common memory, wherein the processor system outputs data to the signal ring bus, and writes data to the common memory when the input access signal signifies writing. The transfer circuit includes an upstream receiving unit that receives the access signal from the signal ring bus, an upstream priority queue and an upstream general queue that temporarily store an access signal from the upstream receiving unit, and the upstream priority queue. And an upstream transmission unit that reads an access signal from the upstream general queue and passes the access signal to memory control, a downstream reception unit that receives the access signal from the memory control unit, and temporarily receives the access signal from the downstream reception unit A downlink queue that accumulates, and a downlink receiver that reads an access signal from the downlink queue and transmits the read signal to the signal ring bus,
The uplink receiver first reads from the uplink priority queue according to the timing value of the timing ring bus when the access signal arrives, and the uplink general queue when the uplink priority queue is empty 3. The processor system having a common memory according to claim 2, wherein the access signal is transferred to the signal ring bus.

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