JP4126984B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device provided with a triac.
[0002]
[Prior art]
Conventionally, a semiconductor device represented by an equivalent circuit as shown in FIG. 5 has been proposed in Japanese Patent Publication No. 61-23666. Here, the equivalent circuit shown in FIG. 5 is obtained by mounting and wiring the semiconductor chips as shown in FIGS. 6 and 7 as shown in FIG.
[0003]
Hereinafter, after describing the equivalent circuit of FIG. 5, FIGS. 6 to 8 will be described.
[0004]
The triac TR in the equivalent circuit of FIG. 5 is a thyristor (hereinafter referred to as a first thyristor) having a pnpn4 layer structure of a p-type anode region 4, an n-type gate region (n semiconductor substrate) 1, a p-type gate region 2, and an n-type cathode region 3. A thyristor (hereinafter referred to as a thyristor) having a pnpn4 layer structure of a p-type anode region layer 4 ′, an n-type gate region (n semiconductor substrate) 1, a p-type gate region 2 ′, and an n-type cathode region 3 ′. 25 ′ (referred to as a second thyristor) is connected in antiparallel, and the p-type anode region 4 of the first thyristor 25 and the n-type cathode region 3 ′ of the second thyristor 25 ′ are one output terminal. The n-type cathode region 3 of the second thyristor 25 and the p-type anode region 4 of the second thyristor 25 ′ are connected to the other output terminal 23.
[0005]
In the semiconductor device, a resistor R is connected between the p-type gate region 2 and the n-type cathode region 3 of the first thyristor 25, and the p-type gate region 2 ′ and the n-type cathode region 3 of the second thyristor 25 are connected. A resistor R 'is connected between' and. Further, between the p-type gate region 2 and the n-type cathode region 3 of the first thyristor 25, the drain and source of the insulated gate field effect transistor T are connected, and the p-type gate region of the second thyristor 25 ′. The drain-source of the insulated gate field effect transistor T ′ is connected between the 2 ′ and the n-type cathode region 3 ′. Here, the gate of each insulated gate field effect transistor T is connected to the n-type gate region 1.
[0006]
Incidentally, the semiconductor device described above has a semiconductor chip C ′ shown in FIGS. 6 and 7 as a main configuration. In this semiconductor chip C ′, two p-type anode regions 4, 4 ′ are formed on the main surface side of the n-type semiconductor substrate 1 so as to be separated from each other, and are separated from each p-type anode region 4, 4 ′. P-type gate regions 2 and 2 ′ are formed on the main surface side of the semiconductor substrate 1, and n-type cathode regions 3 and 3 ′ are formed on the main surface side in each of the p-type gate regions 2 and 2 ′.
[0007]
The semiconductor chip C ′ has a p-type anode in which the resistor R including the p-type region is formed between the p-type anode region 4 ′ and the p-type gate region 2 on the main surface side of the n-type semiconductor substrate 1. A resistor R ′ made of a p-type region is formed between the region 4 and the p-type gate region 2 ′. Furthermore, the insulated gate field effect transistors T and T ′ are formed on the semiconductor chip C ′. Here, one insulated gate field effect transistor T (the right insulated gate field effect transistor T in FIG. 6) is a p-type well formed inside the p-type anode region 4 ′ on the main surface side of the n-type semiconductor substrate 1. In the region 12, the n-type drain region 17 and the n-type source region 18 are formed to be separated from each other, and the gate electrode 11 is formed across the n-type drain region 17 and the n-type source region 18. The other insulated gate field effect transistor T (left insulated gate field effect transistor T ′ in FIG. 6) is a p-type well region formed inside the p-type anode region 4 on the main surface side of the n-type semiconductor substrate 1. 12 ′, an n-type drain region 17 ′ and an n-type source region 18 ′ are formed apart from each other, and a gate electrode 11 ′ is formed across the n-type drain region 17 ′ and the n-type source region 18 ′. ing.
[0008]
An insulating film 9 made of a silicon oxide film is formed on the main surface of the n-type semiconductor substrate 1, and the p-type anode region 4, the n-type cathode region 3 ′, and the n-type source region 17 ′ are each region 4. , 3 ', 17' are connected by a metal wiring 19 through respective contact portions 14, 15 ', 10'. Each contact portion 14, 15 ′, 10 ′ is formed by embedding a part of the metal wiring 19 in the contact hole opened in the insulating film 9.
[0009]
Similarly, the p-type anode region 4 ′, the n-type cathode region 3, and the n-type source region 17 are connected to each other by the metal wiring 19 ′ through the contact portions 14 ′, 15, 10 of the regions 4 ′, 3, 17. It is connected. Each contact portion 14 ′, 15, 10 is formed by embedding a part of the metal wiring 19 ′ in a contact hole opened in the insulating film 9.
[0010]
The p-type gate region 2 ′ and the n-type drain region 18 ′ are connected by a metal wiring 21 ′ via respective contact portions 8 ′ and 9 ′. Each contact portion 8 ′, 9 ′ is formed by embedding a part of the metal wiring 21 ′ in the contact hole opened in the insulating film 9.
[0011]
Similarly, the p-type gate region 2 and the n-type drain region 18 are connected by a metal wiring 21 via respective contact portions 8 and 9. Each contact portion 8, 9 is formed by embedding a part of the metal wiring 21 in a contact hole opened in the insulating film 9.
[0012]
Incidentally, a protective film 31 (see FIG. 7) is formed on the main surface side of the semiconductor chip C ′ so as to cover the metal wirings 19, 19 ′, 21, 21 ′ and the insulating film 9. Are formed on the pad 16 (see FIG. 6) made of a part of the metal wiring 20 connected to the gate electrode 11 of the insulated gate field effect transistor T and the gate electrode 11 ′ of the insulated gate field effect transistor T ′. A pad 16 ′ (see FIG. 6) made of a part of the connected metal wiring 20 ′ is formed.
[0013]
Although not shown in FIG. 6, on the main surface side of the semiconductor chip C ′, the p-type anode region 4 of the first thyristor 25 and the n-type cathode region 3 ′ of the second thyristor 25 ′ are formed. Pads 13 ′ (see FIG. 8) made of a part of the connected metal wiring 19 and pads 13 (see FIG. 8) made of a part of the metal wiring 19 ′ are formed.
[0014]
In the semiconductor device described above, as shown in FIG. 8, the semiconductor chip C ′ is die-bonded onto the metal frame 22, and the pad 13 is connected via the metal frame 23 and the metal wire 27 on the right side of the metal frame 22 in FIG. The pad 13 'is connected to the left metal frame 24 and the metal wire 27' in the drawing, so that the metal frames 23 and 24 constitute the output terminals 23 and 24, respectively. Further, in the above-described semiconductor device, the other ends of the metal wires 7 and 7 ′ whose one ends are bonded to the pads 16 and 16 ′ are bonded to the metal frame 22.
[0015]
The operation of the above-described semiconductor device will be described below with reference to the equivalent circuit shown in FIG. When considering the operation of the triac described above, when the output terminal 24 is at a higher potential than the output terminal 23, the p-type anode region 4, the n-type semiconductor substrate 1, the p-type gate region 2, and the n-type cathode region 3 are used. When the output terminal 23 is set to a high potential with respect to the output terminal 24 , the p-type anode region layer 4 ′, the n-type semiconductor substrate 1, the p-type gate region 2 ′, and the n-type cathode region are considered. A 3 ′ pnpn4 layer structure may be considered.
[0016]
In the semiconductor device, when the voltage higher than the threshold value of the insulated gate field effect transistor T is applied between the output terminals 24 and 23 with the output terminal 24 as the high potential side, the insulated gate field effect transistor T is in the on state. Thus, since the impedance between the p-type gate region 2 and the n-type cathode region 3 is low, the p-type anode region 4, the n-type gate region 1, the p-type gate region 2 and the n-type cathode region 3 are formed. The first thyristor 25 cannot be ignited. Similarly, in a state where a voltage higher than the threshold value of the insulated gate field effect transistor T ′ is applied between the output terminals 23 and 24 with the output terminal 23 as a high potential side, the insulated gate field effect transistor T ′ is turned on. Thus, since the impedance between the p-type gate region 2 ′ and the n-type cathode region 3 ′ is low, the p-type anode region 4 ′, the n-type gate region 1, the p-type gate region 2 ′, and the n-type cathode region The second thyristor 25 'formed by 3' cannot be ignited. Conversely, when the voltage between the output terminals 23 and 24 is lower than the threshold value of the insulated gate field effect transistors T and T ′, the insulated gate field effect transistors T and T ′ are not turned on. 25 'can be fired. That is, this semiconductor device is a triac having a zero cross function (hereinafter referred to as a zero cross type triac) that cannot be ignited when a high voltage is applied between the output terminals 23 and 24.
[0017]
[Problems to be solved by the invention]
By the way, the semiconductor device having the above-described conventional structure operates as a triac having a zero-cross function by including the above-described insulated gate field effect transistors T and T ′, but is not limited to the zero-cross type triac. There is also a need for a triac that does not have (hereinafter referred to as a non-zero cross type triac). However, the semiconductor device having the above-described conventional structure operates as a triac having a zero-cross function by including the above-described insulated gate field-effect transistors T and T ′. It was necessary to manufacture a semiconductor chip without transistors T and T ′.
[0018]
The present invention has been made in view of the above reasons, and an object of the present invention is to provide a semiconductor device in which a zero cross function is prohibited while employing a semiconductor substrate on which an insulated gate field effect transistor for adding a zero cross function is formed. It is to provide.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor substrate is provided with a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on the semiconductor substrate. A semiconductor device formed in a well region formed on a main surface side, wherein each insulated gate field effect transistor and each resistor are connected between gates and cathodes of two thyristors constituting the triac, the insulated gate are those gates of the field effect tiger Njisuta is characterized by comprising electrically connected only to the cathode of the thyristor, each supposed to between the gate and source of each insulated gate field effect transistor is connected The insulated gate field effect transistor can always be off. Therefore, the triac can be ignited even in a high voltage application state, and it is used as a semiconductor device in which the zero cross function is prohibited while employing a semiconductor substrate on which an insulated gate field effect transistor for adding the zero cross function is formed. Can do.
[0020]
According to the first aspect of the present invention, the other ends of the first metal wire having one end connected to the gate of the insulated gate field effect transistor and the second metal wire having one end connected to the cathode of the thyristor are since the gate of the insulated gate field effect tiger Njisuta by being connected to the same metal frame is connected to the cathode of said thyristor, identical to the other ends of the first metal wire and the second metal wires By connecting to the metal frame, the gate and source of each insulated gate field effect transistor are connected, while adopting a semiconductor substrate on which an insulated gate field effect transistor is formed for adding a zero cross function. A semiconductor device in which the zero cross function is prohibited can be easily realized.
[0021]
According to a second aspect of the present invention, in the first aspect of the invention, the outer peripheral shape of the semiconductor substrate is rectangular, and the pads to which the one end of the first metal wire is connected are four sides of the outer periphery of the semiconductor substrate. Since the pad to which the one end of the second metal wire is connected is disposed in the vicinity of the other side of the two sides, because it is disposed in the vicinity of one of the two sides separated from each other. A short circuit between the first metal wire and the second metal wire can be prevented.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor device of this embodiment has the equivalent circuit shown in FIG. 1 by mounting the semiconductor chip C configured as shown in FIGS. 2 and 3 as shown in FIG. Here, the equivalent circuit of FIG. 1 is described first, and then FIGS. 2 to 4 are described.
[0023]
The triac TR in the equivalent circuit of FIG. 1 is a thyristor (hereinafter referred to as a first thyristor) having a pnpn4 layer structure of a p-type anode region 4, an n-type gate region (n semiconductor substrate) 1, a p-type gate region 2, and an n-type cathode region 3. A thyristor (hereinafter referred to as a thyristor) having a pnpn4 layer structure of a p-type anode region layer 4 ′, an n-type gate region (n semiconductor substrate) 1, a p-type gate region 2 ′, and an n-type cathode region 3 ′. 25 ′ (referred to as a second thyristor) is connected in antiparallel, and the p-type anode region 4 of the first thyristor 25 and the n-type cathode region 3 ′ of the second thyristor 25 ′ are one output terminal. The n-type cathode region 3 of the second thyristor 25 and the p-type anode region 4 of the second thyristor 25 ′ are connected to the other output terminal 23.
[0024]
In the semiconductor device, a resistor R is connected between the p-type gate region 2 and the n-type cathode region 3 of the first thyristor 25, and the p-type gate region 2 ′ and the n-type cathode region 3 of the second thyristor 25 are connected. A resistor R 'is connected between' and. Further, between the p-type gate region 2 and the n-type cathode region 3 of the first thyristor 25, the drain and source of the insulated gate field effect transistor T are connected, and the p-type gate region of the second thyristor 25 ′. The drain-source of the insulated gate field effect transistor T ′ is connected between the 2 ′ and the n-type cathode region 3 ′. Here, the gate of the former insulated gate field effect transistor T is connected to the output terminal 23, and the gate of the latter insulated gate field effect transistor T ′ is connected to the output terminal 24.
[0025]
By the way, the semiconductor device described above has a semiconductor chip C shown in FIGS. 2 and 3 as a main configuration. In this semiconductor chip C, two p-type anode regions 4 and 4 ′ are formed on the main surface side of the n-type semiconductor substrate 1 so as to be separated from each other, and are separated from each p-type anode region 4 and 4 ′. P-type gate regions 2 and 2 ′ are formed on the main surface side of the substrate 1, and n-type cathode regions 3 and 3 ′ are formed on the main surface side in each of the p-type gate regions 2 and 2 ′.
[0026]
Further, in the semiconductor chip C, the resistor R including the p-type region is formed between the p-type anode region 4 ′ and the p-type gate region 2 on the main surface side of the n-type semiconductor substrate 1. A resistor R ′ composed of a p-type region is formed between 4 and the p-type gate region 2 ′. Further, the insulated gate field effect transistors T and T ′ are formed on the semiconductor chip C. Here, one insulated gate field effect transistor T (the right insulated gate field effect transistor T in FIG. 2) is a p-type well formed inside the p-type anode region 4 ′ on the main surface side of the n-type semiconductor substrate 1. In the region 12, the n-type drain region 17 and the n-type source region 18 are formed to be separated from each other, and the gate electrode 11 is formed across the n-type drain region 17 and the n-type source region 18. The other insulated gate field effect transistor T (left insulated gate field effect transistor T ′ in FIG. 2) is a p-type well region formed inside the p-type anode region 4 on the main surface side of the n-type semiconductor substrate 1. 12 ′, an n-type drain region 17 ′ and an n-type source region 18 ′ are formed apart from each other, and a gate electrode 11 ′ is formed across the n-type drain region 17 ′ and the n-type source region 18 ′. ing.
[0027]
An insulating film 9 made of a silicon oxide film is formed on the main surface of the n-type semiconductor substrate 1, and the p-type anode region 4, the n-type cathode region 3 ′, and the n-type source region 17 ′ are each region 4. , 3 ', 17' are connected by a metal wiring 19 through respective contact portions 14, 15 ', 10'. Each contact portion 14, 15 ′, 10 ′ is formed by embedding a part of the metal wiring 19 in the contact hole opened in the insulating film 9.
[0028]
Similarly, the p-type anode region 4 ′, the n-type cathode region 3, and the n-type source region 17 are connected to each other by the metal wiring 19 ′ through the contact portions 14 ′, 15, 10 of the regions 4 ′, 3, 17. It is connected. Each contact portion 14 ′, 15, 10 is formed by embedding a part of the metal wiring 19 ′ in a contact hole opened in the insulating film 9.
[0029]
The p-type gate region 2 ′ and the n-type drain region 18 ′ are connected by a metal wiring 21 ′ via respective contact portions 8 ′ and 9 ′. Each contact portion 8 ′, 9 ′ is formed by embedding a part of the metal wiring 21 ′ in the contact hole opened in the insulating film 9.
[0030]
Similarly, the p-type gate region 2 and the n-type drain region 18 are connected by a metal wiring 21 via respective contact portions 8 and 9. Each contact portion 8, 9 is formed by embedding a part of the metal wiring 21 in a contact hole opened in the insulating film 9.
[0031]
Incidentally, a protective film 31 (see FIG. 3) is formed on the main surface side of the semiconductor chip C so as to cover the metal wirings 19, 19 ′, 21, 21 ′ and the insulating film 9, and a part of the protective film 31 is formed. By opening the hole, the pad 16 (see FIG. 2) made of a part of the metal wiring 20 connected to the gate electrode 11 of the insulated gate field effect transistor T is connected to the gate electrode 11 ′ of the insulated gate field effect transistor T ′. A pad 16 ′ (see FIG. 2) made of a part of the formed metal wiring 20 ′ is formed.
[0032]
Further, on the main surface side of the semiconductor chip C, a part of the metal wiring 19 connected to the p-type anode region 4 of the first thyristor 25 and the n-type cathode region 3 ′ of the second thyristor 25 ′ is formed. A pad 13 made of a part of a metal wiring 19 ′ connected to the pad 13 ′, the p-type anode region 4 ′ of the second thyristor 25 ′ and the n-type cathode region 3 of the first thyristor 25 is formed. .
[0033]
In order to realize a semiconductor device having a zero-cross type triac using the semiconductor chip described above, the semiconductor chip C is die-bonded on the metal frame 22 shown in FIG. 8, and the pad 13 ′ is connected to the metal frame 22 in FIG. The right metal frame 23 and the metal wire 27 are connected to each other, the pad 13 'is connected to the left metal frame 24 and the metal wire 27' in the figure, and one end of each pad is bonded to the pads 16 and 16 '. The other ends of the metal wires 7 and 7 ′ may be bonded to the metal frame 22. That is, the metal wirings 20 and 20 ′ are electrically connected to the semiconductor substrate 1 so that the on state and the off state of the insulated gate field effect transistors T and T ′ are appropriately switched by the applied voltage between the output terminals 23 and 24. You can do it.
[0034]
On the other hand, in the semiconductor device of this embodiment, as shown in FIG. 4, the semiconductor chip C is die-bonded onto the metal frame 22, and the pad 13 is connected to the metal frame 23 on the left side of the metal frame 22 in FIG. The pad 13 'is connected via the metal wire 27, and the pad 13' is connected to the left metal frame 24 and the metal wire 27 'in the figure, so that the metal frames 23 and 24 are connected to the output terminals 23 and 24, respectively. It is composed. Further, in the semiconductor device of this embodiment, the other ends of the metal wires 7 and 7 ′ each bonded to the pads 16 and 16 ′ are bonded to the metal frames 23 and 24, respectively. Therefore, the metal wiring 19 ′ and the metal wiring 20 are electrically connected through the pads 13 and 16, respectively, and the metal wiring 19 and the metal wiring 20 ′ are electrically connected through the pads 13 ′ and 16 ′, respectively. The insulated gate field effect transistors T and T ′ are always turned off regardless of the voltage between the output terminals 23 and 24.
[0035]
Thus, in the semiconductor device of this embodiment, the gate electrodes 11 and 11 ′ of the insulated gate field transistors T and T ′ are electrically connected to the n-type cathode regions 3 and 3 ′ of the thyristors 25 and 25 ′, and the insulated gate Since the gates and sources of the field transistors T and T ′ are connected to each other, the insulated gate field effect transistors T and T ′ can always be turned off, so that the triac can be fired even in a high voltage application state. The semiconductor substrate 1 (that is, the semiconductor chip C) on which the insulated gate field effect transistors T and T ′ for adding the zero cross function are formed is used as a semiconductor device in which the zero cross function is prohibited. Can do.
[0036]
In the semiconductor device of the present embodiment, as described above, the metal wires 7 and 7 ′ having one ends connected to the pads 16 and 16 ′ of the gate electrodes 11 and 11 ′ of the insulated gate field effect transistors T and T ′ and The other ends of the thyristors 25 and 25 ′ and the metal wires 27 and 27 ′ connected at one end to the pads 13 and 13 ′ connected to the n-type cathode regions 3 and 3 ′ are connected to the same metal frames 23 and 24, respectively. Therefore, by connecting the other ends of the metal wires 7 and 7 'and the metal wires 27 and 27' to the same metal frame 23 and 24, the gates and sources of the insulated gate field effect transistors T and T 'are connected. The semiconductor substrate 1 (that is, the semiconductor chip C) on which the insulated gate field effect transistors T and T ′ for adding the zero cross function are formed is adopted, but the zero cross function is prohibited. Conductor device can be easily realized.
[0037]
In the semiconductor device of the present embodiment, the outer periphery of the n-type semiconductor substrate 1 is rectangular, and the pads 16 and 16 ′ to which one end of the metal wires 7 and 7 ′ are connected are the outer periphery of the n-type semiconductor substrate 1. The pads 13 and 13 'to which one end of the metal wires 27 and 27' is connected are arranged in the vicinity of the other side of the two sides. Therefore, a short circuit between the metal wires 7 and 7 ′ and the metal wires 27 and 27 ′ can be prevented, and the insulated gate field effect transistors T and T ′ can be reliably kept in the off state.
[0038]
【The invention's effect】
The invention according to claim 1 is a well region in which a semiconductor substrate is provided with a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on the main surface side of the semiconductor substrate. It is formed within, a semiconductor device in which each insulated gate field effect transistor and the resistor connected between the gate and the cathode of each of the two thyristors constituting the triac, the gate of the insulated gate field effect tiger Njisuta said are those formed by electrically connected only to the cathode of thyristor, be always turned off each insulated gate field effect transistor so that the gate-source is connected in each insulated gate field effect transistor Because it can be The can be ignited, there is an effect that can be used as a semiconductor device is also prohibited the zero crossing function while employing a semiconductor substrate formed of an insulated gate field effect transistor for adding a zero-cross function.
[0039]
According to the first aspect of the present invention, the other ends of the first metal wire having one end connected to the gate of the insulated gate field effect transistor and the second metal wire having one end connected to the cathode of the thyristor are since the gate of the insulated gate field effect tiger Njisuta by being connected to the same metal frame is connected to the cathode of said thyristor, identical to the other ends of the first metal wire and the second metal wires By connecting to the metal frame, the gate and source of each insulated gate field effect transistor are connected, while adopting a semiconductor substrate on which an insulated gate field effect transistor is formed for adding a zero cross function. There is an effect that a semiconductor device in which the zero cross function is prohibited can be easily realized.
[0040]
According to a second aspect of the present invention, in the first aspect of the invention, the outer peripheral shape of the semiconductor substrate is rectangular, and the pads to which the one end of the first metal wire is connected are four sides of the outer periphery of the semiconductor substrate. Since the pad to which the one end of the second metal wire is connected is disposed in the vicinity of the other side of the two sides, because it is disposed in the vicinity of one of the two sides separated from each other. There is an effect that it is possible to prevent a short circuit between the first metal wire and the second metal wire.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of a semiconductor device according to a first embodiment.
FIG. 2 is a schematic plan view of a semiconductor chip in the above semiconductor device.
3 is a cross-sectional view taken along the line BB ′ of FIG. 2 of the semiconductor chip in the semiconductor device same as above. FIG.
FIG. 4 is a schematic configuration diagram of the above semiconductor device.
FIG. 5 is an equivalent circuit diagram showing a conventional example.
FIG. 6 is a schematic plan view of a semiconductor chip in the semiconductor device same as above.
7 is a cross-sectional view taken along the line BB ′ of FIG. 6 of the semiconductor chip in the semiconductor device.
FIG. 8 is a schematic configuration diagram of the above semiconductor device.
[Explanation of symbols]
1 n-type semiconductor substrate (n-type gate region)
2, 2 'p-type gate region 3, 3' n-type cathode region 4, 4 'p-type anode region 9 insulating film 11, 11' gate electrode 12, 12 'p-type well region 17, 17' n-type drain region 18 , 18 'n-type source region 19, 19' surface electrode 21, 21 'surface electrode 22 metal frame 23 output terminal (metal frame)
24 Output terminal (metal frame)
31 Protective film R, R ′ Resistance T, T ′ Insulated gate field effect transistor

Claims (2)

A semiconductor substrate is provided with a triac, two insulated gate field effect transistors and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed in a well region formed on the main surface side of the semiconductor substrate. a semiconductor device having a gate field effect transistor and the resistor connected between the gate and the cathode of each of the two thyristors constituting the triac, the gate of the insulated gate field effect tiger Njisuta electricity only in the cathode in the thyristor The other ends of the first metal wire having one end connected to the gate of the insulated gate field effect transistor and the second metal wire having one end connected to the cathode of the thyristor are the same. The insulated gate field effect by being connected to the metal frame Wherein a gate of the transistor is connected to the cathode of the thyristor. The outer peripheral shape of the semiconductor substrate is a rectangular shape, and a pad to which the one end of the first metal wire is connected is in the vicinity of one of two sides separated from each other among the four sides of the outer periphery of the semiconductor substrate. The semiconductor device according to claim 1, wherein a pad to which the one end of the second metal wire is connected is disposed near the other side of the two sides .

Images