JP4126987B2 - Image display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a self-luminous flat panel display using a thin film electron source.
[0002]
[Prior art]
A display that uses a small and stackable cold cathode electron source is called FED (Field Emission Display). Cold cathode electron sources are classified into field emission electron sources and hot electron electron sources. The former includes spindt electron sources, surface conduction electron sources, carbon nanotube electron sources, etc., and the latter includes metals. -Insulator-metal stacked MIM (Metal-Insulator-Metal) type, metal-insulator-semiconductor stacked MIS (Metal-Insulator-Semiconductor) type, metal-insulator-semiconductor-metal type, etc. For example, JP-A-7-65710 for MIM type, MOS type (J. Vac. Sci. Techonol. B11 (2) p.429-432 (1993)) for metal-insulator-semiconductor type, metal-insulator ―For semiconductor-metal type, HEED type (described in high-efficiency-electro-emission device, Jpn.J.Appl. Phys., Vol 36, p L939, etc.), EL type (Electroluminescence, Applied Physics Vol.63, No.6) No., described on page 592), porous silicon type (applied physics Vol. 66, No. 5, page 437, etc.) have been reported.
The MIM type electron source is disclosed in, for example, Japanese Patent Laid-Open No. 10-153979. Fig. 2 shows the structure and operating principle of the MIM type electron source. When a drive voltage V _d is applied between the upper electrode 13 and the lower electrode 11 and the electric field in the insulating layer 12 is set to about 1 to 10 MV / cm, electrons near the Fermi level in the lower electrode 11 are tunneled. By passing through the barrier, it is injected into the conduction band of the insulating layer 12 which is the electron acceleration layer, becomes hot electrons, and flows into the conduction band of the upper electrode 13. Of these hot electrons, those that reach the electrode surface with energy equal to or higher than the work function φ of the upper electrode 13 are released into the vacuum 20.
[0003]
[Problems to be solved by the invention]
When image display is performed in the FED, a driving method called a line sequential driving method is adopted as a standard. This is a method of displaying each frame for each scanning line (horizontal direction) when displaying 60 still images (frames) per second. Therefore, all the cold cathode electron sources corresponding to the number of signal lines on the same scanning line operate simultaneously. A current obtained by multiplying the current consumed by the cold cathode electron source included in the sub-pixel by the total number of signal lines flows through the scanning line during operation. Since this scanning line current causes a voltage drop along the scanning line due to the wiring resistance, the uniform operation of the cold cathode electron source is hindered. In particular, a voltage drop due to the wiring resistance of the scanning line is a big problem in realizing a large display device.
In order to solve this problem, it is necessary to reduce the wiring resistance of the scanning line. In the case of a thin film type electron source, it is conceivable to increase the thickness of the lower electrode or the upper bus electrode that supplies power to the upper electrode. However, when the thickness of the lower electrode is increased, the unevenness of the wiring becomes severe and the upper bus electrode and the like are easily disconnected, causing a problem in reliability. On the other hand, when the upper bus electrode is made thick, there is a problem that the connection portion with the thin upper electrode is easily broken. Therefore, there is a method to prevent disconnection of the upper electrode by taper etching of the upper bus electrode, but taper etching is generally performed by using side etching of the resist being etched, so control is performed for a thick upper bus electrode film having a long etching time. Difficulties arise in sex. Therefore, there is a structure in which the upper bus electrode is made of a laminated metal film, and a thin upper bus electrode lower layer responsible for connection with the upper electrode or a taper-etched upper bus electrode lower layer and a thick upper bus electrode upper layer responsible for power feeding are laminated. The metal laminated film is susceptible to electrochemical corrosion during processes such as wet etching, and the upper bus electrode is likely to deteriorate.
[0004]
[Means for Solving the Problems]
An object of the present invention is a thin film type having a lower electrode and an upper electrode, an electron acceleration layer sandwiched between them, and emitting electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode In an image display device having a substrate on which an electron source is formed and a phosphor screen, the thin film electron source array has an upper bus electrode serving as a power supply line to the upper electrode, and the upper bus electrode is an interlayer It can be realized by forming multi-layer wirings connected through through-holes in an insulating layer, displaying image information by a line-sequential driving method, using the lower electrode as a signal line and the upper bus electrode as a scanning line. .
[0005]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of the present invention that achieves the above object will be described with reference to FIGS. 4 to 15 and FIG. 1, taking a MIM electron source as an example.
First, a metal film for a lower electrode is formed on an insulating substrate 10 such as glass. Al or Al alloy is used as the lower electrode material. The reason why Al or Al alloy is used is that a good quality insulating film can be formed by anodic oxidation. Here, an Al—Nd alloy doped with 2% by weight of Nd was used. For example, a sputtering method is used for film formation. The film thickness was 300 nm. After the film formation, a stripe-shaped lower electrode 11 was formed by a photo process and an etching process. For example, wet etching using a mixed aqueous solution of phosphoric acid, acetic acid and nitric acid is used for the etching (FIG. 3).
Next, the protective insulating layer 14 and the insulating layer 12 are formed to limit the electron emission portion and prevent electric field concentration on the lower electrode edge. First, a portion to be an electron emission portion on the lower electrode 11 is masked with a resist film 25, and the other portion is selectively thickly anodized to form a protective insulating layer 14 (FIG. 4). If the formation voltage is 100 V, the protective insulating layer 14 having a thickness of about 136 nm is formed. Next, the resist film 25 is removed, and the surface of the remaining lower electrode 11 is anodized. For example, if the formation voltage is 6 V, the insulating layer 12 having a thickness of about 10 nm is formed on the lower electrode 11 (FIG. 5).
Next, an upper bus electrode film lower layer 26 serving as a power supply line to the upper electrode 13 and a second protective insulating layer 19 formed thereunder are formed by, for example, sputtering. As the second protective insulating layer 19, for example, Si oxide was used, and the film thickness was 40 nm. When there is a pinhole in the protective insulating layer 14 formed by anodization, the second protective insulating layer 19 fills in the defect and plays a role of maintaining insulation between the lower electrode 11 and the upper bus electrode lower layer 26. An Al—Nd alloy was used as a material for the upper bus electrode lower layer 26. (Figure 6).
Subsequently, the upper bus electrode 26 is processed and formed so as to be orthogonal to the lower electrode 11 by a photoetching process. The etchant uses a mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid (FIG. 7).
Next, an interlayer insulating layer 27 is formed. For example, SiO ₂ or Si ₃ N ₄ can be used for the interlayer insulating layer 27. In this example, a SiN _x film formed by sputtering was used. In this example, the film thickness was 500 nm (FIG. 8).
Subsequently, a through hole is opened in the interlayer insulating layer 27 on the upper bus electrode by a photoetching process. The through hole is formed in a portion other than the electron emission portion, for example, in the gap between the wirings of the lower electrode 11. For this processing, for example, dry etching using CF ₄ or SF ₆ may be used. In dry etching using a fluoride-based etching gas such as CF ₄ or SF _6, the SiO ₂ film of the interlayer insulating layer 27 is etched with a high selectivity with respect to the Al alloy of the upper bus electrode lower layer 26, so that the upper bus electrode lower layer 26 It is possible to process only the interlayer insulating layer 27 using this Al alloy as a stopper film (FIG. 9).
Subsequently, the upper bus electrode upper layer 28 is formed. As the upper bus electrode upper layer 28, for example, Cu having a low specific resistance is used. In this embodiment, a film formed by sputtering is used. In this example, Cu was 5 mm. It is also effective to lay a thin Cr film under the Cu as an adhesive layer (Fig. 10).
Subsequently, the upper bus electrode upper layer 28 is processed by wet etching. For example, ferric chloride aqueous solution is used as the etchant (FIG. 11).
In the above embodiment, a Cu film having a thickness of 5 mm formed by sputtering was used. However, in order to further increase the thickness in order to manufacture a large display device, a sputtering film is used as a seed film to form Cu. Plating can be performed to further increase the film thickness. By using the plating method, the upper bus electrode upper layer 28 having a thickness of 10 to 75 mm can be formed.
Subsequently, the interlayer insulating layer 27 in the electron emission portion is opened by a photoetching process. For this processing, for example, dry etching using CF ₄ or SF ₆ may be used. In dry etching using a fluoride-based etching gas such as CF ₄ or SF _6, the SiO ₂ film of the interlayer insulating layer 27 is etched with a high selectivity with respect to the Al alloy of the upper bus electrode lower layer 26, so that the upper bus electrode lower layer 26 It is possible to process only the interlayer insulating layer 27 using this Al alloy as a stopper film (FIG. 12).
Next, the Al—Nd alloy of the upper bus electrode lower layer 26 is tapered by a photo process and a wet etching process so that the film thickness decreases toward the electron emission portion side. Taper processing can be realized by changing the resist baking temperature to lower the resist adhesion and retracting the resist during wet etching (Figure 13).
Next, the SiO ₂ of the second protective insulating layer 19 is dry etched to open the electron emission portion. In the dry etching method using a fluoride-based etching gas such as CF ₄ or SF _6, the SiO ₂ of the second protective insulating layer 19 is higher than the insulating layer 12 made of an anodized film of Al alloy and the protective insulating layer 14 Since the etching is performed with the selectivity, damage to the insulating layer 12 can be reduced (FIG. 14).
Next, the insulating layer 12 is anodized again to repair the damage.
After repairing the insulating layer 12, the upper electrode 13 film is finally formed. For example, sputtering film formation is used as the film formation method. As the upper electrode 13, for example, a laminated film of Ir, Pt, and Au is used, and the film thickness is several nm. Here, it was 5 nm. The upper electrode 13 can be processed by attaching a shadow mask using the upper bus electrode upper layer 28 as a partition. The formed thin upper electrode 13 is cut for each opening of the interlayer insulating layer 27, separated for each electron source, and Al of the upper bus electrode lower layer 26 which is processed into a tapered shape on the electron emission side. -Nd film is in contact with the power supply structure (Fig. 1).
Also, as shown in FIG. 15, after processing the upper bus electrode upper layer 28, if a material having a dry etching rate slower than the interlayer insulating layer 27, such as SiO ₂ , is formed thereon as the surface insulating layer 29, the electrons At the time of opening the emission part, a saddle structure can be formed by utilizing the difference in dry etching rate between the interlayer insulating layer 27 and the surface insulating layer 29, and the upper electrode 13 can be processed using this as a mask. Further, the surface insulating layer 29 covers the surface of the upper bus electrode upper layer 28, whereby the oxidation resistance of the upper bus electrode upper layer 28 can be improved.
In this way, by connecting the upper bus electrode lower layer 26 that is in contact with the upper electrode 13 and the upper bus electrode upper layer 28 of low resistance mainly for power supply through the through hole of the interlayer insulating layer 27, The wiring resistance of the upper bus electrode can be greatly reduced, and can be used as a scanning line for a large image display device. This structure does not cause electrochemical corrosion because the connection portion of the through hole in contact with the dissimilar metal is not exposed to the etchant during the wet etching of the upper bus electrode upper layer 28 or the upper bus electrode lower layer 26. Accordingly, it is possible to realize a large-sized image display device with high manufacturing yield and high reliability.
(Second embodiment)
Next, as an example, a method for forming the display device of the present invention by bonding the thin film type electron source array substrate (FIG. 16) prepared in the first embodiment and a phosphor screen via a spacer will be described.
The display substrate is created as follows (Figure 17). The face plate 110 is made of translucent glass or the like. First, the black matrix 120 is formed for the purpose of increasing the contrast of the display device. The black matrix 120 is prepared by applying a mixed solution of PVA (polyvinyl alcohol) and sodium dichromate to the face plate 110, exposing the areas other than the areas where the black matrix 120 is to be formed by irradiating with ultraviolet rays, and then exposing the unexposed areas. It is formed by removing, applying a solution in which graphite powder is dissolved, and lifting off the PVA.
Next, a red phosphor 111 is formed. After applying an aqueous solution containing phosphor particles mixed with PVA (polyvinyl alcohol) and sodium dichromate on the face plate 110, the phosphor-forming portion is exposed to ultraviolet light and exposed to light, and then the unexposed portion is washed with running water. Remove with. In this way, the red phosphor 111 is patterned. The pattern is formed in a stripe shape as shown in FIG. Similarly, a green phosphor 112 and a blue phosphor 113 are formed. For example, Y ₂ O ₂ S: Eu (P22-R) is used for red, ZnS: Cu, Al (P22-G) is used for green, and ZnS: Ag, Cl (P22-B) is used for blue. .
Next, after filming with a film such as nitrocellulose, Al is deposited on the entire face plate 110 to a thickness of about 75 nm to form a metal back 114. This metal back 114 serves as an acceleration electrode. Thereafter, the face plate 110 is heated to about 400 ° C. in the atmosphere to thermally decompose organic substances such as a filming film and PVA. In this way, the display side substrate is completed.
The display-side substrate thus manufactured and the substrate 10 are sealed with the frit glass 115 around the peripheral frame 116 via the spacer 40.
FIG. 18 shows a portion corresponding to the AA ′ section and the BB ′ section of the bonded display panel. The height of the spacer 40 is set so that the distance between the face plate 110 and the substrate 10 is about 1 to 3 mm. Here, for the sake of explanation, the spacer 40 is set up for every dot that emits light in R (red), G (green), and B (blue), but the number of spacers 40 (density) is within the range that the mechanical strength can withstand. ) Is reduced, and it should be about every 1cm.
The sealed panel is evacuated to a vacuum of about 10 ^-7 Torr and sealed. After sealing, the getter is activated and the vacuum in the panel is maintained. For example, in the case of a getter material mainly composed of Ba, a getter film can be formed by high frequency induction heating or the like. Further, a non-evaporable getter containing Zr as a main component may be used.
Thus, in this embodiment, the distance between the face plate 110 and the substrate 10 is as long as about 1 to 3 mm, so that the acceleration voltage applied to the metal back 114 can be set to a high voltage of 3 to 6 KV. Therefore, as described above, a phosphor for a cathode ray tube (CRT) can be used as the phosphor.
FIG. 19 is a connection diagram to the drive circuit of the display device panel thus manufactured. The lower electrode 11 is connected to the lower electrode drive circuit 50, and the upper bus electrode lower layer 26 is connected to the upper electrode drive circuit 60. If the present invention is used, the wiring resistance of the upper bus electrode lower layer 26 and the upper bus electrode upper layer 28 can be made lower than that of the lower electrode 11, so that the upper bus electrode side is used as a scanning line and the lower electrode 11 side is used as a signal line. The intersection of the mth upper bus electrode 26 Cm and the nth lower electrode 11 Kn is represented by (m, n). An acceleration voltage 70 of about 3 to 6 KV is constantly applied to the metal back 114.
FIG. 20 shows an example of the waveform of the voltage generated by each drive circuit. At time t0, since no voltage is applied to any electrode, no electrons are emitted, and the phosphor does not emit light. At time t1, a voltage V1 is applied to the upper bus electrode 28C1, and a voltage -V2 is applied to the lower electrodes 11K1 and K2. Since a voltage of (V1 + V2) is applied between the lower electrode 11 and the upper electrode 13 at the intersections (1,1) and (1,2), if (V1 + V2) is set to be equal to or higher than the electron emission start voltage, Electrons are emitted into the vacuum from the thin film electron source at these two intersections. The emitted electrons are accelerated by the acceleration voltage 70 applied to the metal back 114, and then enter the phosphor to emit light. At time t2, when a voltage V1 is applied to C2 of the upper bus electrode and a voltage of -V2 is applied to K1 of the lower electrode 11, the intersection (2, 1) is similarly turned on. In this way, a desired image or information can be displayed by changing the signal applied to the lower electrode 11. Further, an image with gradation can be displayed by appropriately changing the magnitude of the applied voltage -V2 to the lower electrode 11. The inversion voltage for releasing the electric charge accumulated in the insulating layer 12 is applied to all lower electrode 11 after V1 is applied to all lower bus electrodes lower layer 26, then to V3 and all upper bus electrodes kasou 26. This was done by applying -V3.
[0006]
【The invention's effect】
As described above, a display device that is less affected by a voltage drop due to the wiring resistance of the scanning line can be realized, and a large-sized image display device can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing the structure of a thin film electron source of the present invention.
FIG. 2 is a diagram showing an operating principle of a thin film type electron source.
FIG. 3 is a diagram showing a conventional structure of a thin film type electron source.
FIG. 4 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 5 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 6 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 7 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 8 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 9 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 10 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 11 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 12 is a diagram showing a method of manufacturing a thin film type electron source of the present invention.
FIG. 13 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 14 is a view showing a structure of a thin film type electron source of the present invention.
FIG. 15 is a diagram showing a method for producing a thin film type electron source of the present invention.
FIG. 16 is a view showing an electron source substrate of a display device using the thin film type electron source of the present invention.
FIG. 17 is a view showing a phosphor screen substrate of a display device using the thin film type electron source of the present invention.
FIG. 18 is a cross-sectional view of a display device using the thin film type electron source of the present invention.
FIG. 19 is a diagram showing a connection to a drive circuit in a display device using the present invention.
FIG. 20 is a diagram showing driving voltage waveforms in the display device of the present invention.
[Explanation of symbols]
10 ... Substrate, 11 ... Lower electrode, 12 ... Insulating layer, 13 ... Upper electrode, 14 ... Protective insulating layer, 15 ... Upper bus electrode, 19 ... Second protection Insulating layer, 20 ... vacuum, 25 ... resist film, 26 ... lower layer of upper bus electrode, 27 ... interlayer insulating film, 28 ... upper layer of upper bus electrode, 29 ... surface insulating layer, 40 ... spacer, 50 ... lower electrode drive circuit, 60 ... upper electrode drive circuit, 70 ... acceleration voltage, 110 ... face plate, 111 ... red phosphor, 112 ... green Phosphor, 113 ... Blue phosphor, 114 ... Metal back, 115 ... Frit glass, 116 ... Frame.

Claims (4)

An electron source having an electron acceleration layer sandwiched between a first electrode and a second electrode, and emitting electrons from the second electrode side by applying a voltage between the first electrode and the second electrode. In an image display apparatus having a plurality of formed substrates and a phosphor screen, the electron source array has bus electrodes that are electrically connected to the second electrodes of two or more electron sources and serve as scanning lines . The bus electrode is formed of a multi-layer wiring having at least a first wiring and a second wiring, each extending along an arrangement direction of the two or more electron sources, and in the electron source array, An image display device, wherein the second wiring is electrically connected through a plurality of through holes formed in an interlayer insulating layer therebetween . A plurality of thin-film electron sources are formed which have an electron acceleration layer sandwiched between a lower electrode and an upper electrode and emit electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode. In the image display device having the substrate and the phosphor screen, the thin film electron source array has an upper bus electrode that is electrically connected to each upper electrode of two or more thin film electron sources and serves as a scanning line. The upper bus electrode is formed by a multilayer wiring composed of an upper bus electrode lower layer and an upper bus electrode upper layer, each extending along an arrangement direction of the two or more thin film electron sources, and the thin film electron source array In the image display device, the lower layer of the upper bus electrode and the upper layer of the upper bus electrode are electrically connected through a plurality of through holes formed in an interlayer insulating layer therebetween . The image display device according to claim 2, wherein a part of the upper layer of the upper bus electrode is formed of a plating film. 3. The image display device according to claim 2, wherein the image information is displayed by a line sequential driving method.

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