JP4127467B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device (semiconductor device) including a circuit formed of a thin film transistor (hereinafter referred to as TFT) on an insulator and a manufacturing method thereof. In particular, the present invention provides an electro-optical device (semiconductor device) represented by a liquid crystal display device in which a pixel portion and a drive circuit provided in the periphery thereof are provided on the same substrate, and the electro-optical device (semiconductor device) as a display portion. It relates to the electric appliance used.
[0002]
[Prior art]
In recent years, a polycrystalline semiconductor film (polysilicon film) obtained by crystallizing an amorphous semiconductor film (amorphous silicon film) formed on an insulating substrate such as glass has been activated, particularly a crystalline semiconductor film (crystalline silicon film). TFTs used as layers have been developed extensively.
[0003]
In addition, research and development are continuing on a process for forming a large-area polysilicon film on a substrate having low heat resistance such as a glass substrate or a plastic substrate. Examples of so-called low-temperature crystallization techniques include a method of crystallizing using laser light, a method of adding a catalyst element that promotes crystallization, and heat-treating to crystallize.
[0004]
A technique for adding a catalytic element for promoting crystallization to an amorphous silicon film, heat-treating and crystallizing is disclosed in Japanese Patent Laid-Open No. 7-130652.
[0005]
With this technique, the crystallization temperature of the amorphous silicon film can be lowered by 50 to 100 ° C. by the action of the catalytic element, and the time required for crystallization can be reduced to 1/5 to 1/10. Therefore, it is possible to form a large-area crystalline silicon film on the above-described substrate having low heat resistance. It has also been confirmed that the crystalline silicon film obtained by this technique has excellent crystallinity.
[0006]
[Problems to be solved by the invention]
In the crystallization technique using the catalyst element described above, a metal element such as Ni or Co is used as the catalyst element. These metal elements form deep energy levels in the silicon film, trap carriers, and recombine. Therefore, when a TFT is manufactured using the obtained crystalline silicon film, the electrical characteristics of the TFT and It can be expected to adversely affect reliability.
[0007]
In addition, it has been confirmed that the catalyst element remaining in the silicon film segregates irregularly, and this segregation is observed particularly at the grain boundary. This segregation becomes a weak current escape path (leakage path), and the off-current ( This is considered to cause a sudden increase in current when the TFT is in the off state.
[0008]
Therefore, when the crystallization process is completed, it is necessary to remove the catalytic element promptly or to reduce it to an extent that does not have an electrical influence. As this means, a technique using a gettering effect can be used.
[0009]
As a method of gettering, after an amorphous silicon film is crystallized with a metal element to form a crystalline silicon film, a channel forming region of the TFT semiconductor layer is covered with a resist mask, and the TFT semiconductor layer is formed. A region other than the channel formation region is doped with a group 15 element such as P, which is effective for gettering, at a high concentration so as to promote gettering (hereinafter referred to as a gettering sink). A method of covering the channel forming region with a resist mask and providing a gettering sink containing a high concentration of a group 15 element such as P around the region where the TFT semiconductor layer is formed is considered. It has been. However, these methods require a process for forming a mask and increase the number of masks and the number of processes, which causes problems in terms of productivity, yield, and manufacturing cost.
[0010]
The p-channel TFT is doped with a large amount of phosphorus for gettering, and then added with a p-type impurity element (boron (B) in this embodiment) to form a p-channel TFT. As a result, a drain region is formed. In order to reverse the n-type imparting by pre-doped phosphorus (P), it is necessary to dope a significant concentration of boron (B).
[0011]
For this reason, there has been a problem that throughput in the doping process is lowered or it is difficult to improve the crystallinity of the source region and the drain region by heat treatment.
[0012]
In order to perform the gettering process, phosphorus (P) needs to be added to the semiconductor layer. However, in order to obtain a p-channel TFT, it is necessary to add a p-type impurity element (typically boron (B)). Since there is a step of adding an n-type impurity element (phosphorus (P)) before the step of adding boron (B) to the semiconductor layer of the p-channel TFT, the concentration at which this n-type can be inverted to p-type The p-type impurity element is added (also called counter-doping or cross-doping). The concentration of boron (B) must be higher than the concentration of added phosphorus (P). However, if the impurity concentration is too high, the resistance of the source / drain region increases, causing a decrease in on-current. End up. Furthermore, when the counter-doping method is employed, there is a problem in manufacturing cost and productivity because ions that serve as acceptors must be excessively doped.
[0013]
[Means for Solving the Problems]
A method for manufacturing an electro-optical device (semiconductor device) disclosed in the present invention will be described. When forming the shape of the gate electrode by etching the conductive film (A) and the conductive film (B) formed over the gate insulating film, the gate electrode of the n-channel TFT is etched into a predetermined shape. However, the gate electrode (C) of the p-channel TFT is used as a mask so that the region where the n-type impurity element is added to the semiconductor layer of the p-channel TFT is not increased in the subsequent n-type impurity element addition step. In this etching step, the conductive film (A) and the conductive film (B) are etched so that the width in the channel length direction is larger than the gate electrode (B) of the n-channel TFT. Using this gate electrode (C) as a mask, the semiconductor layer region that does not overlap with the gate electrode (C) is doped with phosphorus (P). The region where phosphorus (P) is implanted functions as a gettering sink.
[0014]
Next, the gate electrode (D) of the p-channel TFT is etched into a predetermined shape to obtain a gate electrode (E) having a predetermined shape, and then p-type is imparted to the semiconductor layer of the p-channel TFT. Dope boron (B). Through the steps so far, a channel formation region, a region doped with phosphorus (P) and boron (B), and a region doped only with boron (B) are formed in the semiconductor layer of the p-channel TFT. .
[0015]
According to the present invention, during the gettering, the distance that the catalytic element moves through the semiconductor layer of the p-channel TFT can be shortened, so that the segregation of the catalytic element at the crystal grain boundary is reduced and the weak current due to the segregation is reduced. Phenomenon such as escape path (leak path) and off-current (sudden increase in T) can be reduced, and TFT characteristics and reliability can be improved.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The invention disclosed in this specification is characterized by a method of forming a gate electrode of a p-channel TFT in a predetermined shape. The present invention will be described with reference to FIG.
[0017]
In order to solve the above problems, the invention disclosed in this specification has an object of reducing the amount of phosphorus (P) added to a semiconductor layer of a p-channel TFT.
[0018]
In order to prevent the catalytic element from segregating at the grain boundaries and causing this to deteriorate the TFT characteristics, the gettering moves inside the semiconductor layer from the channel formation region to the source region and the drain region. The moving distance of the catalytic element is made as short as possible.
[0019]
Therefore, in the present invention, the etching process for forming the gate electrode of the n-channel TFT and the gate electrode of the p-channel TFT in a predetermined shape is a separate process. As shown in FIG. 1A, first, a gate electrode of an n-channel TFT is formed into a predetermined shape by etching, and an n-type impurity element is added. FIG. 1D shows a top view of the p-channel TFT at this time. The conductive film (A) and the conductive film (B) are etched larger than the shape of the predetermined gate electrode. The conductive film (A) and the conductive film (B) are referred to as the gate electrode 8. Using this gate electrode 8 as a mask, a region 10 to which phosphorus of an n-type impurity element is added is formed.
[0020]
Next, as shown in FIG. 1B, after forming a mask on the n-channel TFT, the conductive film of the p-channel TFT is etched to form a gate electrode 9 having a predetermined shape. Thereafter, a p-type impurity element is added as shown in FIG. By adopting such a process, in the p-channel TFT, as shown in FIG. 1E, only the region 11 doped with phosphorus as the n-type impurity element and boron as the p-type impurity element and boron are added. Although the region 12 is formed, the region 11 to which phosphorus and boron to be counter-doped are added can be narrowed. Note that an impurity element is not added to the semiconductor layer under the gate electrode etched into a predetermined shape, so that a channel formation region 13 is formed.
[0021]
As described above, a region to which both phosphorus (P) and boron (B) are added is formed in the semiconductor layer of the p-channel TFT, as shown in FIG. The object of the present invention is achieved as a ring sink.
[0022]
Note that in the p-channel TFT, the conductive film (A) and the conductive film (B) are etched as shown in FIG. 1F to form a gate electrode 18, and an n-type impurity element is formed using the gate electrode 18 as a mask. It may be added. Thereby, a region 20 to which only phosphorus is added as shown in FIG. 1F is formed. Then, after the gate electrode 18 is etched into a predetermined shape to form the gate electrode 19, a p-type impurity element is added, and the regions 21a and 21b to which the n-type impurity element and the p-type impurity element are added and the p-type impurity element are added. A region 22 to which only an impurity element is added is formed. As described above, a structure in which the distance by which the catalytic element moves to the gettering sink during the gettering shown in FIG. 1G can be realized.
[0023]
(Example 1)
An embodiment of the present invention will be described with reference to FIGS. Here, a method for manufacturing the pixel TFT of the pixel portion and the TFT of the driver circuit provided around the pixel portion over the same substrate will be described in detail according to the process.
[0024]
In FIG. 3A, a low alkali glass substrate or a quartz substrate can be used for the substrate 100. In this example, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. In order to prevent impurity diffusion from the substrate 100, a base film 101 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 100 where the TFT is formed. For example, a silicon oxynitride film made of SiH4, NH3, and N2O is formed by plasma CVD to a thickness of 100 nm, and similarly a silicon oxynitride film made of SiH4 and N2O is formed to a thickness of 200 nm.
[0025]
Next, a semiconductor film having an amorphous structure with a thickness of 20 to 150 nm (preferably 30 to 80 nm) is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film. Further, since the base film 101 and the amorphous silicon film can be formed by the same film formation method, both may be formed continuously. After the base film is formed, it is possible to prevent the surface from being contaminated by not exposing it to the air atmosphere, and it is possible to reduce variation in characteristics and threshold voltage of the TFT to be manufactured (FIG. 3A). )).
[0026]
Then, a semiconductor film including a crystal structure (in this embodiment, a crystalline silicon film) is formed according to the technique described in JP-A-7-130652. The technology described in the publication is based on the catalyst element (Ni, Co, Sn, Pb, Pd, Fe, Cu selected from one or a plurality of elements that promotes crystallization when the amorphous silicon film is crystallized. (Typically, it is Ni.).
[0027]
Specifically, heat treatment is performed with the catalytic element held on the surface of the amorphous silicon film to change the amorphous silicon film into a crystalline silicon film. In this example, the method described in Example 1 of the publication is used, but the method described in Example 2 may be used. Note that the crystalline silicon film includes a so-called single crystal silicon film and a polysilicon film, but the crystalline silicon film formed in this embodiment is a silicon film having a crystal grain boundary.
[0028]
As a method for adding the catalytic element to the amorphous silicon film, a plasma doping method, a vapor phase method such as a vapor deposition method or a sputtering method, or a method of applying a solution containing the catalytic element can be employed. In the method using a solution, the addition amount of the catalyst element can be easily controlled, and a very small amount can be easily added.
[0029]
Further, the crystallinity of the crystalline semiconductor film can be further improved by combining the above-described crystallization method and laser crystallization method. The laser used at this time is a pulse generator. Shake Type or continuous emission type KrF excimer laser, XeCl excimer laser, YAG laser or YVO ₄ A laser can be used. When using these lasers, Shake It is preferable to use a method in which laser light emitted from the vessel is condensed into a linear shape by an optical system and irradiated onto a semiconductor film. The practitioner may select the crystallization conditions as appropriate.
[0030]
When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the film is densified. Therefore, the thickness of the produced crystalline silicon film is larger than the thickness of the initial amorphous silicon film (55 nm in this embodiment). Also decreased by about 1 to 15%.
[0031]
Then, the crystalline silicon film is divided into island shapes, so that island-like semiconductor layers 102 to 105 are formed.
[0032]
Here, for the purpose of controlling the threshold voltage over the entire surface of the island-like semiconductor layers 102 to 105 forming the n-channel TFT, 1 × 10 ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three Boron (B) may be added as an impurity element imparting p-type at a moderate concentration. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film. Although boron (B) is not necessarily added here, the semiconductor layers 102 to 105 to which boron (B) is added are preferably formed in order to keep the threshold voltage of the n-channel TFT within a predetermined range. It was good.
[0033]
Next, the gate insulating film 106 is formed with an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method or a sputtering method. For example, a silicon oxynitride film is formed with a thickness of 120 nm. As the gate insulating film 106, another insulating film containing silicon may be used as a single layer or a stacked structure.
[0034]
Next, a conductive film (A) 107 and a conductive film (B) 108 are formed to form a gate electrode. In this example, a conductive layer (A) 107 made of a conductive nitride metal film and a conductive layer (B) 108 made of a metal film were laminated. The conductive layer (B) 108 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. (Typically, a Mo—W alloy film or a Mo—Ta alloy film) may be used. The conductive layer (A) 107 is a tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or nitride. It is made of molybdenum (MoN). Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be applied to the conductive layer (A) 107 as an alternative material. In the conductive layer (B), the concentration of impurities contained in the conductive layer (B) should be reduced in order to reduce the resistance. In particular, the oxygen concentration should be 30 ppm or less. For example, tungsten (W) was able to realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.
[0035]
The conductive layer (A) 107 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 108 may be 200 to 400 nm (preferably 250 to 350 nm). In this example, a tantalum nitride film having a thickness of 30 nm was used for the conductive layer (A) 107 and a Ta film of 350 nm was used for the conductive layer (B) 108, both of which were formed by sputtering. In film formation by this sputtering method, if an appropriate amount of Xe or Kr is added to the sputtering gas Ar, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 107. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) 107 or the conductive layer (B) 108 is added to the gate insulating film 106. Diffusion can be prevented (FIG. 3A).
[0036]
Next, resist masks 109 to 112 are formed, and a first etching process is performed to form gate electrodes and capacitor wirings of the respective TFTs. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and the etching gas is CF. _Four And Cl ₂ And O ₂ Each gas flow rate ratio is 25/25/10 (sccm), and 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. It was. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching condition so that the end portion of the first conductive layer is tapered.
[0037]
Thereafter, the second etching condition is changed without removing the masks 109 to 112, and the etching gas is changed to CF. _Four And Cl ₂ The gas flow ratio is 30/30 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma for about 30 seconds. Etching was performed. A 20 W RF (13.56 MHz) power is also applied to the substrate side to apply a substantially negative self-bias voltage. CF _Four And Cl ₂ Under the second etching condition in which the W and TaN films are mixed, the W film and the TaN film are etched to the same extent. Through the steps so far, the gate electrode (A) 113 of the n-channel TFT whose end portion is made of the conductive film (A) 107 and the conductive film (B) 108 and the gate electrode (C) 114 of the p-channel TFT are formed. A gate electrode (F) 115 and a capacitor wiring 116 of the pixel TFT are formed. Note that the gate electrode (C) 114 of the p-channel TFT is designed to be larger than the gate electrode (A) 113 of the n-channel TFT and the gate electrode (F) 115 of the pixel TFT. Through the steps so far, the region of the gate insulating film 106 not covered with the masks 109 to 112 is etched and thinned. Note that the gate electrode (A), the gate electrode (C), the gate electrode (F), and the capacitor wiring 116 formed by the first etching treatment are also referred to as a first shape gate electrode and a capacitor wiring. The gate electrode (C) 114 is used as a mask so that a region to which the n-type impurity element is added in the semiconductor layer of the p-channel TFT is not widened in a subsequent n-type impurity element addition step. It is formed wider than the gate electrode (A) 113 in the TFT.
[0038]
Then, an n-type impurity element is added without removing the masks 109 to 112 to form an impurity region 118 (FIG. 3B). As the n-type impurity element, phosphorus (P) or arsenic (As) may be used. Here, phosphorous (PH) is added to add phosphorus (P). _Three ) Was applied.
[0039]
Further, the second etching process is performed without removing the masks 109 to 112. Here, CF is used as an etching gas. _Four And Cl ₂ And O ₂ Each gas flow rate ratio is 20/20/20 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa. Apply voltage. According to the second etching process condition, the W film is selectively etched.
[0040]
By this second etching process, the conductive films (A) 113a to 116a and the conductive films (B) 113b to 116b are etched, and the gate electrode (B) 119, the gate electrode (D) 120, the gate electrode (G) 121, A capacitor wiring 122 is formed. In this step, the gate electrode (B) 119, the gate electrode (G) 121 and the capacitor wiring 122 of the n-channel TFT, which are formed in a predetermined shape, are the gate electrode (D) of the p-channel TFT. Since 120 is used as a mask for narrowing a region containing a high concentration of an n-type impurity element in a semiconductor layer of a p-channel TFT, a predetermined shape (another gate electrode (B) 119, a gate electrode (G ) 121) It is formed in a larger size. Note that the gate electrode (B) 119, the gate electrode (G) 121, the gate electrode (D) 120, and the capacitor wiring 122 which are formed by the second etching treatment are also referred to as a second shape gate electrode and a capacitor wiring. To do.
[0041]
Next, treatment for adding an n-type impurity element to the semiconductor layer is performed. The gate electrode (B) 119, the gate electrode (D) 120, and the gate electrode (G) 121 formed by the second etching process are used as masks, and the semiconductor layer below the tapered portion of the conductive film (A) is also used. N-type impurity regions (A) 123a to 126a and n-type impurity regions (B) 123b to 126b are formed by doping so that an n-type impurity element is added. The impurity (phosphorus (P)) concentration of the impurity regions 123a to 126a formed at this time is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three What should be done. (In this specification, the concentration of the n-type impurity element contained in the n-type impurity regions 123a to 126a is represented as (n +).) Further, the impurity concentration of the n-type impurity regions (B) 123b to 126b is 5 × 10 ¹⁷ ~ 5x10 ¹⁹ atoms / cm ^Three What should be done. In this specification, the concentration of the n-type impurity element contained in the n-type impurity regions 123b to 126b is represented by (n−). Note that an n-type impurity region 123c overlapping with the tapered portion of the conductive layer (A) 119a has an impurity concentration slightly lower than that of the n-type impurity region 123b, although the impurity concentration is slightly lower (see FIG. 4 (A)).
[0042]
Next, after removing the resist masks 109 to 112, a resist mask 127 that covers the n-channel TFT is newly formed, and a third etching process is performed. The etching gas is SF6 and Cl2, and the gas flow ratio is 50/10 (SCCM), and 500 W of RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 1.3 Pa. Then, plasma is generated and etching is performed for about 30 seconds. 10 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Through the above steps, the gate electrode (D ′) 128 of the p-channel TFT and the gate electrode (H) 129 of the pixel TFT in which the conductive films (A) 120a and 121a are etched are formed. Note that the gate electrode (D ′) 128 and the gate electrode (H) 129 formed by the third etching treatment are also referred to as third-shaped gate electrodes.
[0043]
Next, a mask 130 made of resist for etching to make the gate electrode (D ′) 128 of the p-channel TFT have a predetermined size and masks 131 and 132 made of resist covering the pixel TFT and the capacitor wiring are formed. Next, the gate electrode (D ′) 128 of the p-channel TFT is etched to obtain a gate electrode (E) 133 of the p-channel TFT (FIG. 4C). Note that the gate electrode (E) 133 formed by the fourth etching treatment is also referred to as a fourth shape gate electrode.
[0044]
Next, a p-type impurity element (boron (B) in this embodiment) is added to the semiconductor layer of the p-channel TFT to form p-type impurity regions 134 to 137. The impurity concentration of the p-type impurity element in the p-type impurity regions 134 and 136 is 2 × 10 ²⁰ ~ 2x10 ^{twenty one} atoms / cm ^Three Add to be. In this embodiment, the TaN film provided above the region of the semiconductor layer to which boron (B) is added is removed before adding boron (B) to the semiconductor layer of the p-channel TFT. Boron (B) can be added at a low acceleration, and damage to the semiconductor layer during the addition can be reduced.
[0045]
Through the steps so far, an n-type impurity region and a p-type impurity region are formed in each semiconductor region (FIG. 4D).
[0046]
Next, the masks 130 to 132 are removed, and an inorganic interlayer insulating film 138 is formed. A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed to a thickness of 50 to 500 nm (typically 100 to 300 nm). In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Of course, the inorganic interlayer insulating film is not limited to a silicon oxynitride film, and an insulating film containing other silicon may have a single layer or a laminated structure.
[0047]
Next, a step of activating the impurity element added to the semiconductor layer is performed. This activation process is performed using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, 550 ° C. Activation treatment was performed by heat treatment for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing (RTA) method can be applied.
[0048]
In this example, simultaneously with the activation process, gettering was performed on the n-type impurity region containing high-concentration phosphorus in order to reduce the remaining amount of the catalyst element used as a catalyst during crystallization. . The concentration of phosphorus (P) necessary for gettering is approximately the same as that of the impurity region (n +) formed in FIG. 4B. By the heat treatment in the activation process performed here, an n-channel TFT and The catalytic element could be gettered from the channel formation region of the p-channel TFT. The obtained TFT has a low off-state current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0049]
Further, the activation treatment may be performed before the inorganic insulating film 138 is formed. However, when the material used for the gate electrode is weak against heat, an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed for the purpose of protecting the wiring and the like as in this embodiment. It is desirable to perform an activation process later.
[0050]
Furthermore, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the semiconductor layer. In this embodiment, heat treatment is performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0051]
In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the hydrogenation.
[0052]
Next, an organic interlayer insulating film 139 made of an organic insulating material is formed on the inorganic interlayer insulating film 138. In this example, an acrylic resin film having a thickness of 1.6 μm was formed. Next, patterning is performed to form contact holes that reach the impurity regions.
[0053]
Thereafter, a transparent conductive film is formed with a thickness of 80 to 120 nm, and the pixel electrode 140 is formed by patterning. For the transparent conductive film, indium oxide zinc oxide alloy (In ₂ O _Three -ZnO) and zinc oxide (ZnO) are also suitable materials, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added in order to increase the transmittance and conductivity of visible light can also be applied. .
[0054]
In the driver circuit portion 205, wirings 141 to 143 that are electrically connected to the impurity regions are formed. Note that these electrodes are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm.
[0055]
In the pixel portion 206, wirings 144 to 147 in contact with the impurity regions are formed.
[0056]
The pixel electrode 140 is electrically connected to the semiconductor layer 105 functioning as one electrode forming a storage capacitor by the wiring 146.
[0057]
Note that although a transparent conductive film is used as the pixel electrode 140 in this embodiment, a reflective display device can be manufactured if the pixel electrode is formed using a conductive material having reflectivity. it can. In that case, the pixel electrode can be formed at the same time in the step of manufacturing the electrode, and the material of the pixel electrode should be a material having excellent reflectivity such as a film containing Al or Ag as a main component or a laminated film thereof. Is desirable.
[0058]
In this way, a substrate having the TFT of the driving circuit and the pixel TFT of the pixel portion on the same substrate was completed. An n-channel TFT 201 and a p-channel TFT 202 are formed in the driver circuit, and a pixel TFT 203 and a storage capacitor 204 are formed in the pixel portion. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0059]
FIG. 2 shows a top view of the active matrix substrate manufactured through the steps up to here. Note that the AA ′ line in FIG. 2 corresponds to the AA ′ line in FIG. 5B, and the semiconductor layer 104, the gate electrode 121, the wiring 144, the gate line, and the source line are formed. Similarly, the BB ′ line in FIG. 2 corresponds to the BB ′ line in FIG. 5B, and the semiconductor layer 105, the pixel electrode 140, and the wiring 146 are formed.
[0060]
The n-channel TFT 201 of the driver circuit includes an impurity region 123c (hereinafter referred to as this region) that overlaps the island-shaped semiconductor layer 102 with the channel formation region, the source or drain region 123a, the impurity region 123b, and the second shape gate electrode (B) 119. Such an impurity region is referred to as Lov). The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. In addition, a gate electrode (B) 119 having a second shape formed by stacking a conductive film (A) 119a and a conductive film (B) 119b is provided.
[0061]
The p-channel TFT 202 of the driver circuit includes a channel formation region, a source or drain region 124a, and an impurity region 124b in the island-like semiconductor layer 103. In addition, a gate electrode (E) 133 having a fourth shape formed by stacking a conductive film (A) 133a and a conductive film (B) 133b is provided.
[0062]
The pixel TFT 203 in the pixel portion includes a channel formation region, a source or drain region 125a, and impurity regions 125b and 125c in the island-like semiconductor layer 104. In addition, a gate electrode (H) 129 having a third shape formed by stacking a conductive film (A) 129a and a conductive film (B) 129b is provided.
[0063]
Further, a storage capacitor 204 is formed from the capacitor wiring 122, an insulating film made of the same material as the gate insulating film, and the semiconductor layer 105 to which a p-type impurity element is added. In FIG. 5, the pixel TFT 203 has a double gate structure, but it may have a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided.
[0064]
As described above, the present invention can optimize the structure of TFTs constituting each circuit in accordance with specifications required by the pixel portion and the drive circuit, and can improve the operation performance and reliability of the semiconductor device. it can. Further, activation of the LDD region, the source region, and the drain region can be facilitated by forming the gate electrode from a heat-resistant conductive material, and wiring resistance can be sufficiently reduced by forming the wiring from a low-resistance material. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inches class or more.
[0065]
(Example 2)
In this embodiment, a process for manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 6 is used for the description.
[0066]
First, after an active matrix substrate in the state of FIG. 5B is obtained according to Embodiment 1, an alignment film 180 is formed on the active matrix substrate of FIG. 5B and a rubbing process is performed. In this embodiment, before forming the alignment film 180, columnar spacers 181 for holding the substrate interval are formed at predetermined positions by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0067]
Next, a counter substrate 182 is prepared. Color layers 183 and 184 and a planarizing film 185 are formed on the counter substrate. The red colored layer 183 and the blue colored layer 184 are partially overlapped to form the second light shielding portion. Although not shown in FIG. 6, the first light-shielding portion is formed by partially overlapping the red colored layer and the green colored layer.
[0068]
Next, a counter electrode 186 was formed in the pixel portion, an alignment film 187 was formed on the entire surface of the counter substrate, and a rubbing process was performed.
[0069]
Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are attached to each other with a sealant 188. A filler is mixed in the sealing material 188, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 189 is injected between both the substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 189. Thus, the active matrix type liquid crystal display device shown in FIG. 6 is completed. Then, if necessary, the active matrix substrate or the counter substrate is divided into a predetermined shape. Furthermore, a polarizing plate or the like was appropriately provided using a known technique. And FPC was affixed using the well-known technique.
[0070]
The structure of the liquid crystal display panel thus obtained will be described with reference to the top view of FIG. In addition, the same code | symbol was used for the part corresponding to FIG.
[0071]
The top view shown in FIG. 7A is a pixel portion 206, drive circuits 205a and 205b, an external input terminal 210 to which an FPC (Flexible Printed Circuit Board: Flexible Printed Circuit) is pasted, an external input terminal and an input portion of each circuit. An active matrix substrate on which connection wiring 211 or the like is connected and a counter substrate 182 provided with a color filter or the like are attached to each other with a sealant 188 interposed therebetween.
[0072]
FIG. 7B shows a cross-sectional view of the external input terminal 210 shown in FIG. An FPC composed of a base film 213 and a wiring 214 is bonded to the external input terminal with an anisotropic conductive resin 215, and the mechanical strength is enhanced by a reinforcing plate. Reference numeral 217 denotes a wiring made of a conductive film formed to form the pixel electrode 140. Since the outer diameter of the conductive particles 216 is smaller than the pitch of the wirings 217, if the amount dispersed in the adhesive 215 is appropriate, it is electrically connected to the corresponding wiring on the FPC side without short-circuiting with the adjacent wirings. Can be formed.
[0073]
The liquid crystal display panel manufactured as described above can be used as a display portion of various electric appliances.
[0074]
(Example 3)
In this embodiment, a method for manufacturing a semiconductor device, which is different from that in Embodiment 1, will be described.
[0075]
After forming the gate electrode (E) 133 in the third etching process according to the process shown in Example 1, the gate electrode (B) 119, the gate electrode (E) 133, and the gate electrode (H) formed in the above process are used. The gate insulating film 117 in a region that does not overlap with the gate electrodes 119, 129, 133 and the capacitor wiring 122 is removed by etching using the gate electrode 129 and the capacitor wiring 122 as a mask.
[0076]
If the gate insulating film is removed by etching, the gate insulating film is likely to vary in position depending on the position in the gate electrode etching process several times during the impurity doping process. There is no need to consider the thickness.
[0077]
The present embodiment can be applied in combination with the first embodiment and the second embodiment.
[0078]
Example 4
A block diagram of a semiconductor device manufactured using the present invention is shown in FIG. FIG. 8 shows a circuit configuration for performing analog driving. This embodiment shows a semiconductor device having a source side driver circuit 90, a pixel portion 91, and a gate side driver circuit 92. Note that in this specification, a driving circuit refers to a generic name including a source side driving circuit and a gate side driving circuit.
[0079]
The source side driver circuit 90 includes a shift register 90a, a buffer 90b, and a sampling circuit (transfer gate) 90c. The gate side driving circuit 92 includes a shift register 92a, a level shifter 92b, and a buffer 92c. Further, if necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.
[0080]
In this embodiment, the pixel unit 91 includes a plurality of pixels, and each of the plurality of pixels includes a TFT element.
[0081]
Although not shown, a gate side drive circuit may be further provided on the opposite side of the gate side drive circuit 92 with the pixel portion 91 interposed therebetween.
[0082]
In the case of digital driving, as shown in FIG. 9, a latch (A) 93b and a latch (B) 93c may be provided instead of the sampling circuit. The source side driving circuit 93 includes a shift register 93a, a latch (A) 93b, a latch (B) 93c, a D / A converter 93d, and a buffer 93e. The gate side driving circuit 95 includes a shift register 95a, a level shifter 95b, and a buffer 95c. If necessary, a level shifter circuit may be provided between the latch (B) 93c and the D / A converter 93d.
[0083]
In addition, the said structure is realizable according to the manufacturing process shown in Example 1. FIG. In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of the present invention, a memory and a microprocessor can be formed.
[0084]
Example 5
The CMOS circuit and the pixel portion formed by implementing the present invention can be used for various semiconductor devices (active matrix liquid crystal displays). That is, the present invention can be applied to all electric appliances in which these semiconductor devices are incorporated in a display portion.
[0085]
Such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned. Examples of these are shown in FIGS. 10, 11 and 12. FIG.
[0086]
FIG. 10A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.
[0087]
FIG. 10B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be applied to the display portion 2102 and other signal control circuits.
[0088]
FIG. 10C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.
[0089]
FIG. 10D illustrates a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302 and other signal control circuits.
[0090]
FIG. 10E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.
[0091]
FIG. 10F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.
[0092]
FIG. 11A illustrates a front projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 constituting a part of the projection device 2601 and other signal control circuits.
[0093]
FIG. 11B shows a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like. The present invention can be applied to the liquid crystal display device 2808 constituting a part of the projection device 2702 and other signal control circuits.
[0094]
Note that FIG. 11C illustrates an example of the structure of the projection devices 2601 and 2702 in FIGS. 11A and 11B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0095]
FIG. 11D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 11D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0096]
However, the projector shown in FIG. 11 shows a case where a transmissive semiconductor device is used, and an application example using a reflective semiconductor device is not shown.
[0097]
FIG. 12A shows a mobile phone, 3001 is a display panel, and 3002 is an operation panel. The display panel 3001 and the operation panel 3002 are connected at a connection portion 3003. An angle θ between the surface of the connection unit 3003 on which the display unit 3004 of the display panel 3001 is provided and the surface of the operation panel 3002 on which the operation keys 3006 are provided can be arbitrarily changed.
Further, it has an audio output unit 3005, operation keys 3006, a power switch 3007, and an audio input unit 3008. The present invention can be applied to the display portion 3004.
[0098]
FIG. 12B illustrates a portable book (electronic book) which includes a main body 3101, display portions 3102 and 3103, a storage medium 3104, operation switches 3105, an antenna 3106, and the like. The present invention can be applied to the display portions 3102 and 3103 and other signal circuits.
[0099]
FIG. 12C illustrates a display, which includes a main body 3201, a support base 3202, a display portion 3203, and the like. The present invention can be applied to the display portion 3203. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0100]
As described above, the application range of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-4.
[0101]
【The invention's effect】
According to the present invention, gettering of the semiconductor layer of the p-channel TFT can be sufficiently performed without increasing the number of masks and the number of processes, and the resistance of the source region and the drain region can be reduced. In addition, since gettering can be sufficiently performed, adverse effects due to the catalytic element can be reduced, and a highly reliable p-channel TFT can be manufactured relatively easily and with a high yield.
[Brief description of the drawings]
FIG. 1 shows an embodiment of the present invention.
FIG. 2 is a diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing an example of an embodiment of the present invention.
FIG. 4 is a diagram showing an example of an embodiment of the present invention.
FIG. 5 is a diagram showing an example of an embodiment of the present invention.
FIG. 6 is a diagram showing an example of an embodiment of the present invention.
FIG. 7 is a diagram showing an example of an embodiment of the present invention.
FIG. 8 is a diagram showing an example of an embodiment of the present invention.
FIG. 9 is a diagram showing an example of an embodiment of the present invention.
FIG. 10 is a diagram showing an example of an electric appliance using a semiconductor device manufactured according to the present invention for a display portion.
FIG. 11 is a diagram showing an example of an electric appliance using a semiconductor device manufactured according to the present invention for a display portion.
FIGS. 12A and 12B illustrate an example of an electrical appliance in which a semiconductor device manufactured using the present invention is used for a display portion. FIGS.

Claims (15)

A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A conductive film is provided on the gate insulating film, and the conductive film is etched to be a first conductive layer that later becomes a gate electrode of an n-channel TFT, and a second conductive layer that later becomes a gate electrode of a p-channel TFT. A fifth step of forming
A sixth step of adding an n-type impurity element to the semiconductor layer using the first conductive layer and the second conductive layer as a mask;
A seventh step of etching the first conductive layer and the second conductive layer to form a third conductive layer to be a gate electrode of an n-channel TFT and a gate electrode of a p-channel TFT, respectively; ,
An eighth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT and the third conductive layer as a mask;
A region to be an n-channel TFT is covered with a resist mask, the third conductive layer is etched to form a gate electrode of the p-channel TFT, and then a p-type impurity element is formed in the semiconductor layer of the p-channel TFT. A ninth step of adding
The second conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The first conductive layer is formed to have a larger width in the channel length direction, and the third conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element has been added to form a crystalline semiconductor layer and increasing the crystallinity of the crystalline semiconductor layer using a laser irradiation method;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A conductive film is provided on the gate insulating film, and the conductive film is etched to be a first conductive layer that later becomes a gate electrode of an n-channel TFT, and a second conductive layer that later becomes a gate electrode of a p-channel TFT. A fifth step of forming
A sixth step of adding an n-type impurity element to the semiconductor layer using the first conductive layer and the second conductive layer as a mask;
A seventh step of etching the first conductive layer and the second conductive layer to form a third conductive layer to be a gate electrode of an n-channel TFT and a gate electrode of a p-channel TFT, respectively; ,
An eighth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT and the third conductive layer as a mask;
A region to be an n-channel TFT is covered with a resist mask, the third conductive layer is etched to form a gate electrode of the p-channel TFT, and then a p-type impurity element is formed in the semiconductor layer of the p-channel TFT. A ninth step of adding
The second conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The first conductive layer is formed to have a larger width in the channel length direction, and the third conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer as a mask;
Etching the second conductive layer, the third conductive layer, and the fourth conductive layer to form a gate electrode of an n-channel TFT having a narrower width than the second conductive layer, and the third conductive layer A fifth conductive layer that becomes a gate electrode of a p-channel TFT after a narrower width and an eighth conductive layer that becomes a gate electrode of a pixel TFT after a narrower width than the fourth conductive layer are formed. And the process of
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer, and the sixth conductive layer as a mask;
A tenth step of etching the fifth conductive layer and the sixth conductive layer to form a seventh conductive layer that will later become a gate electrode of a p-channel TFT and a gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
And adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element has been added to form a crystalline semiconductor layer and increasing the crystallinity of the crystalline semiconductor layer using a laser irradiation method;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer as a mask;
Etching the second conductive layer, the third conductive layer, and the fourth conductive layer to form a gate electrode of an n-channel TFT having a narrower width than the second conductive layer, and the third conductive layer A fifth conductive layer that becomes a gate electrode of a p-channel TFT after a narrower width and an eighth conductive layer that becomes a gate electrode of a pixel TFT after a narrower width than the fourth conductive layer are formed. And the process of
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer, and the sixth conductive layer as a mask;
A tenth step of etching the fifth conductive layer and the sixth conductive layer to form a seventh conductive layer that will later become a gate electrode of a p-channel TFT and a gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
And adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
A sixth conductive layer is formed by etching the first conductive layer to form a second conductive layer that later becomes a gate electrode of an n-channel TFT and a third conductive layer that later becomes a gate electrode of a p-channel TFT. Process,
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer and the third conductive layer formed in the sixth step as a mask;
The second conductive layer and the third conductive layer formed in the sixth step are etched to form a fourth conductive layer that becomes a gate electrode of an n-channel TFT and a gate electrode of a p-channel TFT later. An eighth step of forming each of the layers;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT formed in the eighth step and the fourth conductive layer as a mask;
a tenth step of covering the n-channel TFT with a resist mask and etching the fourth conductive layer to form a gate electrode of the p-channel TFT;
And an eleventh step of adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fourth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element has been added to form a crystalline semiconductor layer and increasing the crystallinity of the crystalline semiconductor layer using a laser irradiation method;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
A sixth conductive layer is formed by etching the first conductive layer to form a second conductive layer that later becomes a gate electrode of an n-channel TFT and a third conductive layer that later becomes a gate electrode of a p-channel TFT. Process,
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer and the third conductive layer formed in the sixth step as a mask;
The second conductive layer and the third conductive layer formed in the sixth step are etched to form a fourth conductive layer that becomes a gate electrode of an n-channel TFT and a gate electrode of a p-channel TFT later. An eighth step of forming each of the layers;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT formed in the eighth step and the fourth conductive layer as a mask;
a tenth step of covering the n-channel TFT with a resist mask and etching the fourth conductive layer to form a gate electrode of the p-channel TFT;
And an eleventh step of adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fourth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer formed in the sixth step as a mask;
The second conductive layer, the third conductive layer, and the fourth conductive layer formed in the sixth step are etched to form an n-channel TFT gate electrode, and later a p-channel TFT gate. An eighth step of forming a fifth conductive layer to be an electrode and a sixth conductive layer to be a gate electrode of the pixel TFT later;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer and the sixth conductive layer formed in the eighth step as a mask; When,
The n-channel TFT formed in the driver circuit is covered with a mask made of resist, the fifth conductive layer and the sixth conductive layer are etched, and a seventh conductive layer that later becomes the gate electrode of the p-channel TFT. A tenth step of forming each of the layer and the gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
And adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer formed in the sixth step as a mask;
The second conductive layer, the third conductive layer, and the fourth conductive layer formed in the sixth step are etched to form an n-channel TFT gate electrode, and later a p-channel TFT gate. An eighth step of forming a fifth conductive layer to be an electrode and a sixth conductive layer to be a gate electrode of the pixel TFT later;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer and the sixth conductive layer formed in the eighth step as a mask; When,
The n-channel TFT formed in the driver circuit is covered with a mask made of resist, the fifth conductive layer and the sixth conductive layer are etched, and a seventh conductive layer that later becomes the gate electrode of the p-channel TFT. A tenth step of forming each of the layer and the gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
A twelfth step of adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask;
A thirteenth step of heat treatment;
A fourteenth step of covering the entire surface with an inorganic interlayer insulating film;
A fifteenth step of forming an organic interlayer insulating film on the inorganic interlayer insulating film;
A sixteenth step of forming a contact hole reaching the semiconductor layer in the inorganic interlayer insulating film and the organic interlayer insulating film;
A seventeenth step of forming a pixel electrode on the organic interlayer insulating film;
An 18th step of forming connection wiring,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer formed in the sixth step as a mask;
The second conductive layer, the third conductive layer, and the fourth conductive layer formed in the sixth step are etched to form an n-channel TFT gate electrode, and later a p-channel TFT gate. An eighth step of forming a fifth conductive layer to be an electrode and a sixth conductive layer to be a gate electrode of the pixel TFT later;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer and the sixth conductive layer formed in the eighth step as a mask; When,
The n-channel TFT formed in the driver circuit is covered with a mask made of resist, the fifth conductive layer and the sixth conductive layer are etched, and a seventh conductive layer that later becomes the gate electrode of the p-channel TFT. A tenth step of forming each of the layer and the gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
A twelfth step of adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask;
A thirteenth step of covering the entire surface with an inorganic interlayer insulating film;
A fourteenth step of heat treatment to getter the catalytic element;
A fifteenth step of forming an organic interlayer insulating film on the inorganic interlayer insulating film;
A sixteenth step of forming a contact hole reaching the semiconductor layer in the inorganic interlayer insulating film and the organic interlayer insulating film;
A seventeenth step of forming a pixel electrode on the organic interlayer insulating film;
An 18th step of forming connection wiring,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element has been added to form a crystalline semiconductor layer and increasing the crystallinity of the crystalline semiconductor layer using a laser irradiation method;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer formed in the sixth step as a mask;
The second conductive layer, the third conductive layer, and the fourth conductive layer formed in the sixth step are etched to form an n-channel TFT gate electrode, and later a p-channel TFT gate. An eighth step of forming a fifth conductive layer to be an electrode and a sixth conductive layer to be a gate electrode of the pixel TFT later;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer and the sixth conductive layer formed in the eighth step as a mask; When,
The n-channel TFT formed in the driver circuit is covered with a mask made of resist, the fifth conductive layer and the sixth conductive layer are etched, and a seventh conductive layer that later becomes the gate electrode of the p-channel TFT. A tenth step of forming each of the layer and the gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
A twelfth step of adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask;
A thirteenth step of heat treatment;
A fourteenth step of covering the entire surface with an inorganic interlayer insulating film;
A fifteenth step of forming an organic interlayer insulating film on the inorganic interlayer insulating film;
A sixteenth step of forming a contact hole reaching the semiconductor layer in the inorganic interlayer insulating film and the organic interlayer insulating film;
A seventeenth step of forming a pixel electrode on the organic interlayer insulating film;
An 18th step of forming connection wiring,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element has been added to form a crystalline semiconductor layer and increasing the crystallinity of the crystalline semiconductor layer using a laser irradiation method;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer formed in the sixth step as a mask;
The second conductive layer, the third conductive layer, and the fourth conductive layer formed in the sixth step are etched to form an n-channel TFT gate electrode, and later a p-channel TFT gate. An eighth step of forming a fifth conductive layer to be an electrode and a sixth conductive layer to be a gate electrode of the pixel TFT later;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer and the sixth conductive layer formed in the eighth step as a mask; When,
The n-channel TFT formed in the driver circuit is covered with a mask made of resist, the fifth conductive layer and the sixth conductive layer are etched, and a seventh conductive layer that later becomes the gate electrode of the p-channel TFT. A tenth step of forming each of the layer and the gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
A twelfth step of adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask;
A thirteenth step of covering the entire surface with an inorganic interlayer insulating film;
A fourteenth step of heat treatment to getter the catalytic element;
A fifteenth step of forming an organic interlayer insulating film on the inorganic interlayer insulating film;
A sixteenth step of forming a contact hole reaching the semiconductor layer in the inorganic interlayer insulating film and the organic interlayer insulating film;
A seventeenth step of forming a pixel electrode on the organic interlayer insulating film;
An 18th step of forming connection wiring,
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer formed in the sixth step as a mask;
The second conductive layer, the third conductive layer, and the fourth conductive layer formed in the sixth step are etched to form an n-channel TFT gate electrode, and later a p-channel TFT gate. An eighth step of forming a fifth conductive layer to be an electrode and a sixth conductive layer to be a gate electrode of the pixel TFT later;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer and the sixth conductive layer formed in the eighth step as a mask; When,
The n-channel TFT formed in the driver circuit is covered with a mask made of resist, the fifth conductive layer and the sixth conductive layer are etched, and a seventh conductive layer that later becomes the gate electrode of the p-channel TFT. A tenth step of forming each of the layer and the gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
A twelfth step of removing the gate insulating film using the gate electrode of the n-channel TFT, the gate electrode of the p-channel TFT, and the gate electrode of the pixel TFT as a mask;
A thirteenth step of covering the n-channel TFT and the pixel TFT with a resist mask, and adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask And having
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . A first step of forming an amorphous semiconductor layer on the insulator;
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer;
A third step of heating the amorphous semiconductor layer to which the catalytic element has been added to form a crystalline semiconductor layer and increasing the crystallinity of the crystalline semiconductor layer using a laser irradiation method;
A fourth step of forming a gate insulating film on the crystalline semiconductor layer;
A fifth step of forming a first conductive layer on the gate insulating film;
The first conductive layer is etched to form a second conductive layer that later becomes a gate electrode of an n-channel TFT, a third conductive layer that later becomes a gate electrode of a p-channel TFT, and a gate of a pixel TFT later. A sixth step of forming a fourth conductive layer serving as an electrode;
A seventh step of adding an n-type impurity element to the semiconductor layer using the second conductive layer to the fourth conductive layer formed in the sixth step as a mask;
The second conductive layer, the third conductive layer, and the fourth conductive layer formed in the sixth step are etched to form an n-channel TFT gate electrode, and later a p-channel TFT gate. An eighth step of forming a fifth conductive layer to be an electrode and a sixth conductive layer to be a gate electrode of the pixel TFT later;
A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the n-channel TFT, the fifth conductive layer and the sixth conductive layer formed in the eighth step as a mask; When,
The n-channel TFT formed in the driver circuit is covered with a mask made of resist, the fifth conductive layer and the sixth conductive layer are etched, and a seventh conductive layer that later becomes the gate electrode of the p-channel TFT. A tenth step of forming each of the layer and the gate electrode of the pixel TFT;
An eleventh step of etching the seventh conductive layer to form a gate electrode of a p-channel TFT;
A twelfth step of removing the gate insulating film using the gate electrode of the n-channel TFT, the gate electrode of the p-channel TFT, and the gate electrode of the pixel TFT as a mask;
A thirteenth step of covering the n-channel TFT and the pixel TFT with a resist mask, and adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode of the p-channel TFT as a mask And having
The third conductive layer is formed so that the region to which the n-type impurity element is added in the p-channel TFT is narrower than the region to which the n-type impurity element is added in the n-channel TFT. The fifth conductive layer is formed to have a larger width in the channel length direction than the gate electrode of the n-channel TFT. A method for manufacturing a semiconductor device . In any one of claims 3 to 1 3,
The method for manufacturing a semiconductor device , wherein the first conductive layer is formed by stacking a first conductive film and a second conductive film. Claim 2, claim 4, claim 6, claim 1 0, according to claim 1 1 or claim 1 3, the irradiating laser to improve the crystallinity of the crystalline semiconductor film, a pulse oscillation type of KrF A method for manufacturing a semiconductor device , which is an excimer laser, a XeCl excimer laser, a YAG laser, or a YVO4 laser.

Images