JP4127826B2 - Silicon-on-insulator latch-up pulse radiation detector - Google Patents

Description

  The present invention relates generally to integrated circuits, and more particularly to latch-up pulse radiation detectors formed using silicon-on-insulator (SOI) technology.

  Silicon on insulator (SOI) technology is becoming increasingly important in the field of integrated circuits, but semiconductor devices (eg, diodes, transistors, etc.) within a relatively thin layer of semiconductor material, overlying a layer of insulating material. Etc.). SOI technology offers many advantages over bulk complementary metal oxide semiconductor (CMOS) processes, including, for example, high performance, high mounting density, low power consumption, and a substantial reduction in latch-up.

  It is a parasitic PNPN path that causes latch-up in all junction isolation or bulk CMOS processes. The parasitic PNP and NPN bipolar transistor formed by such a parasitic PNPN path cannot be activated under normal conditions. However, under certain conditions, for example, in response to a spurious current spike, parasitic PNP and NPN transistors may activate, thereby forming a circuit with long positive feedback. That is, latch-up occurs.

  To take advantage of the latch-up caused by parasitic PNPN bipolar transistors, a bulk CMOS process is often used to form a radiation detector. Specifically, bulk CMOS type radiation detectors are responsive to interactions with alpha particles, cosmic rays, or other types of radiation that can produce sufficiently large current spikes inside the detector. Designed to selectively enter a latch-up state. Unfortunately, since one of the features of SOI technology is to substantially reduce latch-up, it is not possible to create an SOI radiation detector that can cause ionizing radiation-triggered latch-up. It turns out to be very difficult. It would be desirable to have such an SOI type radiation detector because SOI technology offers many advantages over bulk CMOS processes.

  A PNPN diode structure formed using a bulk CMOS process is commonly used to fabricate radiation detectors. Unfortunately, this bulk CMOS structure utilizes a current path just below the element isolation that does not exist in SOI technology, and therefore this design is not suitable for use as a radiation detector.

  1 includes an insulating substrate 12, a silicon layer 14 formed on the insulating substrate 12, a gate oxide layer (eg, silicon dioxide) 16 formed on the silicon layer 14, and a gate oxide layer. A gate layer 18 formed on the gate layer 16 and a silicide strap 20 formed on the gate layer 18. The silicon layer 14 includes a highly doped P + region 22, a highly doped N + region 24, a lightly doped N well 26, and a lightly doped P well 28. The gate layer 18 comprises a highly doped P + region 30 and a highly doped N + region 32 coupled by a silicide strap 20. The interface 46 between the side surface 34 of the P + region 30 and the side surface 36 of the N + region 32 of the gate layer 18 substantially coincides with the interface 48 between the side surface 38 of the N well 26 and the side surface 40 of the P well 28 of the silicon layer 14. The opposing side surface 42 of the P + region 30 of the gate layer 18 partially extends over the P + region 22 of the silicon layer 14. Similarly, the opposing side surface 44 of the N + region 32 of the gate layer 18 partially extends above the N + region 24 of the silicon layer 14. The PNPN diode structure 10 can be formed using a conventional SOI process known to those skilled in the art.

  As shown in FIG. 2, in operation, the P + region 22 of the silicon layer 14 is coupled to a source voltage (eg, VDD), and the N + region 24 of the silicon layer 14 is coupled to ground (eg, VSS) while the other gate Layer 18 is at a certain operating voltage. The source (Sp) is formed by the P + region 22, the body (Bp) is formed by the N well 26, the drain (Dp) is formed by the P well 28, and the gate (Gp) is formed by the P + region 30 of the gate layer 18. The parasitic PMOSFET 50 thus formed is formed in the silicon layer 14. Similarly, the source (Sn) is formed of the N + region 24, the body (Bn) is formed of the P well 28, the drain (Dn) is formed of the N well 26, and the gate (Gn) is the N + region of the gate layer 18. A parasitic NMOSFET 52 formed at 32 is formed in the silicon layer 14.

  The threshold voltage (Vtp) of the parasitic PMOSFET 50 is usually about -0.2 volts. Therefore, to prevent the parasitic PMOSFET 50 from turning on, the P + region 30 of the gate layer 18 (ie, Gp) must be coupled to a voltage approximately equal to the source voltage (VDD). Similarly, the threshold voltage (Vtn) of the parasitic NMOSFET 52 is usually about 0.2 volts. Therefore, to prevent the parasitic NMOSFET 52 from turning on, the N + region 32 of the gate layer 18 (ie, Gn) must be coupled to a voltage approximately equal to VSS. Therefore, there are two conflicting requirements for the voltage on the gate layer 18. That is, the gate layer 18 must be coupled to VDD to prevent the parasitic PMOSFET 50 from being turned on, and at the same time must be coupled to VSS to prevent the parasitic NMOSFET 52 from being turned on. Since both of these requirements cannot be met at the same time, either one of the parasitic FETs 50, 52 will always be in the ON state in response to a minimum gate bias, and latch-up will begin.

  Therefore, there is a need in the art for radiation detectors formed using SOI technology.

  The present invention provides a latch-up pulse radiation detector formed using silicon-on-insulator (SOI).

  A first aspect of the present invention includes a silicon layer formed on an insulating substrate, the silicon layer including a PNPN structure and a gate layer formed on the PNPN structure, and the gate layer is a PN gate. And a silicon-on-insulator radiation detector in which latch-up occurs only in response to incident radiation within the radiation detector.

  The second aspect of the present invention is directed to a radiation detector that includes a silicon-on-insulator PNPN diode structure and that latch-up occurs only in response to incident radiation within the radiation detector.

  A third aspect of the present invention includes a silicon layer formed on an insulating substrate, and the silicon layer includes a PNPN structure and a gate layer formed on the PNPN structure, and the gate layer is a PNPN. It is intended for silicon-on-insulator radiation detectors that have a gate and latch up occurs only in response to incident radiation within the radiation detector.

  The above and other features of the present invention will become apparent from the more specific description of the embodiments of the present invention.

  Embodiments of the present invention will be described in detail with reference to the following drawings. Here, the same symbol indicates the same component.

  A first embodiment of an SOI radiation detector according to the present invention formed as a PNPN diode structure 100 is shown in FIG. The PNPN diode structure 100 shown in FIG. 3 includes an insulating substrate 112, a silicon layer 114 formed on the insulating substrate, a gate oxide layer 116 formed on the silicon layer 114, and a gate layer 118 formed on the gate oxide layer 116. , And a silicide strap 120 formed on the gate layer 118. The silicon layer 114 includes a highly doped P + region 122, a highly doped N + region 124, a lightly doped N well 126, and a lightly doped P well 128. The gate layer 118 comprises a highly doped P + region 130 and a highly doped N + region 132 coupled by a silicide strap 120. The PNPN diode structure 100 can be formed using a conventional SOI process known to those skilled in the art.

  As described in detail above, in the PNPN diode structure 10 shown in FIG. 1, the interface 46 between the P + region 30 and the N + region 32 of the gate layer 18 is substantially at the interface 48 between the N well 26 and the P well 28 of the silicon layer 14. Match. However, in the PNPN diode structure 100, the interface 146 between the side surface 134 of the P + region 130 of the gate layer 118 and the side surface 136 of the N + region 132 is the interface 148 between the side surface 138 of the N well 126 of the silicon layer 114 and the side surface 140 of the P well 128. Is deviated from. Specifically, as shown in FIG. 3, the interface 146 between the P + region 130 and the N + region 132 of the gate layer 118 is located on the P well 128 of the silicon layer 114. That is, the P + region 130 extends a significant distance above the P well 128 of the silicon layer 114. The opposing side 142 of the P + region 130 of the gate layer 118 partially extends over the P + region 122 of the silicon layer 114, while the opposing side 144 of the N + region 132 of the gate layer 118 is the N + region of the silicon layer 114. It extends partially over 124.

  In operation, as shown in FIG. 4, the P + region 122 of the silicon layer 114 is connected to a source voltage (eg, VDD) and the N + region 124 of the silicon layer 114 is connected to ground (eg, VSS). The source (Sp) is formed by the P + region 122, the body (Bp) is formed by the N well 126, the drain (Dp) is formed by the P well 128, and the gate (Gp) is formed by the P + region 130 of the gate layer 118. The parasitic PMOSFET 150 is formed in the silicon layer 114. The parasitic PMOSFET 150 normally has a threshold voltage (Vtp) of about −0.2 volts. In the present invention, in order to prevent the parasitic PMOSFET 150 from being turned on, the P + region 130 of the gate layer 118 is set to a voltage substantially equal to the source voltage (VDD).

  The source (Sn) is formed by the N + region 124, the body (Bn) is formed by the P well 128, the drain (Dn) is formed by the N well 126, and the gate (Gn) is the P + region 130 of the gate layer 118. A parasitic NMOSFET 152 formed in (1) is formed in the silicon layer 114. However, unlike the parasitic NMOSFET 52 described with reference to FIG. 2, the threshold voltage (Vtn) of the parasitic NMOSFET 152 is not about 0.2. Rather, the P + region 130 of the gate layer 118 extends a significant distance above the P-well 128 to form the gate of the parasitic NMOSFET 152 so that the threshold voltage (Vtn) of the parasitic NMOSFET 152 is about 1.0 volts. Is increased by an amount approximately equal to the silicon band gap voltage to a value equal to about 1.2 volts. In this case, parasitic NMOSFET 152 remains off because of its unusually high threshold voltage (Vtn) of about 1.2 volts as long as VDD is kept below 1.2 volts.

  The PNPN diode structure 100 described above can be used as a radiation detector. Specifically, in response to incident radiation, a large number of electron-hole pairs are formed in both the N-well 126 and the P-well 128, where the carrier lifetime tends to be very long. . The electron / hole pairs generated in response to the incident radiation are drift diffused through the N well 126 and the P well 128. More specifically, electrons drift and diffuse toward the P + region 122, while holes drift and diffuse toward the N + region 124. The holes act like the base current of a parasitic npn bipolar transistor formed by N well 126, P well 128, and N + region 124, while the electrons act as N well 126, P well 128, and P + region 122. It acts like the base current of the parasitic pnp transistor formed by Gain occurs when the lifetime of electrons and holes is sufficiently long. That is, for each electron that enters the P + region 122 from the N well 126, a large number of holes leave the P + region 122 and enter the N well 126. Similarly, for each electron that enters the N + region 124 from the P well 128, a large number of electrons leave the N + region 124 and enter the P well 128. This process continues to create a runaway (ie, latch-up) condition. The current flowing through the PNPN diode structure 100 continues to flow and increases until it reaches a maximum level determined by the parasitic resistance in the structure.

  A complementary version of the PNPN diode structure 200 is shown in FIG. 5, which is also used in the radiation detector. In this embodiment of the invention, the interface 146 between the side surface 134 of the P + region 130 of the gate layer 118 and the side surface 136 of the N + region 132 is located above the N well 126 of the silicon layer 114. The P + region 122 of the silicon layer 114 is connected to a source voltage (eg, VDD), and the N + region 124 of the silicon layer 114 is connected to ground (eg, VSS). The source (Sn) is formed by the N + region 124, the body (Bn) is formed by the P well 128, the drain (Dn) is formed by the N well 126, and the gate (Gn) is formed by the N + region 132 of the gate layer 118. A parasitic NMOSFET 252 is formed in the silicon layer 114. The parasitic NMOSFET 252 normally has a threshold voltage (Vtn) of about 0.2 volts. In the present invention, in order to prevent the parasitic NMOSFET 252 from being turned on, the N + region 132 of the gate layer 118 is connected to a voltage substantially equal to VSS.

  Further, the source (Sp) is formed by the P + region 122, the main body (Bp) is formed by the N well 126, the drain (Dp) is formed by the P well 128, and the gate (Gp) is formed by the N + region 132 of the gate layer 118. A parasitic PMOSFET 250 formed in (1) is formed in the silicon layer 114. Since the N + region 132 of the gate layer 118 extends a significant distance above the N-well 126 to form the gate of the parasitic PMOSFET 250, the threshold voltage (Vtp) of the parasitic PMOSFET 250 is approximately equal to the silicon band gap voltage. Is reduced to a value equal to about -1.2 volts. In this case, the parasitic PMOSFET 250 remains off because of its unusually high threshold voltage (Vtp) of about −1.2 volts as long as VDD is kept below 1.2 volts.

  Another embodiment of a radiation detector comprising a PNPN diode structure 300 having characteristics in common with both PNPN diode structures 100 and 200 is shown in FIG. In the present embodiment, the gate layer 118 includes a first highly doped P + region 302, a first highly doped N + region 304 located above the N well 126, and a second highly doped P + located above the P well 128. Region 306 and a second highly doped N + region 308 are provided. The interface 310 between the N + region 304 and the P + region 306 of the gate layer 118 is at a position approximately equal to the interface 148 between the N well 126 and the P well 128 of the silicon layer 114.

  The P + region 122 of the silicon layer 114 is connected to a source voltage (eg, VDD), and the N + region 124 of the silicon layer 114 is connected to ground (eg, VSS). The source (Sp) is formed by the P + region 122, the body (Bp) is formed by the N well 126, the drain (Dp) is formed by the P well 128, and the gate (Gp) is formed by the N + region 304 of the gate layer 118. A parasitic PMOSFET 350 is formed in the silicon layer 114. Since the first N + region 304 of the gate layer 118 is located above the N well 126 and forms the gate (Gp) of the parasitic PMOSFET 350, the threshold voltage (Vtp) of the parasitic PMOSFET 350 is about -1.2 volts. . Similarly, the source (Sn) is formed by the N + region 124, the body (Bn) is formed by the P well 128, the drain (Dn) is formed by the N well 126, and the gate (Gn) is the second of the gate layer 118. A parasitic NMOSFET 352 formed in the P + region 306 is formed in the silicon layer 114. The position of the second P + region 306 above the P-well 128 results in an NMOSFET 352 with a threshold voltage (Vtn) on the order of about 1.2 volts. In this embodiment of the invention, the parasitic PMOSFET 350 remains off as long as the gate voltage is kept higher than (VDD-1.2 volts), while the parasitic NMOSFET 352 keeps the gate below 1.2 volts. Stay off as long as you can. Thus, when VDD is lower than 1.2 volts, the gate layer 118 can be connected to VDD, VSS or another suitable voltage between VDD and VSS.

  As described in detail above with respect to FIG. 2, N-well 126 and P-well 128 form the bases of parasitic pnp and npn bipolar transistors. For example, the floating base (ie, N-well 126 and P-well 128) can be fixed at VDD and VSS, respectively, to prevent sudden latch-up caused by capacitive coupling. One way to do this in the PNPN diode structure 100 is shown in FIG.

  A process for providing the PNPN structure 100 of FIG. 3 with a fixed N-well 126 and P-well 128 is summarized in FIG. Various processing steps known to those skilled in the art have been omitted for the sake of simplicity and ease of viewing the figure.

  A mask 400 is provided to form a silicon island 402. Another mask 404 is used to form a gate electrode 406 (ie, a gate layer) over the silicon island 402. A gate dielectric (not shown) is located between the gate electrode 406 and the silicon island 402. The region of silicon island 402 below gate electrode 406 and covered by N well mask 408 forms N well 126 of PNPN diode structure 100. The region of the silicon island 402 below the gate electrode 406 and not covered by the N-well mask 408 forms the P-well 128 of the PNPN diode structure 100. A region of the silicon island 402 that is not covered by the gate electrode 406 is heavily doped to P + or N + by ion implantation. Specifically, the region of the silicon island 402 that is not covered by the gate electrode 406 and that is covered by the mask 410 is doped with P +, while the silicon island 402 is not covered by the gate electrode 406. Or the region not covered by mask 410 is doped N +. Thereby, the N + region 124 and the P + region 122 of the silicon layer 114 are formed. This also creates an npn base contact 412 coupled to the P well 128 and a pnp base contact 414 coupled to the N well 126. The npn base contact 412 and the pnp base contact 414 are connected to VSS and VDD, respectively, to fix the floating base. A similar doping process is used to dope the gate electrode 406 to P + or N +, again forming the P + region 130 and N + region 132 of the gate layer 118 depending on the position of the mask 410.

  Although the invention has been described with respect to the specific embodiments outlined above, it will be apparent that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the above-described embodiments of the present invention are illustrative rather than limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.

It is a figure which shows the 4 layer SOIPNPN diode structure which has the problem of a sudden latch-up. It is a figure which shows the 4 layer SOIPNPN diode structure which has the problem of a sudden latch-up. FIG. 3 shows a radiation detector comprising a PNPNSOI diode structure according to an embodiment of the invention. FIG. 3 shows a radiation detector comprising a PNPNSOI diode structure according to an embodiment of the invention. FIG. 4 shows a radiation detector comprising a PNPNSOI diode structure according to another embodiment of the invention. FIG. 6 shows a radiation detector comprising a PNPNSOI diode structure according to yet another embodiment of the present invention. It is a figure which shows the structure for forming the radiation detector provided with the PNPNSOI diode structure which fixed N well and P well.

Explanation of symbols

100 PNPN diode structure 112 Insulating substrate 114 Silicon layer 116 Gate oxide layer 118 Gate layer 120 Silicide strap 122 Highly doped P + region 124 Highly doped N + region 126 Lowly doped N well 128 Lowly doped P well 130 Highly doped P + region 132 Highly doped N + region 134 P + region 130 side surface 136 N + region 132 side surface 138 N well 126 side surface 140 P well 128 side surface 142 118 P + region 130 opposing side surface 144 118 N + region 132 opposing side surface 146 130 side surface 134 132 Interface of Side 136 of Side 148 Interface of Side 138 of N Well 126 and Side 140 of P Well 128 150 Parasitic PMOSFET
152 Parasitic NMOSFET
200 PNPN diode structure 250 Parasitic PMOSFET
252 Parasitic NMOSFET
300 PNPN diode structure 302 first highly doped P + region 304 first highly doped N + region 306 second highly doped P + region 308 second highly doped N + region 310 interface between region 304 and region 306 350 parasitic PMOSFET
352 Parasitic NMOSFET
400 mask 402 silicon island 404 mask 406 gate electrode 408 n-well mask 410 mask 412 npn base contact 414 pnp base contact

Claims (4)

A silicon layer formed on an insulating substrate and having a PNPN structure;
A gate layer formed on the PNPN structure and comprising a PN gate;
The PNPN structure includes a P + region, an N well, a P well, and an N + region, and the PN gate includes a first P + region and a first N + region,
Wherein said first P + region of the PN gate, said covering the N-well, and considerable distance spread only divorce on insulator radiation detector over the P-well of the PNPN structure of the PNPN structure. And parasitic PMOSFET in the radiation detector to prevent the turned on by coupling the first P + region of the the P + region of the PNPN structure gate source voltage, 1. Has a threshold voltage of 2 volts, the threshold voltage prevents the parasitic NMOSFET is turned on, further comprising said parasitic NMOSFET in the radiation detector, the silicon-on-insulator according to claim 1 Radiation detector. The silicon-on-insulator radiation of claim 1 , wherein the first N + region of the gate covers the P-well of the PNPN structure and extends a substantial distance above the N-well of the PNPN structure. Detector. A parasitic PMOSFET in the radiation detector that prevents an on state by coupling the N + region of the PNPN structure and the first N + region of the gate to ground ;
- 1.2 having a threshold voltage of the bolt, the threshold voltage, the parasitic PMOSFET further comprises said parasitic PMOSFET in the radiation detector to prevent from being turned on, a silicon-on according to claim 3 -Insulator radiation detector.

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