JP4128050B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a vertical power element using a U-shaped insulated gate.
[0002]
[Prior art]
In a conventional semiconductor device, for example, a structure shown in Japanese Patent Application Laid-Open No. 06-252408 is known as a normally-off type transistor having excellent controllability and low on-resistance during switching.
[0003]
With reference to FIG. 4 and FIG. 5, an example of the structure is shown below. 4A is a perspective view of the element, and FIG. 4B is a top view. FIG. 5 is a cross-sectional view taken along the line CC of FIG.
[0004]
First, as shown in FIG. 4A, in the conventional semiconductor device, an N + type semiconductor substrate 51 and an N− type epitaxial layer 52 are formed on the N + type semiconductor substrate 51. An N + type source region 54 and a trench 57 are formed in the N− type epitaxial layer 52 so as to be orthogonal to each other. In addition, an insulating film 56 and a fixed potential insulating electrode 55 made of high-concentration P + type polycrystalline silicon (polysilicon) are formed in the trench 57 so as to cover the side wall thereof. The fixed potential insulating electrode 55 and the source region 54 are in ohmic contact with an aluminum (Al) layer 61, for example, and the potential is fixed. The epitaxial layer 52 is mainly used as the drain region 53, and a region sandwiched between the fixed potential insulating electrodes 55 in the epitaxial layer 52 is referred to as a channel region 58.
[0005]
In the channel region 58, since the fixed potential insulating electrode 55 adjacent to the insulating film 56 is made of high-concentration P + type polysilicon, a depletion layer is formed due to a work function difference. As a result, a potential barrier against conduction electrons is formed in the channel region 58, and the source region 54 and the drain region 53 are electrically cut off from the beginning.
[0006]
Next, as shown in FIG. 4B, the fixed potential insulating electrode 55 has a stripe shape, and both ends thereof are in contact with the P-type gate region 59. A gate electrode G is formed on the surface of the gate region 59, and minority carriers (holes) are supplied from this to the drain region 53. In addition, the channel region 58 surrounded by the fixed potential insulating electrodes 55 forms one unit cell. Note that the shape of the fixed potential insulating electrode 55 and the shape of the source region 54 constituting the unit cell are arbitrary as long as the condition that the current can be interrupted or the amount of current can be controlled depending on the channel state.
[0007]
The gate region 59 is a diffusion region formed by implanting impurities into the substrate. The gate electrode G is in ohmic contact with the surface of the P-type gate region 59, and minority carriers (holes) are supplied to the drain region 53 from here.
[0008]
Note that the broken lines in the figure indicate the presence of the fixed potential insulating electrode 55. In the drawings, the corners of the insulating film 56 in the cross-sectional view and the surface view are drawn with a square shape, but these are schematic views and may actually be rounded. In other words, in order to suppress electric field concentration, rounding these corners is widely adopted.
[0009]
As shown in FIG. 5, Hc is called channel thickness and L is called channel length. That is, the channel thickness Hc is the distance between the insulating films 56 facing each other in the channel region, and the channel length L is the distance from the bottom surface of the source region 54 to the bottom surface of the fixed potential insulating electrode 55 along the sidewall of the groove. Say distance. For example, channel thickness (distance between trenches) Hc = 0.8 μm, channel length L = 3 μm, and trench depth 5 μm.
[0010]
Further, an Al layer 60 is formed on the back surface of the substrate 51 to serve as the drain electrode D. On the other hand, an Al layer 61 is also formed on the surface of the drain region 53 to form the source electrode S, and is in contact with the source region 54 and the fixed potential insulating electrode 55. That is, the potential of the fixed potential insulating electrode 55 is fixed to the potential of the source electrode S.
[0011]
[Problems to be solved by the invention]
FIG. 6 is a cross-sectional view taken along the line DD of FIG. 4B, and shows a case where only the area of the source region 64 is different with the same chip size and the same number of cells. That is, in the plan view of FIG. 4B, the source region length SL is wide (FIG. 6A: SL1) and narrow (FIG. 6B: SL2).
[0012]
The holes injected from the gate region 59 are used to flow the main current with a low resistance while repelling the depletion layer extending in the channel region 58 and opening the channel. In FIG. 6, since the number of cells, the number of channels, and the number of source regions are the same, the current density of the channel region 58 is equal if the same main current is supplied. Since the source region 54 is an N + type region and the source electrode S is grounded, as shown in FIG. 6A, when the area of the source region 54 is large, holes are generated at the interface of the source region 54. It becomes easy to be taken in. In other words, since the amount of holes from the gate region 59 that contribute to conductivity modulation is reduced, hFE is lowered.
[0013]
On the other hand, FIG. 7 shows a cross-sectional view taken along the line DD of FIG. In this cross-sectional view, the source region is a region provided on the surface between adjacent trenches. To reduce the area of the source region, the thickness SW of the source region, that is, the channel thickness Hc, which is the distance between the trenches, is reduced. It will be. Here, as in FIG. 6, a structure having the same chip size and the same number of cells and different channel thicknesses is considered. That is, when one trench and one channel region have a basic structure, the distance (hereinafter referred to as unit cell thickness Hs) is the same, and the channel region is wide (FIG. 7A: Hc1). In this case, the number of channels and the number of source regions in the chip are the same (FIG. 7B: Hc2).
[0014]
If the same main current is made to flow through these two elements, the current density increases as the channel thickness is smaller (Hc2). If the current density of the main current is large, the hole density at the source region interface increases, so that holes are easily taken into the source region at the source region interface. That is, among the holes injected from the gate region, those that contribute to conductivity modulation are reduced, and there is a problem that hFE is deteriorated.
[0015]
That is, when the source area is large, the component (ineffective component) that jumps into the source out of the holes injected from the gate into the source increases. However, reducing the channel thickness to reduce the source area leads to an increase in the main current density flowing through the channel. An increase in the main current density means an increase in carrier density at the source region interface. Carriers (holes) existing at the interface of the source region jump into the source and disappear, and in order to replenish the disappeared holes, holes are replenished from the gate. This causes an increase in gate current and a decrease in hFS, so there is a limit to improving the characteristics.
[0016]
[Means for Solving the Problems]
The present invention has been made in view of the above-described problems. First, a plurality of trenches provided on one main surface of a one-conductivity-type semiconductor substrate serving as a drain region and arranged in parallel to each other at regular intervals. A source region of one conductivity type provided on the main surface sandwiched between the trenches, an insulating film provided on the inner wall of the trench, and embedded in the trench and maintained at the same potential as the source region. A fixed-potential insulating electrode made of a conductive material, and a plurality of reverse-conductivity-type gate regions spaced apart from the source region and in contact with each of the insulating films and spaced apart from each other by the semiconductor substrate; A channel region located in the semiconductor substrate sandwiched between the trenches below the source region, and a distance between adjacent trenches having a thickness of the channel region is from the substrate surface to the trench It solves by widening towards the part.
[0017]
Second, the thickness of the channel region near the bottom of the trench extends to a limit where the channel region is filled with a depletion layer when the semiconductor device is in a cut-off state.
[0018]
Thirdly, in the trench opening, the distance from the adjacent trench is close to the limit of the process.
[0019]
Fourth, the distance of the channel region from the interface with the source region to the vicinity of the bottom of the trench is about 2 to 3 times the thickness of the channel region near the bottom of the trench.
[0020]
Fifth, the thickness of the channel region near the bottom of the trench is about twice the thickness of the channel region near the interface with the source region.
[0021]
Sixth, the gate region is provided deeper than the bottom of the trench.
[0022]
Seventhly, the gate region is in contact with a plurality of the channel regions adjacent to each other with the fixed potential insulating electrode interposed therebetween, and the gate region has a gate electrode connected to the channel region. is there.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
An example of the structure of an embodiment of the present invention will be described in detail with reference to FIGS.
[0024]
The basic structure of the element will be described with reference to FIG. FIG. 1A is a perspective view showing the structure of a semiconductor element used in the semiconductor device of the present invention, and FIG. 1B is a top view showing the structure of the semiconductor element used in the semiconductor device of the present invention. In this figure, the surface electrode (metal film) is omitted.
[0025]
As shown in FIG. 1A, an N− type epitaxial layer 2 is deposited on an N + type semiconductor substrate 1. The substrate 1 is used as a drain extraction region, and the epitaxial layer 2 is used as a drain region 3. The N − type epitaxial layer 2 has a plurality of trenches 7 formed in parallel with each other at regular intervals from the main surface. The trench 7 is formed so that its thickness in the minor axis direction (left and right direction in the drawing) becomes narrower toward the bottom, and an insulating film 6 is provided on the inner wall for the purpose of insulation from the drain region 3.
[0026]
Further, as shown in FIGS. 1A and 1B, a plurality of gate regions 9 are provided at regular intervals in the N − type epitaxial layer 2 which is separated from the source region 4 and is in contact with the insulating film 6. It has been. As shown in FIG. 1B, the fixed potential insulating electrode 5 has a comb-like shape, and the fixed potential insulating electrode 5 in the Y-axis direction (hereinafter referred to as a shaft portion) is centered in the left and right X-axis directions. The comb teeth are extended. That is, in the present embodiment, the gate region 9 is formed so as to overlap a part of the both ends of the comb teeth with the formation region and to contact the insulating film 6 and the channel region 8 in that region. In other words, the shaft portion of the fixed potential insulating electrode 5 is equidistant from the two adjacent gate regions 9.
[0027]
Further, for example, polycrystalline silicon (polysilicon) into which a P-type impurity is implanted is deposited in the trench 7. Although details will be described later, the polysilicon in the trench 7 is electrically connected to the source region 4 on the surface of the epitaxial layer 2 via, for example, aluminum (Al). As a result, the P-type polysilicon in the trench 7 is used as the fixed potential insulating electrode 5 having the same potential as the source region.
[0028]
The channel region 8 is formed in the N − type epitaxial layer 2 sandwiched between the trenches 7 below the source region 4. Since the width of the trench 7 is formed narrower toward the bottom, the channel region 8 has a trapezoidal shape that extends toward the bottom of the trench 7. In other words, the trapezoidal shape of the trench 7 facilitates the carrier concentration gradient and reduces the area of the source region 3.
[0029]
The source region 4 is provided on the main surface of the semiconductor substrate sandwiched between the trenches 7 by implanting N + type impurities at a desired distance on both sides of the shaft portion.
[0030]
As described above, the area of the source region 4 is desirably small, and the source region width SL can be reduced to some extent by controlling the diffusion region of the impurity to be implanted. However, since there is a limit to the reduction of the source region width SL, in this embodiment, the source region thickness SW is reduced by reducing the distance between the adjacent trench 7 openings.
[0031]
Thus, as will be described in detail later, the area of the source region 3 can be reduced while easily providing a carrier concentration gradient even in a cross section taken along the line AA, which is a cross section parallel to the shaft portion, and this can contribute to further improvement in characteristics. become.
[0032]
Next, the cross-sectional structure of the semiconductor element of the present invention will be described with reference to FIG. 2A is a cross-sectional view taken along the line AA of FIG. 1B, and FIG. 2B is a cross-sectional view taken along the line BB of FIG. 1B.
[0033]
As shown in FIG. 2A, a region surrounded by the trench 7 in the surface region of the N − type epitaxial layer 2 is a channel region 8, and an arrow L is a channel length. That is, the channel length L is the distance from the interface with the source region 4 to the bottom of the train 7-inch.
[0034]
In the semiconductor device of the present invention, the channel thickness is not constant because the channel region 8 has a trapezoidal shape. Conventionally, the channel region 7 is between the vertically formed trenches 7 and the thickness thereof is constant. However, in the present invention, as shown in the figure, the channel thickness is wide from the substrate surface toward the bottom of the trench 7 because it is narrow near the opening of the trench 7 and widens toward the bottom of the trench 7. Here, for the sake of convenience, the distance between adjacent trench 6 openings on the surface of the substrate is Hct. Further, this Hct is the thickness SW of the source region 4. The narrowest channel thickness at the interface with the source region 4 is Hcc, and the widest channel thickness below the trench 7 is Hcb. The widest channel thickness Hcb is assumed to be wider than the channel thickness Hc of the conventional vertical structure shown in FIG. In addition, it is assumed that L / Hcb = 2 to 3, which is a limit condition in which the channel is completely filled with the depletion layer extending around the trench 7, is satisfied. Further, the separation distance Hct of the opening of the trench 7 is reduced to the limit of the process as long as the source region 4 can be contacted.
[0035]
Source regions 4 are formed on the surface of the epitaxial layer 2 between the trenches 7 by introducing N + type impurities. The source thickness SW is Hct as described above, and the area of the source region 4 is reduced by reducing the contact as much as possible or the process limit.
[0036]
Conventionally, since the trench 7 and the channel region 8 are formed vertically, as described above, when the source thickness SW is reduced, the channel thickness Hc is also reduced and the carrier concentration near the surface of the source region is increased. It was supposed to deteriorate.
[0037]
Therefore, in the present invention, the channel region 8 has a trapezoidal shape that is narrow at the top and wide at the bottom. Thereby, an element in which the area of the source region 4 is reduced while maintaining a sufficient carrier concentration gradient can be realized.
[0038]
A drain electrode 10 made of, for example, Al in ohmic contact is formed on the back surface of the N + type substrate 1 used as a drain extraction region. The Al layer 11 is in ohmic contact with the source region 4 and the fixed potential insulating electrode 5, and the potential of the fixed potential insulating electrode 5 is fixed to the potential with the source region 4.
[0039]
As shown in FIG. 2B, a silicon oxide film 12 is deposited on the surface of the epitaxial layer including the gate region 9. A gate electrode G made of, for example, Al is formed on the gate region 9 through a contact hole provided in the silicon oxide film 12. The broken line in the figure indicates the presence of the fixed potential insulating electrode 5. As shown in the drawing, the corners of the insulating film 6 in the cross-sectional view and the surface view are drawn with a square shape, but these are schematic views and may be rounded in practice. That is, it is widely adopted to round these corners in order to suppress electric field concentration.
[0040]
Next, the operation principle of the semiconductor element of the present invention will be described.
[0041]
First, the OFF state of the semiconductor element will be described. The current path of the semiconductor element includes an N + type substrate 1 serving as a drain extraction region, a drain region 3 including an N− type epitaxial layer 2, and an N− type located between the plurality of trenches 7 in the surface region of the epitaxial layer 2. It comprises a channel region 8 and an N + type source region 4. That is, all the regions are composed of N-type regions. At first glance, it seems that the OFF state cannot be established when a positive voltage is applied to the drain electrode D and the source electrode S is grounded.
[0042]
However, as described above, the N-type region composed of the source region 4 and the channel region 8 and the P-type region which is the fixed potential insulating electrode 5 are connected via the Al layer and have the same potential. Therefore, in the channel region 8 around the fixed potential insulating electrode 5, a depletion layer spreads so as to surround the fixed potential insulating electrode 5 due to a work function difference between the P + type polysilicon and the N− type epitaxial layer 2. That is, by adjusting the width between the trenches 7 forming the fixed potential insulating electrode 5, that is, the channel thickness H, the channel region 8 is filled with the depletion layers extending from the fixed potential insulating electrodes 5 on both sides. Although details will be described later, the channel region 8 filled with the depletion layer is a pseudo P-type region.
[0043]
With this structure, the N− type drain region 3 and the N + type source region 4 form a PN junction isolation structure with a channel region 8 which is a pseudo P type region. That is, the semiconductor element of the present invention is in the cutoff state (OFF state) from the beginning by forming a pseudo P-type region in the channel region 8. When the semiconductor element is OFF, a positive voltage is applied to the drain electrode D, and the source electrode S and the gate electrode G are grounded. At this time, a depletion layer is formed in the downward direction of the drawing by applying a reverse bias from the boundary surface between the channel region 8 which is a pseudo P-type region and the drain region 3 which is an N-type region. The formation state of this depletion layer affects the breakdown voltage characteristics of the semiconductor element.
[0044]
Here, the pseudo P-type region described above will be described below with reference to FIG. FIG. 3A shows an energy band diagram in the channel region 8 when OFF, and FIG. 3B schematically shows a depletion layer formed in the channel region 8 when OFF. The P + type polysilicon region which is the fixed potential insulating electrode 5 and the N− type epitaxial layer 2 region which is the channel region 8 are opposed to each other via the insulating film 6. Both are maintained at the same potential through the Al layer on the surface of the epitaxial layer 2. As a result, a depletion layer is formed around the trench 7 due to the work function difference between the two, and a P-type region is formed by a small number of free carriers (holes) slightly present in the depletion layer.
[0045]
Specifically, when the P + type polysilicon region and the N− type epitaxial layer 2 region are set to the same potential through the Al layer, an energy band diagram is formed as shown in FIG. First, in the P + type polysilicon region, the valence band is formed with a negative slope at the interface of the insulating film 6, and the interface of the insulating film 6 has high potential energy for free carriers (holes). Show. That is, free carriers (holes) in the P + type polysilicon region cannot exist at the interface of the insulating film 6 and are driven away from the insulating film 6. As a result, negative charges composed of ionized acceptors are left behind at the interface of the insulating film 6 in the P + type polysilicon region. A negative charge composed of an ionized acceptor exists at the interface of the insulating film 6 in the P + type polysilicon region. As a result, in the N− type epitaxial layer 2 region, a negative charge consisting of this ionization acceptor and a positive charge consisting of an ionized donor pairing with it are required. For this reason, the channel region 8 is depleted from the interface of the insulating film 6.
[0046]
However, the impurity concentration of the channel region 8 is 1E14 (/ cm ³ ) And the thickness is about 1 μm, and is completely occupied by a depletion layer extending from the fixed potential insulating electrode 5 formed so as to surround the channel region 8. Actually, since the positive charge enough to balance with the ionization acceptor cannot be secured only by forming the channel region 8 into a depletion layer, a small number of free carriers (holes) also exist in the channel region 8. As a result, as shown in the figure, the ionized acceptor in the P + type polysilicon region and the free carriers (holes) or ionized donors in the N− type epitaxial layer 2 form a pair to form an electric field. As a result, the depletion layer formed from the interface of the insulating film 6 becomes a P-type region, and the channel region 8 filled with this depletion layer becomes a P-type region.
[0047]
Next, a state where the semiconductor element turns from OFF to ON will be described. First, a positive voltage is applied to the gate electrode G from the ground state. At this time, free carriers (holes) are introduced from the gate region 9, but as described above, free carriers (holes) are attracted by the ionization acceptor and flow into the interface of the insulating film 6. Then, free carriers (holes) are filled in the interface of the insulating film 6 in the channel region 8 so that only an ionization acceptor and free carriers (holes) in the P + type polysilicon region form a pair to form an electric field. As a result, free carriers (electrons) are present from a region farthest from the insulating film 6 in the channel region 8, that is, a central region of the channel region 8, and a neutral region appears. As a result, the depletion layer in the channel region 8 is reduced, the channel is opened from the central region, free carriers (electrons) move from the source region 4 to the drain region 3, and a main current flows.
[0048]
That is, free carriers (holes) instantaneously spread through the wall surface of the trench 7, the depletion layer extending from the fixed potential insulating electrode 5 to the channel region 8 recedes, and the channel opens. Further, when a voltage higher than a predetermined value is applied to the gate electrode G, the PN junction formed by the gate region 9, the channel region 8, and the drain region 3 becomes a forward bias. Free carriers (holes) are directly injected into the channel region 8 and the drain region 3. As a result, a large number of free carriers (holes) are distributed in the channel region 8 and the drain region 3, whereby conductivity modulation occurs, and the main current flows with a low on-resistance.
[0049]
Finally, a state where the semiconductor element turns from ON to OFF will be described. In order to turn off the semiconductor element, the potential of the gate electrode G is set to the ground state (0 V) or a negative potential. Then, a large amount of free carriers (holes) existing in the drain region 3 and the channel region 8 disappear due to the conductivity modulation, or are eliminated outside the device through the gate region 9. As a result, the channel region 8 is again filled with the depletion layer, becomes a pseudo P-type region again, maintains the breakdown voltage, and the main current stops.
[0050]
The feature of the present invention is that the shape of the channel region 8 is made narrower at the top and wide at the bottom by devising the shape of the trench 7, thereby obtaining the following advantages.
[0051]
First, as compared with the conventional structure having the same number of channels and the same chip size, the ratio of the area of the source region 4 to the area of the channel region 8 can be reduced even in the cross-sectional direction parallel to the shaft portion. Conventionally, when the area of the source region 4 is reduced in the cross-sectional direction parallel to the shaft portion, the area of the channel region 8 is also reduced. When the same main current flows, the current density increases as the area of the channel region 8 decreases, and the hole density present at the source region interface increases. As a result, the probability that holes are drawn into the source region 4 at the interface of the source region 4 increases, and there is a problem that hFE is not improved. However, according to the present invention, the area of the source region 4 can be reduced without significantly reducing the area of the channel region 8. Since the increase in the number of holes at the interface of the source region can be suppressed and the area of the source region can be reduced, it contributes to the improvement of hFE.
[0052]
Specifically, the channel thickness of the conventional structure is 0.8 μm, the trench width is 1.4 μm, and the unit cell thickness Hs is 2.2 μm. In the present embodiment, without changing the unit cell thickness Hs, the trench opening width Ht is 1.7 μm, the trench separation distance Hct is 0.5 μm, and the channel bottom thickness Hcb is 1.0 μm. The trench depth is 5 μm, the source region depth is 2.0 μm, and the channel length L is 3.0 μm, which are the same values as before. Since the unit cell thickness Hs is also the same, the number of channels is not changed if the chip size is the same. That is, without changing the unit cell thickness Hs, the thickness Hcb at the bottom of the channel region can be made larger than the conventional channel thickness H, and the separation distance Hct of the trench opening can be made narrower than before, thereby improving hFE. Can do.
[0053]
The thickness Hcb at the bottom of the widest channel region is formed as wide as possible within the range filled with the depletion layer, and it is necessary to satisfy the condition of L / Hcb = 2-3. In the present embodiment, Hcb = 1.0 μm and L may be in the range of 2.0 to 3.0 μm. Although the channel length is 3.0 μm, the channel region becomes narrower toward the top, so that it is sufficiently blocked by the depletion layer.
[0054]
Secondly, a breakdown voltage can be secured. For example, if the channel thickness is too wide, the withstand voltage at the OFF time may deteriorate. Most of the drain electric field at OFF is applied to the depletion layer extending to the drain side, but part of the electric field also penetrates into the channel. Here, if the channel thickness is large, the electric field that has entered the channel region may reach the source region and cause punch-through.
[0055]
According to the structure of the present invention, since it becomes narrower as it goes to the upper part of the channel, the depletion layer spreads sufficiently at any position, and there is almost no influence on the withstand voltage due to punch-through which is likely to occur especially when the channel is wide. . That is, the hFE can be improved while ensuring the breakdown voltage.
[0056]
For example, according to the value of this embodiment described above, the thickness Hcc of the upper portion of the channel region is about 0.5 μm. This is a value smaller than the conventional channel thickness of 0.8 μm. That is, it is possible to realize an element that contributes to improvement of hFE while ensuring a predetermined breakdown voltage.
[0057]
Here, the above-described values are examples. The present invention is characterized in that the area of the source region is reduced without increasing the number of holes at the source interface so much in the cross section parallel to the axial portion by forming the shape narrower at the top and narrowly below the channel region. Yes. That is, the value is not limited to the above value, and the shape is narrow to the process limit at the upper part of the channel region and wide at the lower part, and the relationship between the channel thickness and the channel length should satisfy L / Hcb = 2 to 3. .
[0058]
【The invention's effect】
The feature of the present invention is that the shape of the channel region is made narrower at the upper part and wider at the bottom part by devising the trench shape, and the following advantages are obtained.
[0059]
First, even in the cross-sectional direction parallel to the shaft portion, the area of the source region can be reduced without significantly increasing the number of holes at the source interface. Conventionally, when the source region area is reduced, the channel thickness is reduced and hFE deteriorates due to the increase in hole density at the source region interface. However, according to the structure of the present invention, the source region is maintained while maintaining a certain carrier concentration gradient. HFE can be improved.
[0060]
Secondly, a breakdown voltage can be secured. Even the thickness Hcb at the bottom of the channel is a distance that is completely filled with a depletion layer. If the channel thickness is too wide, the drain electric field that has entered the channel region may reach the source region and cause punch-through.
[0061]
According to the structure of the present invention, even if the thickness is Hcb at the bottom of the channel, it is a distance that is filled with the depletion layer and becomes narrower toward the top of the channel, so that the depletion layer is sufficiently wide at any position. It is. That is, the hFE can be improved while suppressing the deterioration of the breakdown voltage due to punch-through, which is likely to occur when the channel is wide, while ensuring the conventional breakdown voltage.
[Brief description of the drawings]
FIG. 1A is a perspective view and FIG. 1B is a plan view for explaining the present invention.
FIG. 2 is a cross-sectional view for explaining the present invention.
FIG. 3 is a conceptual diagram for explaining the present invention.
4A is a perspective view and FIG. 4B is a plan view for explaining a conventional technique.
FIG. 5 is a cross-sectional view for explaining the prior art.
FIG. 6 is a cross-sectional view for explaining the prior art.
FIG. 7 is a cross-sectional view for explaining the prior art.

Claims (6)

Trenches provided on one main surface of a semiconductor substrate of one conductivity type to be a drain region and arranged in parallel with each other at equal intervals;
A source region of one conductivity type provided on the main surface sandwiched between the trenches;
An insulating film provided on the inner wall of the trench;
A fixed potential insulating electrode made of a conductive material embedded in the trench and kept at the same potential as the source region;
A plurality of reverse conductivity type gate regions spaced apart from the source region and in contact with each of the insulating films and provided at a predetermined interval on the semiconductor substrate;
A channel region located in the semiconductor substrate sandwiched between the trenches under the source region,
The distance between the said adjacent trench used as the thickness of the said channel area | region becomes large toward the said trench bottom part from the said substrate surface.   2. The semiconductor device according to claim 1, wherein the thickness of the channel region near the bottom of the trench extends to a limit where the channel region is completely filled with a depletion layer in a cutoff state of the semiconductor device. 2. The semiconductor device according to claim 1, wherein the distance of the channel region from the interface with the source region to the vicinity of the bottom of the trench is two to three times the thickness of the channel region near the bottom of the trench. 2. The semiconductor device according to claim 1, wherein the thickness of the channel region near the bottom of the trench is twice the thickness of the channel region near the interface with the source region. The semiconductor device according to claim 1, wherein the gate region is provided deeper than a bottom of the trench. 2. The gate region according to claim 1, wherein the gate region is in contact with a plurality of the channel regions adjacent to each other with the fixed potential insulating electrode interposed therebetween, and the gate region has a gate electrode connected to the channel region. Semiconductor device.

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