JP4130051B2 - Sensorless motor drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a drive circuit for a sensorless motor that can be reliably restarted.
[0002]
[Prior art]
In the sensorless motor, the counter-induced waveform generated in the drive coil and the neutral point waveform of the drive coil are added to the rotation position detection comparator, a comparator output signal is obtained, the comparator output signal is added to the control logic circuit, and Japanese Patent Application Laid-Open No. 10-146089 filed by the present applicant describes that a control logic signal for sequentially turning on and off transistors for supplying drive current to the drive coil is obtained.
[0003]
FIG. 2 shows a conventional circuit described in the above publication, wherein 1, 2, 3 are U-phase, V-phase, and W-phase drive coils, 4, 5, and 6 are comparators, 7, 8, 9, 10, 11 , 12 is an output transistor, 20, 21 and 22 are DFFs, and 23 is a logic circuit. In addition to the six types of control signals Usour, Usink, Vsource, Vsink, Wsink, Wsink, and U phase that control the output transistors 7 to 12 , V-phase and W-phase drive coils 4, 5 and 6 are energized logic signals Ulogic, Vlogic, Wlogic, and rectangular waves obtained from the Q terminals of the DFFs 20, 21 and 22 indicating that they are on or off. Based on this, a 60 degree signal that repeats a high level and a low level is output every 60 degrees of electrical angle.
[0004]
Reference numeral 24 denotes a trigger pulse generating circuit, to which the 60 degree signal is applied, and a trigger pulse is generated at the rise and fall of the 60 degree signal. Reference numeral 25 denotes a voltage controlled oscillation circuit, which forms a closed loop with a low-pass filter 26 composed of a capacitor and a resistor, a voltage controlled oscillator 27, a 1 / N frequency divider 28, and a phase comparison circuit 29.
[0005]
The phase comparison circuit 29 compares the phase of the trigger pulse generated from the trigger pulse generation circuit 24 at an electrical angle interval of 60 degrees with the signal of the predetermined frequency output from the voltage controlled oscillator 27 divided by N. Therefore, the number of pulses of the voltage-controlled oscillator 27 is N cycles in the period from the rising edge of the 60-degree signal to the immediately following falling edge, that is, the electric angle 60-degree period of the motor driving waveform.
[0006]
In FIG. 3, 30 is a delay circuit and comprises a plurality of DFFs 31-1, 31-2 and 31-m.
[0007]
FIG. 5 is an operation waveform, and the explanation will be made focusing on the V phase. The period a is the period in which the output transistor 9 is on, the period b is the period in which the output transistor 10 is on, This is a period during which the output transistors 9 and 10 are off.
[0008]
Therefore, the logic circuit 23 outputs the control signal Vsource that is low level by an electrical angle of 120 degrees in the period a and the control signal Vsink that is low level by the electrical angle of 120 degrees in the period b. The control signal Vsource and the control signal are output from the logic circuit 23. Since Vsink is turned on and off at a predetermined timing by the comparator, Vsink causes a drive current to flow through the drive coil 2 to rotate the motor.
[0009]
The drive current flowing in the drive coil 2 is switched from the energized state to the non-energized state at the time point c when the periods a and b end, and therefore a kickback pulse is generated in the drive coil 2.
[0010]
For this reason, noise that changes between the high level and the low level instantaneously at a high frequency is superimposed on the output COMPv of the comparator 5 due to the influence of the kickback pulse.
[0011]
As shown in FIG. 3, when the 60-degree signal and the output of the voltage controlled oscillator 27 are applied to the delay circuit 30, the output frequency of the voltage controlled oscillator 27 is output by a plurality of DFFs 31-1, 31-2 and 31-m. A delayed signal delay obtained by delaying the phase of the signal by 60 degrees by the predetermined period is obtained.
[0012]
In the V-phase masking circuit 33, the 60-degree signal and the delay signal delay are first obtained from the EXNOR gate 35 as an inverted output Vlogic of exclusive OR. Further, the logical product of the output of the EXNOR gate 35 and the energization logic signal Vlogic is output from the AND gate 36.
[0013]
The output of the AND gate 36 is a signal obtained by ANDing the signal obtained by delaying the 60-degree signal and the control signal Vlogic that is at a high level when the drive transistor is in the OFF state. It goes high from the time when the kickback pulse occurs until the time when it is further delayed. Therefore, this period is a period not affected by the kickback voltage.
[0014]
Further, a logical product of the output of the AND gate 36 and the output of the voltage controlled oscillator 27 is output from the AND gate 37 as a masking signal Vmask. The output from the AND gate 37 is a signal delayed by an integral multiple of the output frequency of the voltage controlled oscillator 27 and has a high level period from the rise of the delay signal delay to the fall of the 60 degree signal. Is a period obtained by subtracting the delay time within a period of 60 electrical angles.
[0015]
Therefore, the masking signal Vmask has an integer multiple period in the high level output period of the AND gate 36. The falling edge of the maskin signal Vmask becomes the C terminal input of the DFF 21. Therefore, after the kickback pulse is generated, the masking signal Vmask is generated from the time when a predetermined delay time elapses until the time when the comparator output COMPv elapses. Therefore, the output COMPv of the comparator 5 that is not affected by the kickback pulse. Can be obtained. Similarly, the influence of the kickback pulse can be removed from the U phase and the V phase.
[0016]
By the way, in a sensorless motor, it is required to reduce power consumption as much as possible. Therefore, when the operation is interrupted, the reference power supply is turned off, and the constant current source that supplies a constant current to each circuit block such as a comparator, a logic circuit or a voltage controlled oscillation circuit is shut off. It will be in the power saving state where it does not flow and power is not consumed.
[0017]
If the reference power is turned off from normal operation and the power is saved immediately, the motor will free run, decelerate and stop. However, the control voltage of the control oscillation circuit used to generate the mask signal to suppress the kickback pulse is held by the charge accumulated in the capacitor of the low-pass filter.
[0018]
[Problem to be Solved by the Invention]
As described above, in the sensorless motor using the voltage controlled oscillation circuit for generating the mask signal, when the motor is immediately put into the standby state from the normal operation state, the control voltage of the voltage controlled oscillator is applied to the capacitor of the low-pass filter or the like. Since it is held by the accumulated charge, the oscillation frequency of the voltage-controlled oscillator is high and the width of the masking signal for masking the kickback pulse signal is narrow even though the motor rotation speed is low at the next restart. Therefore, it cannot mask enough and cannot be restarted.
[0019]
[Means for Solving the Problems]
In the present invention, when the operation is temporarily interrupted, a standby signal is added to make the energization logic in a short brake state, the motor is decelerated, and the counter is operated to start counting with the oscillation signal from the voltage controlled oscillator. The counter is reset by a speed signal from the logic circuit so that it is not counted up.
[0020]
However, since the energization logic is switched from the counter at the time of start-up and a start-up pulse is generated, the voltage-controlled oscillator oscillates at the minimum frequency for operating the counter even when the motor is decelerated and no speed signal is input. Therefore, even when the motor is sufficiently decelerated, the oscillation frequency of the voltage-controlled oscillator continues to oscillate at the lowest frequency, while the speed signal counts up before the counter is reset because the interval becomes longer, and the count generated by the counter This is a sensorless motor drive circuit that saves power by turning off the reference power supply with a signal.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
[0022]
In FIG. 1, reference numerals 42, 43, and 44 denote U-phase, V-phase, and W-phase drive coils of the motor constituting the drive circuit 41. Each drive coil is Y-connected, and one end is connected to each phase drive coil. The other end is connected to the common connection end COM.
[0023]
Reference numerals 45, 46, and 47 denote position detection comparators corresponding to the U-phase, V-phase, and W-phase drive coils 42, 43, and 44 of the motor. Reverse induced waveforms Vu, Vv, and Vw generated in the phase, V phase, and W phase drive coils 42, 43, and 44 are applied, and the midpoint voltage waveform VCOM of the common connection terminal COM is applied to the other input terminals. Instead of adding the midpoint voltage waveform VCOM to the other input terminals of the position detection comparators 45, 46, 47, an output combined voltage waveform VCO obtained by combining the output voltages of the drive coils 42, 43, 44 may be added.
[0024]
50 and 51 are PNP-type and NPN-type output transistors for supplying a drive current to the U-phase drive coil 42, and their emitter-collector paths are connected in series between the power supply VCC and the ground. The drive coil 42 is connected to one end. Similarly, 52 and 53 are PNP-type and NPN-type output transistors for supplying a drive current to the V-phase drive coil 43. The emitter-collector path is connected in series between the power supply VCC and the ground, and the collector is common. The connection point is connected to one end of the drive coil 43. Reference numerals 54 and 55 denote PNP type and NPN type output transistors for supplying a drive current to the W-phase drive coil 4. The emitter / collector paths are connected in series between the power supply VCC and the ground, and the collector common connection point. Is connected to one end of the drive coil 44.
[0025]
A control logic circuit 56 generates a logic signal based on the comparator outputs COMPu, COMPV, COMPw of the position detection comparators 45, 46, 47, and the output transistors 50-55 from the energization logic circuit 57 based on the logic signal. 6 types of control signals Usour, Usink, Vsource, Vsink, Wsource, and Wsink are generated.
[0026]
The control signal Ussource is applied to the base of the output transistor 50 via the buffer 58, and the control signal Usink is applied to the base of the output transistor 51 via the inverter 59. Similarly, the control signal Vsource is applied to the base of the output transistor 52 via the buffer 60, and the control signal Vsink is applied to the base of the output transistor 53 via the inverter 61.
[0027]
Further, the control signal Wsource is applied to the base of the output transistor 54 via the buffer 62, and the control signal Wsink is applied to the base of the output transistor 55 via the inverter 63.
[0028]
The control logic circuit 56 generates a speed signal 3FG that changes at an electrical angle interval of 60 degrees in accordance with the rotational speed of the motor. Reference numeral 65 denotes a PLL circuit, which is connected to a phase comparison circuit 66 to which the speed signal 3FG is added and a capacitor C constituting a low-pass filter, and a voltage controlled oscillator 67 that changes an oscillation frequency by a phase comparison output from the phase comparison circuit 66. And a frequency divider 68 that divides the frequency of the oscillation from the voltage-controlled oscillator 67 and applies it to the phase comparison circuit 66. Reference numeral 69 denotes a counter which counts up with an oscillation signal from the voltage controlled oscillator 67 and is reset with the speed signal 3FG.
[0029]
70 is a standby signal source, 72 is a reference voltage source, and a constant current source 74 that supplies a constant current to each circuit block such as the position detection comparators 45, 46, 47, the control logic circuit 56, the energization logic 57, and the voltage control oscillation circuit 65. Is connected. When both the standby signal STB applied from the standby signal source 70 via the buffer 71 and the count signal KT from the counter circuit 69a become high level, the AND circuit 73 turns the output to high level and turns off the reference voltage source 72. The voltage supply to the source 74 is stopped.
[0030]
Note that the counter circuit 69b is a circuit for switching the energization logic circuit 57 and generating a starting pulse at the time of starting. For this reason, the voltage-controlled oscillator 67 oscillates at the lowest frequency for operating the counter 69b even when no 3FG signal is input. The counter 69b counts up after the counter 69a is counted up and generates an output.
[0031]
That is, when a power switch (not shown) is turned on for activation, the voltage controlled oscillator 67 oscillates at the lowest frequency and counts up the counters 69a and 69b. If the motor is not rotating at this time, the speed signal 3FG is not generated, so the counters 69a and 69b continue to count without being reset, finally count up to the end of the counter 69b, generate an output signal from the counter 69b, and generate energization logic. In addition to the circuit 57, the energization logic circuit is switched to generate a starting pulse.
[0032]
Next, the operation will be described.
[0033]
As shown in FIG. 5, when the reference voltage source 72 is in an operating state, the energization logic circuit 57 drives the U-phase, V-phase, and W-phase output transistors 50 to 55 in a predetermined order according to the drive mode. In addition to the six types of control signals Usource, Usink, Vsource, Vsink, Wsource, Wsink, the U-phase, V-phase, and W-phase drive coils 42, 43, and 44 are energized to indicate that they are energized and de-energized. Output logic signals Ulogic, Vlogic, Wlogic (not shown). The energization logic signals Ulogic, Vlogic, and Wlogic are signals that are at a high level only for a period of 60 degrees in which no energization is performed in each of the U phase, V phase, and W phase.
[0034]
Referring mainly to the V phase in FIG. 5, the control signal Vsource that is low level by an electrical angle of 120 degrees in the period a and the energization logic signal Vsink that is low level by the electrical angle of 120 degrees in the period b are output. The energization logic signal Wsource and the energization logic signal Wsink that are low in phase with an electrical angle of 120 degrees are output, and the energization logic signal Usource and the energization logic signal Usink that are further out of phase with an electrical angle of 120 degrees are output.
[0035]
Accordingly, the power transistor side output transistor 52 is turned on during the period a, the output transistor 55 is turned on at the first electrical angle of 60 degrees, the output transistor 51 is subsequently turned on, and the ground side output transistor 53 is turned on during the period b. At the same time, the output transistor 50 is turned on for the first electrical angle of 60 degrees, and then the output transistor 54 is turned on. The periods other than the periods a and b are periods in which both the output transistors 52 and 53 are off.
[0036]
As shown in FIG. 5, a drive signal flows through the drive coil 43 to rotate the motor to generate a counter-inductive waveform Vv, and similarly to the drive coils 42 and 44, counter-inductive waveforms Vu and Vw are generated.
[0037]
For example, the reverse induction waveform Vv generated by the drive coil 43 is added to the input of the position detection comparator 46. Further, the neutral point voltage waveform VCOM is applied to the other input of the position detection comparator 46, which is compared by the position detection comparator 46 to generate a comparator output COMPv, which is applied to the control logic circuit 56 to generate a control logic signal. The control logic signal enters the energization logic circuit 57 and generates the energization logic signal Vsource and the energization logic signal Vsink from the energization logic circuit 57.
[0038]
Similarly, the reverse induction waveform Vu generated in the drive coil 42 is added to the input of the position detection comparator 45, and the reverse induction waveform Vw generated in the drive coil 44 is added to the input of the position detection comparator 47. A neutral point voltage waveform VCOM is applied to the other inputs of the position detection comparators 45 and 47, and is compared by the position detection comparators 45 and 47 to generate a comparator output COMPu or COMPw, which is applied to the control logic circuit 56. The energization logic circuit 57 generates the energization logic signal Usource, the energization logic signal Usink, the energization logic signal Wsource, and the energization logic signal Wsink, and rotates the motor.
[0039]
When the motor rotates, a speed signal 3FG is generated from the control logic circuit 56 and applied to the phase comparison circuit 66 of the PLL circuit 65, an error signal is generated from the phase comparison circuit 66, and the oscillation signal OSC from the voltage control oscillator 67 is divided. The frequency is divided by the frequency divider 68, fed back to a different terminal of the phase comparison circuit 66, phase-compared with the speed signal 3FG, and the oscillation frequency of the voltage controlled oscillator 67 is controlled in addition to the voltage controlled oscillator 67 through a filter. To do.
[0040]
Next, when a temporary stop switch (not shown) is operated to temporarily stop the motor, when the standby signal STB from the standby signal source 70 becomes high level and is applied to the energization logic circuit 57, the energization logic circuit 57. The energization logic signals Usource, Vsource, and Wsource are simultaneously turned to the low level, in addition to the output transistors 50, 52, and 54 through the buffers 58, 60, and 62, and the output transistors 50, 52, and 54 are simultaneously turned on and a short brake is applied. Decelerate.
[0041]
When the standby signal STB from the standby signal source 70 is set to the high level, the counter circuit 69a also starts counting, but at the beginning of the deceleration of the motor, the speed signal 3FG from the control logic circuit 56 is added to the counter circuit 69a, Since the counter circuit 69a continues to be reset and is not counted up, one terminal of the AND circuit 73 remains at a low level because the count signal is at a low level, the output of the AND circuit 73 is at a low level, and the standby signal STB Is not applied to the reference voltage source 72 and remains in the operating state.
[0042]
When the rotational speed of the motor decreases, the frequency of the speed signal 3FG also decreases, so the control signal from the speed signal phase comparison circuit 66 also decreases and the oscillation frequency of the voltage controlled oscillator 67 also decreases.
[0043]
However, even when the rotational speed of the motor is sufficiently reduced, the voltage-controlled oscillator 67 continues to oscillate at the lowest frequency. Therefore, the counter circuit 69a continues to count with the oscillation signal OSC, but the speed signal 3FG decreases until the electrical angle 60 is reached. Since the relationship in which a predetermined number of pulses are input does not hold and is not reset, the count output KT from the counter circuit 69a is set to the high level. Since the count signal KT is applied to the AND circuit 73 together with the standby signal STB of high level, the output of the AND circuit 73 becomes high level, the reference voltage source 72 is turned off, and the voltage to the constant current source 74 is cut off. Stops the supply of constant current to the circuit block and puts it in a power save state.
[0044]
In the above description, it has been explained that the output transistors 50, 52, and 54 are simultaneously turned on and the motor is decelerated by applying a short brake. However, the output currents are reduced by turning off all of the output transistors 50, 51, 52, 53, 54, and 55. It may be decelerated by shutting off and entering a free-run state.
[0045]
Next, when the temporary stop switch (not shown) is opened to rotate the motor again, the standby signal STB from the standby signal source 70 becomes low level, so that the output of the AND circuit 73 becomes low level and the reference voltage source 72 is put into operation. As a result, the supply of voltage to the constant current source 74 is resumed, a constant current is supplied to each circuit block, and the motor begins to rotate, and the energization logic circuit 57 outputs U-phase, V-phase, and W-phase as described above. The transistors 50 to 55 are driven in a predetermined order according to the drive mode, and control signals Usource, Usink, Vsource, Vsink, Wsource, Wsink are output. Accordingly, the output transistors 50 to 55 are sequentially turned on and off, and a drive current is supplied to the drive coils 42, 43, and 44 to rotate the motor.
[0046]
The counter-induced waveforms Uv, Vv, Wv generated in the drive coils 42, 43, 44 as the motor rotates are added to the inputs of the position detection comparators 45, 46, 47. Further, the neutral voltage waveform VCOM is applied to the other input of the position detection comparator 46 and is compared by the position detection comparators 45, 46, 47 to generate comparator outputs COMPu, COMPv, COMPw. In addition, the energization logic circuit 57 is entered, and control signals Usource, Usink, Vsource, Vsink, Wsource, Wsink are output from the energization logic circuit 57, the output transistors 50 to 55 are sequentially turned on and off, and the motor continues to rotate. .
[0047]
The oscillation signal OSC from the voltage-controlled oscillator 67 is shifted to the standby state after the motor speed is sufficiently lowered and the frequency is lowered. Therefore, the timing mask corresponding to the speed at that time when the motor is started next time. Since the signal can be obtained, the kickback pulse included in the comparator outputs COMPu, COMPv, COMPw of the position detection comparators 45, 46, 47 is masked and the control logic signal is generated, so that it can be easily restarted from the standby state. .
[0048]
【The invention's effect】
The drive circuit of the sensorless motor of the present invention adds a standby signal to the energizing logic circuit that supplies the drive current to the drive circuit to bring it into a brake state, the motor rotation speed is reduced, and the oscillation signal of the voltage controlled oscillator is sufficiently reduced. In this case, since the reference voltage source is turned off because the counter is counted up with the oscillation signal, the kickback pulse signal included in the comparator output signal can be masked even when restarted.
[0049]
In addition, the standby signal and the count signal generated when the counter counts up by a predetermined value are gated by an AND circuit and added to the reference voltage source, and the reference voltage source is set in the standby state, so that power saving can be reliably performed. .
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a drive circuit for a sensorless motor of the present invention.
FIG. 2 is a circuit diagram illustrating a driving circuit of a conventional sensorless motor.
3 is a block diagram showing a delay circuit of the conventional sensorless motor shown in FIG. 2. FIG.
4 is a circuit diagram of a delay circuit portion of the conventional sensorless motor shown in FIG. 2. FIG.
FIG. 5 is a waveform diagram of each part of the drive circuit of the present invention and a conventional sensorless motor.
[Explanation of symbols]
41 drive circuit 42, 43, 44 drive coil 45, 46, 47 position detection comparator 50, 51, 52, 53, 54, 55 output transistor 56 control logic circuit 57 energization logic circuit 65 voltage control oscillation circuit 66 phase comparison circuit 67 voltage Control oscillator 69 Counter circuit 72 Reference voltage source

Claims (1)

An output transistor that supplies a drive current to a drive coil of a plurality of phases, an output combined waveform that combines a reverse induction waveform generated in each of the drive coils of the plurality of phases and an output voltage waveform of the drive coils of the plurality of phases, or the neutrality of the motor A plurality of position detection comparators for comparing point voltage waveforms, a control logic circuit for generating a control signal based on a comparator output of the position detection comparator, and a drive current to the drive coil based on the control signal of the control logic circuit An energization logic circuit that generates an energization timing signal for sequentially turning on and off the output transistors that supply the voltage, a voltage-controlled oscillator whose oscillation frequency changes according to a speed signal generated according to the rotation speed from the control logic circuit, and the voltage From the counter circuit that counts up with the oscillation signal of the controlled oscillator and is reset with the speed signal Ri,
A standby signal is added to the energization logic circuit to set the brake state or the free-run deceleration state to reduce the motor rotation speed, and when the oscillation signal of the voltage controlled oscillator is sufficiently reduced, the counter is counted up ,
A sensorless motor driving circuit , wherein a standby signal and a count signal generated when the counter counts up a predetermined time are added to an AND circuit, and a reference voltage source is turned off by an output signal of the AND circuit .

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