JP4133630B2 - Frequency synthesizer, tuner and receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frequency synthesizer, a tuner and a receiver used for a digital terrestrial television broadcast receiving terminal.
[0002]
[Prior art]
Conventionally, the transmission path coding method and operation guidelines for digital terrestrial television broadcasting are, for example, ARIB STD-B31 1.1, which is a standard document issued by the Association of Radio and Businesses (ARIB). It is shown in paragraphs 10 to 15, 70 and 71 of the edition (created on May 31, 2001, revised on November 15, 2001, 1.1).
[0003]
The frequency of terrestrial digital television broadcasting has the configuration shown in FIG. Digital terrestrial television broadcasting is performed on 50 channels from 13 to 62 channels in the UHF band. The bandwidth of one channel is 6 MHz. 6-5 / 14-1 / 14 = 6 × 13/14 MHz (about 5.6 MHz) excluding the lower 5/14 MHz and the upper 1/14 MHz in this band is divided into 13 segments, and one segment ( 6/14 MHz = about 430 KHz), and the modulation method can be changed. Here, the center of 13 segments included in the 13 + N channel band (N is an integer from 0 to 49) of the UHF band, that is, the center of one central segment is 6N + 473 + 1/7 MHz.
[0004]
As a method of using the 13 segments, it is considered that one central segment of the 13 segments is used for broadcasting for mobile terminals and the remaining 12 segments are used for broadcasting for fixed terminals. Broadcasting for portable terminals employs a QPSK (Quaternary Phase Shift Keying) modulation method that has a low data transfer rate but a low required C / N and is easy to receive even in poor reception conditions. This makes it easy to receive terrestrial digital TV broadcasts even when moving, and mobile terminals such as mobile phones and PDAs (Personal Digital Assistance) with built-in tuners for receiving 1-segment digital terrestrial TV broadcasts may become widespread. Expected.
[0005]
When such a one-segment reception tuner is designed by a normal method, an intermediate frequency (IF) is 57 MHz. However, when such an intermediate frequency is selected, the sampling frequency used in the analog-to-digital converter provided for digital processing in the OFDM (Orthogonal Frequency Division Multiplexing) demodulator at the latter stage of the tuner becomes high. There is a problem that increases.
[0006]
In addition, such a one-segment reception tuner is not currently known, but is assumed to be configured as follows.
[0007]
The band of 13 segments is 6 × 13/14 MHz, whereas the band of 1 segment is 6/14 MHz = about 430 KHz, so the intermediate frequency of the tuner for receiving 1 segment can be set low. Specifically, since the FFT (Fast Fourier Transform) sample frequency at the time of demodulation of digital terrestrial television broadcasting is determined to be 512/63 MHz, it is 1/16, 1/8, 1/4 or 1/2. It is considered reasonable to set a certain 32/63 MHz, 64/63 MHz, 128/63 MHz or 256/63 MHz as the predetermined intermediate frequency.
[0008]
When the intermediate frequency is 32/63 MHz, since the center frequency of the segment is 6N + 473 + 1/7 MHz (N is an integer from 0 to 49), the default oscillation frequency of the frequency synthesizer used for the tuner is 6N + 473 + 1/7 + 32/63 MHz or 6N + 473 + 1 / 7-32 / 63 MHz.
[0009]
The center frequency of the UHF 13 channel, which is the lowest channel in the UHF band used for terrestrial digital broadcasting, is 473 + 1/7 MHz as shown in FIG.
[0010]
However, a frequency synthesizer having such an oscillation frequency has the following problems.
[0011]
In the frequency synthesizer, a frequency component deviated from a desired oscillation frequency, that is, phase noise becomes a problem, but the phase noise is suppressed within the loop band of the loop filter constituting the frequency synthesizer. The upper limit of the loop band is set to be about 1/10 of the reference frequency.
[0012]
However, when the oscillation frequency is 6N + 473 + 1/7 + 32/63 MHz or 6N + 473 + 1 / 7−32 / 63 MHz, the reference frequency is, for example, 1/7 + 32/63 = 41/63 MHz or 1 + 1 / 7−32 / 63 = 40 / It is set as low as 1/63 MHz, which is an integer of 63 (1/41 or 1/40). In this case, the upper limit of the loop band is as low as about 1/640 MHz (about 1.6 KHz), and it is difficult to suppress phase noise in the loop filter.
[0013]
Further, when the reference frequency is low, the frequency dividing number of the variable frequency divider constituting the frequency synthesizer increases, so that the circuit scale increases and the power consumption increases. Further, since the frequency dividing number is large, the frequency of phase comparison with respect to the oscillation frequency is reduced, and phase noise is likely to occur.
[0014]
In the case of the predetermined intermediate frequency of 64/63 MHz, 128/63 MHz or 256/636 MHz, there is a similar problem if the reference frequency is set low as 1/63 MHz.
[0015]
As a technique for setting the reference frequency high, for example, a phase locked loop circuit disclosed in Patent Document 1 can be cited. In this document, an integer value + fractional value is obtained as an average division ratio by switching a plurality of integer division ratios using a variable frequency divider having a variable number of integer division ratios. It is disclosed that the reference frequency is increased.
[0016]
[Patent Document 1]
JP 2002-16494 (release date: January 18, 2002)
[0017]
[Problems to be solved by the invention]
However, in the above-described phase-locked loop circuit, the circuit for switching the frequency division ratio is complicated, so that not only the number of parts increases, but also power consumption increases. Also, in the in-phase locked loop circuit, CPU control using a memory and a CPU is necessary for switching the frequency divider, and access to the memory at a high frequency may not be in time because the memory access speed is low. It is a problem to have sex.
[0018]
The present invention has been made in view of the above problems, and in a band assignment broadcasting system such as digital terrestrial television broadcasting, the reference frequency is high, phase noise can be easily suppressed, circuit scale and power consumption. Is intended to provide a low frequency synthesizer, tuner and receiver.
[0019]
[Means for Solving the Problems]
In order to solve the above problem, a frequency synthesizer according to the present invention is a frequency synthesizer including a phase-locked loop that controls a first reference frequency and an integer frequency of an output frequency to coincide with each other. A crystal oscillator that generates a reference signal of a predetermined frequency; The first reference frequency is a frequency synthesizer The output frequency And a sub-phase locked loop that outputs a fixed frequency signal having a fixed frequency based on the second reference frequency, and is set in the phase locked loop to A mixing unit that mixes an output frequency and the fixed frequency, and the phase-locked loop includes: Predetermined frequency of reference signal Having a first fixed frequency divider that generates the first reference frequency by dividing the frequency by a fixed division ratio, and the sub-phase locked loop includes: Predetermined frequency of reference signal It is characterized by having a second fixed frequency divider that generates the second reference frequency by dividing the frequency by a fixed frequency division ratio.
[0020]
In the above frequency synthesizer, the phase locked loop is controlled based on, for example, a phase comparator that outputs a phase difference between a reference frequency signal and a frequency-divided signal output from a variable frequency divider, and an output of the phase comparator. A control voltage generator for generating a voltage; a voltage-controlled oscillator that outputs an oscillation frequency signal having a frequency controlled based on the control voltage; and a variable that divides the oscillation frequency signal into a number of different frequencies according to the number of channels. And a frequency divider. The reference frequency may be obtained by, for example, a fixed frequency divider or directly from a crystal oscillator that generates a reference signal, but a higher reference frequency can be obtained by dividing the frequency by the fixed frequency divider. .
[0021]
In the above configuration, since the reference frequency is set to be a fraction of an integer obtained by offsetting the predetermined oscillation frequency by a predetermined frequency, the numerical value of the denominator of the oscillation frequency (output frequency) can be reduced. . Therefore, the reference frequency can be increased.
[0022]
For example, if the default oscillation frequency is 6N + 473 + 1/7 + 32/63 MHz with respect to the number of channels of terrestrial digital television broadcasting 13 + N (N is an integer from 0 to 49), an offset of −1/126 MHz is provided for this default oscillation frequency. From the phase locked loop, an oscillation frequency of 6N + 473 + 1/7 + 1/2 MHz is obtained. Thereby, since the fractional part of the oscillation frequency is 1/7 + 1/2 = 9/14 MHz, the numerical value of the denominator of the oscillation frequency becomes 14, which is smaller than the conventional numerical value. Therefore, if the reference frequency is set to 1/14 MHz, which is 1/9 of an integer of 9/14 MHz, a high reference frequency can be obtained.
[0023]
Similarly to the above case, when the default oscillation frequency is 6N + 473 + 1/7 + 32/63 MHz, if a 1/63 MHz offset is provided for this default oscillation frequency, the oscillation becomes 6N + 473 + 1/7 + 33/63 MHz from the phase-locked loop. The frequency is obtained. As a result, since the fractional part of the oscillation frequency is 1/7 + 33/63 MHz = 2/3 MHz with respect to 1/7 + 32/63 = 41/63 MHz, the numerical value of the denominator of the oscillation frequency is 3, which is smaller than the conventional numerical value. Become. Therefore, if the reference frequency is set to 1/3 MHz, which is an integral fraction (1/2) of 2/3 MHz, a high reference frequency can be obtained.
[0024]
Therefore, the upper limit of the loop band of the phase locked loop is also increased according to the reference frequency (about 1/10 of the reference frequency).
[0025]
The frequency synthesizer includes a sub-phase locked loop that outputs a fixed frequency, and a mixing unit that mixes the output frequency and the fixed frequency in the phase locked loop. By Since the fixed frequency output from the secondary phase locked loop and the output frequency output from the phase locked loop are mixed in the mixing section, the reference frequency is further increased compared to the frequency synthesizer with a single phase locked loop. be able to.
[0026]
In this frequency synthesizer, it is preferable that the reference frequency f1 of the phase-locked loop and the reference frequency f2 of the sub-phase-locked loop are set as follows.
(A) f1 = 1/2 MHz, f2 = 8/7 MHz
(B) f1 = 1 MHz, f2 = 8/3 MHz
(C) f1 = 3 MHz, f2 = 16/3 MHz
In the combination (a), the upper limit of the loop band can be increased to about 1/20 MHz. Thereby, phase noise can be suppressed more greatly.
[0027]
In the combination (b), the upper limit of the loop band can be increased to about 1/10 MHz. Thereby, phase noise can be suppressed more greatly.
[0028]
In the combination (c), the upper limit of the loop band can be increased to about 3/10 MHz. Thereby, phase noise can be suppressed more greatly.
[0029]
A tuner according to the present invention includes the frequency synthesizer having any one of the above-described configurations. As a result, it is possible to provide a tuner with a small phase noise and a small circuit scale and power consumption.
[0030]
This tuner preferably outputs an intermediate frequency of 1/2 MHz or 33/63 MHz. 1/2 MHz is the lowest frequency among the frequencies corresponding to the offset of 1/126 MHz of the oscillation frequency in the frequency synthesizer. 33/63 MHz is the lowest frequency among the frequencies corresponding to the offset of 1/63 MHz of the oscillation frequency in the frequency synthesizer. The intermediate frequency is sampled by using an analog-to-digital converter provided for digital processing in the OFDM demodulator at the latter stage of the tuner, so that the lower one can lower the sampling frequency, and the analog-to-digital converter Power consumption can be reduced.
[0031]
The receiver according to the present invention includes the tuner and an offset removing unit that removes the offset from an intermediate frequency output from the tuner.
[0032]
In such a configuration, since the offset included in the intermediate frequency output from the tuner is removed by the removal unit, a predetermined intermediate frequency can be obtained. Therefore, the intermediate frequency can be normally amplified.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIGS. 1 to 8 as follows.
[0034]
[First Reference example ]
FIG. 1 shows the first Reference example 1 shows the configuration of a direct frequency dividing type frequency synthesizer.
[0035]
This frequency synthesizer includes a crystal oscillator 1, a fixed frequency divider 2, a phase comparator 3, a loop filter 4, a voltage controlled oscillator 5, and a variable frequency divider 6. In this frequency synthesizer, a phase locked loop 7 is formed by the phase comparator 3, the loop filter 4, the voltage controlled oscillator 5, and the variable frequency divider 6.
[0036]
The crystal oscillator 1 generates a signal having a predetermined frequency, for example, 16 MHz. The fixed divider 2 divides the 16 MHz signal by a fixed division ratio 224 and outputs a 1/224 1/14 MHz signal as a reference frequency signal. The reference frequency signal of 1/14 MHz becomes 1 / (1/9) of an integer of 41 / 63-1 / 126 = 9/14 obtained by subtracting the offset of 1/126 MHz from 1/7 + 32/63 = 41/63 MHz. ing.
[0037]
The phase comparator 3 detects the phase difference between the input reference frequency signal and the frequency-divided signal from the variable frequency divider 6 and outputs the phase difference as a voltage or current pulse-like phase difference signal. The loop filter 4 integrates the phase difference signal and removes the unnecessary component included in the phase difference signal output from the phase comparator 3 and determines the overall response characteristic of the phase locked loop 7. A control voltage applied to the controlled oscillator 5 is output. The voltage controlled oscillator 5 generates an output signal having a frequency corresponding to the input control voltage.
[0038]
The variable frequency divider 6 divides the output signal of the voltage controlled oscillator 5, that is, the output signal of the frequency synthesizer, to 1 / (84N + 6631) by a variable frequency division ratio 84N + 6631 (N is an integer from 0 to 49). The result of the rotation is output to the phase comparator 3 as a divided signal. The variable frequency divider 6 is constituted by a programmable counter in order to divide by a variable frequency dividing ratio 84N + 6631. For example, the frequency dividing ratio of the variable frequency divider 6 is 6631 to 10747, which is realized by a 14-bit counter.
[0039]
More specifically, the variable frequency divider 6 is configured by a variable frequency dividing circuit generally called a “pulse swallow counter”. This variable frequency dividing circuit includes a frequency dividing circuit capable of switching between M frequency dividing and M + 1 frequency dividing, and a counter for counting pulses after frequency division by the frequency dividing circuit. This counter counts the divided pulses, thereby controlling the frequency dividing circuit so that the LA count is divided by M and the A count is divided by M + 1. Thereby, as a total, (LA) × M + A × (M + 1) = L × M + A frequency division is realized, and an output pulse obtained by dividing the input pulse by L × M + A is output. The variable frequency divider 6 has a time interval of about 1 / L of one comparison cycle in the phase comparator 3 (because it becomes about 1 / L because the period of dividing by M is different from the period of dividing by M + 1). Switch between frequency division and M + 1 frequency division. Therefore, the integer division of 84N + 6631 can be realized by appropriately setting the integers M, L, and A.
[0040]
In the frequency synthesizer configured as described above, the frequency control of the output signal is performed as follows. When the phase of the frequency-divided signal is ahead of the phase of the reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 5 is lowered. On the other hand, when the phase of the divided signal is delayed from the phase of the reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage controlled oscillator 5 becomes higher. Thereby, the phases of the reference frequency signal and the frequency-divided signal match, and the frequencies of the reference frequency signal and the frequency-divided signal match. Therefore, the frequency of the output signal of the frequency synthesizer is 1/14 × (84N + 6631) = 6N + 473 + 1/7 + 1/2 MHz.
[0041]
As above, the book Reference example The frequency synthesizer provides an offset of −1/126 MHz to the predetermined oscillation frequency 6N + 473 + 1/7 + 32/63 MHz, and obtains an output signal frequency of 6N + 473 + 1/7 + 32 / 63-1 / 126 MHz = 6N + 473 + 1/7 + 1/2 MHz. Thereby, the reference frequency can be set to a high 1/14 MHz by using the fact that 1/7 + 1/2 = 9/14 MHz. Therefore, since the upper limit of the loop band is increased to about 1/140 MHz (about 7 kHz), which is 1/10 of the reference frequency, phase noise can be easily suppressed.
[0042]
[No. 1 Embodiment of
FIG. 1 1 shows a configuration of a mixer-type frequency synthesizer according to the embodiment.
[0043]
This frequency synthesizer includes a crystal oscillator 11, a fixed divider 12, a phase comparator 13, a loop filter 14, a voltage control oscillator 15, a mixer 16, a low-pass filter 17, a variable divider 18, a fixed divider 19, and a phase comparison. 20, a loop filter 21, a voltage controlled oscillator 22, and a variable frequency divider 23. In this frequency synthesizer, the phase comparator 13, the loop filter 14, the voltage controlled oscillator 15, the mixer 16, the low pass filter 17 and the variable frequency divider 18 form a first phase locked loop 24. In this frequency synthesizer, the phase comparator 20, the loop filter 21, the voltage controlled oscillator 22, and the variable frequency divider 23 form a second phase locked loop 25.
[0044]
The crystal oscillator 11 generates a signal having a predetermined frequency, for example, 16 MHz, similarly to the crystal oscillator 1 described above. The fixed frequency divider 12 divides the 16 MHz signal by a fixed division ratio 32 and outputs a 1/32 1/2 MHz signal as the first reference frequency signal.
[0045]
The phase comparator 13 detects the phase difference between the input first reference frequency signal and the frequency-divided signal from the variable frequency divider 18 and outputs the phase difference as a voltage or current pulse-like phase difference signal. To do. The loop filter 14 integrates the phase difference signal in order to remove unnecessary components included in the phase difference signal output from the phase comparator 13 and to determine the overall response characteristic of the first phase locked loop 24. Then, the control voltage applied to the voltage controlled oscillator 15 is output. The voltage controlled oscillator 15 generates an output signal having a frequency corresponding to the control voltage from the loop filter 14.
[0046]
The mixer 16 synthesizes the frequency of the output signal of the voltage controlled oscillator 15 and the frequency of the fixed frequency signal from the voltage controlled oscillator 22 described later. Specifically, the mixer 16 generates frequencies of fa−fb and fa + fb by multiplying, for example, two frequencies of fa and fb (fa> fb).
[0047]
The low pass filter 17 removes unnecessary high frequency components in the synthesized frequency signal from the mixer 16.
[0048]
The variable frequency divider 18 divides the synthesized frequency signal from the low-pass filter 17 by 1 / (12N + 17) by a variable frequency division ratio 12N + 17 (N is an integer from 0 to 49), and divides the frequency division result. The signal is output to the phase comparator 13 as a signal. Since the variable frequency divider 18 divides the frequency by a variable frequency dividing ratio 12N + 17, the variable frequency divider 18 is constituted by a programmable counter such as a pulse swallow counter as in the above-described variable frequency divider 6 (see FIG. 1). For example, the frequency dividing ratio of the variable frequency divider 18 is 17 to 605, which is realized by a 10-bit counter.
[0049]
The fixed frequency divider 19 divides the 16 MHz signal generated by the crystal oscillator 11 by a fixed frequency dividing ratio 14 and outputs a 1/14 8/7 MHz signal as the second reference frequency signal.
[0050]
The phase comparator 20 detects the phase difference between the input second reference frequency signal and the frequency-divided signal from the fixed frequency divider 23, and outputs the phase difference as a voltage or current pulse-like phase difference signal. To do. The loop filter 21 integrates the phase difference signal in order to remove unnecessary components included in the phase difference signal output from the phase comparator 20 and to determine the overall response characteristic of the second phase locked loop 25. Then, a control voltage applied to the voltage controlled oscillator 22 is output.
[0051]
The voltage controlled oscillator 22 generates a fixed frequency signal having a frequency corresponding to the control voltage from the loop filter 21, that is, 3256/7 MHz. The fixed divider 23 divides the output signal from the voltage controlled oscillator 22 by 1/407 with a fixed division ratio 407 and outputs the divided result to the phase comparator 20 as a divided signal.
[0052]
Here, a method for setting the first and second reference frequencies will be described.
[0053]
With respect to 6N + 473 + 1/7 + 1/2, a reference frequency is considered as follows by dividing into an integral multiple of 1/7 and an integral multiple of 1/2.
[0054]
6N + 473 + 1/7 + 1/2
= (6N + K + 1/2) + (473-K + 1/7)
= (12N + 2K + 1) / 2 + (3312-7K) / 7
Here, K is an integer. From the first term on the right side, the first reference frequency is determined to be 1/2 MHz. The second term on the right side is a fixed frequency synthesized by the mixer 16, and the second reference frequency is an integral fraction of (3312-7K) / 7 MHz.
[0055]
For the fixed frequency of the second term, K is determined by performing the following three evaluations.
(1) Increase the second reference frequency as much as possible.
(2) The second reference frequency is set to a value that can be generated by a signal from the crystal oscillator 11 that is the same as the first reference frequency.
(3) (3312-7K) / 7 so that the low-frequency filter 17 can sufficiently remove unnecessary high-frequency components out of the low-frequency components and the high-frequency components generated by the mixer 16. Increase
[0056]
K = 8 satisfies the above conditions. In this case, (3312-7K) / 7 = 3256/7 = 2 ³ Since × 11 × 37/7, the second reference frequency is 2 ³ / 7 = 8/7 MHz.
[0057]
Note that the above condition is satisfied even when K = 0. That is, when K = 0,
(12N + 2K + 1) / 2 + (3312-7K) / 7
= (12N + 1) / 2 + (3311 + 1) / 7
= 6N + 1/2 + 473 + 1/7
It becomes.
[0058]
In the frequency synthesizer configured as described above, the frequency control of the output signal is performed as follows. When the phase of the frequency-divided signal from the variable frequency divider 18 is ahead of the phase of the first reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 15 is lowered. On the other hand, when the phase of the frequency-divided signal from the variable frequency divider 18 is delayed from the phase of the first reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 15 becomes higher. As a result, the phases of the first reference frequency signal and the frequency-divided signal match, and the frequencies of the first reference frequency signal and the frequency-divided signal match.
[0059]
Therefore, the output signal of the frequency synthesizer is ½ × (12N + 17) + 3256/7 = 6N + 473 + 1/7 + ½ MHz by combining the frequencies fa and fb of the first and second phase locked loops 24 and 25. Further, in the mixer 16, fa− = fb = ((12N + 17) / 2 + 3256/7) by multiplying fa (= 6N + 473 + 1/7 + 1/2 = (12N + 17) / 2 + 3256/7 MHz) and fb (= 3256/7 MHz). )-(3256/7) = (12N + 17) / 2 MHz, the first reference frequency can be set to 1/2 MHz.
[0060]
In fa = 6N + 473 + 1/7 + 1/2 MHz, when trying to collectively deal with 1/7 and 1/2 terms that cannot be expressed as integers, 1/7 + 1/2 = 9/14 and the denominator becomes large, so the reference frequency becomes low. Therefore, if the 1/7 and 1/2 terms are separated and the 1/2 term is considered as the center, the 1/7 term becomes a frequency that cannot be expressed by an integral multiple of 1/2. Therefore, by generating the frequency fb of 3256/7 obtained by adding 465 to 1/7, the frequency to be generated by the phase locked loop 24 is 6N + 473 + 1/7 + 1 / 2−3256 / 7 = (12N + 17 ) / 2 (an integral multiple of 1/2).
[0061]
As described above, in the frequency synthesizer of the present embodiment, the default oscillation frequency is 6N + 473 + 1/7 + 32/63 MHz with an offset of −1/126 MHz, and 6N + 473 + 1/7 + 32 / 63-1 / 126 MHz = 6N + 473 + 1/7 + 1/2 MHz. The output signal frequency is obtained. The frequency synthesizer obtains the above frequency by synthesizing the frequencies generated by the first and second phase locked loops 24 and 25.
[0062]
Thereby, the first reference frequency can be set high to 1/2 MHz, and the second reference frequency can also be set high to 8/7 MHz. As a result, the first having a single phase-locked loop Reference example An output frequency higher than that of the frequency synthesizer can be obtained. Therefore, the upper limit of the loop band is increased to about 1/20 MHz (about 50 kHz), so that phase noise can be easily suppressed. Further, by having the first and second phase locked loops 24 and 25, it is possible to appropriately set the combination of the frequencies to be generated so that the reference frequency of any phase locked loop is increased.
[0063]
Since the first reference frequency 1/2 MHz is smaller than the second reference frequency 8/7 MHz, the upper limit of the loop band of the loop filter 14 is lower than the upper limit of the loop band of the loop filter 21. Therefore, it is the loop band of the loop filter 14 that affects the phase noise of the entire frequency synthesizer. This is the second 2 And second 3 This also applies to the embodiment.
[0064]
[No. 2 of Reference example ]
FIG. 2 of Reference example 1 shows the configuration of a direct frequency dividing type frequency synthesizer.
[0065]
This frequency synthesizer includes a crystal oscillator 31, a fixed frequency divider 32, a phase comparator 33, a loop filter 34, a voltage controlled oscillator 35, and a variable frequency divider 36. In this frequency synthesizer, a phase locked loop 37 is generated by a phase comparator 33, a loop filter 34, a voltage controlled oscillator 35 and a variable frequency divider 36.
[0066]
The crystal oscillator 31 generates a signal having a predetermined frequency, for example, 16 MHz, similarly to the crystal oscillator 1 described above. The fixed frequency divider 32 divides the 16 MHz signal by a fixed frequency division ratio 48 and outputs a 1/48 1/3 MHz signal as a reference frequency signal. The reference frequency signal of 1/3 MHz is 1/7 + 32/63 = 41/63 MHz plus an offset of 1/63 MHz, which is 1/1/2 of an integer of 41/63 + 1/63 = 2/3 MHz. .
[0067]
The phase comparator 33 detects the phase difference between the input reference frequency signal and the frequency-divided signal from the variable frequency divider 36, and outputs the phase difference as a voltage or current pulse-like phase difference signal. The loop filter 34 integrates the phase difference signal and removes the unnecessary component contained in the phase difference signal output from the phase comparator 33 and determines the overall response characteristic of the phase locked loop 37. A control voltage applied to the control oscillator 35 is output. The voltage controlled oscillator 35 generates an output signal having a frequency corresponding to the input control voltage.
[0068]
The variable frequency divider 36 divides the output signal of the voltage controlled oscillator 35, that is, the output signal of the frequency synthesizer, into 1 / (18N + 1421) by a variable frequency dividing ratio 18N + 1421 (N is an integer from 0 to 49). The result of the rotation is output to the phase comparator 33 as a divided signal. Since the variable frequency divider 36 divides the frequency by a variable frequency dividing ratio 18N + 1421, it is constituted by a programmable counter such as a pulse swallow counter, similar to the above-described variable frequency divider 6 (see FIG. 1). For example, the frequency dividing ratio of the variable frequency divider 36 is 1421 to 2303, and is realized by a 12-bit counter.
[0069]
In the frequency synthesizer configured as described above, the frequency control of the output signal is performed as follows. When the phase of the frequency-divided signal is ahead of the phase of the reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 35 is lowered. On the other hand, when the phase of the frequency-divided signal is delayed from the phase of the reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 35 becomes higher. Thereby, the phases of the reference frequency signal and the frequency-divided signal match, and the frequencies of the reference frequency signal and the frequency-divided signal match. Therefore, the frequency of the output signal of the frequency synthesizer is 1/3 × (18N + 1422) = 6N + 473 + 1/7 + 33/63 MHz.
[0070]
As above, the book Reference example The frequency synthesizer provides an output signal frequency of 6N + 473 + 1/7 + 32/63 + 1/63 MHz = 6N + 473 + 1/7 + 33/63 MHz by providing an offset of 1/63 MHz to the predetermined oscillation frequency 6N + 473 + 1/7 + 32/63 MHz. Thereby, the reference frequency can be set to a high 1/3 MHz by using the fact that 1/7 + 33/63 = 2/3 MHz. Therefore, since the upper limit of the loop band is increased to about 1/30 MHz (about 33 kHz), phase noise can be easily suppressed.
[0071]
The variable frequency divider 36 includes a first Reference example This frequency synthesizer is realized by a 12-bit counter because the frequency division ratio is smaller than that of the variable frequency divider 6 realized by a 14-bit counter. Thereby, compared with the variable frequency divider 6, the circuit scale of the variable frequency divider 36 can be made small, and power consumption can be reduced. Further, since the frequency division ratio is small, the frequency of phase comparison in the phase comparator 33 with respect to the oscillation frequency increases, so that phase noise is less likely to occur.
[0072]
[No. 2 Embodiment of
FIG. 2 1 shows a configuration of a mixer-type frequency synthesizer according to the embodiment.
[0073]
This frequency synthesizer includes a crystal oscillator 41, a fixed frequency divider 42, a phase comparator 43, a loop filter 44, a voltage controlled oscillator 45, a mixer 46, a low-pass filter 47, a variable frequency divider 48, a fixed frequency divider 49, and a phase comparison. 50, a loop filter 51, a voltage controlled oscillator 52, and a variable frequency divider 53. In this frequency synthesizer, the phase comparator 43, the loop filter 44, the voltage controlled oscillator 45, the mixer 46, the low-pass filter 47 and the variable frequency divider 48 form a first phase locked loop 54. In the present frequency synthesizer, the phase comparator 50, the loop filter 51, the voltage controlled oscillator 52, and the variable frequency divider 53 form a second phase locked loop 55.
[0074]
The crystal oscillator 41 generates a signal having a predetermined frequency, for example, 16 MHz, like the crystal oscillator 1 described above. The fixed divider 42 divides the 16 MHz signal by a fixed division ratio 16 and outputs a 1/16 1 MHz signal as a first reference frequency signal.
[0075]
The phase comparator 43 detects the phase difference between the input first reference frequency signal and the frequency-divided signal from the variable frequency divider 48, and outputs the phase difference as a voltage or current pulse-like phase difference signal. To do. The loop filter 44 integrates the phase difference signal in order to remove unnecessary components included in the phase difference signal output from the phase comparator 43 and to determine the overall response characteristic of the first phase locked loop 54. Then, a control voltage to be applied to the voltage controlled oscillator 45 is output. The voltage controlled oscillator 45 generates an output signal having a frequency corresponding to the control voltage from the loop filter 44.
[0076]
The mixer 46 combines the frequency of the output signal of the voltage controlled oscillator 45 with the frequency of the fixed frequency signal from the voltage controlled oscillator 52 described later. The low pass filter 47 removes unnecessary high frequency components in the synthesized frequency signal from the mixer 46. The variable frequency divider 48 divides the synthesized frequency signal from the low-pass filter 47 into 1 / (6N + 7) by a variable frequency division ratio 6N + 7 (N is an integer from 0 to 49), and divides the frequency division result. The signal is output to the phase comparator 43 as a signal. Since the variable frequency divider 48 divides the frequency by a variable frequency dividing ratio 6N + 7, the variable frequency divider 48 is configured by a programmable counter such as a pulse swallow counter like the above-described variable frequency divider 6 (see FIG. 1). For example, the frequency dividing ratio of the variable frequency divider 48 is 7 to 301, which is realized by a 9-bit counter.
[0077]
The fixed divider 49 divides the 16 MHz signal generated by the crystal oscillator 41 by a fixed division ratio 6 and outputs a 1/6 8/3 MHz signal as the second reference frequency signal. The phase comparator 50 detects the phase difference between the input second reference frequency signal and the frequency-divided signal from the fixed frequency divider 53, and outputs the phase difference as a voltage or current pulse-like phase difference signal. To do. The loop filter 51 integrates the phase difference signal in order to remove unnecessary components included in the phase difference signal output from the phase comparator 50 and to determine the overall response characteristic of the second phase locked loop 55. As a result, the control voltage applied to the voltage controlled oscillator 52 is output.
[0078]
The voltage controlled oscillator 52 generates a frequency corresponding to the control voltage from the loop filter 51, that is, a fixed frequency signal of 1400/3 MHz. The fixed frequency divider 53 divides the output signal from the voltage controlled oscillator 52 by a fixed frequency division ratio, for example, 175 to 1/175, and outputs the frequency division result to the phase comparator 50 as a frequency divided signal.
[0079]
Here, a method for setting the first and second reference frequencies will be described.
[0080]
With respect to 6N + 473 + 1/7 + 33/63 = 6N + 473 + 2/3, a reference frequency is considered as follows by dividing into an integral multiple of 1 and an integral multiple of 1/3.
[0081]
6N + 473 + 2/3 = (6N + K) + (473-K + 2/3)
= (6N + K) + (1421-3K) / 3
Here, K is an integer. From the first term on the right side, the first reference frequency is determined to be 1 MHz. Also, the second term on the right side is a fixed frequency synthesized by the mixer 46, and the second reference frequency is an integral fraction of (1421-3K) / 3 MHz.
[0082]
For the fixed frequency of the second term, K is determined by performing the following three evaluations.
(1) Increase the second reference frequency as much as possible.
(2) The second reference frequency is set to a value that can be generated by a signal from the crystal oscillator 41 that is the same as the first reference frequency.
(3) (1421-3K) / 3 so that the low-frequency filter 47 can sufficiently remove unnecessary high-frequency components out of the low-frequency components and the high-frequency components generated by the mixer 46. Increase
[0083]
K = 7 satisfies the above conditions. In this case, (1421-3K) / 3 = 1400/3 = 2 ³ × 5 ² Since x 7/3, the second reference frequency is 2 ³ / 3 = 8/3 MHz.
[0084]
In the frequency synthesizer configured as described above, the frequency control of the output signal is performed as follows. When the phase of the frequency-divided signal from the variable frequency divider 48 is ahead of the phase of the first reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 45 is lowered. On the other hand, when the phase of the frequency-divided signal from the variable frequency divider 48 is delayed from the phase of the first reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 45 becomes higher. As a result, the phases of the first reference frequency signal and the frequency-divided signal match, and the frequencies of the first reference frequency signal and the frequency-divided signal match. Therefore, the output signal of the frequency synthesizer is (6N + 7) + 1400/3 = 6N + 473 + 1/7 + 33/63 MHz by synthesizing the frequencies of the first and second phase locked loops 54 and 55.
[0085]
As described above, the frequency synthesizer according to the present embodiment provides an output signal of 6N + 473 + 1/7 + 32/63 + 1/63 MHz = 6N + 473 + 1/7 + 33/63 MHz by providing a predetermined oscillation frequency of 6N + 473 + 1/7 + 32/63 MHz with a 1/63 MHz offset. Is getting the frequency of The frequency synthesizer obtains the above frequency by synthesizing the frequencies generated by the first and second phase locked loops 54 and 55.
[0086]
Thereby, the first reference frequency can be set high to 1 MHz, and the second reference frequency can also be set high to 8/3 MHz. This results in a second phase having a single phase-locked loop. 2 of Reference example An output frequency higher than that of the frequency synthesizer can be obtained. Therefore, the upper limit of the loop band is increased to about 1/10 MHz (about 100 kHz), so that phase noise can be easily suppressed. The second 1 As with the frequency synthesizer of the embodiment, by having the first and second phase locked loops 54 and 55, the combination of the frequencies to be generated is appropriately set so that the reference frequency of any phase locked loop is increased. can do.
[0087]
The variable frequency divider 48 has a first 1 In the frequency synthesizer of this embodiment, the frequency division ratio is smaller than that of the variable frequency divider 18 realized by a 10-bit counter, so that it is realized by a 9-bit counter. Thereby, compared with the variable frequency divider 18, the circuit scale of the variable frequency divider 48 can be reduced and the power consumption can be reduced. In addition, since the frequency division ratio is small, the frequency of the phase comparator 43 performing phase comparison with respect to the oscillation frequency is increased, so that phase noise is less likely to occur.
[0088]
[No. 3 Embodiment of
FIG. 3 1 shows a configuration of a mixer-type frequency synthesizer according to the embodiment.
[0089]
This frequency synthesizer includes a crystal oscillator 61, a fixed frequency divider 62, a phase comparator 63, a loop filter 64, a voltage controlled oscillator 65, a mixer 66, a low pass filter 67, a variable frequency divider 68, a fixed frequency divider 69, and a phase comparison. 70, a loop filter 71, a voltage controlled oscillator 72, and a variable frequency divider 73. In the present frequency synthesizer, a first phase locked loop 74 is formed by the phase comparator 63, the loop filter 64, the voltage controlled oscillator 65, the mixer 66, the low pass filter 67 and the variable frequency divider 68. In this frequency synthesizer, the phase comparator 70, the loop filter 71, the voltage controlled oscillator 72, and the variable frequency divider 73 form a second phase locked loop 75.
[0090]
The crystal oscillator 61 generates a signal having a predetermined frequency, for example, 48 MHz. The fixed divider 62 divides the 48 MHz signal by a fixed division ratio 16 and outputs a 1/16 3 MHz signal as a first reference frequency signal.
[0091]
The phase comparator 63 detects the phase difference between the input first reference frequency signal and the frequency-divided signal from the variable frequency divider 68, and outputs the phase difference as a voltage or current pulse-like phase difference signal. To do. The loop filter 64 integrates the phase difference signal in order to remove unnecessary components included in the phase difference signal output from the phase comparator 63 and determine the overall response characteristic of the first phase locked loop 74. Then, the control voltage applied to the voltage controlled oscillator 65 is output. The voltage controlled oscillator 65 generates an output signal having a frequency corresponding to the control voltage from the loop filter 64.
[0092]
The mixer 66 synthesizes the frequency of the output signal of the voltage controlled oscillator 65 and the frequency of the fixed frequency signal from the voltage controlled oscillator 72 described later. The low pass filter 67 removes unnecessary high frequency components in the synthesized frequency signal from the mixer 66. The variable frequency divider 68 divides the synthesized frequency signal from the low-pass filter 67 into 1 / (2N + 5) by a variable frequency dividing ratio 2N + 5 (N is an integer from 0 to 49), and divides the frequency division result. The signal is output to the phase comparator 63 as a signal. Since the variable frequency divider 68 divides the frequency by a variable frequency dividing ratio 2N + 5, the variable frequency divider 68 is constituted by a programmable counter such as a pulse swallow counter as in the above-described variable frequency divider 6 (see FIG. 1). For example, the frequency dividing ratio of the variable frequency divider 68 is 5 to 103, and is realized by a 7-bit counter.
[0093]
The fixed frequency divider 69 divides the 48 MHz signal generated by the crystal oscillator 61 by a fixed frequency dividing ratio of 9, and outputs a 1/9 16/3 MHz signal as a second reference frequency signal. The phase comparator 70 detects the phase difference between the input second reference frequency signal and the frequency-divided signal from the fixed frequency divider 73, and outputs the phase difference as a voltage or current pulse-like phase difference signal. To do. The loop filter 71 integrates the phase difference signal in order to remove unnecessary components included in the phase difference signal output from the phase comparator 70 and determine the overall response characteristic of the second phase locked loop 75. As a result, the control voltage applied to the voltage controlled oscillator 72 is output.
[0094]
The voltage controlled oscillator 72 generates a fixed frequency signal having a frequency corresponding to the control voltage from the loop filter 71, that is, 1376/3 MHz. The fixed frequency divider 73 divides the output signal from the voltage controlled oscillator 72 by 1/86 by a fixed frequency division ratio 86 and outputs the frequency division result to the phase comparator 70 as a frequency division signal.
[0095]
Here, a method for setting the first and second reference frequencies will be described.
[0096]
In this frequency synthesizer, 1 Or second 2 The first reference frequency is raised by raising the oscillation frequency of the crystal oscillator 61 to 48 MHz as compared with the frequency synthesizer of the embodiment. That is, with respect to 6N + 473 + 1/7 + 33/63 = 6N + 473 + 2/3, the reference frequency is considered as follows by dividing into an integral multiple of 3 and an integral multiple of 1/3.
[0097]
6N + 473 + 2/3 = 3 (2N + K) + (473-3K + 2/3)
= 3 (2N + K) + (1421-9K) / 3
Here, K is an integer. From the first term on the right side, the first reference frequency is determined to be 3 MHz. The second term on the right side is a fixed frequency synthesized by the mixer 66, and the second reference frequency is an integral fraction of (1421-9K) / 3 MHz.
[0098]
For the fixed frequency of the second term, K is determined by performing the following three evaluations.
(1) Increase the second reference frequency as much as possible.
(2) The second reference frequency is set to a value that can be generated by the same signal from the crystal oscillator 61 as the first reference frequency.
(3) (1421-9K) / 3 so that the low-frequency filter 67 can sufficiently remove unnecessary high-frequency components out of the low-frequency components and the high-frequency components generated by the mixer 66. Increase
[0099]
The condition that satisfies the above condition is K = 5. In this case, (1421-9K) / 3 = 1376/3 = 2 ⁵ Since × 43/3, the second reference frequency is 2 ⁴ / 3 = 16/3 MHz.
[0100]
In the frequency synthesizer configured as described above, the frequency control of the output signal is performed as follows. When the phase of the frequency-divided signal from the variable frequency divider 68 is ahead of the phase of the first reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 65 is lowered. On the other hand, when the phase of the frequency-divided signal from the variable frequency divider 68 is delayed from the phase of the first reference frequency signal, the control voltage is controlled so that the oscillation frequency of the voltage-controlled oscillator 65 becomes higher. As a result, the phases of the first reference frequency signal and the frequency-divided signal match, and the frequencies of the first reference frequency signal and the frequency-divided signal match. Therefore, the output signal of the frequency synthesizer is 3 × (2N + 5) + 1376/3 = 6N + 473 + 1/7 + 33/63 MHz by synthesizing the frequencies of the first and second phase locked loops 74 and 75.
[0101]
As described above, the frequency synthesizer according to the present embodiment provides an output signal of 6N + 473 + 1/7 + 32/63 + 1/63 MHz = 6N + 473 + 1/7 + 33/63 MHz by providing a predetermined oscillation frequency of 6N + 473 + 1/7 + 32/63 MHz with a 1/63 MHz offset. Is getting the frequency of The frequency synthesizer obtains the above frequency by synthesizing the frequencies generated by the first and second phase locked loops 74 and 75.
[0102]
Thereby, the first reference frequency can be set high to 3 MHz, and the second reference frequency can also be set high to 16/3 MHz. As a result, 2 An output frequency higher than that of the frequency synthesizer of the embodiment can be obtained. Therefore, since the upper limit of the loop band is increased to about 3/10 MHz (about 300 kHz), the phase noise can be easily suppressed. The second 1 Similar to the frequency synthesizer of the embodiment, by having the first and second phase locked loops 74 and 75, the combination of the generated frequencies is appropriately set so that the reference frequency of any phase locked loop is increased. can do.
[0103]
The variable frequency divider 68 includes a first 2 In the frequency synthesizer of this embodiment, since the frequency division ratio is smaller than that of the variable frequency divider 48 realized by a 9-bit counter, the frequency synthesizer is realized by a 7-bit counter. Thereby, compared with the variable frequency divider 48, the circuit scale of the variable frequency divider 68 can be reduced and the power consumption can be reduced. Further, since the frequency division ratio is small, the frequency of phase comparison in the phase comparator 63 with respect to the oscillation frequency is increased, so that phase noise is less likely to occur.
[0104]
The first 1 The second 2 And second 3 In the frequency synthesizer of the embodiment, a fixed frequency to be synthesized with the output frequency by the mixer is generated in the second phase-locked loop, but the present invention is not limited to this. For example, even if the configuration includes another circuit for generating a fixed frequency, the first reference frequency can be increased. As another circuit, for example, apart from the crystal oscillator 11 shown in FIG. 2, a crystal oscillator that directly generates a fixed frequency can be cited. In such a configuration, the circuit after the fixed frequency divider 19 becomes unnecessary.
[0105]
However, by generating a fixed frequency in the phase locked loop, two different frequencies can be generated by a common crystal oscillator. Thereby, the number of parts can be reduced, and the fixed frequency can be easily increased as described above.
[0106]
Further, when a fixed frequency higher than that obtained by a crystal oscillator is required, a phase locked loop is generally used. First 1 The second 2 And second 3 If the value of K used in the description of the fixed frequency setting in the embodiment is increased, the fixed frequency becomes a value that can be generated by a crystal oscillator. In this case, an unnecessary frequency component is removed by a low-pass filter. There is an inconvenience that it becomes difficult to remove.
[0107]
[No. 4 Embodiment of
FIG. 6 shows the first Reference example Or second 1 2 shows a configuration of a tuner including the frequency synthesizer of the embodiment as a component.
[0108]
The tuner includes an RF filter 81, an RF amplifier 82, a mixer 83, a frequency synthesizer 84, an image removal filter 85, an IF filter 86, and an IF amplifier 87.
[0109]
The RF filter 81 removes unnecessary components from the RF input, and passes only components that need to be subjected to subsequent processing. The RF amplifier 82 is a circuit that amplifies the signal from the RF filter 81 with a gain controlled based on a control signal (RF AGC signal). The mixer 83 mixes the local oscillation signal generated by the frequency synthesizer 84 and the signal passed through the RF amplifier 82. In the mixer 83, the frequency of the RF input from the RF amplifier 82 is multiplied by the local oscillation frequency of the frequency synthesizer 84.
[0110]
The frequency synthesizer 84 is the first synthesizer described above. Reference example Or second 1 And generates a signal having a local oscillation frequency of 6N + 473 + 1/7 + 1/2 MHz corresponding to a designated channel 13 + N (N is an integer from 0 to 49). The image removal filter 85 removes unnecessary image components from the frequency of the signal input from the mixer 83. The IF filter 86 further removes unnecessary frequency components from the signal input from the image removal filter 85. The IF amplifier 87 amplifies the signal that has passed through the IF filter 86 with a gain controlled based on the control signal (IF AGC signal).
[0111]
In the tuner configured as described above, the local oscillation frequency of 6N + 473 + 1/7 + 1/2 MHz generated by the frequency synthesizer 84 is multiplied by the input frequency, and after processing by the image removal filter 85 and IF filter 86, the IF amplifier 87 The frequency of the IF output obtained is ½ MHz. This intermediate frequency has an offset frequency fo of −1/126 MHz with respect to a predetermined intermediate frequency of 32/63 MHz of terrestrial digital television broadcasting.
[0112]
[No. 5 Embodiment of
FIG. Reference example of 2 The second 2 Or second 3 2 shows a configuration of a tuner including the frequency synthesizer of the embodiment as a component.
[0113]
The tuner includes an RF filter 91, an RF amplifier 92, a mixer 93, a frequency synthesizer 94, an image removal filter 95, an IF filter 96, and an IF amplifier 97.
[0114]
The RF filter 91 removes unnecessary components from the RF input and allows only components that need to be subjected to subsequent processing to pass therethrough. The RF amplifier 92 is a circuit that amplifies the signal from the RF filter 91 with a gain controlled based on a control signal (RF AGC signal). The mixer 93 mixes the local oscillation signal generated by the frequency synthesizer 94 and the signal passed through the RF amplifier 92. In the mixer 93, the frequency of the RF input from the RF amplifier 92 is multiplied by the local oscillation frequency of the frequency synthesizer 94.
[0115]
The frequency synthesizer 94 is Reference example of 2 The second 2 Or second 3 And generates a signal having a local oscillation frequency of 6N + 473 + 1/7 + 33/63 MHz corresponding to a designated channel 13 + N (N is an integer from 0 to 49). The image removal filter 95 removes unnecessary image components from the frequency of the signal input from the mixer 93. The IF filter 96 further removes unnecessary frequency components from the signal input from the image removal filter 95. The IF amplifier 97 amplifies the signal that has passed through the IF filter 96 with a gain controlled based on the control signal (IF AGC signal).
[0116]
In the tuner configured as described above, the local oscillation frequency of 6N + 473 + 1/7 + 33/63 MHz generated by the frequency synthesizer 94 is multiplied by the input frequency, and after processing by the image removal filter 95 and IF filter 96, the IF amplifier 97 The frequency of the obtained IF output is 33/63 MHz. This intermediate frequency has an offset frequency fo of 1/63 MHz with respect to a predetermined intermediate frequency 32/63 MHz of terrestrial digital television broadcasting.
[0117]
As mentioned above First reference example, second reference example, first to fifth In this embodiment, the default oscillation frequency of the frequency synthesizer is 6N + 473 + 1/7 + 32/63 MHz (N is an integer from 0 to 49), but is not limited thereto. For example, the predetermined oscillation frequency may be 6M + 473 + 1 / 7-32 / 63 MHz (N is an integer from 0 to 49), and the same effect can be obtained by this predetermined oscillation frequency. In addition, the predetermined intermediate frequency is 32/63 MHz, but the same effect can be obtained even if 64/63 MHz and 128/63 MHz are 256/63 MHz.
[0118]
[No. 6 Embodiment of
FIG. 4 Or second 5 2 shows a configuration of a receiver including the tuner according to the embodiment as a constituent element.
[0119]
The receiver includes an antenna 101, a tuner 102, an automatic frequency controller (AFC (Automatic Frequency Control) in the figure) 103, and an OFDM (Orthogonal Frequency Division Multiplex) demodulator 104.
[0120]
The tuner 102 is the first one described above. 4 Or second 5 It is comprised by the tuner of embodiment. The tuner 102 selects a signal of a designated channel 13 + N (N is an integer from 0 to 49) from the RF input for UHF band digital terrestrial television received by the antenna 101, and converts the selected signal to IF output. Convert. As described above, the IF output frequency is obtained by adding the offset frequency fo to 32/63 MHz, which is a predetermined intermediate frequency of digital terrestrial television broadcasting. This offset frequency fo is the first frequency synthesizer in the tuner 102. Reference example Or second 1 In the case of the frequency synthesizer of the embodiment, −1/126 MHz, and the frequency synthesizer in the tuner 102 is the first Reference example of 2 The second 2 Or second 3 In the case of the frequency synthesizer of the embodiment, the frequency is 1/63 MHz.
[0121]
The automatic frequency controller 103 controls the frequency so that the intermediate frequency is correctly 32/63 MHz. The automatic frequency controller 103 adjusts the intermediate frequency to 32/63 MHz using a phase locked loop or the like if the inputted intermediate frequency is within the range of the pull-in frequency. For example, in the case of the automatic frequency controller 103 having a pull-in frequency of about ± 60 KHz, the offset frequency fo of 1/126 MHz = 7.9 KHz or 1/63 MHz = 15.9 KHz is absorbed by the above adjustment operation.
[0122]
If the offset frequency fo is simply removed, the offset frequency fo can be stored in the memory and the offset can be removed from the inputted intermediate frequency. However, such a configuration requires a memory and a circuit for controlling the memory. In addition, since the local oscillation frequency in the frequency synthesizer varies depending on the ambient temperature and changes with time, it is necessary to absorb such variations. Therefore, the automatic frequency controller 103 is required to satisfy such a requirement.
[0123]
The OFDM demodulator 104 demodulates the IF output from the automatic frequency controller 103 and outputs a TS (Transport Stream) output that is a multiplexed format signal of terrestrial digital television broadcasting.
[0124]
In the receiver configured as described above, the automatic frequency controller 103 adjusts the input frequency so as to be a predetermined intermediate frequency. As a result, even if the offset frequency fo is included in the intermediate frequency from the tuner 102, 32/63 MHz which is a predetermined intermediate frequency is obtained, so that the OFDM demodulator 104 can perform normal demodulation.
[0125]
In the above configuration, the adjustment of the intermediate frequency is performed by the automatic frequency controller 102, but this adjustment may be performed by the OFDM demodulator 104.
[0126]
【The invention's effect】
As described above, the frequency synthesizer of the present invention includes a phase-locked loop that controls the first reference frequency and an integer frequency of the output frequency to match, Also equipped with a crystal oscillator that generates a reference signal of a predetermined frequency, The first reference frequency is a frequency synthesizer The output frequency And a sub-phase locked loop that outputs a fixed frequency signal having a fixed frequency based on the second reference frequency, and is set in the phase locked loop to A mixing unit that mixes an output frequency and the fixed frequency, and the phase-locked loop includes: Predetermined frequency of reference signal Having a first fixed frequency divider that generates the first reference frequency by dividing the frequency by a fixed division ratio, and the sub-phase locked loop includes: Predetermined frequency of reference signal Is divided by a fixed frequency dividing ratio, and has a second fixed frequency divider that generates the second reference frequency.
[0127]
Thereby, the numerical value of the denominator of the oscillation frequency (output frequency) can be reduced. Therefore, the upper limit of the loop band of the phase locked loop is also increased according to the reference frequency (about 1/10 of the reference frequency). Therefore, phase noise can be easily suppressed. Further, by increasing the reference frequency, the frequency division ratio for dividing the oscillation frequency according to the number of channels can be reduced. Therefore, the circuit scale and power consumption of the frequency divider used for the frequency division can be reduced.
[0128]
The frequency synthesizer includes a sub-phase locked loop that outputs a fixed frequency, and a mixing unit that mixes the output frequency and the fixed frequency in the phase-locked loop. Since the fixed frequency and the output frequency output from the phase locked loop are mixed by the mixing unit, the reference frequency can be further increased as compared with the frequency synthesizer having a single phase locked loop.
[0129]
In addition, the tuner of the present invention includes the frequency synthesizer having the above-described configuration, so that it is possible to provide a tuner with little phase noise, small circuit scale, and low power consumption.
[0130]
The receiver according to the present invention includes the tuner and an offset removing unit that removes the offset from an intermediate frequency output from the tuner. Thereby, since the offset contained in the intermediate frequency is removed, a predetermined intermediate frequency can be obtained. Therefore, the intermediate frequency can be normally amplified.
[Brief description of the drawings]
FIG. 1 shows the first of the present invention. Reference example It is a block diagram which shows the structure of the direct frequency division type frequency synthesizer concerning.
FIG. 2 shows the first of the present invention. 1 It is a block diagram which shows the structure of the mixer type frequency synthesizer which concerns on this embodiment.
FIG. 3 shows the first aspect of the present invention. 2 of Reference example It is a block diagram which shows the structure of the direct frequency division type frequency synthesizer concerning.
FIG. 4 shows the first aspect of the present invention. 2 It is a block diagram which shows the structure of the mixer type frequency synthesizer which concerns on this embodiment.
FIG. 5 shows the first of the present invention. 3 It is a block diagram which shows the structure of the mixer type frequency synthesizer which concerns on this embodiment.
FIG. 6 shows the first of the present invention. 4 It is a block diagram which shows the structure of the tuner which concerns on this embodiment.
FIG. 7 shows the first of the present invention. 5 It is a block diagram which shows the structure of the tuner which concerns on this embodiment.
FIG. 8 shows the first of the present invention. 6 It is a block diagram which shows the structure of the receiver which concerns on this embodiment.
FIG. 9 is a diagram showing a frequency configuration used in digital terrestrial television broadcasting.
[Explanation of symbols]
1,11,31,41,61 crystal oscillator
2,12,19,32,42,49,62,69 Fixed frequency divider
7,37 Phase-locked loop
24, 54, 74 First phase locked loop (phase locked loop)
25, 55, 75 Second phase locked loop (sub-phase locked loop)
84,94 frequency synthesizer
102 Tuner
103 Automatic frequency controller (offset removal unit)

Claims (8)

In a frequency synthesizer including a phase locked loop that controls a first reference frequency and a frequency that is a fraction of an output frequency to coincide with each other,
A crystal oscillator that generates a reference signal of a predetermined frequency;
The first reference frequency is set to be an integer fraction of a frequency obtained by offsetting the output frequency of the frequency synthesizer by a predetermined frequency;
A sub-phase locked loop that outputs a fixed frequency signal having a fixed frequency based on a second reference frequency;
A mixing unit for mixing the output frequency and the fixed frequency in the phase-locked loop;
The phase-locked loop includes a first fixed frequency divider that generates the first reference frequency by dividing a predetermined frequency of the reference signal by a fixed division ratio;
The sub-phase locked loop includes a second fixed frequency divider that generates the second reference frequency by dividing the predetermined frequency of the reference signal by a fixed division ratio. Frequency synthesizer to play.   The frequency synthesizer according to claim 1, wherein the offset is 1/126 MHz, the reference frequency of the phase-locked loop is 1/2 MHz, and the reference frequency of the sub-phase-locked loop is 8/7 MHz. .   2. The frequency synthesizer according to claim 1, wherein the offset is 1/63 MHz, the reference frequency of the phase-locked loop is 1 MHz, and the reference frequency of the sub-phase-locked loop is 8/3 MHz.   The frequency synthesizer according to claim 1, wherein the offset is 1/63 MHz, the reference frequency of the phase-locked loop is 3 MHz, and the reference frequency of the sub-phase-locked loop is 16/3 MHz.   A tuner comprising the frequency synthesizer according to any one of claims 1 to 4.   6. The tuner according to claim 5, wherein an intermediate frequency of 1/2 MHz is output.   6. The tuner according to claim 5, wherein an intermediate frequency of 33/63 MHz is output. A tuner according to claim 5;
A receiver comprising: an offset removing unit that removes the offset from an intermediate frequency output from the tuner.

Images