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JP4134770B2 - Semiconductor device and manufacturing method thereof - Google Patents
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JP4134770B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP4134770B2
JP4134770B2 JP2003071688A JP2003071688A JP4134770B2 JP 4134770 B2 JP4134770 B2 JP 4134770B2 JP 2003071688 A JP2003071688 A JP 2003071688A JP 2003071688 A JP2003071688 A JP 2003071688A JP 4134770 B2 JP4134770 B2 JP 4134770B2
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JP
Japan
Prior art keywords
rewiring
metal layer
film
base metal
columnar electrode
Prior art date
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Expired - Fee Related
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JP2003071688A
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Japanese (ja)
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JP2004281744A (en
Inventor
一能 新井
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は、再配線および柱状電極を有する半導体装置およびその製造方法に関する。
【0002】
【従来の技術】
従来の半導体装置には、CSP(chip size package)と呼ばれるもので、半導体基板上に銅からなる再配線が設けられ、再配線の接続パッド部上に銅からなる柱状電極が設けられたものがある(例えば、特許文献1参照)。
【0003】
【特許文献1】
特開平5−218042号公報
【0004】
【発明が解決しようとする課題】
ところで、上記従来の半導体装置では、再配線を含む半導体基板上の柱状電極間に封止膜が設けられていても、使用環境中の水分が封止膜に浸透すると、プラス電圧が印加されている柱状電極から溶け出した銅イオンが移動してマイナス電圧が印加されている柱状電極に析出し、いわゆるイオンマイグレーションによるショートが発生することがあるという問題があった。
そこで、この発明は、いわゆるイオンマイグレーションによるショートが発生しにくいようにすることができる半導体装置およびその製造方法を提供することを目的とする。
【0005】
【課題を解決するための手段】
請求項1に記載の発明は、半導体基板上に設けられた下地金属層と、該下地金属層上に設けられた再配線と、該再配線の接続パッド部上に設けられた、前記再配線と同材料の柱状電極と、前記柱状電極の外周面および前記再配線の少なくとも上面に設けられた陽極酸化膜とを備えていることを特徴とするものである。
請求項2に記載の発明は、請求項1に記載の発明において、前記再配線を含む前記半導体基板上の前記柱状電極間に封止膜が設けられていることを特徴とするものである。
請求項3に記載の発明は、半導体基板の一面上に下地金属層を形成する工程と、前記下地金属層をメッキ電流路として前記下地金属層上に再配線を形成する工程と、前記下地金属層をメッキ電流路として前記再配線の接続パッド部上に、前記再配線と同材料の柱状電極を形成する工程と、前記下地金属層を一方の電極として前記柱状電極および前記再配線に陽極酸化膜を形成する工程とを有することを特徴とするものである。
請求項4に記載の発明は、請求項3に記載の発明において、前記陽極酸化膜を含む前記半導体基板上に封止膜を形成する工程と、前記柱状電極の上面の前記陽極酸化膜を除去して前記柱状電極の上面を露出させる工程とを有することを特徴とするものである。
そして、この発明によれば、柱状電極の外周面および前記再配線の少なくとも上面に陽極酸化膜を設けているので、いわゆるイオンマイグレーションによるショートが発生しにくいようにすることができる。
【0006】
【発明の実施の形態】
図1はこの発明の一実施形態としての半導体装置の断面図を示したものである。この半導体装置はシリコン基板(半導体基板)1を備えている。シリコン基板1の上面中央部には集積回路(図示せず)が設けられ、上面周辺部にはアルミニウム系金属からなる複数の接続パッド2が集積回路に接続されて設けられている。
【0007】
接続パッド2の中央部を除くシリコン基板1の上面には酸化シリコンや窒化シリコンなどからなる絶縁膜3およびポリイミドやベンゾシクロブテン(BCB)などからなる保護膜(絶縁膜)4が設けられている。接続パッド2の中央部は、絶縁膜3および保護膜4に設けられた開口部5を介して露出されている。
【0008】
開口部5を介して露出された接続パッド2の上面から保護膜4の上面の所定の箇所にかけて下地金属層6が設けられている。下地金属層6の上面には銅からなる再配線7が設けられている。再配線7の接続パッド部上面には銅からなる柱状電極8が設けられている。再配線7の上面および柱状電極8の外周面には陽極酸化膜9が設けられている。
【0009】
再配線7上の陽極酸化膜9を含む保護膜4の上面にはエポキシ系樹脂などからなる封止膜10がその上面が柱状電極8およびその外周面の陽極酸化膜9の上面と面一となるように設けられている。従って、柱状電極8およびその外周面の陽極酸化膜9の上面は露出されている。この露出された柱状電極8およびその外周面の陽極酸化膜9の上面には半田ボール11が設けられている。
【0010】
次に、この半導体装置の製造方法の一例について説明する。まず、図2に示すように、ウエハ状態のシリコン基板1の上面にアルミニウム系金属からなる接続パッド2が形成され、その上面の接続パッド2の中央部を除く領域に酸化シリコンなどからなる絶縁膜3およびポリイミドなどからなる保護膜4が形成され、接続パッド2の中央部が絶縁膜3および保護膜4に形成された開口部5を介して露出されたものを用意する。
【0011】
次に、図3に示すように、開口部5をを介して露出された接続パッド2の上面を含む保護膜4の上面に下地金属層6を形成する。この場合、下地金属層6は、詳細には図示していないが、スパッタにより形成されたチタン層上にスパッタにより銅層を形成したものである。なお、下地金属層6は、無電解メッキにより形成された銅層のみであってもよい。
【0012】
次に、下地金属層6の上面に第1のメッキレジスト膜21をパターン形成する。この場合、再配線7形成領域に対応する領域における第1のメッキレジスト膜21には開口部22が形成されている。次に、下地金属層6をメッキ電流路として銅の電解メッキを行うことにより、第1のメッキレジスト膜21の開口部22内における下地金属層6の上面に再配線7を形成する。次に、第1のメッキレジスト膜21を剥離する。
【0013】
次に、図4に示すように、再配線7を含む下地金属層6の上面に第2のメッキレジスト膜23をパターン形成する。この場合、再配線7の接続パッド部に対応する領域における第2のメッキレジスト膜23には開口部24が形成されている。次に、下地金属層6をメッキ電流路として銅の電解メッキを行うことにより、第2のメッキレジスト膜23の開口部24内における再配線7の接続パッド部上面に柱状電極8を形成する。次に、第2のメッキレジスト膜23を剥離する。
【0014】
次に、図5に示すように、再配線7によって覆われずに露出された下地金属層6の上面に陽極酸化用レジスト膜25をパターン形成する。次に、下地金属層6をプラス電極とし、白金電極(図示せず)をマイナス電極とし、陽極酸化用電解液として0.01WT%クエン酸水溶液を用いて陽極酸化を行なうと、柱状電極8の表面および再配線7の上面と側面に陽極酸化膜9が形成される。
【0015】
次に、陽極酸化用レジスト膜25を剥離し、次いで陽極酸化膜9をマスクとして下地金属層6の不要な部分をエッチングして除去すると、図6に示すように、再配線7下にのみ下地金属層6が残存される。次に、図7に示すように、陽極酸化膜9を含む保護膜4の上面にエポキシ系樹脂などからなる封止膜10をその厚さが柱状電極8の高さよりもやや厚くなるように形成する。従って、この状態では、柱状電極8上の陽極酸化膜9の上面は封止膜10によって覆われている。
【0016】
次に、封止膜10の上面側および少なくとも柱状電極8上の陽極酸化膜9を研磨して除去することにより、図8に示すように、柱状電極8およびその外周面の陽極酸化膜9の上面を露出させるとともに、この露出された柱状電極8およびその外周面の陽極酸化膜9の上面を封止膜10の上面とほぼ面一とする。次に、図9に示すように、柱状電極8およびその外周面の陽極酸化膜9の上面に半田ボール11を形成する。次に、図10に示すように、ダイシング工程を経ると、図1に示す半導体装置が複数個得られる。
【0017】
このようにして得られた半導体装置では、柱状電極8の外周面および再配線7の上面の陽極酸化膜9により、柱状電極8の外周面および再配線7の上面でのマイグレーションの発生を抑制することができ、従っていわゆるイオンマイグレーションによるショートが発生しにくいようにすることができる。また、エポキシ系樹脂などからなる封止膜10の陽極酸化膜9に対する密着性が銅層のみの場合と比較して良くなり、従って封止膜10が柱状電極8の外周面および再配線7の上面から剥離しにくいようにすることができる。
【0018】
なお、図3に図示する第1のメッキレジスト膜21の開口部22内における下地金属層6の上面に再配線7を形成した後、第1のメッキレジスト膜21を剥離せず残存したまま、開口部24を有する第2のメッキレジスト膜23をパターン形成し、下地金属層6をメッキ電流路とする電解メッキを行うことにより、第2のメッキレジスト膜23の開口部24内に柱状電極8を形成し、この後、第2のメッキレジスト膜23を剥離して再配線7の上面および柱状電極8の表面に陽極酸化膜9を形成するようにしてもよい。
【0019】
この製造方法によっても、図5に図示する状態となり(但し、図5における陽極酸化用レジスト膜25は第1のメッキレジスト膜21に置き換えるものとする)、この後は、前述と同じ工程を経ればよいので、フォトリソグラフィ工程を1つ低減することが可能となる。上記製造方法において、第1のメッキレジスト膜21をポジ型、第2のメッキレジスト膜23をネガ型とすると、、第2のメッキレジスト膜23のエッチング液で第1のメッキレジスト膜21がエッチングされないので、作業を一層確実なものとすることができる。
【0020】
また、上記実施形態では、再配線は1層であったが、再配線は多層としてもよく、その場合、陽極酸化膜は、柱状電極が形成される再配線のみでなく、必要に応じ、各層の再配線に形成してもよい。
【0021】
【発明の効果】
以上説明したように、この発明によれば、柱状電極の外周面および前記再配線の少なくとも上面に陽極酸化膜を設けているので、いわゆるイオンマイグレーションによるショートが発生しにくいようにすることができる。
【図面の簡単な説明】
【図1】この発明の一実施形態としての半導体装置の断面図。
【図2】図1に示す半導体装置の製造に際し、当初の製造工程の断面図。
【図3】図2に続く製造工程の断面図。
【図4】図3に続く製造工程の断面図。
【図5】図4に続く製造工程の断面図。
【図6】図5に続く製造工程の断面図。
【図7】図6に続く製造工程の断面図。
【図8】図7に続く製造工程の断面図。
【図9】図8に続く製造工程の断面図。
【図10】図9に続く製造工程の断面図。
【符号の説明】
1 シリコン基板
2 接続パッド
3 絶縁膜
4 保護膜
5 開口部
6 下地金属層
7 再配線
8 柱状電極
9 陽極酸化膜
10 封止膜
11 半田ボール
21 第1のメッキレジスト膜
23 第2のメッキレジスト膜
25 陽極酸化用レジスト膜
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having rewiring and columnar electrodes, and a method for manufacturing the same.
[0002]
[Prior art]
A conventional semiconductor device is called a CSP (chip size package), in which a rewiring made of copper is provided on a semiconductor substrate, and a columnar electrode made of copper is provided on a connection pad portion of the rewiring. Yes (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 5-218042
[Problems to be solved by the invention]
By the way, in the conventional semiconductor device, even if the sealing film is provided between the columnar electrodes on the semiconductor substrate including the rewiring, a positive voltage is applied when moisture in the use environment penetrates the sealing film. There is a problem in that the copper ions dissolved from the columnar electrodes that have moved move and deposit on the columnar electrodes to which a negative voltage is applied, so that a short circuit may occur due to so-called ion migration.
In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent a short circuit due to so-called ion migration.
[0005]
[Means for Solving the Problems]
The invention according to claim 1 is the rewiring provided on the base metal layer provided on the semiconductor substrate, the rewiring provided on the base metal layer, and the connection pad portion of the rewiring. And a anodic oxide film provided on at least the upper surface of the outer peripheral surface of the columnar electrode and the rewiring.
According to a second aspect of the present invention, in the first aspect of the present invention, a sealing film is provided between the columnar electrodes on the semiconductor substrate including the rewiring.
The invention described in claim 3 includes a step of forming a base metal layer on one surface of a semiconductor substrate, a step of forming a rewiring on the base metal layer using the base metal layer as a plating current path, and the base metal. Forming a columnar electrode of the same material as the rewiring on the connection pad portion of the rewiring using a layer as a plating current path, and anodizing the columnar electrode and the rewiring with the underlying metal layer as one electrode And a step of forming a film.
According to a fourth aspect of the present invention, in the third aspect of the present invention, the step of forming a sealing film on the semiconductor substrate including the anodic oxide film and the anodic oxide film on the upper surface of the columnar electrode are removed. And exposing the upper surface of the columnar electrode.
According to the present invention, since the anodic oxide film is provided on the outer peripheral surface of the columnar electrode and at least the upper surface of the rewiring, it is possible to prevent a short circuit due to so-called ion migration.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a cross-sectional view of a semiconductor device as an embodiment of the present invention. This semiconductor device includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) is provided at the center of the upper surface of the silicon substrate 1, and a plurality of connection pads 2 made of aluminum-based metal are provided connected to the integrated circuit at the periphery of the upper surface.
[0007]
An insulating film 3 made of silicon oxide, silicon nitride, or the like and a protective film (insulating film) 4 made of polyimide, benzocyclobutene (BCB), or the like are provided on the upper surface of the silicon substrate 1 excluding the central portion of the connection pad 2. . A central portion of the connection pad 2 is exposed through an opening 5 provided in the insulating film 3 and the protective film 4.
[0008]
A base metal layer 6 is provided from the upper surface of the connection pad 2 exposed through the opening 5 to a predetermined location on the upper surface of the protective film 4. A rewiring 7 made of copper is provided on the upper surface of the base metal layer 6. A columnar electrode 8 made of copper is provided on the upper surface of the connection pad portion of the rewiring 7. An anodic oxide film 9 is provided on the upper surface of the rewiring 7 and the outer peripheral surface of the columnar electrode 8.
[0009]
On the upper surface of the protective film 4 including the anodic oxide film 9 on the rewiring 7, the upper surface of the sealing film 10 made of epoxy resin is flush with the upper surface of the columnar electrode 8 and the anodic oxide film 9 on the outer peripheral surface thereof. It is provided to become. Therefore, the upper surfaces of the columnar electrode 8 and the anodic oxide film 9 on the outer peripheral surface thereof are exposed. Solder balls 11 are provided on the upper surfaces of the exposed columnar electrodes 8 and the anodic oxide film 9 on the outer peripheral surface thereof.
[0010]
Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a connection pad 2 made of an aluminum-based metal is formed on the upper surface of a silicon substrate 1 in a wafer state, and an insulating film made of silicon oxide or the like in a region excluding the central portion of the connection pad 2 on the upper surface. 3 and a protective film 4 made of polyimide or the like is formed, and the connection pad 2 is exposed through the opening 5 formed in the insulating film 3 and the protective film 4.
[0011]
Next, as shown in FIG. 3, a base metal layer 6 is formed on the upper surface of the protective film 4 including the upper surface of the connection pad 2 exposed through the opening 5. In this case, although not shown in detail, the base metal layer 6 is obtained by forming a copper layer by sputtering on a titanium layer formed by sputtering. Note that the base metal layer 6 may be only a copper layer formed by electroless plating.
[0012]
Next, the first plating resist film 21 is patterned on the upper surface of the base metal layer 6. In this case, an opening 22 is formed in the first plating resist film 21 in a region corresponding to the rewiring 7 formation region. Next, by performing electrolytic plating of copper using the base metal layer 6 as a plating current path, the rewiring 7 is formed on the upper surface of the base metal layer 6 in the opening 22 of the first plating resist film 21. Next, the first plating resist film 21 is peeled off.
[0013]
Next, as shown in FIG. 4, a second plating resist film 23 is patterned on the upper surface of the base metal layer 6 including the rewiring 7. In this case, an opening 24 is formed in the second plating resist film 23 in a region corresponding to the connection pad portion of the rewiring 7. Next, the columnar electrode 8 is formed on the upper surface of the connection pad portion of the rewiring 7 in the opening 24 of the second plating resist film 23 by performing copper electroplating using the base metal layer 6 as a plating current path. Next, the second plating resist film 23 is peeled off.
[0014]
Next, as shown in FIG. 5, an anodic oxidation resist film 25 is patterned on the upper surface of the underlying metal layer 6 exposed without being covered by the rewiring 7. Next, when the base metal layer 6 is a plus electrode, a platinum electrode (not shown) is a minus electrode, and anodization is performed using a 0.01 WT% aqueous citric acid solution as an anodizing electrolyte, the columnar electrode 8 An anodized film 9 is formed on the surface and the upper surface and side surfaces of the rewiring 7.
[0015]
Next, the resist film 25 for anodic oxidation is peeled off, and then unnecessary portions of the base metal layer 6 are removed by etching using the anodic oxide film 9 as a mask. As shown in FIG. The metal layer 6 remains. Next, as shown in FIG. 7, a sealing film 10 made of epoxy resin or the like is formed on the upper surface of the protective film 4 including the anodic oxide film 9 so that the thickness thereof is slightly larger than the height of the columnar electrode 8. To do. Therefore, in this state, the upper surface of the anodic oxide film 9 on the columnar electrode 8 is covered with the sealing film 10.
[0016]
Next, by polishing and removing the upper surface side of the sealing film 10 and at least the anodic oxide film 9 on the columnar electrode 8, as shown in FIG. 8, the columnar electrode 8 and the anodic oxide film 9 on the outer peripheral surface thereof are removed. The upper surface is exposed, and the exposed columnar electrode 8 and the upper surface of the anodic oxide film 9 on the outer peripheral surface thereof are substantially flush with the upper surface of the sealing film 10. Next, as shown in FIG. 9, solder balls 11 are formed on the upper surfaces of the columnar electrodes 8 and the anodic oxide film 9 on the outer peripheral surface thereof. Next, as shown in FIG. 10, after a dicing process, a plurality of semiconductor devices shown in FIG. 1 are obtained.
[0017]
In the semiconductor device thus obtained, the occurrence of migration on the outer peripheral surface of the columnar electrode 8 and the upper surface of the rewiring 7 is suppressed by the anodic oxide film 9 on the outer peripheral surface of the columnar electrode 8 and the upper surface of the rewiring 7. Therefore, a short circuit due to so-called ion migration is less likely to occur. Further, the adhesion of the sealing film 10 made of epoxy resin or the like to the anodic oxide film 9 is better than that of the copper layer alone, and therefore the sealing film 10 is formed on the outer peripheral surface of the columnar electrode 8 and the rewiring 7. It can be made difficult to peel from the upper surface.
[0018]
In addition, after forming the rewiring 7 on the upper surface of the base metal layer 6 in the opening 22 of the first plating resist film 21 illustrated in FIG. 3, the first plating resist film 21 remains without being peeled off. By patterning the second plating resist film 23 having the opening 24 and performing electrolytic plating using the base metal layer 6 as a plating current path, the columnar electrode 8 is formed in the opening 24 of the second plating resist film 23. Then, the second plating resist film 23 may be peeled off to form the anodic oxide film 9 on the upper surface of the rewiring 7 and the surface of the columnar electrode 8.
[0019]
This manufacturing method also results in the state shown in FIG. 5 (however, the anodic oxidation resist film 25 in FIG. 5 is replaced with the first plating resist film 21), and thereafter, the same process as described above is performed. Therefore, it is possible to reduce one photolithography process. In the above manufacturing method, if the first plating resist film 21 is a positive type and the second plating resist film 23 is a negative type, the first plating resist film 21 is etched by the etching solution of the second plating resist film 23. Since this is not done, the work can be made more reliable.
[0020]
In the above embodiment, the rewiring is one layer. However, the rewiring may be a multi-layer. In that case, the anodic oxide film is not limited to the rewiring on which the columnar electrodes are formed, but each layer as necessary. The rewiring may be formed.
[0021]
【The invention's effect】
As described above, according to the present invention, since the anodic oxide film is provided on the outer peripheral surface of the columnar electrode and at least the upper surface of the rewiring, it is possible to prevent a short circuit due to so-called ion migration.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device as one embodiment of the present invention.
FIG. 2 is a cross-sectional view of an initial manufacturing process in manufacturing the semiconductor device shown in FIG. 1;
FIG. 3 is a cross-sectional view of the manufacturing process following FIG. 2;
FIG. 4 is a cross-sectional view of the manufacturing process following FIG. 3;
FIG. 5 is a cross-sectional view of the manufacturing process following FIG. 4;
6 is a cross-sectional view of the manufacturing process following FIG. 5. FIG.
7 is a cross-sectional view of a manufacturing step that follows FIG. 6. FIG.
FIG. 8 is a cross-sectional view of the manufacturing process following FIG. 7;
FIG. 9 is a cross-sectional view of the manufacturing process following FIG. 8;
10 is a cross-sectional view of a manufacturing step that follows FIG. 9; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 4 Protective film 5 Opening 6 Base metal layer 7 Rewiring 8 Columnar electrode 9 Anodized film 10 Sealing film 11 Solder ball 21 First plating resist film 23 Second plating resist film 25 Anodizing resist film

Claims (4)

半導体基板上に設けられた下地金属層と、該下地金属層上に設けられた再配線と、該再配線の接続パッド部上に設けられた、前記再配線と同材料の柱状電極と、前記柱状電極の外周面および前記再配線の少なくとも上面に設けられた陽極酸化膜とを備えていることを特徴とする半導体装置。A base metal layer provided on a semiconductor substrate, a rewiring provided on the base metal layer, a columnar electrode of the same material as the rewiring provided on a connection pad portion of the rewiring, and A semiconductor device comprising: an outer peripheral surface of a columnar electrode; and an anodized film provided on at least an upper surface of the rewiring. 請求項1に記載の発明において、前記再配線を含む前記半導体基板上の前記柱状電極間に封止膜が設けられていることを特徴とする半導体装置。  2. The semiconductor device according to claim 1, wherein a sealing film is provided between the columnar electrodes on the semiconductor substrate including the rewiring. 半導体基板の一面上に下地金属層を形成する工程と、前記下地金属層をメッキ電流路として前記下地金属層上に再配線を形成する工程と、前記下地金属層をメッキ電流路として前記再配線の接続パッド部上に、前記再配線と同材料の柱状電極を形成する工程と、前記下地金属層を一方の電極として前記柱状電極および前記再配線に陽極酸化膜を形成する工程とを有することを特徴とする半導体装置の製造方法。Forming a base metal layer on one surface of the semiconductor substrate; forming a rewiring on the base metal layer using the base metal layer as a plating current path; and rewiring the base metal layer as a plating current path. on the connection pad portion, said to have a step of forming a columnar electrode redistribution same material, and forming the columnar electrode and the anodic oxide film to the rewiring of the underlying metal layer as one electrode A method for manufacturing a semiconductor device. 請求項3に記載の発明において、前記陽極酸化膜を含む前記半導体基板上に封止膜を形成する工程と、前記柱状電極の上面の前記陽極酸化膜を除去して前記柱状電極の上面を露出させる工程とを有することを特徴とする半導体装置の製造方法。  4. The method according to claim 3, wherein a sealing film is formed on the semiconductor substrate including the anodic oxide film, and the anodic oxide film on the upper surface of the columnar electrode is removed to expose the upper surface of the columnar electrode. A method of manufacturing a semiconductor device.
JP2003071688A 2003-03-17 2003-03-17 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4134770B2 (en)

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