JP4135533B2 - Tester device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a tester apparatus that outputs a calculated value based on data from an HDL memory to a device under measurement and inputs a response from the device under measurement.
[0002]
[Prior art]
A conventional tester device includes an HDL memory having a capacity equal to or greater than the total number of required patterns (for example, see Patent Document 1).
[0003]
[Patent Document 1]
JP 2000-276368 A [0004]
Such a conventional tester device will be described with reference to FIGS. FIG. 2A is a configuration diagram of a conventional tester device.
[0005]
The tester apparatus 10 ′ is formed by a program and an engineering work station EWS or the like as a terminal. The program is stored in a storage medium such as a hard disk in the engineering work station EWS.
[0006]
The tester device 10 ′ includes a file 1 ′, an HDL memory 2 ′, a calculation unit 3, and a sequencer 4. The file 1 ′, the HDL memory 2 ′, the calculation unit 3, and the sequencer 4 may be a program described in a hardware description language (HDL) or may be actual hardware.
[0007]
Furthermore, the device under test 5 may be a virtual device under test DUT program modeled by software, or may be actual hardware.
[0008]
Here, the case where the file 1 ′, the HDL memory 2 ′, the calculation unit 3, the sequencer 4, and the device under test 5 are programs are the same as the case where they are actual hardware. I will explain only.
In addition, when the HDL memory 2 ′ is actual hardware, the HDL memory is called a memory.
[0009]
When the file 1 ′, the HDL memory 2 ′, the calculation unit 3, the sequencer 4, and the device under measurement 5 are programs, the tester apparatus in FIG. 2 is mainly used for verification of the inspection program as a virtual tester.
[0010]
The file 1 ′, the HDL memory 2 ′, the calculation unit 3, the sequencer 4, and the device under measurement 5 are described in the hardware description language HDL.
However, the HDL memory 2 'is closely related to the actual hardware memory of the engineering work station EWS. Therefore, the capacity is limited.
[0011]
The file 1 ′ is formed by a storage block on the hardware description language HDL. The file 1 ′ stores test signal pattern data PD for the device under measurement 5.
[0012]
Further, the sequencer 4 sequentially outputs the execution address PA_C to the HDL memory 2 ′ during the test.
[0013]
The HDL memory 2 ′ is formed of storage blocks on the hardware description language HDL. The actual hardware memory of the engineering work station EWS is formed in the same manner. In addition, the HDL memory 2 ′ includes addresses whose addresses are serial numbers from address 0 to address 0xffffffff.
[0014]
Further, when the test is executed, all the pattern data PD of the file 1 ′ is downloaded to the HDL memory 2 ′. Data based on the execution address PA_C is validated.
[0015]
The calculation unit 3 performs calculation by inputting data that is valid in the HDL memory 2 ′, and outputs the calculated value to the device under measurement 5. Then, a response from the device under measurement 5 is input.
[0016]
Further, these outputs and inputs are compared, and if the result is assumed in advance, the device under test or the inspection program is judged good. Further, the output and the input are compared, and if the result is not assumed in advance, the device under test or the inspection program is regarded as defective, and the device under test or the inspection program is reviewed.
[0017]
Such verification is repeated to suppress defects in the device under test or the inspection program.
[0018]
Further, FIG. 2B is a diagram showing an address space between the pattern data PD of the test signal for the device under measurement 5 stored in the file 1 ′ and its pattern address PA. As shown in the figure, the pattern address PA is provided with sequential addresses from the pattern address 0 to the pattern address 0xffffffff, similarly to the address of the HDL memory 2 ′.
[0019]
In such a conventional test of FIG. 2, the sequencer 4 sequentially outputs the execution address PA_C from the pattern address PA range (0 to 0xffffffff). Then, the test of the device under test or the inspection program is executed according to the execution address PA_C.
[0020]
[Problems to be solved by the invention]
However, such a conventional tester device has a problem that when the pattern address PA and the pattern data PD have a large capacity, all of them cannot be stored in the HDL memory 2 'at a time. Also, it is expensive and difficult to increase the actual hardware memory of the engineering work station EWS.
[0021]
In particular, a tester device for IC inspection has a large pattern data address PA and pattern data PD, and requires, for example, 130 GB or more. Therefore, it is difficult to use a general-purpose engineering work station EWS.
[0022]
An object of the present invention is to solve the above-described problems and to provide a tester device that can execute a test with a small HDL memory.
Another object of the present invention is to provide a low-cost tester device suitable for IC inspection.
[0023]
[Means for Solving the Problems]
The present invention which achieves such an object is as follows.
(1) In a tester apparatus that outputs a calculated value based on data from the HDL memory to a device under test and inputs a response of the device under test, the tester device has an address number based on the number of addresses of the HDL memory, Select a plurality of data files that store test signal pattern data for the measurement device separately, and the data file based on the quotient obtained by dividing the execution address sequentially output during the test by the number of addresses in the HDL memory The HDL memory, the data of the data file selected by the selection means is downloaded, and the data based on the remainder obtained by dividing the execution address by the number of addresses of the HDL memory is valid. A tester device characterized by that.
(2) The number of addresses based on the number of addresses in the HDL memory in an IC tester device that outputs a calculated value based on data from the HDL memory to the virtual device under test and inputs a response of the virtual device under test. A plurality of data files for dividing and storing test signal pattern data for the virtual device under test, and a quotient obtained by dividing the execution address sequentially output during the test by the number of addresses in the HDL memory And a division unit for calculating the remainder, storage means for storing the quotient, comparison means for invalidating the selection means when the value of the storage means matches the quotient, and the quotient based on the quotient Selection means for selecting a data file, and the HDL memory downloads data of the data file selected by the selection means. Is, tester for IC examination, characterized in that an effective data based on the remainder.
(3) In a tester apparatus that outputs a calculation value based on data from the HDL memory to a device under test and inputs a response of the device under test, a plurality of test signal pattern data for the device under test are divided and stored. And a selection means for selecting the data file based on the upper bits of the execution address sequentially output at the time of the test, and the HDL memory stores the data file selected by the selection means. A tester apparatus, wherein data is downloaded and data based on the lower bits of the execution address is validated.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1A is a block diagram of the present invention. FIG. 1B is a diagram showing an address space between the pattern data PD of the test signal for the device under measurement 5 and its pattern address PA. Elements equivalent to those in the conventional example of FIGS. 2A and 2B are denoted by the same reference numerals and description thereof is omitted.
[0025]
1A includes a plurality of data files PAT0, PAT1,... PAT (M-2), PAT (M-1), and selection means 6. It is in. A second feature of the embodiment of FIG. 1A is that a division unit 7 is provided. Further, the third feature of the embodiment of FIG. 1A is that a comparison means 8 and a storage means 9 are provided.
[0026]
Further, in FIG. 1B, the pattern address PA includes addresses that are serial numbers from the pattern address 0 to the pattern address L-1. The pattern address L-1 is between the pattern address (M-1) × N and the pattern address M × N. The number of pattern addresses PA is L.
[0027]
The structure of FIG. 1A will be described in detail below.
1A, the tester device 10 includes a file 1, an HDL memory 2, a calculation unit 3, a sequencer 4, a selection unit 6, a division unit 7, a selection unit 8, and a storage unit 9.
[0028]
The HDL memory 2 includes sequential addresses from 0 to an address N-1. The number of addresses in the HDL memory 2 is N.
[0029]
File 1 is formed from M data files of data files PAT0, PAT1,..., PAT (M-2), PAT (M-1).
[0030]
The data file PAT0 includes sequential addresses from pattern address 0 to pattern address N-1. The number of addresses in the data file PAT0 is N, which is equal to the number N of addresses in the HDL memory 2.
[0031]
The data file PAT1 includes sequential addresses from the pattern address N to the pattern address 2N-1. The number of addresses of the data file PAT1 is N, which is equal to the number N of addresses of the HDL memory 2.
[0032]
Similarly, the data file PAT (M-2) includes sequential addresses from pattern address (M-2) × N to pattern address (M−1) × N−1. Further, the number of addresses of the data file PAT (M−2) is N, which is equal to the number N of addresses of the HDL memory 2.
[0033]
Further, the data file PAT (M−1) includes sequential addresses from the pattern address (M−1) × N to the pattern address L−1. The number of addresses of the data file PAT (M−1) is L− (M−1) × N <N, which is smaller than the number N of addresses in the HDL memory 2.
[0034]
Therefore, the M data files PAT0, PAT1,..., PAT (M-2), and PAT (M-1) each have sequential addresses, and addresses based on the number N of addresses in the HDL memory 2, respectively. Have a number.
[0035]
Further, the M data files PAT0, PAT1,..., PAT (M-2), PAT (M-1) store the pattern data PD divided into M pieces. FIG. 1B shows a state in which the pattern data PD is divided into M pieces.
[0036]
The above relationship can be summarized as follows. The pattern data PD of 0 ≦ pattern address PA <N is stored in the data file PAT0. The pattern data PD with N ≦ pattern address PA <2N is stored in the data file PAT1. .... The pattern data PD of (M−2) × N ≦ pattern address PA <(M−1) × N is stored in the data file PAT (M−2). The pattern data PD of (M−1) × N ≦ pattern address PA <L is stored in the data file PAT (M−1).
[0037]
The selection means 6 is arranged between the file 1 (data files PAT0, PAT1,... PAT (M-2), PAT (M-1)) and the HDL memory 2. Further, the selection unit 6 selects one of the data files based on the execution address PA_C.
[0038]
Further, the division unit 7 calculates a quotient PA_C / N and a remainder PA_C% N obtained by dividing the execution address PA_C output from the sequencer 4 by the number N of addresses in the HDL memory 2.
The quotient PA_C / N is output to the selection means 6 via the comparison means 8. Further, the remainder PA_C% N is output to the HDL memory 2.
[0039]
The storage unit 9 stores the quotient PA_C / N as the value PA_N / N of the storage unit 9.
[0040]
Further, the comparison unit 8 compares the value PA_N / N of the storage unit 9 with the quotient PA_C / N of the division unit 7. When the value PA_N / N of the storage means 9 and the quotient PA_C / N of the division unit 7 coincide with each other, the selection means 6 is invalidated. When the value PA_N / N of the storage means 9 and the quotient PA_C / N do not match, the selection means 6 is validated.
[0041]
Furthermore, the HDL memory 2 is connected to data files PAT0, PAT1,..., PAT (M-2), PAT (M-1) which are selected and made valid by the selection means 6. Then, the pattern data PD that is valid and stored in the selected data file (for example, the data file PAT1) is downloaded. Further, the data based on the remainder PA_C% N is validated and connected to the calculation unit 3.
[0042]
The operation of the embodiment shown in FIGS. 1A and 1B will be described.
When the value of the execution address PA_C output from the sequencer 4 is between the pattern address N and the pattern address 2N-1, the quotient PA_C / N becomes 1 in the division unit 7, and the selection means 6 selects the data file PAT1. .
[0043]
Next, the HDL memory 2 downloads the pattern data PD stored in the data file PAT1. Further, the remainder PA_C% N becomes (PA_C-N), and the data of the address (PA_C-N) of the HDL memory 2 is valid.
[0044]
Then, the calculation unit 3 calculates the data of the address (PA_C-N) that is valid in the HDL memory 2 and outputs the calculated value to the device under measurement 5. Further, a response from the device under measurement 5 is input.
[0045]
Further, when the value of the execution address PA_C output from the sequencer 4 is between the pattern address (M−2) × N and the pattern address (M−1) × N−1, the division unit 7 uses the quotient PA_C / N. Becomes M-2, and the selection means 6 selects the data file PAT (M-2).
[0046]
The HDL memory 2 downloads the pattern data PD stored in the data file PAT (M-2). Further, the remainder PA_C% N becomes (PA_C- (M-2) * N), and the data of the address (PA_C- (M-2) * N) in the HDL memory 2 is valid.
[0047]
Then, the calculation unit 3 calculates the data of the address (PA_C−M + 2) that is valid in the HDL memory 2 and outputs the calculated value to the device under measurement 5. Further, the response of the device under measurement 5 is input.
[0048]
In this way, in the embodiment of FIG. 1, as in the conventional example of FIG. 2, the sequencer 4 sequentially outputs the execution address PA_C from the range (0 to L-1) of the pattern address PA during the test. Then, the test is executed according to the execution address PA_C.
[0049]
Accordingly, the two or more data files PAT0, PAT1,... PAT (M-2), PAT (M-1) for storing the pattern data PD in a divided manner and the selection means 6 are small HDL memories 2. Make the test viable.
[0050]
When the value PA_N / N of the storage means 9 is between the pattern address 0 and the pattern address N-1, and the execution address PA_C from the sequencer 4 is between the pattern address N and the pattern address 2N-1, the comparison means 8 enables the selection means 6, the selection means 6 selects the data file PAT1, and the HDL memory 2 downloads the pattern data PD stored in the data file PAT1. Further, the storage means 9 rewrites the quotient PA_C / N as the value PA_N / N of the storage means 9.
[0051]
However, when the value PA_N / N of the storage means 9 and the execution address PA_C are both between the pattern address N and the pattern address 2N-1, the comparison means 8 invalidates the selection means 6 and the HDL memory 2 is downloaded. Retain data. Further, the storage unit 9 holds this value without rewriting the value PA_N / N of the storage unit 9.
[0052]
As described above, when the comparison unit 8 and the storage unit 9 are provided, useless processing is reduced and processing is simplified. That is, the HDL memory 2 is downloaded only when necessary without performing a wasteful process of downloading every time.
[0053]
The operation of the embodiment of FIG. 1 described above will be described again in detail.
First, the sequencer 4 can be broadly divided into two cases: when the sequencer 4 outputs the first execution address PA_C, and when the sequencer 4 outputs the first and subsequent execution addresses PA_C. This will be explained in order.
[0054]
First, the sequencer 4 outputs the first execution address PA_C.
[0055]
Then, the division unit 7 outputs the quotient PA_C / N and the remainder PA_C% N based on the execution address PA_C.
[0056]
Further, the comparison unit 8 enables the selection unit 6. The storage unit 9 stores the quotient PA_C / N as the value PA_N / N of the storage unit 9.
[0057]
Then, the selection unit 6 selects one of the data files corresponding to the execution address PA_C (for example, the data file PAT0).
[0058]
In addition, the HDL memory 2 downloads data of a data file (for example, the data file PAT0) selected and valid by the selection unit 6. Further, the HDL memory 2 validates data based on the remainder PA_C% N.
[0059]
Then, the calculation unit 3 calculates the data of the address (PA_C-N) that is valid in the HDL memory 2 and outputs the calculated value to the device under measurement 5. Further, the response of the device under measurement 5 is input.
[0060]
Next, the sequencer 4 outputs the first and subsequent execution addresses PA_C.
[0061]
Then, the division unit 7 outputs the quotient PA_C / N and the remainder PA_C% N based on the execution address PA_C.
[0062]
Here, the process branches in the following two cases.
First, the case where the value PA_N / N of the storage means 9 and the quotient PA_C / N do not match will be described.
The comparison unit 8 validates the selection unit 6 and the storage unit 9 rewrites the quotient PA_C / N as the value PA_N / N of the storage unit 9.
[0063]
Then, the selection unit 6 selects one of the data files (for example, the data file PAT0) based on the execution address PA_C.
[0064]
In addition, the HDL memory 2 downloads data of a data file (for example, the data file PAT0) selected and valid by the selection unit 6. Further, the HDL memory 2 validates data based on the remainder PA_C% N.
[0065]
Then, the calculation unit 3 calculates the data of the address (PA_C-N) that is valid in the HDL memory 2 and outputs the calculated value to the device under measurement 5. Further, the response of the device under measurement 5 is input.
[0066]
Second, the case where the value PA_N / N of the storage means 9 and the quotient PA_C / N match will be described.
The comparison unit 8 invalidates the selection unit 6 and does not rewrite the value PA_N / N of the storage unit 9 in the storage unit 9.
Further, the HDL memory 2 does not download data.
[0067]
The HDL memory 2 validates the data based on the remainder PA_C% N.
[0068]
Then, the calculation unit 3 calculates the data of the address (PA_C-N) that is valid in the HDL memory 2 and outputs the calculated value to the device under measurement 5. Further, the response of the device under measurement 5 is input.
[0069]
In this way, the tester apparatus of the present invention performs a test.
[0070]
In the above example, the quotient PA_C / N obtained by dividing the execution address PL_C by the number N of addresses in the HDL memory 2 is used. However, separately from this, the upper bits of the execution address PA_C are used. Also good. Using the upper bits is equivalent to performing a division. At this time, the HDL memory 2 validates the data using the lower bits of the execution address PA_C.
[0071]
Furthermore, in the above example, the data file PAT0 to the data file PAT (M-2) all have N addresses, but apart from this, the data file PAT0 to the data file PAT (M-2). The number of addresses can be changed and modified so that the test can be executed with the small HDL memory 2 even if the addresses are not uniform, such as N-1 or N-2.
[0072]
However, the selection means 6 at this time selects the data file based on the lower limit value and the upper limit value of the addresses of the data files PAT0, PAT1,..., PAT (M-2), PAT (M-1). It is better to select.
[0073]
As described above, the present invention is not limited to the above-described embodiments, and includes many changes and modifications without departing from the essence thereof.
[0074]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a tester device that can execute a test with a small HDL memory.
[0075]
Further, the present invention can provide a tester device for IC inspection at low cost.
[0076]
Furthermore, the number of patterns that can be executed by the tester device can be set regardless of the capacity of the HDL memory of the engineering work station.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a tester device of the present invention.
FIG. 2 is a configuration diagram of a conventional tester device.
[Explanation of symbols]
10, 10 'tester device 1, 1' file 2, 2 'HDL memory 3 operation unit 4 sequencer 5 virtual device under measurement 6 selection unit 7 division unit 8 comparison unit 9 storage unit PAT0, PAT1, ... PAT (M -2), PAT (M-1) Data file PA Pattern address PD Pattern data PA_C Execution address PA_C / N Quotient PA_C% N Remainder PA_N / N Value of storage means

Claims (3)

In a tester apparatus that outputs a calculated value based on data from an HDL memory to a device under measurement and inputs a response of the device under measurement,
A plurality of data files having a number of addresses based on the number of addresses in the HDL memory, and dividing and storing test signal pattern data for the device under test;
Selecting means for selecting the data file based on the quotient obtained by dividing the execution address sequentially output at the time of the test by the number of addresses of the HDL memory, and the HDL memory is selected by the selecting means A tester device, wherein data of the data file is downloaded and data based on a remainder obtained by dividing the execution address by the number of addresses in the HDL memory is validated. In an IC tester device for outputting a calculated value based on data from an HDL memory to a virtual device under test and inputting a response of the virtual device under test,
A plurality of data files having a number of addresses based on the number of addresses of the HDL memory, and dividing and storing test signal pattern data for the virtual device under test;
A division unit for calculating a quotient and a remainder obtained by dividing execution addresses sequentially output during a test by the number of addresses in the HDL memory;
Storage means for storing the quotient;
Comparison means for invalidating the selection means when the value of the storage means and the quotient match;
Selecting means for selecting the data file based on the quotient,
A tester device for IC inspection, wherein the data in the data file selected by the selection means is downloaded to the HDL memory, and data based on the remainder is validated. In a tester apparatus that outputs a calculated value based on data from an HDL memory to a device under measurement and inputs a response of the device under measurement,
A plurality of data files for dividing and storing test signal pattern data for the device under test;
Selecting means for selecting the data file based on the higher order bits of the execution address sequentially output at the time of the test,
The tester apparatus, wherein the data of the data file selected by the selection means is downloaded to the HDL memory, and data based on the lower bits of the execution address is validated.

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