JP4136361B2 - MOS gate thyristor and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a MOS gate thyristor having a so-called MOS gate having a metal (M) -oxide film (O) -semiconductor (S) structure and a control method therefor.
[0002]
[Prior art]
  An insulated gate bipolar transistor (hereinafter referred to as IGBT) is known as one of high breakdown voltage semiconductor elements having a MOS gate.
  FIG. 14 is a cross-sectional view of a main part of a punch-through type n-channel vertical IGBT having a trench gate as a conventional IGBT.
[0003]
  N of high specific resistance^-P base region 22, n on the surface layer of the drift layer 21⁺Emitter region 24, p⁺Contact region 23 is formed, and n⁺N from the emitter region 24 through the p base region 22^-A trench 35 reaching the drift layer 21 is dug down. A gate electrode 26 is buried in the trench 35 via a gate insulating film 25. n^-N on the back side of the drift layer 21^-There are an n buffer layer 27 and a p collector layer 28 having an impurity concentration higher than that of the drift layer 21, and a collector electrode 29 is provided on the surface.
[0004]
  30 is n⁺Emitter region 24, p⁺The emitter electrode is in common contact with the surface layer of the contact region 23. On the other hand, a thyristor is known as a high breakdown voltage semiconductor element having an on-resistance lower than that of an IGBT. FIGS. 15 and 16 show an emitter-switched thyristor (hereinafter referred to as EST, Shekar, M.S.et.al.; Proc.of 3rd) as a conventional MOS gate thyristor.International  Symposium on Power Semiconductor Devices and ICs, (1991), p.128] and Base Resistance Controlled Thyristor (hereinafter referred to as BRT, Nandakumar, M. et.al .: Proc. Of 3^rd  International  Symposium on Power Semiconductor Devices and ICs (1991), see p.138].
[0005]
  The EST in FIG. 15 includes a p collector layer 48, an n buffer layer 47, n^-Drift layer 41, p base region 42, n⁺A pnpn main thyristor portion comprising a floating region 44a, a p collector layer 48, an n buffer layer 47, n^-Drift layer 41, p⁺Contact region 43, n⁺There is a parasitic thyristor portion comprising an emitter region 44.
  The main thyristor part is n^-Drift layer 41 and n⁺Via a gate insulating film 45 on the surface of the p base region 42 sandwiched between the floating region 44a.Gate electrode 46 Is providedAnd n⁺Floating regions 44a and n⁺On the surface of the p base region 42 sandwiched between the emitter region 44 and the gate insulating film 45a.Auxiliary gate electrode 46 a is provided and the gate electrode 46 ,It can be turned on by applying a positive voltage to the auxiliary gate electrode 46a, and can be turned off by applying a zero or negative voltage.
[0006]
  In FIG.BRTIs n^-P base region 52, n on the surface layer of drift layer 51⁺An emitter region 54 is formed and n^-Drift layer 51 and n⁺A gate electrode 56 is provided on the surface of the p base region 52 sandwiched between the emitter region 54 via a gate insulating film 55. n^-A p diverter region 61 facing the p base region 52 is formed on the surface layer of the drift layer 51. The p base region 52, the p diverter region 61, the gate insulating film 55, and the gate electrode 56 constitute a p-channel MOSFET. Yes. The auxiliary electrode 62 provided in contact with the surface of the p diverter region 61 is n⁺An emitter electrode 60 provided in contact with the surface of the emitter region 54 is connected.
[0007]
  By applying a positive voltage to the gate electrode 56BRTOn the other hand, by applying zero or negative voltage, the p-channel MOSFET is turned on and n^-Carrier discharge from the drift layer 51 can be accelerated and turned off. At turn-off, n^-A MOS gate thyristor having an insulated gate transistor for extracting carriers from the drift layer is disclosed in Japanese Patent Laid-Open No. 5-41515.
[0008]
[Problems to be solved by the invention]
  However, the conventional IGBT as shown in FIG. 14 has three drawbacks.
  First, the lower limit of the on-resistance is determined by the resistance of the FET channel formed at the interface between the p base region 22 and the gate insulating film 25, and the carrier does not become a high injection compared to the thyristor. There was a problem that the series resistance of the layer 21 could not be ignored. In order to solve this problem, it has been attempted to increase the FET channel density per device area by introducing a trench structure in the emitter portion, but it has been impossible to reduce the on-resistance to the same level as a thyristor.
[0009]
  Second, n of the emitter section⁺The parasitic thyristor latches up due to the voltage drop caused by the hole current 31 flowing inside the p base region 22 along the boundary between the emitter region 24 and the p base region 22, and control by the gate electrode 26 becomes impossible. is there. In particular, latch-up is likely to occur when the load is short-circuited, and there is a problem that the element is destroyed by overcurrent. P to eliminate this⁺Although the contact region 23 is provided to reduce the voltage drop and improve the latch-up resistance, it cannot be said that a sufficient effect is obtained. P⁺There is a problem in that the number of steps for providing the contact region 23 increases and the cost increases. Furthermore, in a highly integrated trench IGBT, n⁺Emitter region 24 and p⁺Since the contact region 23 is densely present at an interval of 1 μm or less, mask alignment and drive conditions in ion implantation become severe.
[0010]
  The third drawback is p⁺Contact region 23, n^-The pnp transistor composed of the drift layer 21 and the p collector region 28 has a high amplification factor, and the leakage current is amplified at the reverse breakdown voltage, so that it cannot be used as a bidirectional device. This problem is p⁺This can be solved by lowering the impurity concentration of the contact region 23, but the latch-up mentioned as the second drawback is likely to occur.⁺The impurity concentration of the contact region 23 cannot be lowered as much as possible.
[0011]
  On the other hand, the conventional MOS gate thyristor has the following three drawbacks.
  First, the structure is complicated and not suitable for integration, and the number of processes is large, so the cost is high. Secondly, since the method of extracting carriers at the time of turn-off is a method of short-circuiting from a semiconductor region to another semiconductor region by an FET channel, the extraction efficiency is poor and the interruptable current capacity is small. Therefore, the problem that the gate cannot be controlled when the load is short-circuited and the element is destroyed is more serious than that of the IGBT. Third, as a result of poor carrier extraction efficiency, the switching speed is slow and the turn-off loss is large.
[0012]
  There are four purposes of this invention.
  First, a thyristor operation is performed during the on operation, thereby providing a semiconductor element having an on-resistance lower than that of the IGBT and arranged in the thyristor.
  The second is to provide a semiconductor element aligned with the IGBT by performing an IGBT operation at the time of turn-off so that the current capacity that can be cut off is larger than that of the thyristor, the turn-off time is short, the turn-off loss is small.
[0013]
  The third is to provide a control method for fully extracting the characteristics of the semiconductor element.
  The fourth is to provide a semiconductor element that has a low leakage current even at a reverse breakdown voltage and can be used as a bidirectional device.
  In other words, to realize a semiconductor element having both advantages in turning on the thyristor and in turning off the IGBT, and a control circuit thereof.sois there.
[0014]
[Hand throws to solve problems]
  In order to achieve the above object, a structure in which the emitter portion is thinned and miniaturized is adopted, and conventionally, n⁺An emitter electrode provided in contact with both the emitter region and the p base region is defined as n⁺The first emitter electrode that contacts only the emitter region and the second emitter electrode that contacts only the p base region are separated.
[0015]
  Specifically, the first conductivity type drift layer having a high resistivity, the second conductivity type base region formed in the surface layer of the drift layer, and the surface layer of the second conductivity type base region are formed.Is itA first conductivity type emitter region not connected to the first conductivity type drift layer; a first trench reaching the drift layer dug down from the surface of the first conductivity type emitter region through the second conductivity type base region; A gate insulating film formed on the inner wall of the first trench, a gate electrode provided in the first trench so as to face the second conductive type base region via the gate insulating film, and a first conductive type emitter region A first emitter electrode provided in contact with the surface and not in contact with the second conductivity type base region, and dug down from the surface of the first conductivity type emitter region;BeforeA second trench reaching the second conductivity type base region, and a second emitter electrode that contacts only the second conductivity type base region provided in the second trench and does not contact the first conductivity type emitter region A MOS gate thyristor comprising: a second conductivity type collector layer formed on the back side of the first conductivity type drift layer; and a collector electrode provided in contact with the surface of the second conductivity type collector layer;
  The first conductivity type drift layer having a high resistivity, the second conductivity type base region formed in the surface layer of the drift layer, and the surface layer of the second conductivity type base region.Is itA first conductivity type emitter region not connected to the first conductivity type drift layer; a first trench reaching the drift layer dug down from the surface of the first conductivity type emitter region through the second conductivity type base region; A gate insulating film formed on the inner wall of the first trench, a gate electrode provided in the first trench so as to face the second conductive type base region via the gate insulating film, and a first conductive type emitter region A first emitter electrode provided in contact with the surface and not in contact with the second conductivity type base region, and only in contact with the surface of the second conductivity type base region sandwiched between the first conductivity type emitter regions; A second emitter electrode not in contact with the emitter region; a second conductivity type collector layer formed on the back side of the first conductivity type drift layer; and a collector electrode provided in contact with the surface of the second conductivity type collector layer. MOS gate thyristor having a doorThe
SomeYes
  A gate electrode formed on the first conductivity type drift layer via an insulating film, an insulating film covering a side surface and an upper surface of the gate electrode, and a first conductivity type thin film semiconductor layer formed on the insulating film on the gate electrode And a connected semiconductor portion connecting the first conductivity type drift layer and the first conductivity type thin film semiconductor layer along the side of the gate electrode,A first-conductivity-type emitter region, a second-conductivity-type base region, and a first-conductivity-type thin-film semiconductor layer disposed in order from an end of the first-conductivity-type thin-film semiconductor layer that is far from the connecting semiconductor portion ,Provided only in contact with the first conductivity type emitter regionThe secondThe first emitter electrode that does not contact the two conductivity type base region and the second emitter type base region that is in contact onlyThe secondProvided in contact with the second emitter electrode not contacting the one conductivity type emitter region, the second conductivity type collector layer formed on the back side of the first conductivity type drift layer, and the surface of the second conductivity type collector layer A MOS gate thyristor having a collector electrode. The connecting semiconductor portion may be a part of the semiconductor substrate or a semiconductor thin film layer.
[0016]
  If the first emitter electrode and the second emitter electrode are connected to each other through a switching element such as a MOSFET in this way, the MOS gate thyristor is immediately turned on with the second emitter electrode floating. Latch up and shift to thyristor operation. As a result, a low on-resistance can be realized.
  Next, at the time of turn-off, the first emitter electrode and the second emitter electrode are short-circuited, and at the same time, the gate input is turned off so that the IGBT mode can be turned off. At this time, since the emitter layer is a thin film with a small volume and carriers are extracted from the semiconductor region to the metal region, the efficiency of extracting carriers from the emitter b electrode is increased, and the interruptable current capacity is increased.
[0017]
  If the first conductivity type buffer layer having a higher impurity concentration than the first conductivity type drift layer is provided between the first conductivity type drift layer and the second conductivity type collector layer, the spread of the depletion layer is suppressed, so-called punch-through. The structure is suitable for a high voltage element as a type.
  The thickness of the second conductivity type collector layer is 1 μm or less, and the impurity doping level is 10¹⁸cm^-3The following can increase the switching speed by controlling the injection amount of minority carriers.
[0018]
  In the second conductivity type base regionImpuritiesConcentration is 10¹⁵-10¹⁸cm^-3It shall be in the range.
  If there is a voltage drop due to the hole current flowing inside the second conductivity type base region along the boundary between the first conductivity type emitter region and the second conductivity type base region in the emitter section, It gets smaller. In order to prevent this, it is advantageous that the width of the second conductivity type base region is narrow. In addition, if the width is narrow, the high-concentration second conductivity type contact region, which was necessary for conventional IGBTs to reduce the voltage drop, can be eliminated, reducing manufacturing costs and reducing leakage current at reverse breakdown voltage. It can be used as a bidirectional device.
[0019]
  FIG. 16 of JP-A-5-41515 mentioned above describes an example in which a second emitter electrode other than the first emitter electrode is provided in the second conductivity type base region. FIG. 17 is a perspective sectional view of the example.
  n^-P base region 72, n on the surface layer of drift layer 71⁺An emitter region 73 is formed and n⁺N from the surface of the emitter region 73^-A trench reaching the drift layer 71 is dug down, and a gate electrode 75 is buried in the trench through a gate insulating film 74. n⁺An auxiliary electrode 76 that contacts the surface of the p base region 72 is provided independently of the emitter electrode 78 that contacts the surface of the emitter region 73. In this example, the auxiliary electrode 76 that contacts the p base region 72 is provided not on the surface in the trench or between the trenches, but on the surface at the end of the trench in the longitudinal direction. In this case, the path of the hole current in the p base region 72 is the path indicated by the arrow 83. When such a long distance flows, the potential does not drop in the p base region 72 near the center of the trench, and in fact, a quick turn-off is not performed. In order to perform a quick turn-off, as described above,All ofIt is necessary that the point is close to the auxiliary electrode 76 and the voltage drop caused by the hole current 83 is small.
[0020]
  First trenchPlaneThe shape on the figure may be a stripe shape, or a lattice shape or a net shape. Can take a variety of shapes.
  If a switching semiconductor element such as a MOSFET connected between the first emitter electrode and the second emitter electrode is monolithically formed on the same semiconductor substrate, it is convenient as an integrated MOS gate thyristor.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
  Embodiments of the present invention will be described below with reference to the drawings.
  [First Embodiment]
  FIG. 1 is a cross-sectional view of the main part of an insulated gate thyristor according to the first embodiment of the present invention. In the following description, an n-channel insulated gate thyristor is illustrated.
[0022]
  The present invention relates to an emitter structure, and the collector structure is arbitrary. Therefore, the present invention can be applied to a structure in which a collector layer is thinned using a thin substrate and devices having a punch-through type collector layer. In FIG. 1, 1 is n of high resistance.^-It is a drift layer, and p base region 2 and n⁺An emitter region 3 is formed. And that n⁺N through the p base region 2 from the surface of the emitter region 3^-A first trench 15 that reaches the drift layer 1 is dug down, and a second trench 16 that stops at the p base region 2 is dug down between two adjacent first trenches 15.
[0023]
  A polycrystalline silicon gate electrode 5 is buried in the first trench 15 via a gate insulating film 4. Further, only the p base region 2 is in contact with the second trench 16 and n⁺A second emitter electrode (Eb) 6 that is not in contact with the emitter region 3 is provided. N in the second trench 16⁺The exposed portion of the emitter region 3 is protected by the interlayer insulating film 7.
[0024]
  In addition, n between the first trench 15 and the second trench 16⁺A first emitter electrode (Ea) 8 is provided in contact with the surface of the emitter region 3. On the other hand, n^-On the back side of the drift layer 1, there is a p collector layer 9, and a collector electrode 10 in contact with the surface is provided.
  For punch-through and field stop devices, n^-N between the drift layer 1 and the p collector layer 9^-An n buffer layer having a higher impurity concentration than the drift layer 1 may be sandwiched.
[0025]
  A method for manufacturing the insulated gate control thyristor of FIG. 1 will be described with reference to FIGS. 18A to 18D and cross-sectional views in the order of steps of FIG. However, FIG. 1 shows an active portion of an insulated gate control thyristor. Besides this, a breakdown voltage structure such as a guard ring is mainly provided in the peripheral portion, but these are formed in the same manner as other general semiconductor elements. I will omit it.
[0026]
  n^-A p-type base region 2 and an n-type impurity are implanted into the surface layer of the high-resistance n-type substrate to be the drift layer 1 by ion implantation of p-type and n-type impurities and heat treatment.⁺The emitter region 3 is formed [FIG. 18 (a)].
  n⁺For example, an oxide film serving as a mask is formed on the surface of the emitter region 3, and after patterning by photolithography or the like, n is performed by reactive ion etching using hydrogen bromide or the like.^-A first trench 15 reaching the drift layer 1 is formed, and its inner wall is thermally oxidized to form a gate insulating film 4. Subsequently, the first trench 15 is filled with polycrystalline silicon by a plasma CVD method or the like so as to be in close contact with the gate insulating film 4 to form the gate electrode 5 [FIG.
[0027]
  Subsequently, in the center of the region sandwiched between the two first trenches 15, n is similarly formed by mask formation and reactive ion etching.⁺A second trench 16 penetrating the emitter region 3 and slightly reaching the p base region 2 is formed and buried with an insulating film 7 [FIG. The insulating film 7 may be an oxide film such as tetraethoxysilane (TEOS), HDP, or HTO, or a nitride film.
[0028]
  Subsequently, a window is opened using a mask (not shown) in the insulating film 7 and dug so as not to penetrate the p base region 2 [(d)].
  Next, the second emitter electrode (Eb) 6 is embedded in the second trench 16 [FIG. 19]. The electrode material is preferably tungsten or copper by metal CVD, but may be aluminum or polycrystalline silicon.
[0029]
  Further, after the back side of the n-type substrate 1 is polished and adjusted to a predetermined thickness, the p collector layer 9 is formed by ion implantation of p-type impurities and heat treatment. n⁺An aluminum alloy is deposited on the surface of the emitter region 3 by sputtering and patterned to form a first emitter electrode (Ea) 8. At this time, a part of the gate metal electrode in contact with the gate electrode 5 is also formed at the same time. Three layers of titanium, gold, and nickel are deposited on the back surface of the p collector layer 9 by sputtering vapor deposition to form a collector electrode 10. Finally, a passivation film (not shown) is formed on the surface to complete the insulated gate control thyristor of FIG.
[0030]
  FIG. 3 shows a typical size of this insulated gate control thyristor. n^-The thickness t1 of the drift layer 1 is determined by the breakdown voltage value of the semiconductor element. For example, in the case of a 600V breakdown voltage product, the thickness t1 is 70 to 100 μm, and the doping level is about 10¹⁴cm^-3And The thickness t2 of the p base region 2 is arbitrary, but if considering the ease of process and mass production, the thickness is set to 1 to 5 μm, and the doping level is 10¹⁵-10¹⁸cm^-3It is good to do. If the doping level of the p base region 2 is too high, there is a risk that the leakage current at the time of reverse breakdown voltage becomes large. n⁺The thickness t3 of the emitter region 3 is arbitrary, but if considering the ease of process and mass productivity, the thickness is set to 5 μm or less, and the doping level is 10¹⁷cm^-3It is good to be the above.
[0031]
  The thickness t4 of the gate insulating film 4 is preferably 10 to 100 nm as long as it functions as a gate insulating film. The width t5a of the first trench 15 is preferably 5 μm or less in order to increase the degree of integration. Further, the depth t5b depends on the p base region 2 and n.⁺Pierce through emitter region 3^-It only needs to reach the drift region 1 and is determined by the values of t2 and t3. The thickness t6 of the second emitter electrode (Eb) 6 is set to be smaller than the thickness t2 of the p base region 2, and the upper surface and the lower surface of the second emitter electrode (Eb) 6 are It is necessary to determine so as not to penetrate the lower surface, and it is preferable to set it to 5 μm or less. The thickness t7 of the interlayer insulating film 7 is n⁺It must be larger than the thickness t3 of the emitter region 3. The width t6a of the second trench 16 is preferably 5 μm or less in order to increase the degree of integration. The interval t between the first trench 15 and the second trench 16 is 10 μm or less. When the interval t is large, the carrier extraction efficiency is reduced and the interruptable current capacity is reduced.
[0032]
  Although the thickness t9 of the p collector layer 9 is arbitrary, it is set to 1 μm or less from the viewpoint of reducing the turn-off loss, and the doping level is set to 10¹⁸cm^-3The following is desirable.
  Next, the operating characteristics of this MOS gate thyristor will be described. FIG. 2 shows the most basic circuit when the power of the inductive load is controlled by the MOS gate thyristor 11 shown in FIG. That is, the MOSFET 12 is connected between the first emitter electrode (Ea) 8 and the second emitter electrode (Eb) 6.If a switching semiconductor element such as a MOSFET connected between the first emitter electrode and the second emitter electrode is monolithically formed on the same semiconductor substrate, it is convenient as an integrated MOS gate thyristor.
[0033]
  In order to change the MOS gate thyristor 11 from the off state to the on state, the following operation is performed. First, the MOSFET 12 is turned off, and the first emitter electrode (Ea) 8 and the second emitter electrode (Eb) 6 are insulated. Next, for example, +15 V is applied to the gate of the MOS gate thyristor 11, and an FET channel is formed at the interface between the p base region 2 and the gate insulating film 4 to pass a current. This operation is an FET operation. However, p base region 2 and n⁺Due to the potential difference generated between the emitter region 3 and the thyristor operation is immediately shifted from the FET operation. As a result, the on-resistance is the same as that of a normal thyristor, and is almost close to the limit as a bipolar device.
[0034]
  Next, the turn-off operation will be described. In turn-off, the gate input of the MOS thyristor 11 is turned off, for example, from 0 V to -15 V, and at the same time, the MOSFET 12 is turned on by the gate input to short-circuit the first emitter electrode (Ea) 8 and the second emitter electrode (Eb) 6. . When the first emitter electrode (Ea) 8 and the second emitter electrode (Eb) 6 are short-circuited, the circuit becomes equivalent to the IGBT. At this time, holes present in a high injection state in the p base region 2 are extracted to the second emitter electrode (Eb) 6. Since the p base region 2 has a thin film structure and a small volume and is extracted from the semiconductor region to the metal, the hole extraction efficiency is extremely high.
[0035]
  Furthermore, the hole current in the emitter is n⁺Since it does not flow along the boundary between the emitter region 3 and the p base region 2, there is no voltage drop due to the hole current, and the p base region 2 and n⁺The emitter region 3 is at the same potential, and the thyristor operation is immediately terminated. Further, since the FET channel is cut at the interface between the p base region 2 and the gate insulating film 4 by the gate input, the FET is turned off by the same principle as the conventional IGBT. As a result, the turn-off time is 10 times faster than the conventional thyristor along with the conventional IGBT, and the turn-off loss is comparable to that of the conventional IGBT.
[0036]
  According to the present invention, the on-resistance is lower than that of the conventional IGBT, close to the limit of the bipolar device along with the thyristor, and the turn-off time and turn-off loss are aligned with those of the conventional IGBT, one digit compared with the conventional thyristor. As described above, a high voltage semiconductor device having good characteristics can be obtained. That is, a semiconductor element having the advantages of the conventional IGBT and the advantages of a thyristor can be realized.
[0037]
  In addition, the conventional IGBT has a problem that once it is latched up, it cannot control the gate and an overcurrent flows, leading to element breakdown. On the other hand, the MOS gate thyristor 11 is always on and latched up. Can be blocked at any time. Although the current capacity that can be interrupted depends on the design parameters, it is possible to exceed the current capacity that can be interrupted by the conventional IGBT by 5 times or more and nearly 10 times according to the simulation.
[0038]
  Further, the MOS gate thyristor 11 of this embodiment can be easily protected even when the load is short-circuited. When a load short-circuit is detected, the MOSFET 12 can be turned on immediately, and at the same time as the gate input can be turned off, the thyristor operation state can be cut off. Since the current capacity that can be cut off is extremely large as described above, it is possible to protect the element before it breaks down.
  Further, during the on-operation, not only the gate input but also the MOSFET 12 is controlled intermediately by the gate input, thereby creating an intermediate state between the thyristor operation and the IGBT operation, thereby enabling finer current control.
[0039]
  [Second Embodiment]
  FIG. 4 is a partial cross-sectional view of the MOS gate thyristor according to the second embodiment. In FIG. 4, the same number is attached | subjected to the area | region corresponding to each area | region of FIG. The external circuit corresponding to FIG. 2 of the first embodiment is also common in this embodiment.
  High resistance n^-A gate electrode 5 made of polycrystalline silicon is formed on the drift layer 1 via an insulating film 4 made of an oxide film, for example. The side surface and the upper surface of the gate electrode 5 are also covered with the insulating film 4. n^-A thin film semiconductor layer 18 is formed from the surface of the drift layer 1 to the gate electrode 5 through the connection semiconductor portion 19 on the side of the gate electrode 5, and at the end of the thin film semiconductor layer 18 far from the connection semiconductor portion 19 p base region 2, n⁺An emitter region 3 is formed. 8 is n⁺First emitter electrodes (Ea) and 6 provided in contact with the emitter region 3 are second emitter electrodes (Eb) provided on the surface of the p base region 2. n^-A p collector layer 9 is formed on the back side of the drift layer 1, and a collector electrode 10 is provided on the surface thereof. In this example, the insulating film on the upper side of the gate electrode 5 becomes the gate insulating film 4.Consolidated Semiconductor Department 19 May be part of a semiconductor substrate or a semiconductor thin film layer.
[0040]
  For punch-through and field stop devices, n^-N between the drift layer 1 and the p collector layer 9^-An n buffer layer having a higher impurity concentration than the drift layer 1 may be sandwiched.
  A method for manufacturing the insulated gate control thyristor of FIG. 4 will be described with reference to cross-sectional views in the order of steps in FIGS. 20A and 20B and FIGS. 21A to 21D.
[0041]
  n^-An oxide film 4a is formed on the high resistance n-type substrate to be the drift layer 1 by thermal oxidation, and subsequently a polycrystalline silicon film 5a to be the gate electrode 5 is formed by low pressure CVD [FIG. 20 (a)].
  Subsequently, a stripe-shaped window is opened in the oxide film 4a and the polycrystalline silicon film 5a using a mask (not shown) [(b) in the figure].
[0042]
  Next, an oxide film 4b is deposited by CVD in the opening part opened (FIG. 21A).
  After polishing and planarizing the surfaces of the oxide film 4b and the polycrystalline silicon film 5a, an oxide film 4c is deposited on the surfaces by CVD [FIG.
  Subsequently, a window is opened in the oxide films 4c and 4b using a mask (not shown) [FIG. Thus, the gate electrode 5 whose upper and lower sides and side surfaces are surrounded by the oxide film is formed.
[0043]
  A single-crystal epitaxial growth layer 1b is epitaxially grown from the opening formed in the window [(d)]. At this time, it is preferable to extend the epitaxial growth layer 1b in the lateral direction using a lateral epitaxial growth (hereinafter referred to as ELO) technique or a molecular beam epitaxy method in which the directivity of the molecular beam is uniform.
  Thereafter, a p base region is formed at the tip of the epitaxial growth layer 1b by ion implantation and heat treatment, and n at the tip.⁺An emitter region is formed.
[0044]
  Subsequently, an aluminum alloy is deposited by sputtering vapor deposition and patterned to form a second emitter electrode (Eb) 6, n on the surface of the p base region 2.⁺A first emitter electrode (Ea) 8 is provided on the surface of the emitter region 3. At this time, a part of the gate metal electrode in contact with the gate electrode 5 is also formed at the same time. Further, after the back side of the n-type substrate 1 is polished and adjusted to a predetermined thickness, the p collector layer 9 is formed by ion implantation of p-type impurities and heat treatment. Three layers of titanium, gold, and nickel are deposited on the back surface of the p collector layer 9 by sputtering vapor deposition to form a collector electrode 10. Finally, a passivation film (not shown) is formed on the surface to complete the insulated gate control thyristor shown in FIG.
[0045]
  This embodiment is different from the first embodiment in that the p base region 2 and n⁺This is because the emitter portion in which the emitter region 3 is formed is drawn out to the substrate surface. Such a structure can be formed using ELO. In the first embodiment, when the thickness t becomes 1 μm or less due to the thinning of the emitter portion, there is a problem that the emitter portion is mechanically weak and easily broken. Also, the formation of the second emitter electrode 6 becomes difficult. Therefore, in order to maintain mechanical strength, a structure in which the thin film structure of the emitter portion is supported by the substrate is desirable. This embodiment has realized this.
[0046]
  According to the present embodiment, the thickness t of the emitter portion can be 0.1 μm or less. Furthermore, if the design rule becomes smaller, the p base region 2, n⁺The emitter region 3, the first emitter electrode (Ea) 8 and the second emitter electrode (Eb) 6 can be miniaturized to increase the degree of integration. Other effects are the same as those of the first embodiment.
[0047]
  A simulation of current-voltage characteristics (Ic-Vce characteristics) in the present embodiment was performed. FIG. 5 is a cross-sectional view of the structure used for the simulation, and FIG. 6 is an enlarged view of the vicinity of the surface. The cell shape was a stripe shape, and a 1 cm square chip was assumed.
  n^-The thickness of the drift layer is 100 μm, the unit cell width is 20 μm, the thicknesses of the p base region and the n emitter region are both 1 μm, and the widths are 2 μm and 1 μm, respectively. The width of the connecting semiconductor part 19 is 2 μm. The thickness of the gate electrode is 1 μm, and the thickness of the gate insulating film is 50 nm.
[0048]
  FIG. 7 is an Ic-Vce characteristic diagram when the first emitter electrode (Ea) 8 and the second emitter electrode (Eb) 6 are short-circuited. The horizontal axis represents the collector-emitter voltage Vce, and the vertical axis represents the collector current Ic. Chip size is 1cm²Therefore, it can be considered as current density. The parameter was the gate voltage Vg, which was 9V, 10V and 15V. The impurity concentration of the p collector layer 9 is 5 × 10.¹⁶cm^-3It was.
[0049]
  When Vce = 10V, 3500A, 3800A and 4500A flow at Vg = 9V, 10V and 15V, respectively. This operation is close to the IGBT operation, but it can be seen that gate control is possible at a current density much higher than the current density at which a normal IGBT latches up.
  FIG. 8 shows the Ic-Vge (turn-off) characteristic when a 0.1 Ω resistor is sandwiched between the first emitter electrode (Ea) 8 and the second emitter electrode (Eb) 6. The horizontal axis represents the gate voltage Vge, and the vertical axis represents the collector current Ic. Since a current of several tens of amperes flows through this resistor during the on operation, the voltage drop is 0.7 V or more, which satisfies the condition of the thyristor operation. Therefore, Ic tends to increase as compared with the case where both emitter electrodes are short-circuited. An increase in Ic when a resistor is sandwiched indicates that a thyristor operation is occurring.
[0050]
  7 and 8 show a tendency of saturation of Ic. This saturation current value varies depending on the doping level of the p collector layer 9, and the doping level of the p collector layer 9 is changed as shown in FIG. As it increases, the saturation current also increases.
  As can be seen from the Ic-Vge (turn-off) characteristics shown in FIG.²The current capacity of the conventional IGBT can be cut off (approximately 1200 A / cm)²), The current density of 5 times or more can be cut off. In addition, since gate control is possible for Ic, element protection during load short-circuiting is also possible.EasyIt turns out that it becomes.
[0051]
  [Third Embodiment]
  In the first embodiment, the surface cell shape of the emitter trench need not necessarily be a stripe shape. The volume of the p base region 2 is sufficiently small,Second emitter electrode (Eb) 6Other shapes may be used as long as the carrier pulling efficiency by is maintained high.
[0052]
  Therefore, for example, a checkered shape shown in FIG. 11 may be taken as the cell shape. However,Second emitter electrode (Eb) 6The contact hole 14 is necessary to draw out.
  [Fourth Embodiment]
  In the first embodiment, even if the emitter structure is the same as that of the conventional IGBT as shown in FIG. 12, if the width t is narrow, the carrier extraction efficiency from the p base region 2 is maintained to some extent, and from the thyristor operation. Can be shut off.
[0053]
  FIG. 13 is a characteristic diagram showing the dependence of the interruptable current capacity on the interval t of the emitter structure.
  1200A / cm for conventional structure²However, when t is 10 μm or less, the current capacity that can be cut off can be increased as compared with the conventional case. Furthermore, by setting t to 5 μm or less, it is possible to obtain a current capacity that can be interrupted more than twice that of the prior art.
[0054]
  Compared with the first embodiment, since the voltage drop due to the hole current 31 is large, the interruptable current capacity is small, and p⁺Since the contact region 23 exists, it cannot be used as a bidirectional semiconductor element.
  Note that the same argument can be applied to p-channel type IGBTs as long as the above conductivity types are replaced.
[0055]
[Effect of the present invention]
  As described above, according to the present invention, the second trench different from the first trench provided with the gate electrode is dug down, and the second emitter electrode separated from the first emitter electrode is provided in the second trench. Thus, by promoting the discharge of the carrier from the second conductivity type base region, the on-resistance is lower than that of the conventional IGBT and is similar to that of the thyristor, and the turn-off time and turn-off loss are similar to those of the conventional IGBT. Compared with the above, a MOS gate thyristor having a characteristic more than one digit can be obtained. That is, a semiconductor element having the advantages of the conventional IGBT and the advantages of a thyristor can be realized.
[0056]
  Furthermore, the interruptable current capacity is larger than that of a conventional IGBT, and element protection when a load is short-circuited is easier than that of a conventional IGBT or thyristor.
  In addition, the emitter p⁺Since the contact region can be eliminated, the leakage current at the time of reverse breakdown voltage due to this can be reduced, and it can be used as a bidirectional semiconductor device.
[0057]
  Therefore, the MOS gate thyristor according to the present invention contributes to the epoch-making efficiency improvement of the power conversion device.
[Brief description of the drawings]
FIG. 1 is a partial sectional view of a MOS gate thyristor according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a MOS gate thyristor according to the present invention.
FIG. 3 is an explanatory diagram of dimensions of each part of the MOS gate thyristor according to the first embodiment of the present invention.
FIG. 4 is a partial sectional view of a MOS gate thyristor according to a second embodiment of the present invention.
FIG. 5 is a structural diagram of a MOS gate thyristor according to a second embodiment.
FIG. 6 is an enlarged view of the emitter part of the MOS gate thyristor according to the second embodiment.
FIG. 7 is an Ic-Vce characteristic diagram of the MOS gate thyristor according to the second embodiment.
FIG. 8 is an Ic-Vge characteristic diagram of the MOS gate thyristor according to the second embodiment.
FIG. 9 is a characteristic diagram showing the dependence of the Ic-Vce characteristic on the p collector layer concentration.
FIG. 10 is a graph of Ic-Vge characteristics when the p collector layer concentration is high.
FIG. 11 is a perspective sectional view of a MOS gate thyristor according to a third embodiment of the present invention.
FIG. 12 is a partial sectional view of a MOS gate thyristor according to a fourth embodiment of the present invention.
FIG. 13 is a characteristic diagram showing the dependence of the interruptable current on the emitter structure interval t.
FIG. 14 is a partial cross-sectional view of a conventional IGBT.
FIG. 15 is a partial sectional view of a conventional EST.
FIG. 16 is a partial sectional view of a conventional RBT.
FIG. 17 is a partial sectional view of a conventional MOS gate thyristor.
FIGS. 18A to 18D are partial cross-sectional views in order of steps for explaining a method of manufacturing a MOS gate thyristor according to the first embodiment of the present invention;
FIG. 19 is a partial cross-sectional view in order of the steps, explaining the method for manufacturing the MOS gate thyristor according to the first embodiment of the present invention, following FIG.
FIGS. 20A and 20B are partial cross-sectional views in order of steps for explaining a method of manufacturing a MOS gate thyristor according to a second embodiment of the present invention.
FIGS. 21A to 21D are partial cross-sectional views in order of the steps for explaining the manufacturing method of the MOS gate thyristor according to the second embodiment of the present invention following FIG.
[Explanation of symbols]
          1 ... n^-Drift layer
          2 ... p base region
          3 ... n⁺Emitter area
          4… Gate insulation film
          4a, 4b, 4c ... oxide film
          5 ... Gate electrode
          5a… Polycrystalline silicon film
          6 ... Second emitter electrode
          7… Insulating film or interlayer insulating film
          8… First emitter electrode
          9 ... p collector layer
          10 ... Collector electrode
          11 ... MOS gate thyristor
          12 ... MOSFET
          13 ... Hole current
          14 ... Contact hole
          15 ... 1st trench
          16 ... Second trench
          17… Insulating film
          18 ... Thin semiconductor layer
          19 ... Consolidated semiconductor part
          21 ... n^-Drift layer
          22 ... p base region
          23 ... p⁺Contact area
          24 ... n⁺Emitter area
          25… Gate insulation film
          26 ... Gate electrode
          27 ... n + semiconductor region
          28 ... P + semiconductor region
          29 ... Collector electrode
          30 ... Emitter electrode
          31 ... Hole current

Claims (15)

A first conductive type drift layer having a high resistivity, the second conductive type base region and its second conductivity type formed in the surface layer of the base region or Tsu first conductivity type formed in the surface layer of the drift layer A first conductivity type emitter region not connected to the drift layer, a first trench reaching the drift layer dug down from the surface of the first conductivity type emitter region through the second conductivity type base region, and the first trench A gate insulating film formed on the inner wall, a gate electrode provided in the first trench opposite to the second conductivity type base region via the gate insulating film, and a surface of the first conductivity type emitter region a first emitter electrode not in contact with the second conductivity type base region is provided, a second trench et dug from the surface of the first conductive type emitter region is reached before Symbol second conductivity type base region, inside the second trench Set in A second emitter electrode that contacts only the second conductivity type base region and does not contact the first conductivity type emitter region; a second conductivity type collector layer formed on the back side of the first conductivity type drift layer; And a collector electrode provided in contact with the surface of the second conductivity type collector layer. A first conductive type drift layer having a high resistivity, the second conductive type base region and its second conductivity type formed in the surface layer of the base region or Tsu first conductivity type formed in the surface layer of the drift layer A first conductivity type emitter region not connected to the drift layer, a first trench reaching the drift layer dug down from the surface of the first conductivity type emitter region through the second conductivity type base region, and the first trench A gate insulating film formed on the inner wall, a gate electrode provided in the first trench opposite to the second conductivity type base region via the gate insulating film, and a surface of the first conductivity type emitter region The first emitter electrode that does not contact the second conductivity type base region and the surface of the second conductivity type base region sandwiched between the first conductivity type emitter regions contact only the first conductivity type emitter region. Second Emi A second conductivity type collector layer formed on the back side of the first conductivity type drift layer, and a collector electrode provided in contact with the surface of the second conductivity type collector layer. MOS gate thyristor. A gate electrode formed on the first conductivity type drift layer via an insulating film, an insulating film covering a side surface and an upper surface of the gate electrode, and a first conductivity type thin film semiconductor layer formed on the insulating film on the gate electrode A connection semiconductor portion connecting the first conductivity type drift layer and the first conductivity type thin film semiconductor layer through the side portion of the gate electrode, and an end of the first conductivity type thin film semiconductor layer far from the connection semiconductor portion first conductivity type emitter region from parts that are part of are arranged in order and the first-conductivity-type thin film semiconductor layer, a second conductivity type base region, Re et al provided in contact with only the first conductive type emitter region second a first emitter electrode not in contact with the conductive type base region, and a second emitter electrode not in contact with the first one conductivity type emitter region Re et al provided in contact with only the second conductivity type base region, the back surface of the first conductivity type drift layer Second conductivity type core formed on the side Kuta layer and, MOS gate thyristors, characterized by comprising a collector electrode in contact provided on the surface of the second conductivity type collector layer. 4. The MOS gate thyristor according to claim 3, wherein the connecting semiconductor portion is a part of a semiconductor substrate. 4. The MOS gate thyristor according to claim 3, wherein the connecting semiconductor portion is made of a semiconductor thin film layer. 6. The first conductivity type buffer layer having an impurity concentration higher than that of the first conductivity type drift layer is provided between the first conductivity type drift layer and the second conductivity type collector layer. The MOS gate thyristor described in 1. 7. The MOS gate thyristor according to claim 1, wherein the thickness of the second conductivity type collector layer is 1 μm or less. 8. The MOS gate thyristor according to claim 7, wherein an impurity doping level of the second conductivity type collector layer is 10 ¹⁸ cm ⁻³ or less. MOS gate thyristor according to any one of claims 1 to 8 impurity concentration of the second conductivity type base region, characterized in that in the range of 10 ¹⁵ ~10 ¹⁸ cm ^-3. MOS gate thyristor according to claim 1 or 2 shape of drawing flat surface of the first trench, characterized in that a stripe shape. MOS gate thyristor according to claim 1 or 2 shape of drawing flat surface of the first trench is characterized in that it is a lattice or net. MOS gate thyristor according to any one of claims 1 to 11, characterized in that to connect the switching semiconductor element between the first emitter electrode and a second emitter electrode. 13. The MOS gate thyristor according to claim 12 , wherein the switching semiconductor element connected between the first emitter electrode and the second emitter electrode is monolithically formed on the same semiconductor substrate. 14. The MOS gate thyristor according to claim 13 , wherein the switching semiconductor element is a high voltage MOSFET. Claims 12 to switching semiconductor device according to 14, is turned off during on of the MOS gate thyristor, a control method of a MOS gate thyristor, characterized in that it is turned on when turning on the MOS gate thyristor.

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