JP4136393B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The invention relates to the production how a semiconductor device, particularly relates to a n-channel type MOS (Metal Oxide Semiconductor) manufacturing how a semiconductor device having a transistor and a p-channel type MOS transistor.
[0002]
[Prior art]
In a conventional CMOS ( Complementary Metal Oxide Semiconductor ) manufacturing process, activation of the source / drain extension (hereinafter referred to as “extension”) and the source / drain / gate is performed by one activation annealing. In this annealing, the three characteristics of extension of the extension in the lateral direction, impurity activation rate, and gate depletion change.
[0003]
In order to improve the transistor performance, it is better to reduce the thermal budget provided by the activation annealing for the lateral extension of the extension. On the other hand, it is better to increase the thermal budget for impurity activation and gate depletion. For this reason, the performance of the transistor varies greatly depending on the annealing conditions, and the annealing conditions must be set in consideration of the trade-off between these three characteristics.
[0004]
In recent years, the use of a disposal side wall (DSW) process proposed in Japanese Patent Laid-Open No. 6-69439 has been studied for such a problem.
[0005]
In this DSW process, after gate processing, sidewalls are formed without implanting extensions, then impurities are implanted and activation annealing is performed to first form deep sources and drains. Then, after removing the sidewalls, impurities are implanted and activation annealing is performed again to form extensions. Thereby, the implantation conditions and annealing conditions can be set independently for the source / drain / gate and the extension.
[0006]
[Problems to be solved by the invention]
However, it has become difficult to sufficiently respond to the recent demand for further miniaturization of devices even with the conventional DSW process.
[0007]
In general, CMOS extension implantation uses arsenic (As) for an n-channel MOS transistor (hereinafter referred to as “nMOS”) and boron (B) for a p-channel MOS transistor (hereinafter referred to as “pMOS”). It is done. Here, in order to miniaturize the transistor, it is particularly important to optimally design and control the abruptness of the lateral profile of the extension. In this case, arsenic has a characteristic that the impurity profile becomes steeper as the thermal budget given by the activation annealing is increased. On the other hand, boron has a characteristic that the impurity profile becomes steeper when the thermal budget is suppressed.
[0008]
In the conventional technique including the DSW process, as described above, the extension activation annealing is also used for the activation of the deep source / drain, and the activation of the nMOS and the pMOS extension is simultaneously performed. Therefore, for example, it is very difficult to obtain an optimum impurity profile for each extension of nMOS and pMOS such that the thermal budget is insufficient for arsenic and excessive for boron.
[0009]
The present invention has been made in view of these points, and an object thereof is to provide a manufacturing how a semiconductor device having high device performance nMOS and pMOS are optimally designed respectively constituting the CMOS.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a method of manufacturing a semiconductor device that can be realized by the flow shown in FIG. According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an nMOS and a pMOS on a semiconductor substrate; and forming an nMOS formation region where the nMOS is formed and a gate sidewall of the pMOS formation region where the pMOS is formed. Forming a first spacer on the first n-type electrode, and implanting an impurity using the first spacer as a mask, followed by a first activation annealing to form a first impurity in a region to be a source and a drain of the nMOS formation region A step of forming a diffusion region and forming a second impurity diffusion region in a region to be a source and a drain of the pMOS formation region; and the first activation anneal formed on the side wall of the gate after the first activation annealing. of removing the spacer, depositing a first of said semiconductor substrate over the entire surface to the oxide film spacer was removed, the side walls of the gate And forming the thin second spacer than the first spacer on the sidewalls of the formed gate insulating film directly below the preliminary the gate, after forming the second spacer, arsenic or antimony to the nMOS forming area Implanting and performing a second activation annealing to form a third impurity diffusion region shallower than the first impurity diffusion region; and after the second activation annealing, boron is added to the pMOS formation region. And performing a third activation annealing to form a fourth impurity diffusion region shallower than the second impurity diffusion region.
[0011]
According to the manufacturing method of the semiconductor device, the impurity of the third impurity diffusion region or nMOS of d hex tension, until the formation, a second activation annealing at step S7, the third at step S9 The activation annealing is performed twice. On the other hand, the impurity in the fourth impurity diffusion region or pMOS of d hex tension, until the formation, but only through the third activation annealing in step S9. Therefore, a sufficient thermal budget is provided for the nMOS, and the necessary minimum thermal budget is suppressed for the pMOS. That, nMOS, setting pMOS of the activation annealing conditions respectively, can be controlled, it is possible to form an optimum d box tension.
[0012]
Further, in the present invention, the activation of the impurity of the nMOS of d hex tension, and activation of the impurity serving as the source and drain, is performed simultaneously in the first activation anneal, then, pMOS as a second activation annealing perform the error activation of the box tension of impurities. The formation of source and drain, by performing at the same time as the formation of d hex tension, reduce the number of activation annealing, it is possible to simplify the manufacturing process.
[0013]
Thus, nMOS, by forming an optimum error box tension to each of the pMOS, so improving the miniaturization and the device performance of the semiconductor device can be achieved.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to the present invention.
[0015]
First, gates are formed in a region where an nMOS is formed on a p-type silicon substrate (hereinafter referred to as “nMOS formation region”) and a region where a pMOS is formed (hereinafter referred to as “pMOS formation region”). Then, a first spacer serving as a DSW is formed on the gate side wall (step S1).
[0016]
Next, using this first spacer as a mask, impurities to be a source and a drain are implanted into the p-type silicon substrate (step S2). In order to activate the implanted impurities, first activation annealing is performed (step S3), and a source and a drain are formed in the p-type silicon substrate.
[0017]
After the formation of the source and drain, the first spacer formed on the gate sidewall is removed (step S4), and this time, a second spacer thinner than the first spacer is formed on each gate sidewall (step S5). ).
[0018]
Then, an nMOS extension impurity is implanted into the nMOS formation region (step S6), and second activation annealing is performed on the entire surface (step S7) to form an nMOS extension. Subsequently, an impurity of a pMOS extension is implanted into the pMOS formation region (step S8), and third activation annealing is performed on the entire surface (step S9) to form a pMOS extension.
[0019]
As described above, in the method of manufacturing a semiconductor device according to the present invention, the three-stage activation called the first, second, and third activation annealing is performed. Of these three stages of activation annealing, the nMOS extension is formed through the second and third activation annealings, and the pMOS extension is formed only through the third activation annealing.
[0020]
Here, the change of the impurity profile due to the activation annealing in the extension formation will be described with reference to FIGS.
FIG. 2 is a schematic diagram showing impurity profiles of nMOS before and after activation annealing.
[0021]
Arsenic is used as an impurity of the nMOS extension. The ion implantation conditions are an energy of 5 keV or less and a concentration of about 1 × 10 ¹⁵ cm ⁻² . By this ion implantation, before the activation annealing, arsenic shows an impurity profile in which the concentration gradually decreases as the implantation depth increases.
[0022]
After arsenic ion implantation, activation annealing at a temperature of about 1000 ° C. is performed for activation. After this activation annealing, arsenic exhibits a steep impurity profile close to a box shape due to the arsenic diffusion mechanism in which diffusion is promoted in a higher concentration region. Therefore, the nMOS approaches an ideal impurity profile by this activation annealing.
[0023]
FIG. 3 is a schematic diagram showing the impurity profile of the pMOS before and after activation annealing.
Boron (including boron difluoride) is used as an impurity of the pMOS extension. Typical ion implantation conditions for boron are an energy of 0.5 keV or less and a concentration of about 1 × 10 ¹⁵ cm ⁻² . By this ion implantation, before activation annealing, boron exhibits an impurity profile in which the concentration gradually decreases as the depth of implantation increases.
[0024]
When activation annealing is performed after boron ion implantation, unlike the case of arsenic shown in FIG. 2, the steepness of the impurity profile is lost due to the diffusion mechanism of boron that promotes diffusion in the lower concentration region. . That is, the impurity profile of the pMOS is the steepest impurity profile before the activation annealing, and it is more ideal to keep the state before the activation annealing by suppressing the activation annealing as much as possible.
[0025]
When an impurity having such characteristics is used, according to the method for manufacturing a semiconductor device according to the present invention, in the nMOS, arsenic is formed by the second and third activation annealings performed in steps S7 and S9. Give enough thermal budget. Thereby, the nMOS can be brought close to an ideal impurity profile. On the other hand, in the pMOS, only the minimum necessary thermal budget is given to boron by the third activation annealing performed in step S9. This makes it possible to keep the pMOS, a state close to an ideal impurity profile. Therefore, the activation annealing conditions for nMOS and pMOS can be set and controlled, respectively, and an optimum extension can be formed for nMOS and pMOS. Thereby, it becomes possible to miniaturize the CMOS device and improve its performance.
[0026]
Next, the embodiment of the present invention will be specifically described with reference to FIGS.
FIG. 4 is an explanatory diagram of the first spacer forming process.
[0027]
First, an element isolation region 2 is formed on a p-type silicon substrate 1 by an STI (Shallow Trench Isolation) method. Next, a resist is formed in the nMOS formation region on the p-type silicon substrate 1. Then, an impurity such as phosphorus (P) is ion-implanted into the opening pMOS formation region to form an n-well 3.
[0028]
Next, an oxide film is formed on the surface of the p-type silicon substrate 1 by a thermal oxidation method. Subsequently, gate polysilicon is deposited on the oxide film with a film thickness of about 100 nm using a CVD method. A resist is again formed on the entire surface of the p-type silicon substrate 1, and a resist pattern is formed by exposure and development. Then, using this resist pattern as a mask, reactive ion etching (RIE) with high selectivity is performed on the gate polysilicon. Thereby, gates 4a and 4b and gate oxide films 5a and 5b are formed in the nMOS formation region and the pMOS formation region, respectively.
[0029]
Thereafter, an oxide film having a thickness of about 50 nm to 100 nm is further deposited on the entire surface of the p-type silicon substrate 1 by CVD, and etched back by RIE until the upper portions of the gates 4a and 4b are exposed. Thus, first spacers 6a and 6b, which are DSW, are formed on the side walls of the gates 4a and 4b and the gate oxide films 5a and 5b, respectively.
[0030]
FIG. 5 is an explanatory diagram of a source and drain formation process.
After the formation of the first spacers 6a and 6b, first, a resist is formed in the pMOS formation region on the p-type silicon substrate 1, and impurities such as phosphorus are implanted into the open nMOS formation region by ion implantation. inject. The ion implantation conditions for phosphorus ion implantation are an energy range of 3 keV to 15 keV and a concentration range of 1 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² .
[0031]
After the resist is removed, a resist is formed in the nMOS formation region and an impurity such as boron is implanted into the pMOS formation region by an ion implantation method. The implantation conditions for boron ion implantation are an energy range of 2 keV to 5 keV and a concentration range of 1 × 10 ¹⁵ cm ⁻² to 5 × 10 ¹⁵ cm ⁻² .
[0032]
After ion implantation into the nMOS formation region and the pMOS formation region, in order to activate the implanted impurities, for example, first activation annealing is performed at a temperature of 1050 ° C. or more for a time of 0 to 1 second. When the time for the first activation annealing is 0 second, the temperature is lowered when the predetermined temperature is reached. By this first activation annealing, the sources 7a and 7b and the drains 8a and 8b are formed in the nMOS formation region and the pMOS formation region.
[0033]
In the first activation annealing, heat necessary and sufficient for activating the sources 7a and 7b and the drains 8a and 8b is applied to increase the impurity activation rate and suppress gate depletion.
[0034]
FIG. 6 is an explanatory diagram of the first spacer removal step.
After completion of the first activation annealing, the first spacers 6a and 6b shown in FIG. 5 are removed using a chemical such as hydrogen fluoride (HF).
[0035]
FIG. 7 is an explanatory diagram of the formation process of the second spacer.
After removing the first spacers 6a and 6b, an oxide film having a thickness of about 5 nm to 10 nm is deposited on the entire surface of the p-type silicon substrate 1 by the CVD method. Then, this oxide film is etched back using RIE to form second spacers 9a and 9b on the side walls of gate 4a and gate oxide film 5a, and gate 4b and gate oxide film 5b, respectively.
[0036]
The thickness of the second spacer 9a is over nMOS of extension, the second, after the third activation Annie Le performed under the conditions described below, from about 5nm to about 7nm inner side with respect to the gate 4a Set to wrap. Similarly, the thickness of the second spacer 9b are, pMOS the extension, after the third activation Annie Le performed under the conditions described below, overlap from about 5nm to about 7nm inner side with respect to the gate 4b Set to form.
[0037]
FIG. 8 is an explanatory diagram of an nMOS extension forming process.
After the formation of the second spacers 9a and 9b, a resist 10 is formed in the pMOS formation region by exposure / development processing, and only the nMOS formation region is opened. Then, boron as pocket impurities is ion-implanted into the nMOS formation region at an angle of 7 degrees to 30 degrees from the normal incidence condition in an energy range of 5 keV to 10 keV.
[0038]
Subsequently, arsenic is ion-implanted as an impurity of the nMOS extension in the energy range of 1 keV to 5 keV and in the concentration range of 5 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² .
[0039]
Then, after the resist 10 is stripped, at this time, for example, a second activation annealing is performed at a temperature in the range of 950 ° C. to 1000 ° C. for 0 to 1 second. When the second activation annealing time is 0 second, the temperature is lowered when the predetermined temperature is reached. By this second activation annealing, an nMOS pocket 11a is formed in the p-type silicon substrate 1 in the nMOS formation region, and an nMOS extension 12a is formed in a region shallower than the nMOS pocket 11a.
[0040]
This second activation annealing can be performed under the optimum conditions for the nMOS extension 12a without considering the diffusion of boron, since the impurity is not yet ion-implanted in the region for forming the pMOS extension. That is, the second activation annealing can be performed under conditions that make the impurity profile steeper.
[0041]
FIG. 9 is an explanatory diagram of a process for forming a pMOS extension.
Following the formation of the pocket 11a and the nMOS extension 12a, a resist 13 is formed in the nMOS formation region. Then, arsenic as pocket impurities is ion-implanted into the opening pMOS formation region at an angle of 7 to 30 degrees from the normal incidence condition in an energy range of 30 to 100 keV.
[0042]
Subsequently, boron is ion-implanted as an impurity of the pMOS extension in an energy range of 0.2 keV to 1 keV in a concentration range of 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² .
[0043]
After the resist 13 is peeled off, for example, a third activation annealing is performed for a time of 0 second for decreasing the temperature when the temperature reaches a predetermined temperature in the range of 900 ° C. to 1000 ° C. By this third activation annealing, a pMOS pocket 11b is formed in the p-type silicon substrate 1 in the pMOS formation region, and a pMOS extension 12b is formed in a region shallower than the pMOS pocket 11b.
[0044]
This third activation annealing is performed under the optimum conditions for the pMOS extension 12b so as to suppress the diffusion of ion-implanted boron as much as possible. At this time, the previously formed nMOS extension 12a can further apply a thermal budget to arsenic that has already been ion-implanted.
[0045]
FIG. 10 is an explanatory diagram of a third spacer forming process.
After the third activation annealing, a nitride film or an oxide film having a thickness of about 50 nm to 100 nm is deposited on the entire surface of the p-type silicon substrate 1 by the CVD method. Then, this nitride film or oxide film is etched back by RIE to form third spacers 14a and 14b covering the extensions 12a and 12b on the side walls of the second spacers 9a and 9b, respectively.
[0046]
FIG. 11 is an explanatory diagram of a process for forming cobalt silicide.
After the formation of the third spacers 14a and 14b shown in FIG. 10, the cobalt silicide 15 is formed on the surfaces of the sources 7a and 7b, the drains 8a and 8b, and the gates 4a and 4b by a salicide process using cobalt (Co). To do.
[0047]
The subsequent steps are in accordance with a conventionally known MOSFET manufacturing process.
As described above, in the nMOS, a sufficient thermal budget is given to arsenic by the second and third activation annealing, and in the pMOS, the boron thermal budget is minimized by the third activation annealing. This makes it possible to form optimal extensions for each of the nMOS and the pMOS, thereby miniaturizing the CMOS device and improving the performance.
[0048]
In the above description, when the pMOS extension 12b shown in FIG. 9 is formed, the second spacer 9b is removed before ion implantation of boron, and then boron is applied to the p-type silicon substrate 1. Ion implantation may be performed. Alternatively, when forming the pMOS extension 12b, the second spacer 9b can be thinned using a method such as wet etching before boron ion implantation, and then boron ion implantation can be performed. That is, the thicknesses of the second spacers 9a and 9b are made different depending on the diffusion mechanism of impurities implanted in the nMOS extension 12a and the pMOS extension 12b. As a result, the degree of freedom in designing the nMOS extension 12a and the pMOS extension 12b is further increased, and the optimum design becomes possible.
[0049]
In addition, the formation of the sources 7a and 7b and the drains 8a and 8b and the extension 12a in the above description can be simultaneously performed by one activation annealing.
[0050]
In this case, first spacers 6a and 6b are first formed, and impurities to be the sources 7a and 7b and drains 8a and 8b are ion-implanted, and then the first spacers 6a and 6b are removed. Next, after forming the second spacers 9a and 9b and implanting impurities to become the nMOS pocket 11a and the nMOS extension 12a, the first activation annealing is performed at a temperature of 1000 ° C. to 1050 ° C. for a time of 0 seconds, for example. Do. By this first activation annealing, the nMOS pocket 11a and the nMOS extension 12a are formed, and the sources 7a and 7b and the drains 8a and 8b are formed. Thereafter, similarly to the above manufacturing method, the pMOS forming region, pMOS pocket 11b, after implanting impurity serving as p MOS extension 12b, a second activation time 0 seconds in the range of 1000 ° C. from the temperature 900 ° C. Annealing is performed to form the pMOS pocket 11b and the pMOS extension 12b.
[0051]
Further, also in this case, when the pMOS extension 12b is formed, the second spacer 9b is removed or thinned before boron ion implantation, and then boron ions are implanted into the p-type silicon substrate 1. it can.
[0052]
In the above description, the case of manufacturing a CMOS having a single well structure is taken as an example. However, the method for manufacturing a semiconductor device of the present invention is not limited to such a well structure.
[0053]
In the above description, as the impurity of the nMOS extension 12a, antimony (Sb) or the like can be used in addition to arsenic . Further, indium (In) or the like can be used for the nMOS pocket 11a, and antimony or the like can be used for the pMOS pocket 11b.
[0054]
【The invention's effect】
As described above, in the present invention, after the source and drain are formed by the first activation annealing, the second activation annealing is performed after the impurity implantation of the extension of the n-channel MOS transistor is performed, and the p-channel MOS transistor The third activation annealing is performed after the extension impurity is implanted. As a result, the n-channel MOS transistor and the p-channel MOS transistor constituting the CMOS can be optimally designed, and a semiconductor device having high device performance can be manufactured.
[Brief description of the drawings]
FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to the present invention.
FIG. 2 is a schematic diagram showing impurity profiles of nMOS before and after activation annealing.
FIG. 3 is a schematic diagram showing impurity profiles of pMOS before and after activation annealing.
FIG. 4 is an explanatory diagram of a formation process of a first spacer.
FIG. 5 is an explanatory diagram of a process for forming a source and a drain.
FIG. 6 is an explanatory diagram of a first spacer removal step.
FIG. 7 is an explanatory diagram of a formation process of a second spacer.
FIG. 8 is an explanatory diagram of a process of forming an nMOS extension.
FIG. 9 is an explanatory diagram of a process for forming a pMOS extension.
FIG. 10 is an explanatory diagram of a third spacer formation step.
FIG. 11 is an explanatory diagram of a process for forming cobalt silicide.
[Explanation of symbols]
1 p-type silicon substrate 2 element isolation region 3 n well 4a, 4b gate 5a, 5b gate oxide film 6a, 6b first spacer 7a, 7b source 8a, 8b drain 9a, 9b second spacer 10 resist 11a nMOS pocket 11b pMOS pocket 12a nMOS extension 12b pMOS extension 13 resists 14a and 14b third spacer 15 cobalt silicide

Claims (4)

In a method for manufacturing a semiconductor device in which an n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate,
Forming a first spacer on a side wall of a gate of an nMOS formation region where the n-channel MOS transistor is formed and a pMOS formation region where the p-channel MOS transistor is formed;
After the impurity implantation using the first spacer as a mask, a first activation annealing is performed to form a first impurity diffusion region in a region to be a source and a drain of the nMOS formation region, and the pMOS formation region Forming a second impurity diffusion region in a region to be a source and a drain;
Removing the first spacer formed on the side wall of the gate after the first activation annealing;
An oxide film is deposited on the entire surface of the semiconductor substrate from which the first spacer has been removed, and a second spacer thinner than the first spacer is formed on the side wall of the gate and the side wall of the gate insulating film formed immediately below the gate. Forming a step;
After the formation of the second spacer, arsenic or antimony is implanted into the nMOS formation region, and second activation annealing is performed to form a third impurity diffusion region shallower than the first impurity diffusion region. When,
After the second activation annealing, implanting boron into the pMOS formation region, performing a third activation annealing, and forming a fourth impurity diffusion region shallower than the second impurity diffusion region;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein when boron is implanted into the pMOS formation region, the boron is implanted after removing the second spacer in the pMOS formation region.   2. The method of manufacturing a semiconductor device according to claim 1, wherein, when boron is implanted into the pMOS formation region, the boron is implanted after the second spacer in the pMOS formation region is thinned. In a method for manufacturing a semiconductor device in which an n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate,
Forming a first spacer on a side wall of a gate of an nMOS formation region where the n-channel MOS transistor is formed and a pMOS formation region where the p-channel MOS transistor is formed;
Using the first spacer as a mask, a first impurity diffusion region and a second impurity diffusion region are formed in a region to be a source and a drain of the nMOS formation region and a region to be a source and a drain of the pMOS formation region, respectively. A step of implanting impurities for
Removing the first spacer formed on the side wall of the gate after the implantation;
An oxide film is deposited on the entire surface of the semiconductor substrate from which the first spacer has been removed, and a second spacer thinner than the first spacer is formed on the side wall of the gate and the side wall of the gate insulating film formed immediately below the gate. Forming a step;
After the formation of the second spacer, arsenic or antimony is implanted into the nMOS formation region, and a first activation annealing is performed, so that the first impurity diffusion region, the second impurity diffusion region, and the first impurity diffusion region are formed. Forming a third impurity diffusion region shallower than the one impurity diffusion region;
After the first activation annealing, implanting boron into the pMOS formation region, performing a second activation annealing, and forming a fourth impurity diffusion region shallower than the second impurity diffusion region;
A method for manufacturing a semiconductor device, comprising:

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