JP4136646B2 - Semiconductor memory device and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including a nonvolatile rewritable memory cell and a control method thereof.
[0002]
A semiconductor memory device having a nonvolatile and rewritable memory cell uses a high voltage or a negative voltage generated by a voltage generation circuit inside the device for a write operation (program mode) or an erase operation (erase mode). To do. These voltages are applied to the memory cell with a predetermined pulse width during a write operation or an erase operation. Parameters (operation control parameters) for setting voltage values, pulse widths, and the like in these various operations (operation modes) are set to values that are expected to be optimum at the time of design, and a circuit is designed according to the set values.
[0003]
However, there are many cases in which the optimum value at the time of design (for each product chip after the actual wafer process step) deviates from the optimum value due to manufacturing variations and simulation accuracy. These parameters can be adjusted by changing the circuit with mask changes, but it takes time to change and time to market is an important factor. Moreover, it cannot respond to individual product manufacturing variations.
[0004]
For this reason, some semiconductor memory devices are provided with fuses for setting parameters corresponding to manufacturing variations of individual product chips. It is also possible to test individual product chips and cut the fuse with a laser or the like based on the test results. However, the fuse that can be laser cut has a large area of the fuse itself, which leads to an increase in die size, and an increase in the laser process, resulting in an increase in test cost.
[0005]
In addition, it cannot cope with the number of times of rewriting unique to the nonvolatile memory, or change of (operation control) parameter according to the number of times of rewriting. For this reason, it is desired to deal with software by writing (operation control) parameters that need to be adjusted after manufacturing into a control storage area.
[0006]
[Prior art]
2. Description of the Related Art Conventionally, there is a memory system in which memory control information is stored in a dedicated non-volatile storage area and can be changed in software after manufacture (for example, see Patent Document 1 and Patent Document 2). This memory system comprises a non-volatile data storage unit in which the state of control parameter bits including control parameter CP1 is stored separately from an array of flash memory cells provided to the user (accessed by the user). Yes. By storing parameter information such as word configuration, read reference current, internally generated voltage, control pulse width, etc. in this area, the memory system can be controlled.
[0007]
[Patent Document 1]
Japanese National Patent Publication No. 10-510656 (FIG. 1)
[Patent Document 2]
JP 2001-57096 A (FIG. 1)
[0008]
[Problems to be solved by the invention]
However, in the prior art, the non-volatile data storage unit is provided in a separate area from the array of flash memory cells provided to the user. For this reason, a write / read circuit dedicated to the control (operation control) parameter area is required, and there is a problem that the circuit area increases.
[0009]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of suppressing an increase in circuit area and a control method thereof.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the invention described in claim 1 includes a first memory cell to which an external address is assigned and a second memory cell to which an external address is not assigned. Cell , Controlling a read operation to the first memory cell Provided for memory control information, the first and second memory cells are connected to a bit line common to both memory cells, connected to the bit line, and the information of the first memory cell is A first read circuit for reading, a second read circuit connected to the bit line, for reading information of the second memory cell, and an output signal of the second read circuit are connected to the first read circuit.
[0011]
The invention according to claim 2 includes a first memory cell to which an external address is assigned, and a second memory cell to which no external address is assigned, wherein the first and second memory cells are nonvolatile. And the second memory cell is rewritable. , Controlling a read operation to the first memory cell Provided for memory control information, the first and second memory cells are connected to a common bit line and source line for both memory cells, connected to the bit line, and the first memory cell The first read circuit for reading the information, the second read circuit connected to the bit line for reading the information of the second memory cell, and the output signal of the second read circuit connected to the first read circuit Is done.
[0012]
According to a third aspect of the present invention, the first memory cells are arranged in an array of a plurality of the bit lines and a plurality of first word lines, and the plurality of first word lines are based on an address signal. The second memory cell is connected to the decoder via a second word line.
[0013]
According to a fourth aspect of the present invention, the first memory cell and the second memory cell are connected to a common source voltage supply circuit via a common source line for both memory cells.
[0014]
According to a fifth aspect of the present invention, the first read circuit includes a read reference current generation unit and a difference current to which the read reference current line and the bit line that are outputs of the read reference current generation unit are input. And an output signal of the second read circuit is input to the read reference current generator, and changes the read reference current value according to the memory control information.
[0015]
According to a sixth aspect of the present invention, the read reference current generation unit receives a first reference signal that is a first reference current of first polarity information (0 or 1) of the memory cell data, and the first reference current And a second reference signal that is a second reference current of the second polarity information (1 or 0) opposite to the first polarity information of the memory cell data is input to the second constant signal. A second constant current unit for generating a current, and an output signal of the second read circuit is connected to the second constant current unit and changes a read reference current value according to the memory control information.
[0016]
According to a seventh aspect of the present invention, the second constant current unit has a second reference current multiplied by a constant j (0 <j <1) times the driving capability of the first constant current unit according to the memory control information. Generated current.
[0017]
According to an eighth aspect of the present invention, the semiconductor memory device includes a write amplifier connected to the bit line and a change with time of the memory cell. , Said second memory cell Remembered Memory control information is rewritten by the write amplifier, and a second read circuit that reads information of the rewritten second memory cell, and the rewritten Above An output signal of the second read circuit, which is memory control information, is connected to the first read circuit.
[0018]
The invention according to claim 9 is a first memory cell to which an external address is assigned; Control a read operation to the first memory cell. A method of controlling a semiconductor memory device in which a second memory cell provided for memory control information and not assigned an external address is connected to a bit line common to both memory cells, and Accessing the second memory cell through a second read circuit; and output information of the second read circuit According to the operating conditions determined according to The first memory cell by the row decoder The second 1 which includes access through a read circuit.
[0019]
The invention according to claim 10 includes first and second rewritable memory cells that are nonvolatile and rewritable, and the second memory cells are , Controlling a read operation to the first memory cell Provided for memory control information, an external address is assigned to the first memory cell, and an external address is not assigned to the second memory cell. A common bit line and source are used for both memory cells. A method of controlling a semiconductor memory device connected to a line, comprising: accessing a second memory cell through a second read circuit by a row decoder; and output information of the second read circuit According to the operating conditions determined according to The first memory cell by the row decoder The second 1 which includes access through a read circuit.
[0020]
As in the eleventh aspect of the invention, in accordance with the change with time of the memory cell , Said second memory cell Remembered in the A step 3 for rewriting and accessing the memory control information by a write amplifier, the step 3 being executed prior to the step 1 for accessing the second memory cell, and the step 1 for accessing the second memory cell; Is performed prior to step 2 of accessing the first memory cell.
[0021]
As in the twelfth aspect of the present invention, the steps 1 to 3 are performed in a state where the power source of the semiconductor memory device is turned on and maintained.
[0022]
According to a thirteenth aspect of the present invention, the step 2 of reading information of the first memory cell is a step of comparing a read reference current value with a current value of the first memory cell. 2 The read reference current value is changed according to the output information of the read circuit.
[0023]
15. The method according to claim 14, wherein the step 2 of reading information of the first memory cell includes a first reference current which is first polarity information (0 or 1) of the memory cell data and the memory cell. A step of comparing a read reference current value obtained by combining a second reference current which is second polarity information (1 or 0) opposite to the first polarity information of data with a current value of the first memory cell. The read reference current value is changed according to the output information of the second read circuit.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0025]
FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device (flash memory, nonvolatile memory).
The flash memory 10 includes a memory cell array 11. In the memory cell array 11, a plurality of memory cells Ce described later are arranged in an array. The memory cell Ce is a non-volatile and rewritable memory cell.
[0026]
The memory cell array 11 includes a first area (user area) 11a and a second area (control information area) 11b provided adjacent to each other. The first area 11a is an area to which an external address is assigned. That is, the first area 11a is an area accessed from a circuit such as a CPU to which the flash memory 10 is connected (or mounted). The second area 11b is an area to which no external address is assigned (control information area), and memory control information is stored in the second area 11b.
[0027]
The memory control information is an operation control parameter, and is parameter information such as word configuration, read reference current, internally generated voltage, control pulse width, and the like.
In the first region 11a, a plurality of memory cells Ce are arranged in an array by a plurality of first word lines WLa and a plurality of bit lines BL. In the first region 11a, a pair of reference cells (not shown) are arranged for each memory cell in a row unit. The reference cell is a cell for generating a current serving as a reference for determining the read data when the memory cell Ce is read. In the second region 11b, in the present embodiment, a plurality of memory cells Ce are arranged in a column by one second word line WLb and a plurality of bit lines BL.
[0028]
FIG. 3 is a partial circuit diagram illustrating a configuration example of the memory cell array 11.
Each word line WLa, WLb includes a first selected word line SWLxa, a second selected word line SWLxb, and a control word line CWLx (x = 0 to n, where n is the number of word lines). That is, in FIG. 3, the first word line WLa is composed of first selected word lines SWL1a, SWL2a, second selected word lines SWL1b, SWL2b and control word lines CWL1, CWL2, and the second word line WLb is the first selected. A word line SWL0a, a second selected word line SWL0b, and a control word line CWL0 are included.
[0029]
The second region 11b is provided with a plurality of memory cells Ce (Ce0a, Ce1a, Ce0b, Ce1b, Ce2a, Ce3a in the figure). Two memory cells (Ce0a, Ce1a) (Ce0b, Ce1b) (Ce2a, Ce3a) adjacent in the column direction share a bit line BL (BL0, BL1, BL2 in the figure). The memory cells Ce0a, Ce1a, Ce0b, Ce1b, Ce2a, and Ce3a are connected to source lines SL0a, SL0b, SL1a, SL1b, SL2a, and SL2b that are separated for each column.
[0030]
The memory cells Ce0a, Ce1a, Ce0b, Ce1b, Ce2a, Ce3a arranged in the column direction are connected to the control word line CWL0.
In each memory cell in each row unit, one cell Ce0a, Ce0b, Ce2a out of two cells sharing the bit line BL with each other is connected to the same selected word line SWL0a as the first selected word line. The other cells Ce1a, Ce1b, and Ce3a are connected to the same selected word line SWL0b as the second selected word line.
[0031]
Similarly to the above, other memory cells Ce0c, Ce1c, Ce0d, Ce1d, Ce2c, Ce3c provided in the first region 11a are also selected word lines SWL1a, SWL1b, SWL2a, SWL2b, control word lines CWL1, CWL2,. Bit lines BL0, BL1, and BL2 are connected to source lines SL0a, SL0b, SL1a, SL1b, SL2a, and SL2b.
[0032]
As shown in FIG. 1, the first word line WLa and the second word line WLb are connected to the X decoder 12, and the bit line BL is controlled as a Y pass gate 13 as a first read circuit and a second read circuit. The information reading circuit 14 is connected. The source lines SL0a to SL2b shown in FIG. 2 are connected to the write driver 15.
[0033]
The flash memory 10 includes first to third voltage generation circuits 16 to 18. The first voltage generation circuit 16 is a negative voltage generation circuit, and generates a negative voltage (for example, −9.3 V in this embodiment) as a first control voltage supplied to the control word line CWL to the X decoder 12. Supply. The second voltage generation circuit 17 is a high voltage generation circuit that generates a high voltage (for example, 9.5 V in this embodiment) as a second control voltage to be supplied to the control word line CWL and supplies the high voltage to the X decoder 12. To do. The third voltage generation circuit 18 is a high voltage generation circuit that generates a high voltage (for example, 6.0 V in this embodiment) as a first source voltage to be supplied to the source line SL and supplies the high voltage to the write driver 15. . The first to third voltage generation circuits 16 to 18 are driven by the oscillator 19 to generate each voltage based on the reference voltage supplied from the reference voltage generation circuit 20.
[0034]
The flash memory 10 includes an address control circuit 21. The address control circuit 21 includes an address buffer 21a and an address counter 21b.
[0035]
The address buffer 21a takes in the write address WD-ADDR supplied from the outside in byte units [0: 7] and outputs them to the X decoder 12 and the Y decoder 22, respectively.
[0036]
More specifically, the address buffer 21a outputs the upper 5 bits of the write address WD-ADDR used for selecting the control word line CWL at the time of writing to the X decoder 12 as a row address. The X decoder 12 decodes it and selects any one of the plurality of control word lines CWL.
[0037]
The address buffer 21a outputs the lower 3 bits of the write address WD-ADDR used for selecting the source line SL at the time of writing to the Y decoder 22 as a column address. The Y decoder 22 decodes it, takes in the write data to the corresponding source voltage supply circuit, and sets the source voltage.
[0038]
The address counter 21b generates a 3-bit internal address for selecting the memory cell Ce corresponding to the 8-bit read data R-MDATA [0: 7] for each bit. Therefore, the Y decoder 22 sequentially selects the memory cells Ce to be read based on the address output from the address counter 21b, and is read out bit by bit by the read amplifier 24 as the first read circuit, and has 8 bits. The data is sequentially latched in the read data latch.
[0039]
The flash memory 10 includes a read / write control circuit 23. Various control signals such as a write mode signal WRITE-MODE are input to the read / write control circuit 23, and the control signal is a mode signal for operating the flash memory 10 in a special operation mode (in this embodiment, Test mode signal TS) as a test signal. The read / write control circuit 23 supplies each circuit with a control signal generated corresponding to the operation mode based on various control signals.
[0040]
For example, at the time of writing, the read / write control circuit 23 shifts to a write operation in response to a write mode signal WRITE-MODE as a write signal, and writes write data W-MDATA in response to a data transfer signal WRITE-MDATA. Start importing.
[0041]
Then, after all the data of the memory cell Ce to be written is taken in, writing to the memory cells Ce connected to the same control word line CWL is started in response to the write start signal WRITE-START.
[0042]
On the other hand, at the time of reading, the read / write control circuit 23 starts reading in response to the read request signal RD-REQ. Data read from the memory cell Ce to be read is output from the Y pass gate 13 to the read amplifier 24, and read data R-MDATA in byte units [0: 7] is output from the read amplifier 24.
[0043]
A read control circuit 25 is connected to the control information read circuit 14. The control information reading circuit 14 is a circuit for reading the memory control information stored in the second area 11b of the cell array 11, and reads the memory control information from the second area 11b according to the timing set by the read control circuit 25. The timing is the initialization process of the flash memory 10. That is, the control information reading circuit 14 reads memory control information from the second area 11b when the flash memory 10 is initialized. Then, the control information reading circuit 14 latches the read memory control information and outputs it to a circuit for setting it. In the present embodiment, the set value of the read reference current stored as the memory control information is read and the set value is output to the read amplifier 24.
[0044]
The flash memory 10 may be provided with a latch circuit, and the latch function of the control information reading circuit 14 may be realized by the latch circuit. Alternatively, the set value of the internally generated voltage stored as the memory control information in the second area 11b may be read and the set value may be output to the voltage generation circuits 16 to 18, the reference voltage generation circuit 20, and the like.
[0045]
The memory control information is written only in a mode that is not normally used (in this embodiment, a test mode). More specifically, the read / write control circuit 23 outputs a control signal to the X decoder 12 in response to the test mode signal TS. The X decoder 12 selects and activates one of the plurality of first word lines WLa based on the external write address WD-ADDR, and the control supplied from the read / write control circuit 23. And a driver unit 12b for activating the second word line WLb in response to the signal. That is, the memory cell Ce connected to the second word line WLb is activated in the test mode. In that mode, externally supplied write data W-MDATA is supplied to the activated memory cell Ce via the write driver 15 and the bit line BL, and is stored as memory control information in the memory cell Ce in the second area 11b. Remembered.
[0046]
The memory control information stored in the memory cell Ce is read during the initialization process of the flash memory 10 and set in the read amplifier 24. The read amplifier 24 adjusts the circuit based on the set value. In the normal operation mode, the read amplifier 24 outputs read data R-MDATA obtained by amplifying the data read from the first region 11a through the bit line BL and the Y pass gate 13 by the adjusted circuit.
[0047]
Similarly to the memory cell Ce in the second area 11b, the memory cell Ce in the first area 11a includes a memory in which write data W-MDATA supplied from the outside is activated via the write driver 15 and the bit line BL. It is supplied to the cell Ce and stored in the memory cell Ce.
[0048]
That is, in the flash memory 10 of the present embodiment, the second area 11b for storing the memory control information is provided adjacent to the first area 11a for storing the user data, and the memory cells Ce of the areas 11a and 11b are connected to the memory cell Ce. A circuit (write driver 15) for writing is shared. Therefore, the circuit area of the flash memory 10 does not increase as compared with the case where the memory area for the user and the memory area (control information area) for storing the memory control information are formed apart from each other.
[0049]
FIG. 2 is a partial block diagram showing a detailed configuration of the flash memory 10.
FIG. 2 shows two memory cells Ce assigned to the first region 11a and two memory cells Ce assigned to the second region 11b. These memory cells Ce are connected to the selected word line SWL0a and the bit lines BL0 and BL1 shown in FIG. 3 (Ce0a and Ce0b in the figure), and to the selected word line SWL1a and the bit lines BL0 and BL1. It corresponds to the memory cell (Ce0c, Ce1c in the figure).
[0050]
The write driver 15 includes source voltage supply circuits 32 and 33 corresponding to the source lines SL connected to the memory cells Ce in the column direction, respectively. The source voltage supply circuits 32 and 33 are similarly configured.
[0051]
More specifically, the source voltage supply circuits 32 and 33 are provided corresponding to the source lines SL (source lines SL0a and SL1a in FIG. 3) connected to the memory cells Ce0a, Ce0c, Ce0b, and Ce0d, respectively. The source voltage supply circuits 32 and 33 take in the write data W-MDATA supplied from the outside in byte units [0: 7] based on the address decoding result by the Y decoder 22. Then, the source voltage supply circuits 32 and 33 supply the first or second source voltage corresponding to the captured data (“0” or “1”) to the source line SL.
[0052]
The Y pass gate 13 is provided with a Y selection gate 34.
The Y selection gate 34 activates the pair of bit lines BL0 based on the decode signal from the Y decoder 22. The Y selection gate 34 outputs a read signal RDB based on data read from one memory cell Ce0c via the pair of bit lines BL0.
[0053]
The read amplifier 24 includes a read reference current generation circuit 35 and a sense amplifier 36.
The read reference current generation circuit 35 receives a reference cell Y selection gate (not shown) read signal, receives a first reference signal SAref0 which is a read current (first reference current) of data “0”, and data “1”. The second reference signal SAref, which is a read current (second reference current).
[0054]
The sense amplifier 36 compares the read reference current generated based on the first and second reference signals SAref0 and SAref with the read current generated based on the read signal RDB output from the Y selection gate 34. Then, based on the comparison result, it is determined whether the data in the memory cell Ce0c is “1” or “0”, and read data RDATAB is output.
[0055]
The X decoder 12 includes a word line applied voltage selection circuit 37, a word line driver 38 constituting the decoder unit 12a, and a word line driver 39 constituting the driver unit 12b.
[0056]
The word line applied voltage selection circuit 37 selects and outputs the applied voltage VCWL supplied to the control word line CWL. Specifically, the negative first control voltage supplied from the first voltage generation circuit 16 is selected during erasing, and the read voltage VCWL-RD supplied from the read reference current generation circuit 35 is selected during reading. To the word line drivers 38 and 39.
[0057]
The word line driver 38 selects any one control word line CWL based on the decoding result of the write address WD-ADDR by the X decoder 12 when writing to the first region 11a. Then, a negative first control voltage is supplied during erasure, a high second control voltage generated by the second voltage generation circuit 17 is supplied during programming, and a read voltage VCWL-RD is supplied during reading.
[0058]
The word line driver 38 selects the control word line CWL0 based on the control signal from the read / write control circuit 23 in FIG. 1 when writing to the second region 11b. Then, a negative first control voltage is supplied during erasure, a high second control voltage generated by the second voltage generation circuit 17 is supplied during programming, and a read voltage VCWL-RD is supplied during reading.
[0059]
The control information reading circuit 14 is connected to a pair of bit lines BL0 and BL1.
The control information reading circuit 14 reads the data written in the memory cells Ce0a and Ce0b in the second region 11b through the bit lines BL0 and BL1 connected to them, and determines the polarity of each data.
[0060]
More specifically, in the test mode, data “0” and data “1” are written in the memories Ce0a and Ce0b so as to have opposite polarities. The control information reading circuit 14 latches the data read from each of the memory cells Ce0a and Ce0b at the time of initialization processing, compares the current flowing based on both data, and sets the memory control information of “1” or “0”. Is output.
[0061]
The reading of the memory cell Ce in the first area 11a will be described.
The flash memory 10 includes a reference control circuit, and the reference control circuit includes a reference cell read circuit, a reference cell write data generation circuit, and a reference cell Y decoder. (All are not shown)
The reference cell read circuit reads data written in each of the two reference cells via a pair of bit lines connected to them, and determines the polarity of each data.
[0062]
More specifically, when the memory cell Ce is written, data “0” and data “1” are written in the reference cell so that the polarities are reversed. Prior to the writing of the memory cell Ce, the reference cell read circuit latches data read from the reference cell in each row, determines which data “1” is written, and a polarity signal indicating the polarity Is output.
[0063]
The reference cell write data generation circuit, based on the polarity signal from the reference cell read circuit, writes the reference cell write data so that each reference cell is written with the opposite polarity to the currently written data. Is generated.
[0064]
Therefore, data is written to the reference cell so that the polarity is opposite to that of the current data every time the memory cell Ce is written. The reason why the data is inverted at each writing is that it is desirable to keep the threshold distribution of each reference cell for generating the reference current within a predetermined range.
[0065]
The reference cell Y decoder generates a decode signal corresponding to the data (“1” or “0”) currently written in the reference cell based on the polarity signal from the reference cell read circuit.
[0066]
The write driver 15 includes source voltage supply circuits 32 and 33 and a reference voltage source voltage supply circuit for each cell (memory cell Ce, reference cell) in the column direction corresponding to the source line SL connected thereto. Is provided. Note that the source voltage supply circuit for the reference cell is configured in the same manner as the source voltage supply circuits 32 and 33.
[0067]
The reference cell source voltage supply circuit is provided corresponding to each source line connected to the reference cell, and the reference cell write data supplied from the reference cell write data generation circuit (having opposite polarities to each other). Data). Then, the first or second source voltage corresponding to the captured data (“0” or “1”) is supplied to each source line.
[0068]
The Y pass gate 13 includes a reference cell Y selection gate together with the Y selection gate 34 described above. The reference cell Y selection gate decodes the bit line for the reference cell based on the decode signal from the reference cell Y decoder, and reads the data “0” from the reference cell and the reference cell of the data “1”. The read signal from is output.
[0069]
That is, the cell array 11 includes a first region 11a and a second region 11b, and the first region 11a has a memory cell Ce that is normally accessed and a current that serves as a reference for determination of read data from the memory cell Ce. And a reference cell for generating. Then, 1-bit read data is read from the first area 11a by the reference cell.
[0070]
The second area 11b includes a memory cell Ce that is accessed in a predetermined mode, and data having opposite polarity is stored in the pair of memory cells Ce. Data is simultaneously read from the two memory cells Ce in the second region 11b, and 1-bit memory cell information is supplied to the control target circuit based on the data.
[0071]
FIG. 4 is an explanatory diagram illustrating a memory cell according to an embodiment.
In this embodiment, the memory cell Ce is a flash memory cell having a single-layer polysilicon structure, and is composed of three elements: a memory transistor 41, a select transistor 42, and a MOS capacitor 43.
[0072]
As shown in FIGS. 4A to 4C, the memory transistor 41 is formed of, for example, an NMOS transistor having a floating gate 45 as a gate on a P-type substrate 44, and its source is connected to a source line SL.
[0073]
The select transistor 42 is composed of an NMOS transistor (not shown in FIGS. 4B and 4C) having a select gate 46 as a gate on a substrate 44, and its source is connected to the bit line BL. Connected to the selected word line SWL. The drains of the memory transistor 41 and the select transistor 42 are connected to each other.
[0074]
The MOS capacitor 43 is formed by forming an N-type diffusion layer as a control gate 47 on a substrate 44 and forming a floating gate 45 on the control gate 47 with an insulating layer therebetween. The control gate 47 is formed in the triple well of the substrate 44 (in the P well 49 formed in the N well 48 in the figure). The control gate 47 is connected to the control word line CWL. Incidentally, in the memory cell Ce of the single layer polysilicon structure of the present embodiment, when it is simply referred to as a word line, it means the control word line CWL.
[0075]
In such a memory cell Ce, in this embodiment, the state in which electrons are accumulated in the floating gate 45 (high threshold state) is data “0”, and conversely, the state in which electrons are not accumulated in the floating gate 45 (threshold value). Assume that writing is performed in association with data “1” in a low state.
[0076]
Writing to the memory cell Ce consists of two operations: erase (erase) and program.
Erase is an operation of extracting electrons from the floating gate 45 to lower the threshold value of the memory cell Ce (memory transistor 41). In other words, erasing is an operation of rewriting data in the memory cell Ce from data “0” to data “1”.
[0077]
As shown in FIG. 4B, in the erase, a high voltage (for example, 6.0 V) as a first source voltage is applied to the source of the memory transistor 41, and a negative voltage (as a first control voltage) is applied to the control gate 47. For example, -9.3V) is applied. Here, the P well 49 is set to the same potential as the control gate 47 (for example, −9.3 V), and the N well 48 is set to 6.0 V, for example.
[0078]
In this case, the potential of the floating gate 45 is lowered to about −8.2 V by capacitive coupling, and a high voltage of about 14.2 V is applied between the source and the floating gate 45. As a result, an FN tunnel current (indicated by an arrow in the figure) flows, electrons are extracted from the floating gate 45, and the threshold value of the memory cell Ce (memory transistor 41) decreases. Therefore, the memory cell Ce is rewritten from data “0” to data “1”.
[0079]
On the other hand, the program is an operation of injecting electrons into the floating gate 45 to increase the threshold value of the memory cell Ce (memory transistor 41). In other words, the program is an operation of rewriting data in the memory cell Ce from data “1” to data “0”.
[0080]
As shown in FIG. 4C, the program applies a ground voltage (0.0 V) as the second source voltage to the source of the memory transistor 41, and applies a high voltage (for example, the second control voltage to the control gate 47). 9.5V) is applied. Here, the P well 49 is set to a ground voltage (0.0 V), and the N well 48 is set to 6.0 V, for example.
[0081]
In this case, the potential of the floating gate 45 is raised to about 11.3 V by capacitive coupling, and a high voltage of about 11.3 V is applied between the source and the floating gate 45. As a result, an FN tunnel current (indicated by an arrow in the figure) flows, electrons are injected into the floating gate 45, and the threshold value of the memory cell Ce (memory transistor 41) increases. Therefore, the memory cell Ce is rewritten from data “1” to data “0”.
[0082]
In this embodiment, the memory cell Ce has a single-layer polysilicon structure, but a two-layer polysilicon structure (a floating gate is electrically isolated and embedded in a gate oxide film, and the floating gate and the control gate are embedded). It may be embodied in a memory cell of a stacked structure (also called a stack type).
[0083]
The memory cell Ce having a single layer structure has a larger cell area than a memory cell having a two-layer structure (stacked type), but can reduce the number of process steps associated with the formation of a single polysilicon layer. Therefore, this structure is suitable for small-capacity memory applications when the ratio of memory cells to the die size is small.
[0084]
Next, the principle of the writing method of the memory cell Ce of this embodiment will be described.
As shown in FIG. 5, the memory cell array 11 is formed by arranging a plurality of memory cells Ce in an array.
[0085]
The source of each memory cell Ce is separated for each cell in a column unit, and is connected to the source line SL (SL0 to SL3 in the drawing). The control gate 47 of each memory cell Ce is connected to a common control word line CWL (CWL0, CWL1 in the figure) for each cell in a row unit. In the figure, the select transistor 42 is omitted.
[0086]
In such a memory cell array 11, writing (erasing / programming) to the memory cell Ce is performed collectively for the memory cells Ce in units of rows connected to any one selected control word line CWL. .
[0087]
Explaining the principle, at the time of writing, voltages corresponding to write data (“1” or “0”) of each memory cell Ce are supplied to the source lines SL0 to SL3. Here, a high source voltage (eg, 6.0 V) corresponding to data “1” is supplied to the source lines SL1 and SL3, and a ground voltage (0 corresponding to data “0” is applied to the source lines SL0 and SL2. Assume that a second source voltage of .0 V) is supplied.
[0088]
In this state, first, a first control voltage of a negative voltage (for example, −9.3 V) is supplied to any one selected control word line CWL (for example, CWL0 in this case).
Then, in the memory cell Ce to which the first source voltage corresponding to the write data “1” is applied to the source, a tunnel current flows and electrons are extracted from the floating gate 45 and are erased (see FIG. 4B). ). That is, the memory cell Ce to which the second source voltage corresponding to the write data “0” is applied to the source is not erased.
[0089]
Next, a second control voltage of a high voltage (for example, 9.3 V) is supplied to the control word line CWL0 while maintaining the voltages supplied to the source lines SL0 to SL3.
[0090]
Then, the memory cell Ce to which the second source voltage corresponding to the write data “0” is applied to the source is programmed by injecting electrons into the floating gate 45 through the tunnel current (see FIG. 4C). ). That is, the memory cell Ce to which the first source voltage corresponding to the write data “1” is applied to the source is not programmed.
[0091]
Therefore, in such a method, all the devices connected to the same control word line CWL0 are based on the voltages supplied to the source lines SL0 to SL3 in advance according to the write data (“1” or “0”). Writing (erasing / programming) to the memory cell Ce at a time is performed.
[0092]
Hereinafter, details of each circuit will be described.
FIG. 6 is a circuit diagram of the memory cell Ce. A description of the same components as those in FIG. 4 described above will be omitted.
[0093]
The source voltage ARVSS corresponding to the time of writing / reading is supplied from the source voltage supply circuit 32 (or 33) to the source of the memory cell Ce (memory transistor 41) via the source line SL.
[0094]
The floating gate potential FG is set around 3.0 V when the data is “1” and around 0.0 V when the data is “0” according to the data written in the memory cell Ce. The N well potential VNW is set to 6.0 V, for example, at the time of writing. The P well potential VPW is set to the same potential as that of the control gate 47 during erasing and to the ground potential during programming in accordance with erasing / programming.
[0095]
FIG. 7 is a circuit diagram showing a configuration example of the source voltage supply circuit 32. The source voltage supply circuit 33 is similarly configured.
The source voltage supply circuit 32 includes a latch circuit 32a and takes in data WDBj obtained by inverting the write data W-MDATA supplied from the outside based on the decode signal YTi from the Y decoder 22 that has decoded the write address WD-ADDR. It latches in the latch circuit 32a.
[0096]
The output signal of the latch circuit 32a is input to the gates of the transistor Tp1 (PMOS transistor) and the transistor Tn1 (NMOS transistor). The source of the transistor Tp1 is connected to the power supply VS, and the source of the transistor Tn1 is connected to the ground power supply ARGND.
[0097]
A transistor Tp2 (PMOS transistor) is interposed in series between the transistors Tp1 and Tn1, and a reference voltage ARVREF is input to the gate of the transistor Tp2. The source voltage ARVSS is output from the connection point between the transistors Tp2 and Tn1.
[0098]
The power supply VS is voltage-controlled in response to a write signal (write start signal WRITE-START). In the present embodiment, the power supply VS is set to, for example, 3.0 V when the data WDBj is captured by the latch circuit 32a, and the high voltage generated by the third voltage generation circuit 18 at the time of writing (after latching the data WDBj). The first source voltage is set to (for example, 6.0 V). The transistor Tp2 controls the amount of current flowing through the memory cell Ce at the time of writing based on the reference voltage ARVREF.
[0099]
In this configuration, the source voltage supply circuit 32 supplies the source voltage ARVSS corresponding to the data WDBj (inverted signal) taken into the latch circuit 32a. That is, when the captured data WDBj is data “0”, a high first source voltage (power supply VS in the figure) is supplied, and conversely, when the data is “1”, the second source voltage of the ground voltage is supplied. (Ground power supply ARGND in the figure) is supplied. That is, the source voltage supply circuit 32 supplies the power supply VS or the ground power supply ARGND to the source line SL as the source voltage ARVSS corresponding to the write data WDBj. Accordingly, the transistors Tp1 and Tp2 receive the power supply VS that is voltage-controlled in response to the write signal (write start signal WRITE-START), and supply the power supply VS to the source line SL corresponding to the write data (data WDBj). The output part 32b supplied to is configured.
[0100]
FIG. 8 is a circuit diagram showing a configuration example of the control information reading circuit 14, and FIG. 9 is an operation waveform diagram thereof.
Control information reading circuit 14 includes a latch circuit 14a as a control information storage unit and data output circuits 14b and 14c.
[0101]
One node a of the latch circuit 14a is connected to the bit line BL (0) through the transistor Tn2 (NMOS transistor) and to the data output circuit 14b. The other node b of the latch circuit 14a is connected to the bit line BL (1) through the transistor Tn3 (NMOS transistor) and to the data output circuit 14c.
[0102]
Each of the transistors Tn2 and Tn3 is composed of a transistor having a low threshold value, and a bias signal NBIAS is supplied to the gates of the transistors Tn2 and Tn3 when the memory cells Ce0a and Ce0b in the second region 11b are read. (Hereinafter, transistors for which similar threshold values are set are similarly shown in the drawings).
[0103]
The latch circuit 14a is supplied with the power supply VC-CAM and the ground power supply ARGND. The latch circuit 14a receives the potentials of the nodes a and b, that is, the memory cells Ce0a and Ce0b in the second region 11b based on the latch signal LATCH at the time of reading. The read data complementary to each other to be read is latched.
[0104]
The read operation will be described in detail. As shown in FIG. 9, the control information read circuit 14 first releases the latch state of the latch circuit 14a in accordance with the latch signal LATCH. Next, the selected word line SWL0a or the selected word line SWL0bf (see FIG. 2) connected to the memory cells Ce0a and Ce0b in the second region 11b is selected (becomes active) and simultaneously, the data is output based on the control signal RDcam. The circuits 14b and 14c are deactivated.
[0105]
Next, the nodes a and b are equalized (equal potential) based on the short signal SRT for short-circuiting the drains of the transistors Tn2 and Tn3, and then released, thereby releasing the memory cell Ce0a in the second region 11b. , Amplify the read data of Ce0b. That is, a potential difference is gradually generated between the nodes a and b due to the read current of the memory cells Ce0a and Ce0b in the second region 11b flowing through the bit lines BL0 and BL1.
[0106]
Thereafter, the read data of the memory cells Ce0a and Ce0b in the second area 11b latched in the latch circuit 14a by the latch signal LATCH are respectively determined based on the control signal RDcam as the determination signals DB-CAM (polarity signal REF-REV) and D-CAM. Are output from the data output circuits 14b and 14c.
[0107]
FIG. 10 is a circuit diagram illustrating a configuration example of the sense amplifier 36.
The sense amplifier 36 includes a read reference current generation unit 36a and a read current generation unit 36b.
[0108]
The read reference current generation unit 36a includes first and second reference signals SAref0 and SAref from the read reference current generation circuit 35 and a selection signal TRIM- corresponding to the memory control information read from the memory cells in the second area 11b. A read reference current Irefj is generated based on IREF [0: 3]. The read current generator 36b generates a read current Iref based on the read signal RDB from the Y selection gate 34.
[0109]
More specifically, the read reference current generation unit 36a includes a constant current unit 61 and first to fourth constant current units 62 to 65, and is based on the first reference signal SAref0 input to the constant current unit 61. Generate current Iref0.
[0110]
The first to fourth constant current units 62 to 65 are different in the size of the transistors constituting them, and the second constant current unit 63 is twice the driving capability of the first constant current unit 62, and the third constant current The unit 64 has a drive capability of 4 times, and the fourth constant current unit 65 has a drive capability of 8 times.
[0111]
The read reference current generation unit 36a drives at least one of the first to fourth constant current units 62 to 65 by the selection signal TRIM-IREF, and based on the second reference signal SAref input thereto, 2 A current obtained by multiplying the reference current Iref1 by a constant j (0 <j <1) is generated. Therefore, the read reference current generation unit 36a sets the read reference current Irefj as the sum of “first reference current Iref0 + second reference current Iref1 × constant j” according to the selection signal TRIM-IREF corresponding to the memory control information. Generate.
[0112]
The sense amplifier 36 configured as described above compares the read reference current Irefj flowing into the node c with the read current Iref flowing out from the node c, so that the data of the memory cell Ce to be read is “1”. It is determined whether it is “0”. That is, data is determined by detecting the potential (H level or L level) of the node c that changes in accordance with the read current Iref of the memory cell Ce flowing out from the node c, and read data RDATAB indicating the determination result is output.
[0113]
A circuit 36c indicated by a broken line in the figure is provided corresponding to the test mode, and outputs the read data RDATAB to the outside as the read signal R-ANA-OUT in the test mode.
[0114]
FIG. 11 is a circuit diagram showing a configuration example of the word line applied voltage selection circuit 37, and FIG. 12 is an operation waveform diagram thereof.
At the time of erasing, a negative voltage (from the first voltage generating circuit 16 is applied to the source and back gate (P well) of the transistor Tn6 (NMOS transistor) and the back gate (P well) of the transistors Tn7 and Tn8 (NMOS transistors). -9.3V) first control voltage R-NEGP is supplied.
[0115]
A control signal NGNDB is supplied to the gates of the transistors Tn6 and Tn7. The control signal NGNDB is generated based on a plurality of control signals RDmem, ENVPXGD, and NEGPL. Here, the control signal RDmem is a signal that becomes H level at the time of reading, the control signal ENVPXGD is a signal that becomes H level at the time of programming, and the control signal NEGPL is the first control voltage R-NEGP that is not more than a predetermined voltage at the time of erasing (for example, This signal becomes L level when the voltage drops to 0 V or less.
[0116]
Therefore, at the time of erasing, the control signal NGNDB becomes L level (specifically, ground voltage), and the transistors Tn6 and Tn7 are turned on based on the supply of the first control voltage R-NEGP.
[0117]
At this time, the drain potential of the transistor Tn7, that is, the control signal NEGPGND becomes substantially equal to the negative first control voltage R-NEGP, and the transistor Tn8 is turned off by the control signal NEGPGND. Therefore, at the time of erasing, the word line applied voltage selection circuit 37 outputs the first control voltage R-NEGP having a negative voltage (−9.3 V) as the applied voltage VCWL.
[0118]
At this time, as described above, since the control signal NGNDB input to the gate of the transistor Tn6 becomes the ground voltage, a high voltage exceeding the withstand voltage is not applied between the source and gate of the transistor Tn6.
[0119]
At the time of programming, the control signal NGNDB becomes L level (ground voltage) based on the H level control signal ENVPXGD. At this time, the first control voltage R-NEGP becomes 0 V, and the transistors Tn6 and Tn7 are turned off.
[0120]
Further, since the control signal NEGPGND is at the H level, the transistor Tn8 is turned on. At this time, the read voltage VCWL-RD is controlled by the read reference current generating circuit 35 to be in a floating state, and the applied voltage VCWL is As shown in FIG. 12, it becomes a floating potential (for example, about 2.5 V).
[0121]
At the time of reading, the control signal NGNDB similarly becomes the ground voltage based on the control signal RDmem, and the transistors Tn6 and Tn7 are turned off and the transistor Tn8 is turned on as in the programming. Therefore, at the time of reading, the word line applied voltage selection circuit 37 outputs the read voltage VCWL-RD supplied from the read reference current generation circuit 35 as the applied voltage VCWL.
[0122]
A circuit 37a indicated by a broken line in the figure is provided corresponding to the test mode for measuring the read current. In the test mode, the transfer gate TG1 is turned off and the transfer gate TG2 is turned on based on the test signal T-AC. Turned on. A test input signal R-ANA-IN is supplied from the outside, and the input signal R-ANA-IN is output as the applied voltage VCWL.
[0123]
FIG. 13 is a circuit diagram showing a configuration example of the word line driver 38, and FIG. 14 is an operation waveform diagram thereof.
The word line driver 38 selects any one control word line CWLi by predecode signals XD0 to XD2 generated based on the write address WD-ADDR (see FIG. 1) at the time of writing (erasing / programming). At the time of reading, the selected word line SWLia or the selected word line SWLib (i = 1, 2,...) Is selected by decode signals YD2 (1), YD2 (0) generated based on a read address (not shown).
[0124]
The word line driver 38 includes a latch circuit 38a, to which the control signal NPS and the first control voltage R-NEGP are supplied. The latch circuit 38a controls the control signal NEN based on the control signal NENB generated by the predecode signals XD0 to XD2.
Latch. Specifically, the control signal NEN having the voltage level of the control signal NPS is generated.
[0125]
As described above, the control signal NEGPL becomes L level when the first control voltage R-NEGP decreases to a predetermined voltage or lower (for example, −3.0 V or lower) during erasing, and the control signal NPS is determined based on the control signal NEGPL. It becomes L level (specifically, ground voltage). Therefore, the latch circuit 38a generates the control signal NEN that becomes the ground voltage based on the control signal NPS. Incidentally, at this time, since the voltage level of the control signal NGND is equal to the first control voltage R-NEGP, the latch state of the latch circuit 38a is maintained.
[0126]
The control signal NEN generated by the latch circuit 38a is input to the gate of the transistor Tn9 (NMOS transistor) as the first transistor. An applied voltage VCWL is supplied to the source of the transistor Tn9, and a first control voltage R-NEGP having a negative voltage (−9.3 V) is supplied to the back gate (P well) of the transistor Tn9.
[0127]
Accordingly, the transistor Tn9 is turned on at the time of erasing, and as shown in FIG. 14, the applied voltage VCWL (specifically, the first control voltage R) is applied to any one control word line CWLi selected by the predecode signals XD0 to XD2. -NEGP) is supplied.
[0128]
At this time, as described above, since the gate voltage (control signal NEN) input to the gate of the transistor Tn9 becomes the ground voltage, a high voltage exceeding the breakdown voltage is applied between the source and gate of the transistor Tn9. Absent.
[0129]
During such erasing, the transistor Tn10 is turned on by the control signal NEGPL-ER, and the P well potential VPWi (see FIG. 6) of the memory cell Ce becomes the applied voltage VCWL (−9.3 V).
[0130]
At the time of programming, a high voltage (+9.5 V) second control voltage VPX is supplied to the word line driver 38 from the second voltage generation circuit 17. The second control voltage VPX is supplied to the source of the transistor Tp3 (PMOS transistor) as the second transistor.
[0131]
A control signal XINBT is supplied to the gate of the transistor Tp3. This control signal XINBT becomes L level by predecode signals XD0 to XD2 at the time of programming.
[0132]
Accordingly, the transistor Tp3 is turned on at the time of programming, and as shown in FIG. 14, the second control voltage VPX of the high voltage (+ 9.5V) is applied to any one of the control word lines CWLi selected by the predecode signals XD0 to XD2. Is supplied.
[0133]
At this time, the transistor Tn9 is also turned on. However, as described above, the applied voltage VCWL is controlled to a floating potential (for example, about 2.5 V) during programming (see FIG. 12), so that an abnormal current flows through the control word line CWLi. There is nothing.
[0134]
During such programming, the transistor Tn11 is turned on by the control signal NGND, so that the P well potential VPWi (see FIG. 6) of the memory cell Ce becomes the ground voltage.
[0135]
Next, the write operation of the flash memory 10 configured as described above will be described in detail with reference to FIG.
FIG. 15A shows an operation when data “0” is written to the memory cell Ce where data “0” is currently written. In this case, the second source voltage of the ground voltage (0.0 V) corresponding to the data “0” to be written is supplied to the source of the memory cell Ce.
[0136]
In this state, first, a first control voltage of negative voltage (−9.3 V) is supplied to the control word line CWL. At this time, the potential difference between the source and the floating gate is about 8.2 V, and no FN tunnel current flows. Therefore, the memory cell Ce is not erased and the charge amount of the floating gate does not change.
[0137]
Next, the second control voltage of the high voltage (+9.5 V) is supplied to the control word line CWL while maintaining the source voltage at 0.0 V. At this time, the potential difference between the source and the floating gate is about 8.2 V, and no FN tunnel current flows. Accordingly, the charge amount of the floating gate does not change. Therefore, in this case, data “0” of the memory cell before writing is held.
[0138]
FIG. 15B shows an operation when data “1” is written into the memory cell Ce where data “0” is currently written. In this case, the first source voltage of the high voltage (6.0 V) corresponding to the data “1” to be written is supplied to the source of the memory cell Ce.
[0139]
In this state, first, a first control voltage of negative voltage (−9.3 V) is supplied to the control word line CWL. At this time, a voltage of approximately 14.2 V is applied between the source and the floating gate, and an FN tunnel current flows. Therefore, the electrons of the floating gate are extracted and the memory cell Ce is erased.
[0140]
Next, a second control voltage of a high voltage (+9.5 V) is supplied to the control word line CWL while the source voltage is maintained at 6.0 V. At this time, the potential difference between the source and the floating gate is about 5.3 V, and no FN tunnel current flows. Therefore, the memory cell Ce is not programmed, and the charge amount of the floating gate does not change. Therefore, in this case, only erasing is performed, and data “0” of the memory cell before writing is rewritten to data “1”.
[0141]
FIG. 15C shows an operation when data “0” is written to the memory cell Ce where data “1” is currently written. In this case, the second source voltage of the ground voltage (0.0 V) corresponding to the data “0” to be written is supplied to the source of the memory cell Ce.
[0142]
In this state, first, a first control voltage of negative voltage (−9.3 V) is supplied to the control word line CWL. At this time, the potential difference between the source and the floating gate is about 5.3 V, and no FN tunnel current flows. Accordingly, the charge amount of the floating gate does not change.
[0143]
Next, the second control voltage of the high voltage (+9.5 V) is supplied to the control word line CWL while maintaining the source voltage at 0.0 V. At this time, a voltage of approximately 11.3 V is applied between the source and the floating gate, and an FN tunnel current (between the source and the channel) flows. Therefore, electrons are injected into the floating gate and the memory cell Ce is programmed. Therefore, in this case, only programming is performed, and data “1” of the memory cell before writing is rewritten to data “0”.
[0144]
FIG. 15D shows an operation when data “1” is written to the memory cell Ce where data “1” is currently written. In this case, the first source voltage of the high voltage (6.0 V) corresponding to the data “1” to be written is supplied to the source of the memory cell Ce.
[0145]
In this state, first, a first control voltage of negative voltage (−9.3 V) is supplied to the control word line CWL. At this time, a voltage of approximately 11.3 V is applied between the source and the floating gate, and a small amount of FN tunnel current flows (actually hardly flows). Therefore, the charge amount of the floating gate is not substantially changed.
[0146]
Next, a second control voltage of a high voltage (+9.5 V) is supplied to the control word line CWL while the source voltage is maintained at 6.0 V. At this time, the potential difference between the source and the floating gate is about 5.6 V, and no FN tunnel current flows. Therefore, the memory cell Ce is not programmed, and the charge amount of the floating gate does not change. Therefore, in this case, data “1” of the memory cell before writing is held.
[0147]
Next, the operation of the flash memory 10 configured as described above will be described with reference to FIG.
FIG. 16 is an operation flowchart of the flash memory 10.
[0148]
First, the X decoder 12 selects the second area 11b which is a control information area (step 101). Specifically, the word line driver 39 constituting the driver unit 12b of the X decoder 12 activates the selected word line SWL0a or the selected word line SWL0b and the control word line CWL0.
[0149]
Next, the control information reading circuit 14 selects the bit line pair BL and reads the memory control information from the memory cell Ce connected to the bit line pair BL (step 102). Then, the control information reading circuit 14 latches the read memory control information and supplies the memory control information to the read amplifier 24 which is a control target circuit (step 103).
[0150]
Next, the flash memory 10 reads data (cell information) from the memory cell Ce in the first area 11a, which is a normal memory array, in response to a signal supplied from the outside (step 104), or data to the memory cell Ce. (Cell information) is written (step 105).
[0151]
The read reference current generator 36a of the sense amplifier 36 constituting the read amplifier 24 sets the read reference current Irefj to “first reference current Iref0 + second reference current Iref1” according to the selection signal TRIM-IREF corresponding to the memory control information. X constant j "is generated as a combined current. Then, by comparing the read reference current Irefj with the read current Iref flowing out from the node c, it is determined whether the data of the memory cell Ce to be read is “1” or “0”.
[0152]
Therefore, by rewriting the memory control information in the second area 11b, the current value of the read reference current Irefj is changed, that is, the operation of the flash memory 10 is changed in software.
[0153]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The memory cell array 11 includes a first area 11a composed of memory cells to which an external address is assigned, and a second area 11b composed of memory cells to which no external address is assigned. Memory control information for setting the flash memory 10 is stored in the second area 11b. The memory cells in the first region 11a and the second region 11b are connected to a common bit line BL for both memory cells. Therefore, the second area 11b for storing the memory control information is provided adjacent to the first area 11a for storing the user data, and a circuit (write driver 15) for writing to the memory cell Ce in each of the areas 11a and 11b. ) Is shared. As a result, an increase in the circuit area of the flash memory 10 can be suppressed as compared with the case where the memory area for the user and the memory area (control information area) for storing the memory control information are formed apart from each other. .
[0154]
(2) The memory control information is stored in a non-volatile and electrically rewritable memory cell Ce. Therefore, even if the voltage setting including the read reference current Irefj changes due to the aging of the elements of the flash memory 10 and the like, the operation can be compensated by rewriting the memory control information.
[0155]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
For convenience of explanation, the same reference numerals are given to the same components as those in the first embodiment, and the drawings and explanation thereof are partially omitted.
[0156]
FIG. 17 is a partial block diagram showing a schematic configuration of the nonvolatile semiconductor memory device (flash memory) of the present embodiment.
The flash memory 70 includes a memory cell array 11. The memory cell array 11 includes a first area (user area) 11a and a second area (control information area) 11b provided adjacent to each other.
[0157]
In the memory cell array 11, a plurality of memory cells Ce are arranged in an array. In the first region 11a, a plurality of memory cells Ce are arranged in an array by a plurality of first word lines WLa and a plurality of bit lines BL. In the second region 11b, in the present embodiment, a plurality of memory cells Ce are arranged in a column by one second word line WLb and a plurality of bit lines BL.
[0158]
The first word line WLa and the second word line WLb are connected to the X decoder 12, and the bit line BL is connected to the Y pass gate 71 and the control information read circuit 14. The source lines SL0a to SL2b shown in FIG. 2 are connected to the write driver 15.
[0159]
The Y pass gate 71 outputs cell information read from the memory cells in the first region 11a to the read amplifier 72 during normal operation, and the read amplifier 72 outputs read data R-MDATA obtained by amplifying the data from the Y pass gate 71. To do.
[0160]
The Y pass gate 71 outputs the memory control information read from the memory cells in the second area 11b to the read amplifier 72 at the time of initialization, and the read amplifier 72 outputs the memory control information to the control information storage unit 73. . The memory control information from the read amplifier 72 is latched.
[0161]
The control information storage unit 73 supplies the latched memory control information to the read amplifier 24 that is a control target circuit, and the read amplifier 24 adjusts the circuit based on the memory control information (setting value). In the normal operation mode, the read amplifier 24 outputs read data R-MDATA obtained by amplifying data read from the first region 11a through the bit line BL and the Y pass gate 13 by the adjusted circuit.
[0162]
That is, in the flash memory 70 of this embodiment, the cell information of the first area 11a and the memory control information of the second area 11b are performed by the Y pass gate 13 and the read amplifier 24. Therefore, compared with the first embodiment, the circuit area of the flash memory 70 is reduced because the control information reading circuit 14 is not provided.
[0163]
FIG. 18 is an operation flowchart of the flash memory 70.
First, the X decoder 12 selects the second area 11b which is a control information area (step 201). Specifically, the word line driver 39 constituting the driver unit 12b of the X decoder 12 activates the selected word line SWL0a or the selected word line SWL0b and the control word line CWL0.
[0164]
Next, the Y pass gate 13 selects the bit of the control information (activates the bit line pair BL) (step 202), and the read amplifier 24 reads the memory control information from the memory cell Ce of the selected bit (step). 203). Then, the control information storage unit 73 latches the read memory control information for each bit and supplies the memory control information to the read amplifier 24 which is a control target circuit (step 204).
[0165]
Next, the flash memory 70 reads data (cell information) from the memory cell Ce in the first area 11a, which is a normal memory array, in response to a signal supplied from the outside (step 205), or data to the memory cell Ce. (Cell information) is written (step 206).
[0166]
As described above, according to the present embodiment, the following effects can be obtained.
(1) In the flash memory 70 of the present embodiment, the cell information of the first area 11a and the memory control information of the second area 11b are performed by the Y pass gate 13 and the read amplifier 24. Therefore, compared with the first embodiment, the circuit area of the flash memory 70 can be reduced because the control information reading circuit 14 is not provided.
[0167]
In addition, you may change the said embodiment into the following aspects.
In each of the above embodiments, at the time of writing, first, a negative first control voltage is applied to the control word line CWL, and then a high second control voltage is applied. May be. That is, after executing the program by applying the second high control voltage, the erase may be performed by applying the first negative control voltage.
[0168]
In each of the above embodiments, the memory cell Ce has a single-layer polysilicon structure. However, the memory cell may have a two-layer polysilicon structure (stacked type) that does not include a selected word line. Incidentally, in the stack type memory cell, only one word line (selected word line) connected to the control gate shares the control word line CWL and the selected word line SWL of this embodiment.
[0169]
In each of the above embodiments, the single-layer polysilicon memory cell Ce may be a two-element cell that does not include the select transistor 12.
In each of the above embodiments, all the memory cells Ce connected to the same control word line CWL are collectively written as a write target, but may be selectively written.
[0170]
The above embodiments are applied to a nonvolatile semiconductor memory device having a cell array provided with reference cells.
In each of the above embodiments, the memory control information may be read and the steps necessary for it (steps 101 and 102 in the first embodiment, steps 201 to 203 in the second embodiment) may be executed as appropriate. For example, when the memory control information is written in the second area 11b based on the test mode signal TS, the above steps are executed corresponding to the writing. The step is executed both at the initial setting and after the rewriting. In this way, the operation according to the changed memory control information can be performed without turning on the power of the flash memories 10 and 70 again.
[0171]
The various embodiments described above can be summarized as follows.
(Supplementary note 1) a first memory cell to which an external address is assigned;
A second memory cell to which an external address is not assigned,
The second memory cell is provided for memory control information;
The semiconductor memory device, wherein the first and second memory cells are connected to a common bit line for both memory cells.
(Supplementary note 2) a first memory cell to which an external address is assigned;
A second memory cell to which an external address is not assigned,
The first and second memory cells are nonvolatile and rewritable,
The second memory cell is provided for memory control information;
The semiconductor memory device, wherein the first and second memory cells are connected to a common bit line and source line for both memory cells.
(Supplementary Note 3) The first memory cells are arranged in an array by a plurality of the bit lines and a plurality of first word lines,
A decoder for activating one of the plurality of first word lines based on an address signal;
The semiconductor memory device according to appendix 1 or 2, wherein the second memory cell is connected to the decoder via a second word line.
(Additional remark 4) The said 1st memory cell and said 2nd memory cell are connected to a common source voltage supply circuit through a common source line with respect to both memory cells, The additional remark 1 thru | or 1 characterized by the above-mentioned. 4. The semiconductor memory device according to any one of 3.
(Supplementary Note 5) The semiconductor memory according to Supplementary Note 4, wherein the source voltage supply circuit includes a latch circuit that latches the write data in response to a decode signal generated based on a write address. apparatus.
(Supplementary Note 6) The source voltage supply circuit includes an output unit that receives a voltage-controlled signal in response to a write signal and supplies the voltage-controlled signal to a source line in response to write data. The semiconductor memory device according to appendix 4 or 5, wherein:
(Supplementary Note 7) A read circuit connected to the bit line and reading information of the first memory cell;
A read circuit connected to the bit line and for reading information of the second memory cell;
A semiconductor memory device according to any one of appendices 1 to 6, further comprising:
(Supplementary Note 8) The semiconductor memory device according to Supplementary Note 5, wherein a control information storage unit that holds the information is connected to the read circuit that reads the information of the second memory cell.
(Supplementary Note 9) The common bit line is connected to a read circuit that reads information of the first memory cell and the second memory cell,
7. The semiconductor memory device according to any one of appendices 1 to 6, wherein a control information storage unit that holds information read from the second memory cell is connected to the read circuit.
(Supplementary Note 10) The first memory cell and the second memory cell are connected to a first source line and to a first selected word line, respectively, and a second source A second memory cell connected to the line and connected to the second selected word line,
The first memory cell and the second memory cell are respectively connected to a first bit line and a second bit line independent from each other;
10. The semiconductor memory device according to appendix 7 or 9, wherein the first bit line and the second bit line are connected to the read circuit.
(Supplementary note 11) The semiconductor memory device according to supplementary note 10, wherein the first memory cell and the second memory cell write data having opposite polarities in a test mode.
(Supplementary Note 12) The memory cell is a single-layer polysilicon structure cell,
12. The semiconductor memory according to any one of appendices 1 to 11, comprising a capacitor to which a word line is connected, a memory transistor to which a source line is connected, and a select transistor to which a selected word line is connected. apparatus.
(Supplementary Note 13) The memory cell shares a bit line connected to each other select transistor between two memory cells adjacent in the word line direction, and one of the two memory cells has one memory cell. 13. The semiconductor memory device according to appendix 12, wherein a first selected word line is connected and a second selected word line is connected to the other memory cell.
(Supplementary Note 14) A bit line common to both memory cells by a first memory cell assigned an external address and a second memory cell provided for memory control information and not assigned an external address A method of controlling a semiconductor memory device connected to
Accessing the second memory cell by a row decoder;
Accessing the first memory cell by the row decoder;
A method for controlling a semiconductor memory device, comprising:
(Supplementary Note 15) First and second rewritable and non-volatile memory cells are provided, the second memory cell is provided for memory control information, and an external address is assigned to the first memory cell. The second memory cell is not assigned an external address, and is a method for controlling a semiconductor memory device connected to a common bit line and source line for both memory cells,
Accessing the second memory cell by a row decoder;
Accessing the first memory cell by the row decoder;
A method for controlling a semiconductor memory device, comprising:
(Supplementary note 16) The method of controlling a semiconductor memory device according to supplementary note 14 or 15, wherein the step of accessing the second memory cell is executed prior to the step of accessing the first memory cell.
(Supplementary Note 17) The step of reading information of the second memory cell is executed by a read circuit different from the read circuit that executes the step of reading information of the first memory cell. 16. The method for controlling a semiconductor memory device according to claim 16.
(Supplementary note 18) Of the supplementary notes 14 to 16, the step of reading the information of the second memory cell is executed by a read circuit that executes the step of reading the information of the first memory cell. Any one of the control methods of the semiconductor memory device.
(Supplementary note 19) The method of controlling a semiconductor memory device according to supplementary note 17 or 18, further comprising the step of holding the information read by the readout circuit in a control information storage unit.
(Supplementary note 20) Supplementary note 14, wherein data is written into the first memory cell and the second memory cell from a common source voltage supply circuit through the common source line. 20. A method for controlling a semiconductor memory device according to any one of items 1 to 19.
(Supplementary note 21) The method of controlling a semiconductor memory device according to supplementary note 20, wherein the source voltage supply circuit holds the data to be written.
(Supplementary Note 22) The source voltage supply circuit includes:
Inputting a voltage controlled signal in response to the write signal;
Supplying a voltage-controlled signal to a source line in response to write data;
The method of controlling a semiconductor memory device according to appendix 20 or 21, wherein:
(Supplementary Note 23) Information on the first memory cell and the second memory cell is read out to a read circuit through the common bit line, and the information is held in a control information storage unit. 23. A method of controlling a semiconductor memory device according to any one of appendices 14 to 22, which is characterized by the following.
(Supplementary Note 24) The first memory cell and the second memory cell are each connected to a first source line and to a first selected word line;
A second memory cell connected to the second source line and connected to the second selected word line;
The read circuit is connected to a first bit line to which the first memory cell is connected and to a second bit line to which the second memory cell is connected and independent of the first bit line, 24. The method of controlling a semiconductor memory device according to any one of appendices 14 to 23, wherein the data of the second bit line is differentially amplified and read.
(Supplementary note 25) The method of controlling a semiconductor memory device according to supplementary note 24, wherein the first memory cell and the second memory cell write data having opposite polarities in a test mode.
(Supplementary note 26) The method of controlling a semiconductor memory device according to any one of supplementary notes 14 to 25, wherein the step of reading the second memory cell is performed by a test signal.
(Supplementary Note 27) The memory cell is a single-layer polysilicon structure cell and includes a capacitor to which a word line is connected, a memory transistor to which a source line is connected, and a select transistor to which a selected word line is connected. And
27. The method of controlling a semiconductor memory device according to any one of appendices 14 to 26, wherein erasing and programming of the plurality of memory cells are performed using a tunnel current.
[0172]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a semiconductor memory device and a control method thereof in which an increase in circuit area is suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile memory.
FIG. 2 is a block diagram showing a detailed configuration of a nonvolatile memory.
FIG. 3 is a circuit diagram showing a memory cell array.
FIGS. 4A to 4C are configuration explanatory diagrams of nonvolatile memory cells. FIGS.
FIG. 5 is a principle explanatory diagram showing a memory cell writing method;
FIG. 6 is a circuit diagram of a memory cell.
FIG. 7 is a circuit diagram showing a source voltage supply circuit.
FIG. 8 is a circuit diagram showing a control information reading circuit.
FIG. 9 is an operation waveform diagram of the control information reading circuit.
FIG. 10 is a circuit diagram showing a sense amplifier.
FIG. 11 is a circuit diagram showing a word line applied voltage selection circuit.
FIG. 12 is an operation waveform diagram of the word line applied voltage selection circuit.
FIG. 13 is a circuit diagram showing a word line driver.
FIG. 14 is an operation waveform diagram of the word line driver.
FIGS. 15A to 15D are waveform diagrams showing a write operation.
FIG. 16 is an operation flowchart of the first embodiment.
FIG. 17 is a schematic configuration diagram of a nonvolatile memory according to a second embodiment.
FIG. 18 is an operation flowchart of the second embodiment.
[Explanation of symbols]
BL, BL0, BL1 bit lines
SL source line
WLa 1st word line
WLb Second word line
Ce memory cell
32, 33 Source voltage supply circuit

Claims (14)

A first memory cell assigned an external address;
A second memory cell to which an external address is not assigned,
The second memory cell is provided for memory control information for controlling a read operation to the first memory cell ,
The first and second memory cells are connected to a bit line common to both memory cells;
A first read circuit connected to the bit line and reading information of the first memory cell;
A second read circuit connected to the bit line and reading information of the second memory cell;
An output signal of the second read circuit is connected to the first read circuit. A first memory cell assigned an external address;
A second memory cell to which an external address is not assigned,
The first and second memory cells are nonvolatile and rewritable,
The second memory cell is provided for memory control information for controlling a read operation to the first memory cell ,
The first and second memory cells are connected to a common bit line and source line for both memory cells,
A first read circuit connected to the bit line and reading information of the first memory cell;
A second read circuit connected to the bit line and reading information of the second memory cell;
An output signal of the second read circuit is connected to the first read circuit. The first memory cells are arranged in an array by a plurality of bit lines and a plurality of first word lines,
A decoder for activating one of the plurality of first word lines based on an address signal;
3. The semiconductor memory device according to claim 1, wherein the second memory cell is connected to the decoder through a second word line.   4. The first memory cell and the second memory cell are connected to a common source voltage supply circuit via a common source line for both memory cells. A semiconductor memory device according to any one of the above. The first readout circuit includes:
A read reference current generator; and
A differential current amplifier circuit to which a read reference current line that is an output of the read reference current generation unit and the bit line are input;
5. The output signal of the second read circuit is input to the read reference current generation unit, and the read reference current value is changed according to the memory control information. 6. Semiconductor memory device. The read reference current generator is
A first constant current unit that receives a first reference signal, which is a first reference current of first polarity information (0 or 1) of the memory cell data, and generates a first reference current;
A second constant current unit that receives a second reference signal that is a second reference current of second polarity information (1 or 0) opposite to the first polarity information of the memory cell data and generates a second reference current; With
6. The semiconductor memory device according to claim 5, wherein an output signal of the second read circuit is connected to the second constant current unit and changes a read reference current value according to the memory control information. The second constant current portion is
The semiconductor according to claim 6, wherein a current obtained by multiplying the second reference current by a constant j (0 <j <1) is generated with respect to the driving capability of the first constant current unit in accordance with the memory control information. Storage device. The semiconductor memory device includes a write amplifier connected to the bit line,
A second read circuit for reading out the information of the rewritten second memory cell by rewriting the memory control information stored in the second memory cell by the write amplifier in accordance with a change with time of the memory cell. When,
The semiconductor memory apparatus as claimed in one of claims 1 to 7 output signal of the second read circuit is the memory control information is rewritten, characterized in that it is connected to the first readout circuit. Both a first memory cell to which an external address is assigned and a second memory cell that is provided for memory control information that controls a read operation to the first memory cell and to which no external address is assigned are provided. A method for controlling a semiconductor memory device connected to a bit line common to memory cells,
Accessing the second memory cell through a second read circuit by a row decoder;
A step of accessing the first memory cell through the first read circuit by the row decoder in accordance with an operating condition determined according to output information of the second read circuit. Control method. First and second rewritable and non-volatile memory cells are provided, and the second memory cell is provided for memory control information for controlling a read operation to the first memory cell. External address is assigned to each memory cell, and no external address is assigned to the second memory cell, and a method for controlling a semiconductor memory device connected to a common bit line and source line for both memory cells Because
Accessing the second memory cell through a second read circuit by a row decoder;
A step of accessing the first memory cell through the first read circuit by the row decoder in accordance with an operating condition determined according to output information of the second read circuit. Control method. A step 3 of rewriting and accessing the memory control information stored in the second memory cell by a write amplifier in accordance with a change with time of the memory cell;
The step 3 is executed prior to the step 1 for accessing the second memory cell, and the step 1 for accessing the second memory cell is preceded by the step 2 for accessing the first memory cell. 11. The method of controlling a semiconductor memory device according to claim 9, wherein the method is executed.   11. The method of controlling a semiconductor memory device according to claim 9, wherein the steps 1 to 3 are performed in a state where the power of the semiconductor memory device is turned on and maintained. The step 2 of reading the information of the first memory cell includes:
Comparing a read reference current value with a current value of the first memory cell;
13. The method of controlling a semiconductor memory device according to claim 9, wherein the read reference current value is changed in accordance with output information from the second read circuit. The step 2 of reading the information of the first memory cell includes:
A first reference current that is first polarity information (0 or 1) of the memory cell data and a second reference current that is second polarity information (1 or 0) opposite to the first polarity information of the memory cell data Comparing the read reference current value synthesized with and the current value of the first memory cell,
The method of controlling a semiconductor memory device according to claim 9, wherein the read reference current value is changed according to output information of the second read circuit.

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