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JP4137739B2 - Perforated wiring base material for multilayer wiring board with built-in semiconductor device, multilayer wiring board with built-in semiconductor device, and manufacturing method thereof - Google Patents
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JP4137739B2 - Perforated wiring base material for multilayer wiring board with built-in semiconductor device, multilayer wiring board with built-in semiconductor device, and manufacturing method thereof - Google Patents

Perforated wiring base material for multilayer wiring board with built-in semiconductor device, multilayer wiring board with built-in semiconductor device, and manufacturing method thereof Download PDF

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JP4137739B2
JP4137739B2 JP2003288083A JP2003288083A JP4137739B2 JP 4137739 B2 JP4137739 B2 JP 4137739B2 JP 2003288083 A JP2003288083 A JP 2003288083A JP 2003288083 A JP2003288083 A JP 2003288083A JP 4137739 B2 JP4137739 B2 JP 4137739B2
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semiconductor device
wiring
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thermoplastic resin
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JP2005057135A (en
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秀次 鈴木
和夫 吉川
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Mitsubishi Chemical Corp
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Mitsubishi Plastics Inc
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、半導体装置内蔵多層配線基板用穴明き配線基材、半導体装置内蔵多層配線基板及びその製造方法に関し、特に、半導体装置を搭載した配線基材を含む複数の配線基材を積層してなる高密度かつ超小型の3次元実装モジュールに用いて好適な半導体装置内蔵多層配線基板用穴明き配線基材、半導体装置内蔵多層配線基板及びその製造方法に関するものである。 The present invention relates to a perforated wiring base for a multilayer wiring board with a built- in semiconductor device, a multilayer wiring board with a built- in semiconductor device , and a method for manufacturing the same, and in particular, a plurality of wiring bases including a wiring base on which a semiconductor device is mounted. The present invention relates to a perforated wiring base material for a multilayer wiring board with a built- in semiconductor device, a multilayer wiring board with a built- in semiconductor device , and a manufacturing method thereof suitable for use in a high-density and ultra-small three-dimensional mounting module.

近年、プリント積層板やセラミック積層板等の基板上に、抵抗、キャパシタなどの受動部品の他に、小型半導体パッケージ、半導体ベアチップ、FBGA(fine pitch ball grid array)等の小型能動部品を実装することにより、基板における部品の実装密度を向上させ、電子装置の小型化、軽量化、薄型化を図った表面実装法が実用化されている。この表面実装法は、各部品の大きさを小型化しようとするものである。
また、部品の実装密度をさらに向上させるために、半導体装置を3次元的に積み上げる3次元実装技術を用いた3次元実装モジュールも開発されている。この3次元実装モジュールは、上述した表面実装法によっても配置しきれない部品、とりわけ、部品サイズの大きい半導体装置を立体的に配置し、あるいは、基板内部に入れ込んで、実装密度を高めようとするものである。
In recent years, in addition to passive components such as resistors and capacitors, small active components such as small semiconductor packages, semiconductor bare chips, and fine pitch ball grid arrays (FBGA) have been mounted on printed circuit boards and ceramic laminates. Therefore, a surface mounting method has been put into practical use in which the mounting density of components on the substrate is improved and the electronic device is reduced in size, weight, and thickness. This surface mounting method is intended to reduce the size of each component.
In order to further improve the mounting density of components, a three-dimensional mounting module using a three-dimensional mounting technique in which semiconductor devices are stacked three-dimensionally has been developed. This three-dimensional mounting module is intended to increase the mounting density by placing three-dimensionally a part that cannot be placed even by the surface mounting method described above, especially a semiconductor device having a large part size, or by placing it inside the board. To do.

上記の3次元実装技術は、機器の小型化だけではなく、コンピュータや通信機器などの高速化にも寄与する技術として、最近特に注目されている技術である。
例えば、通信機器においては、今後、撮像素子を用いた動画通信機能、Bluetoothのインターフェース機能、GPS機能等が搭載されることが見込まれており、部品点数の増加をともなう多機能化が積極的に押し進められ、実装技術の高密度化を牽引していくものである。このように、半導体装置を3次元的に積層して配線すれば、配線長を短くすることができ、高速信号を伝送することができるようにもなるために、3次元実装技術の採用は不可欠である。
The above-described three-dimensional mounting technology is a technology that has recently attracted attention as a technology that contributes not only to downsizing of devices but also to speeding up of computers and communication devices.
For example, in communication devices, it is expected that video communication functions using an image sensor, Bluetooth interface functions, GPS functions, etc. will be installed in the future. It will be pushed forward and will lead to higher density of mounting technology. As described above, if the semiconductor devices are three-dimensionally stacked and wired, the wiring length can be shortened and high-speed signals can be transmitted. It is.

3次元実装技術には、大きく分けて2種類の技術がある。
一つはプリント配線基板上や内部に部品を積層する3次元実装モジュール等についての技術であるが、3次元実装モジュール等を採用する機器メーカーが専用実装機の研究開発を進める必要があることから、殆ど普及していない。
もう一つはパッケージ内で半導体装置を積層する3次元実装パッケージについての技術であり(例えば、非特許文献1参照)、3次元実装パッケージ等を製造する電気メーカーにとっては、半導体装置の種類や個数、積層する配線基材の枚数が他社との差別化要因になることと、同一の形状であっても、多種多様の機能を発揮することができることのために、LSIメーカーが開発に本腰を入れ始めている。
There are two types of three-dimensional mounting techniques.
One is a technology for 3D mounting modules that stack components on or inside a printed circuit board, but it is necessary for equipment manufacturers that use 3D mounting modules to advance research and development of dedicated mounting machines. It is hardly spread.
The other is a technique regarding a three-dimensional mounting package in which semiconductor devices are stacked in a package (see, for example, Non-Patent Document 1). For an electric manufacturer that manufactures a three-dimensional mounting package, the type and number of semiconductor devices Because of the fact that the number of wiring substrates to be laminated becomes a differentiating factor from other companies and that even if they have the same shape, they can exert a wide variety of functions, LSI manufacturers are serious about development. I'm starting.

この3次元実装パッケージは、耐熱性樹脂からなる絶縁基材に導体配線を形成することにより複数種の配線基材を作製し、これらの配線基材のうち1つ以上に半導体装置を搭載して半導体装置搭載配線基材とし、これらの配線基材を積層し、熱圧着により融着一体化することで作製される(例えば、特許文献1参照)。
積層、熱圧着及び融着一体化は、ヒータ内蔵の積層治具を用いて行われ、融着の温度は、耐熱性樹脂のガラス転移温度以上とされる。
西山 和夫、「デジタル家電の実装ニーズと半導体パッケージング技術」、エレクトロニクス実装学会誌、(社)エレクトロニクス実装学会、2001年、第4巻、第3号、p.166−169 特開2001−119148号公報
In this three-dimensional mounting package, a plurality of types of wiring base materials are formed by forming conductor wiring on an insulating base material made of a heat-resistant resin, and a semiconductor device is mounted on one or more of these wiring base materials. The wiring substrate is mounted on a semiconductor device, and these wiring substrates are laminated and fused and integrated by thermocompression bonding (see, for example, Patent Document 1).
Lamination, thermocompression bonding, and fusion integration are performed using a lamination jig with a built-in heater, and the fusion temperature is equal to or higher than the glass transition temperature of the heat-resistant resin.
Kazuo Nishiyama, “Mounting needs of digital home appliances and semiconductor packaging technology”, Journal of Japan Institute of Electronics Packaging, Japan Institute of Electronics Packaging, 2001, Vol. 4, No. 3, p. 166-169 JP 2001-119148 A

ところで、従来の3次元実装パッケージは、半導体装置を搭載した基材を含む複数の配線基材を積層し、熱圧着により融着一体化したものであるから、この熱融着過程において半導体装置に直接加わる圧力や、半導体装置と配線基材との熱膨張率の差に起因する熱的ストレスにより、半導体装置自体や、半導体装置と配線基材との間に変形や配線歪みが生じ、オープン/ショート(O/S)等の配線不良、寸法のずれ等の不具合が生じる虞があるという問題があった。   By the way, since the conventional three-dimensional mounting package is obtained by laminating a plurality of wiring substrates including a substrate on which a semiconductor device is mounted and fusing and integrating them by thermocompression bonding. Due to the pressure applied directly and the thermal stress caused by the difference in thermal expansion coefficient between the semiconductor device and the wiring substrate, deformation or wiring distortion occurs between the semiconductor device itself or between the semiconductor device and the wiring substrate, and the There has been a problem that defects such as a short circuit (O / S) or the like may occur, or a dimensional shift may occur.

この変形や配線歪みは、高密度かつ超小型の3次元実装モジュールにおいて必須とされる配線ピッチのファイン化にとって無視できない大きな問題となる。
また、熱圧着により融着一体化した後に、融着条件(温度、圧力)によっては、半導体装置と配線基材との間への樹脂の回り込みが不十分なためにボイドが形成され、このボイドに吸湿により水が溜まり、後のリフロー工程で膨れが生じ、吸湿リフロー耐熱性が低下するという虞もあった。
その結果、半導体装置や配線基材の初期特性や動作特性が不安定になったり、その動作特性の経時変化が大きくなり、半導体装置や配線基材の信頼性が低下するという問題があった。
This deformation and wiring distortion become a serious problem that cannot be ignored for finer wiring pitch, which is essential in a high-density and ultra-small three-dimensional mounting module.
In addition, after fusing and integrating by thermocompression bonding, depending on the fusing conditions (temperature and pressure), a void is formed due to insufficient resin wrapping between the semiconductor device and the wiring substrate. Further, there is a possibility that water accumulates due to moisture absorption and swelling occurs in a later reflow process, resulting in a decrease in moisture absorption reflow heat resistance.
As a result, there are problems that the initial characteristics and operational characteristics of the semiconductor device and the wiring substrate become unstable, and the operational characteristics change with time, and the reliability of the semiconductor device and the wiring substrate decreases.

本発明は、上記の課題を解決するためになされたものであって、半導体装置を搭載した基材を含む複数の配線基材を積層し、熱圧着し、融着一体化する際に、半導体装置自体や、半導体装置と配線基材との間に配線歪みや変形が生じる虞がなく、したがって、オープン/ショート(O/S)等の配線不良や寸法のずれ等の不具合が生じる虞がなく、また、ボイドの形成が防止され、したがって、吸湿リフロー耐熱性の低下が防止され、その結果、高密度かつ超小型の3次元実装モジュールにおける配線ピッチのファイン化を達成しつつ、半導体装置や配線基材の初期特性及び動作特性の安定性を図り、かつ、半導体装置や配線基材の信頼性の向上を図ることが可能な半導体装置内蔵多層配線基板用穴明き配線基材、半導体装置内蔵多層配線基板及びその製造方法を提供することを目的とする。 The present invention has been made in order to solve the above-described problem, and a plurality of wiring base materials including a base material on which a semiconductor device is mounted are stacked, thermocompression-bonded, and fused and integrated. There is no risk of wiring distortion or deformation between the device itself or between the semiconductor device and the wiring substrate, and therefore there is no risk of problems such as wiring defects such as open / short (O / S) and dimensional deviations. Further, formation of voids is prevented, and therefore, a decrease in moisture absorption reflow heat resistance is prevented. As a result, finer wiring pitch in a high-density and ultra-small three-dimensional mounting module is achieved, and semiconductor devices and wiring Perforated wiring base material for multi-layer wiring boards with built-in semiconductor devices and built-in semiconductor devices that can stabilize the initial characteristics and operational characteristics of the base materials and improve the reliability of semiconductor devices and wiring base materials Multilayer wiring base Another object of the invention is to provide a manufacturing method thereof.

半導体装置を搭載した配線基材を含む複数の配線基材を積層・熱圧着し、融着一体化させると、開口部を有する配線基材を構成する熱可塑性樹脂は、開口部の面積を小さくするように変形・拡張する。そのとき、本発明者は、この熱可塑性樹脂の変形・拡張は、開口部の辺部においては、角部においてよりも大きいことを見出した。そうすると、開口部の形状を矩形にすると、融着一体化の際に、開口部の辺部において熱可塑性樹脂が先に半導体装置に融着して、角部にボイドが形成されやすくなる等の不具合が生じることが分かった。そこで、本発明者は、鋭意検討の結果、積層・熱圧着前における、半導体装置と熱可塑性樹脂との間の空間が、半導体装置の辺部において角部よりも大きくなるように開口部の形状を工夫することで、こうした不具合が解消されることを見出した。
具体的には、半導体装置を収納するために形成された開口部の平面形状が5箇所以上の凹み部を持たない図形、例えば、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形等のいずれかである穴明き配線基材を用いれば、融着一体化時に、穴明き配線基材を構成する樹脂が形状変化して半導体装置との空間を埋めていく過程で、半導体装置と熱可塑性樹脂との間の空間が、半導体装置の角部と辺部とにおいて同程度に小さくなることにより、半導体装置に対する熱可塑性樹脂の圧力が均等になり、その結果、上記課題を解決し、上記目的を達成することができることが分かり、本発明に至った。
When a plurality of wiring base materials including a wiring base material on which a semiconductor device is mounted are laminated, thermocompression bonded, and fused and integrated, the thermoplastic resin constituting the wiring base material having the opening portion reduces the area of the opening portion. Deform and extend as you do. At that time, the present inventor has found that the deformation / expansion of the thermoplastic resin is larger at the side of the opening than at the corner. Then, when the shape of the opening is rectangular, when the fusion is integrated, the thermoplastic resin is first fused to the semiconductor device at the side of the opening, and voids are easily formed at the corners. It turns out that a malfunction occurs. Therefore, as a result of intensive studies, the present inventor has determined the shape of the opening so that the space between the semiconductor device and the thermoplastic resin before lamination and thermocompression bonding is larger than the corners at the sides of the semiconductor device. It was found that these problems can be resolved by devising the.
Specifically, the planar shape of the opening formed to accommodate the semiconductor device is a figure that does not have five or more recesses, for example, a pentagon or more polygon, and all the corners of the polygon are curved. If a perforated wiring base material that is either a figure, an ellipse, or the like is used, the shape of the resin that forms the perforated wiring base material changes during fusion integration with the semiconductor device. In the process of filling the space, the space between the semiconductor device and the thermoplastic resin becomes the same at the corners and sides of the semiconductor device, so that the pressure of the thermoplastic resin on the semiconductor device is even. As a result, it has been found that the above problems can be solved and the above object can be achieved, and the present invention has been achieved.

即ち、本発明の半導体装置内蔵多層配線基板用穴明き配線基材は、熱可塑性樹脂組成物からなる絶縁基材に導体配線が形成された配線基材であって、半導体装置を収納するために形成された開口部の平面形状は、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形のいずれかであり、かつ、5箇所以上の凹み部を持たないことを特徴とする。 That is, the perforated wiring base material for a multilayer wiring board with a built- in semiconductor device according to the present invention is a wiring base material in which a conductor wiring is formed on an insulating base material made of a thermoplastic resin composition, and is used for housing a semiconductor device. The planar shape of the opening formed in the above is either a pentagon or more polygon, a figure in which all the corners of the polygon are curved, or an ellipse, and five or more indentations. It is characterized by not having.

前記熱可塑性樹脂組成物は、結晶融解ピーク温度が260℃以上である結晶性熱可塑性樹脂組成物、ガラス転移温度が260℃以上である非晶性熱可塑性樹脂組成物、液晶転移温度が260℃以上である液晶ポリマーから選択された1種以上を主成分とすると好ましい。   The thermoplastic resin composition includes a crystalline thermoplastic resin composition having a crystal melting peak temperature of 260 ° C. or higher, an amorphous thermoplastic resin composition having a glass transition temperature of 260 ° C. or higher, and a liquid crystal transition temperature of 260 ° C. The main component is preferably one or more selected from the above liquid crystal polymers.

また、本発明の半導体装置内蔵多層配線基板は、熱可塑性樹脂組成物からなる絶縁基材に導体配線が形成されてなる配線基材が複数、積層され、これら複数の配線基材のうち、1つまたは2つ以上の配線基材に半導体装置が搭載され、この半導体装置が搭載された配線基材に隣接して配置された配線基材には、前記半導体装置を収納するための開口部が形成され、これらの配線基材同士が熱圧着により融着一体化されてなる半導体装置内蔵多層配線基板において、
前記開口部の平面形状は、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形のいずれかであり、かつ、5箇所以上の凹み部を持たないことを特徴とする。
In the multilayer wiring board with a built-in semiconductor device of the present invention, a plurality of wiring base materials in which conductor wiring is formed on an insulating base material made of a thermoplastic resin composition are laminated, and among these wiring base materials, 1 A semiconductor device is mounted on one or two or more wiring base materials, and the wiring base material disposed adjacent to the wiring base material on which the semiconductor device is mounted has an opening for accommodating the semiconductor device. In the multilayer wiring board with a built-in semiconductor device, which is formed and these wiring base materials are fused and integrated by thermocompression bonding,
The planar shape of the opening is a polygon that is a pentagon or more, a figure in which all corners of the polygon are curved, or an ellipse, and does not have five or more indentations. It is characterized by that.

本発明の半導体装置内蔵多層配線基板は、こうした構成をとることにより、積層・熱圧着・融着一体化時に、穴明き配線基材を構成する樹脂が形状変化して半導体装置との空間を埋めていく過程で、半導体装置と熱可塑性樹脂との間の空間が、半導体装置の角部と辺部とにおいて同程度に小さくなることにより、半導体装置に対する熱可塑性樹脂の圧力が均等になり、上記課題を解決し、上記目的を達成することができる。   By adopting such a configuration, the multilayer wiring board with a built-in semiconductor device of the present invention changes the shape of the resin constituting the perforated wiring base material at the time of lamination, thermocompression bonding, and fusion integration, so that the space between the semiconductor device and the semiconductor device is reduced. In the process of filling, the space between the semiconductor device and the thermoplastic resin becomes equally small at the corners and sides of the semiconductor device, so that the pressure of the thermoplastic resin on the semiconductor device becomes equal, It is possible to solve the above problems and achieve the above object.

また、本発明の半導体装置内蔵多層配線基板は、熱可塑性樹脂組成物からなる絶縁基材に導体配線が形成されてなる配線基材が複数、積層され、これら複数の配線基材のうち、1つまたは2つ以上の配線基材に半導体装置が搭載され、この半導体装置が搭載された配線基材に隣接して配置された配線基材に半導体装置を収納することができる開口部が形成され、これらの配線基材同士が熱圧着により融着一体化されてなる半導体装置内蔵多層配線基板において、積層時に、多角形の平面形状を有する半導体装置と前記開口部との隙間が半導体装置の角部において最小であることを特徴とする。   In the multilayer wiring board with a built-in semiconductor device of the present invention, a plurality of wiring base materials in which conductor wiring is formed on an insulating base material made of a thermoplastic resin composition are laminated, and among these wiring base materials, 1 A semiconductor device is mounted on one or two or more wiring substrates, and an opening is formed in the wiring substrate disposed adjacent to the wiring substrate on which the semiconductor device is mounted so that the semiconductor device can be accommodated. In the multilayer wiring board with a built-in semiconductor device in which these wiring base materials are fused and integrated by thermocompression bonding, a gap between the semiconductor device having a polygonal planar shape and the opening is a corner of the semiconductor device when stacked. It is characterized in that it is minimum in the part.

本発明の半導体装置内蔵多層配線基板は、こうした構成をとることにより、積層・熱圧着・融着一体化時に、穴明き配線基材を構成する樹脂が形状変化して半導体装置との空間を埋めていく過程で、半導体装置と熱可塑性樹脂との間の空間が、半導体装置の角部と辺部とにおいて同程度に小さくなることにより、半導体装置に対する熱可塑性樹脂の圧力が均等になり、上記課題を解決し、上記目的を達成することができる。   By adopting such a configuration, the multilayer wiring board with a built-in semiconductor device of the present invention changes the shape of the resin constituting the perforated wiring base material at the time of lamination, thermocompression bonding, and fusion integration, so that the space with the semiconductor device is saved. In the process of filling, the space between the semiconductor device and the thermoplastic resin becomes equally small at the corners and sides of the semiconductor device, so that the pressure of the thermoplastic resin on the semiconductor device becomes equal, It is possible to solve the above problems and achieve the above object.

本発明の半導体装置内蔵多層配線基板においては、前記熱可塑性樹脂組成物は、結晶融解ピーク温度が260℃以上である結晶性熱可塑性樹脂組成物、ガラス転移温度が260℃以上である非晶性熱可塑性樹脂組成物、液晶転移温度が260℃以上である液晶ポリマーから選択された1種以上を主成分とすると好ましい。   In the multilayer wiring board with a built-in semiconductor device of the present invention, the thermoplastic resin composition is a crystalline thermoplastic resin composition having a crystal melting peak temperature of 260 ° C. or higher, and an amorphous property having a glass transition temperature of 260 ° C. or higher. It is preferable that at least one selected from a thermoplastic resin composition and a liquid crystal polymer having a liquid crystal transition temperature of 260 ° C. or higher as a main component.

また、本発明の半導体装置内蔵多層配線基板の製造方法は、熱可塑性樹脂組成物からなる絶縁基材に導体配線が形成されてなる配線基材が複数、積層され、これら複数の配線基材のうち、1つまたは2つ以上の配線基材に半導体装置が搭載され、この半導体装置が搭載された配線基材に隣接されして配置された配線基材には、前記半導体装置を収納するための開口部が形成され、これらの配線基材同士が熱圧着により融着一体化されてなる半導体装置内蔵多層配線基板の製造方法であって、
半導体装置搭載用の配線基材と、基材の一部に前記半導体装置を収納するための開口部が形成され、当該開口部の平面形状が、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形のいずれかであり、かつ、5箇所以上の凹み部を持たない半導体装置内蔵多層配線基板用穴明き配線基材と、それ以外の配線基材を作製し、次いで、前記半導体装置搭載用の配線基材に半導体装置を搭載し、これらの配線基材を積層し、熱圧着により融着一体化することを特徴とする。
The method for manufacturing a multilayer wiring board with a built-in semiconductor device according to the present invention includes a plurality of wiring base materials in which conductor wiring is formed on an insulating base material made of a thermoplastic resin composition, and the plurality of wiring base materials are stacked. Among these, a semiconductor device is mounted on one or two or more wiring base materials, and the wiring base material disposed adjacent to the wiring base material on which the semiconductor device is mounted accommodates the semiconductor device. Are formed, and these wiring base materials are fused and integrated by thermocompression bonding.
A wiring substrate for mounting a semiconductor device, and an opening for housing the semiconductor device is formed in a part of the substrate, and a planar shape of the opening is a pentagon or more polygon, all of the polygons Perforated wiring base material for a multilayer wiring board with a built-in semiconductor device that is either a figure with a curved corner or an ellipse and does not have five or more recesses , and other wiring bases A material is prepared, and then a semiconductor device is mounted on the wiring substrate for mounting the semiconductor device, and these wiring substrates are laminated and fused and integrated by thermocompression bonding.

本発明の半導体装置内蔵多層配線基板の製造方法は、こうした構成をとることにより、積層・熱圧着・融着一体化時に、穴明き配線基材を構成する樹脂が形状変化して半導体装置との空間を埋めていく過程で、半導体装置と熱可塑性樹脂との間の空間が、半導体装置の角部と辺部とにおいて同程度に小さくなることにより、半導体装置に対する熱可塑性樹脂の圧力が均等になり、上記課題を解決し、上記目的を達成することができる。   The manufacturing method of a multilayer wiring board with a built-in semiconductor device of the present invention adopts such a configuration, so that the resin constituting the perforated wiring base material changes its shape during lamination, thermocompression bonding, and fusion integration. In the process of filling the space of the semiconductor device, the space between the semiconductor device and the thermoplastic resin becomes the same at the corners and sides of the semiconductor device, so that the pressure of the thermoplastic resin on the semiconductor device is equalized. Thus, the above problems can be solved and the above object can be achieved.

上記半導体装置内蔵多層配線基板の製造方法においては、複数の配線基材を熱圧着により融着一体化する際の温度は、半導体装置搭載用の配線基材のガラス転移温度以上又は液晶転移温度以上であること好ましい。   In the method for manufacturing a semiconductor device built-in multilayer wiring board, the temperature when fusing and integrating a plurality of wiring base materials by thermocompression bonding is not less than the glass transition temperature or the liquid crystal transition temperature of the wiring base material for mounting the semiconductor device. Preferably it is.

本発明の半導体装置内蔵多層配線基板用穴明き配線基材、半導体装置内蔵多層配線基板及びその配線基板の製造方法によれば、半導体装置を搭載した基材を含む複数の配線基材を積層し、熱圧着し、融着一体化する際に、半導体装置自体や、半導体装置と配線基材との間に配線歪みや変形が生じるのを防止することができ、したがって、オープン/ショート(O/S)等の配線不良や寸法のずれ等の不具合を防止することができる。また、ボイドの形成を防止するので、吸湿リフロー耐熱性の低下を防止することができ、高密度かつ超小型の3次元実装モジュールにおける配線ピッチのファイン化を達成することができる。その結果、半導体装置や配線基材の初期特性及び動作特性の安定性を向上させることができ、半導体装置や配線基材の信頼性を向上させることができる。

According to the perforated wiring base material for a multilayer wiring board with a built- in semiconductor device, the multilayer wiring board with a built- in semiconductor device, and the method for manufacturing the wiring board, a plurality of wiring base materials including the base material on which the semiconductor device is mounted are stacked. Then, when thermocompression bonding and fusion integration are performed, it is possible to prevent the occurrence of wiring distortion or deformation between the semiconductor device itself or between the semiconductor device and the wiring base material. / S) and other problems such as wiring defects and dimensional deviations can be prevented. Further, since the formation of voids is prevented, a decrease in moisture absorption reflow heat resistance can be prevented, and finer wiring pitch can be achieved in a high-density and ultra-small three-dimensional mounting module. As a result, the stability of the initial characteristics and operation characteristics of the semiconductor device and the wiring substrate can be improved, and the reliability of the semiconductor device and the wiring substrate can be improved.

本発明の穴明き配線基材、この穴明き配線基材を用いた半導体装置内蔵多層配線基板及びその製造方法の一実施の形態について説明する。   An embodiment of a holed wiring substrate of the present invention, a multilayer wiring board with a built-in semiconductor device using the holed wiring substrate, and a method for manufacturing the same will be described.

[配線基材]
図1は、本発明の一実施形態の穴明き配線基材を示す断面図である。この穴明き配線基材3は、熱可塑性樹脂組成物からなる薄板状、フィルム状あるいはシート状の絶縁基材15に、この絶縁基材15を貫通するバイアホール13が形成され、このバイアホール13に導電性ペーストを硬化してなる導電材14が充填され、さらに、この絶縁基材15の所定位置には後述する半導体装置18を収納するための開口部16が形成されている。
[Wiring substrate]
FIG. 1 is a cross-sectional view showing a perforated wiring substrate according to an embodiment of the present invention. In the perforated wiring base material 3, a via hole 13 penetrating the insulating base material 15 is formed in a thin plate-like, film-like or sheet-like insulating base material 15 made of a thermoplastic resin composition. 13 is filled with a conductive material 14 obtained by curing a conductive paste, and an opening 16 for accommodating a semiconductor device 18 described later is formed at a predetermined position of the insulating base material 15.

図2は、本発明の開口が形成された穴明き配線基材3の4つの例を示す概略平面図である。但し、図2においては穴明き配線基材3に形成される導体配線は省略している。この例の穴明き配線基材3は、いずれも全体の平面形状が略四角形であるとされる。穴明き配線基材3の中央部には開口部16が形成されている。この開口部16の平面形状は、5箇所以上の凹み部10を持たない図形であるとされる。この5箇所以上の凹み部10を持たない図形の例としては、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形等がある。
また、本発明において、「凹み部」とは、開口部16の平面形状をなす図形において、その内側に向かって膨出した部分をいう。
FIG. 2 is a schematic plan view showing four examples of the perforated wiring substrate 3 in which the opening of the present invention is formed. However, in FIG. 2, the conductor wiring formed on the perforated wiring substrate 3 is omitted. The perforated wiring base material 3 in this example is assumed to have a substantially square overall planar shape. An opening 16 is formed at the center of the perforated wiring substrate 3. The planar shape of the opening 16 is a figure that does not have five or more recessed portions 10. Examples of the figure that does not have the five or more recessed portions 10 include a pentagon or more polygon, a figure in which all corners of the polygon are curved, and an ellipse.
Further, in the present invention, the “dented portion” refers to a portion that bulges toward the inside of the figure forming the planar shape of the opening 16.

図2(a)では、開口部16の平面形状は八角形である。図2(b)では、開口部16の平面形状は、八角形のすべての角部17が円弧とされている図形である。図2(c)では、開口部16の平面形状は楕円である。図2(d)では、開口部16の平面形状は、八角形の4つの角部17に凹み部10が形成された図形である。
開口部16の平面形状としては、八角形以上三十二角形以下で角部17の数が4の倍数である多角形が好ましく、特に八角形、十二角形、十六角形、二十角形が好ましい。また、開口部16の平面形状としてより好ましいのは、これらの多角形のすべての角部17が曲線形状とされている図形である。開口部16の平面形状がこの図形であると、積層・熱圧着・融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、半導体装置18と熱可塑性樹脂との間の空間が、半導体装置18の角部30と辺部とにおいて同程度に小さくなることにより、半導体装置18に対する熱可塑性樹脂の圧力がより均等になるからである。
In FIG. 2A, the planar shape of the opening 16 is an octagon. In FIG. 2B, the planar shape of the opening 16 is a figure in which all the corners 17 of the octagon are arcs. In FIG.2 (c), the planar shape of the opening part 16 is an ellipse. In FIG. 2D, the planar shape of the opening 16 is a figure in which the recess 10 is formed in the four corners 17 of the octagon.
The planar shape of the opening 16 is preferably an octagon or more and a thirty-two or less octagon and a polygon in which the number of corners 17 is a multiple of four, particularly octagons, dodecagons, dodecagons, and decagons. preferable. Further, more preferable as the planar shape of the opening 16 is a figure in which all the corners 17 of these polygons are curved. When the planar shape of the opening 16 is this figure, the thermoplastic resin constituting the perforated wiring substrate 3 changes its shape and fills the space with the semiconductor device 18 during lamination, thermocompression bonding, and fusion integration. In the process, the space between the semiconductor device 18 and the thermoplastic resin is reduced to the same extent at the corners 30 and the sides of the semiconductor device 18, so that the pressure of the thermoplastic resin on the semiconductor device 18 is further increased. Because it becomes even.

この穴明き配線基材3に用いられる熱可塑性樹脂組成物においては、結晶融解ピーク温度(Tm)が260℃以上である結晶性熱可塑性樹脂組成物、または、ガラス転移温度(Tg)が260℃以上である非晶性熱可塑性樹脂組成物、液晶転移温度(Tc)が260℃以上である液晶ポリマーから選択された1種以上が好適に用いられる。   In the thermoplastic resin composition used for the perforated wiring substrate 3, the crystalline thermoplastic resin composition having a crystal melting peak temperature (Tm) of 260 ° C. or higher, or the glass transition temperature (Tg) of 260. One or more selected from an amorphous thermoplastic resin composition having a temperature of not lower than ° C. and a liquid crystal polymer having a liquid crystal transition temperature (Tc) of not lower than 260 ° C. are preferably used.

結晶融解ピーク温度(Tm)が260℃以上である結晶性熱可塑性樹脂組成物としては、例えば、ポリエーテルエーテルケトン(PEEK)を40重量%、ポリエーテルイミド(PEI)を60重量%含む樹脂組成物(PEEK/PEI:Tg=185℃、Tm=335℃)、ポリフェニレンサルファイド(PPS)を40重量%、ポリエーテルイミド(PEI)を60重量%含む樹脂組成物(PPS/PEI:Tg=150℃、Tm=280℃)、シンジオタクチックポリスチレン(SPS)を40重量%、変性ポリフェニレンエーテル(変性PPE)を60重量%含む樹脂組成物(SPS/変性PPE:Tg=120℃、Tm=265℃)等が好適に用いられる。   As the crystalline thermoplastic resin composition having a crystal melting peak temperature (Tm) of 260 ° C. or higher, for example, a resin composition containing 40% by weight of polyetheretherketone (PEEK) and 60% by weight of polyetherimide (PEI) (PEEK / PEI: Tg = 185 ° C., Tm = 335 ° C.), 40% by weight of polyphenylene sulfide (PPS) and 60% by weight of polyetherimide (PEI) (PPS / PEI: Tg = 150 ° C.) , Tm = 280 ° C.), resin composition containing 40% by weight of syndiotactic polystyrene (SPS) and 60% by weight of modified polyphenylene ether (modified PPE) (SPS / modified PPE: Tg = 120 ° C., Tm = 265 ° C.) Etc. are preferably used.

ガラス転移温度(Tg)が260℃以上である非晶性熱可塑性樹脂組成物としては、例えば、ポリアミドイミド(PAI:Tg>260℃)、ポリイミド(PI:Tg>260℃)等、ガラス転移温度(Tg)を分子設計で適宜調製したものが好適に用いられる。   Examples of the amorphous thermoplastic resin composition having a glass transition temperature (Tg) of 260 ° C. or higher include, for example, polyamideimide (PAI: Tg> 260 ° C.), polyimide (PI: Tg> 260 ° C.), and the glass transition temperature. What (Tg) prepared suitably by molecular design is used suitably.

液晶転移温度(Tc)が260℃以上である液晶ポリマーとしては、サーモトロピック液晶ポリマー等の従来公知の各種のものを用いることができる。このような液晶ポリマーとしては、例えば、芳香族ジオール、芳香族カルボン酸、ヒドロキシカルボン酸等のモノマーから合成される、溶融時に液晶性を示すポリエステルがあり、その代表的なものとしては、パラヒドロキシ安息香酸(PHB)とテレフタル酸とビフェノールからなるもの、PHBと2,6−ヒドロキシナフトエ酸からなるもの、PHBとテレフタル酸とエチレングリコールからなるものが好適に用いられる。   As the liquid crystal polymer having a liquid crystal transition temperature (Tc) of 260 ° C. or higher, various conventionally known ones such as a thermotropic liquid crystal polymer can be used. Examples of such liquid crystal polymers include polyesters that are synthesized from monomers such as aromatic diols, aromatic carboxylic acids, and hydroxycarboxylic acids and that exhibit liquid crystallinity when melted. Those composed of benzoic acid (PHB), terephthalic acid and biphenol, those composed of PHB and 2,6-hydroxynaphthoic acid, and those composed of PHB, terephthalic acid and ethylene glycol are preferably used.

この熱可塑性樹脂組成物に対しては、その性質を損なわない程度に、他の樹脂や各種添加剤、例えば、無機充填材、安定剤、紫外線吸収剤、光安定剤、核剤、着色剤、滑剤、難燃剤、無機充填材、接着促進剤等を適宜添加してもよい。
無機充填材としては、特に制限はなく、公知のいかなるものも使用できる。例えば、シリカ、タルク、マイカ、雲母、ガラスフレーク、窒化ホウ素(BN)、板状炭カル、板状水酸化アルミニウム、板状シリカ、板状チタン酸カリウム等が挙げられる。これらは1種類を単独で添加してもよく、2種類以上を組合せて添加してもよい。
また、接着促進剤としては、γ−アミノプロピルトリメトキシシラン、γ−アミノプロピルトリエトキシシラン等が挙げられる。
For this thermoplastic resin composition, other resins and various additives, such as inorganic fillers, stabilizers, ultraviolet absorbers, light stabilizers, nucleating agents, colorants, to the extent that their properties are not impaired. Lubricants, flame retardants, inorganic fillers, adhesion promoters and the like may be added as appropriate.
There is no restriction | limiting in particular as an inorganic filler, Any well-known thing can be used. For example, silica, talc, mica, mica, glass flake, boron nitride (BN), plate-like carbon cal, plate-like aluminum hydroxide, plate-like silica, plate-like potassium titanate and the like can be mentioned. These may be added alone or in combination of two or more.
Examples of the adhesion promoter include γ-aminopropyltrimethoxysilane and γ-aminopropyltriethoxysilane.

[半導体装置内蔵多層配線基板]
図3は本発明の一実施形態の半導体装置内蔵多層配線基板を示す断面図であり、図において、符号1は最上層の配線基材、2は中実の内層基材、3は穴明き配線基材、4は最下層の配線基材となる半導体装置搭載内層基材(以下、単に「半導体装置搭載内装基材」という。)である。
[Multilayer wiring board with built-in semiconductor device]
FIG. 3 is a cross-sectional view showing a multilayer wiring board with a built-in semiconductor device according to an embodiment of the present invention. In the figure, reference numeral 1 is the uppermost wiring substrate, 2 is a solid inner layer substrate, and 3 is perforated. The wiring base material 4 is a semiconductor device mounting inner layer base material (hereinafter simply referred to as “semiconductor device mounting interior base material”) which is the lowermost wiring base material.

最上層の配線基材1は、通常、熱可塑性樹脂組成物からなる100μm以下の厚みの薄板状、フィルム状あるいはシート状の絶縁基材11であり、この絶縁基材11の表面及び裏面は平坦化されている。
本発明においては、この熱可塑性樹脂組成物は、穴明き配線基材3に用いられる熱可塑性樹脂組成物と同様の組成物でよいとされる。即ち、この熱可塑性樹脂組成物においては、結晶融解ピーク温度(Tm)が260℃以上である結晶性熱可塑性樹脂組成物、または、ガラス転移温度(Tg)が260℃以上である非晶性熱可塑性樹脂組成物、液晶転移温度(Tc)が260℃以上である液晶ポリマーから選択された1種以上が好適に用いられる。
The uppermost wiring substrate 1 is usually a thin plate-like, film-like or sheet-like insulating substrate 11 having a thickness of 100 μm or less made of a thermoplastic resin composition, and the front and back surfaces of the insulating substrate 11 are flat. It has become.
In the present invention, the thermoplastic resin composition may be the same composition as the thermoplastic resin composition used for the perforated wiring substrate 3. That is, in this thermoplastic resin composition, a crystalline thermoplastic resin composition having a crystal melting peak temperature (Tm) of 260 ° C. or higher, or an amorphous heat having a glass transition temperature (Tg) of 260 ° C. or higher. One or more selected from a plastic resin composition and a liquid crystal polymer having a liquid crystal transition temperature (Tc) of 260 ° C. or higher are preferably used.

中実の内層基材2は、上述した最上層基材1と全く同様の形状の熱可塑性樹脂組成物からなる薄板状、フィルム状あるいはシート状の絶縁基材11の一方の面(図3では上側)に、配線回路形成用の溝部12が形成されるとともに、絶縁基材11を貫通するバイアホール13が形成され、この溝部12及びバイアホール13には導電性ペーストを硬化してなる導電材14が充填されている。
この導電性ペーストとしては、樹脂系低温焼成タイプの銀(Ag)ペースト、銀(Ag)−パラジウム(Pd)ペースト、銅(Cu)ペースト、金属系低温焼成タイプの銀(Ag)−スズ(Sn)ペースト等が好適に用いられる。
The solid inner layer base material 2 is one surface of a thin plate-like, film-like or sheet-like insulating base material 11 made of a thermoplastic resin composition having exactly the same shape as the above-mentioned uppermost layer base material 1 (in FIG. 3). On the upper side, a groove 12 for forming a wiring circuit is formed, and a via hole 13 penetrating the insulating base material 11 is formed, and a conductive material obtained by curing a conductive paste in the groove 12 and the via hole 13. 14 is filled.
Examples of the conductive paste include resin-based low-temperature firing type silver (Ag) paste, silver (Ag) -palladium (Pd) paste, copper (Cu) paste, metal-based low-temperature firing type silver (Ag) -tin (Sn). ) A paste or the like is preferably used.

半導体装置搭載内層基材4は、上述した最上層の配線基材1と全く同様の形状の熱可塑性樹脂組成物からなる薄板状、フィルム状あるいはシート状の絶縁基材11の一方の面(図3では上側)に、配線回路形成用の溝部12が形成されるとともに、絶縁基材11を貫通するバイアホール13が形成され、この溝部12及びバイアホール13には導電性ペーストを硬化してなる導電材14が充填され、さらに、この絶縁基材11上に半導体装置18が搭載され、この半導体装置18の端子19は導電材14により構成される配線回路に電気的に接続されている。   The semiconductor device mounting inner layer base material 4 is a thin plate-like, film-like or sheet-like insulating base material 11 made of a thermoplastic resin composition having exactly the same shape as the uppermost wiring base material 1 described above (see FIG. In FIG. 3, a wiring circuit forming groove portion 12 is formed on the upper side), and a via hole 13 penetrating the insulating base material 11 is formed. The groove portion 12 and the via hole 13 are formed by curing a conductive paste. A conductive material 14 is filled, and a semiconductor device 18 is mounted on the insulating base material 11, and a terminal 19 of the semiconductor device 18 is electrically connected to a wiring circuit formed of the conductive material 14.

これら最上層の配線基材1、中実の内層基材2、穴明き配線基材3、半導体装置搭載内層基材4は、上からこの順に積層されて基材を構成する熱可塑性樹脂組成物が熱圧着により融着一体化された積層構造とされ、これら基材1〜4各々の配線回路及び各基材1〜4間を電気的に接続する配線は、導電性ペーストを硬化してなる導電材14により構成することで導通するようになっている。   These uppermost wiring base material 1, solid inner layer base material 2, perforated wiring base material 3, and semiconductor device mounting inner base material 4 are laminated in this order from the top to form a thermoplastic resin composition. It is a laminated structure in which the objects are fused and integrated by thermocompression bonding, and the wiring circuit of each of the base materials 1 to 4 and the wiring that electrically connects the base materials 1 to 4 are obtained by curing the conductive paste. By being constituted by the conductive material 14, it becomes conductive.

本発明の半導体装置内蔵多層配線基板では、穴明き配線基材3として、半導体装置18を収納するために形成された開口部16の平面形状が5箇所以上の凹み部10を持たない図形、例えば、五角形以上の多角形、前記多角形のすべての角部17が曲線形状とされている図形、楕円形等のいずれかである配線基材を使用している。   In the multilayer wiring board with a built-in semiconductor device according to the present invention, as the perforated wiring base material 3, the planar shape of the opening 16 formed for housing the semiconductor device 18 does not have five or more recessed portions 10, For example, a wiring base material that is any one of a polygon that is a pentagon or more, a figure in which all corners 17 of the polygon are curved, and an ellipse is used.

図4(a)にこの穴明き配線基材3と半導体装置18を積層融着した半導体装置内蔵多層配線基板の一例を示す。この例では、開口部16の平面形状が八角形であり、半導体装置18の平面形状が四角形であるものを用いている。
こうした構成をとることにより、融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、半導体装置18と熱可塑性樹脂との間の空間が、半導体装置18の角部30と辺部とにおいて同程度に小さくなることにより、半導体装置18に対する熱可塑性樹脂の圧力が均等になる。そのため、半導体装置を搭載した基材を含む複数の配線基材を積層し、熱圧着し、融着一体化する際に、半導体装置自体や、半導体装置と配線基材との間に配線歪みや変形が生じるのを防止することができ、したがって、オープン/ショート(O/S)等の配線不良や寸法のずれ等の不具合を防止することができる。また、ボイドの形成を防止するので、吸湿リフロー耐熱性の低下を防止することができ、高密度かつ超小型の3次元実装モジュールにおける配線ピッチのファイン化を達成することができる。その結果、半導体装置や配線基材の初期特性及び動作特性の安定性を向上させることができ、半導体装置や配線基材の信頼性を向上させることができる半導体装置内蔵多層配線基板を得られる。
FIG. 4A shows an example of a multilayer wiring board with a built-in semiconductor device in which the perforated wiring base material 3 and the semiconductor device 18 are laminated and fused. In this example, the opening 16 has an octagonal planar shape and the semiconductor device 18 has a rectangular planar shape.
By adopting such a configuration, the thermoplastic resin constituting the perforated wiring base material 3 changes its shape and fills the space between the semiconductor device 18 and the thermoplasticity of the semiconductor device 18 during the fusion integration. The space between the resin and the corner portion 30 and the side portion of the semiconductor device 18 are reduced to the same extent, so that the pressure of the thermoplastic resin on the semiconductor device 18 becomes equal. Therefore, when laminating a plurality of wiring base materials including a base material on which a semiconductor device is mounted, thermocompression bonding, and fusing integration, the semiconductor device itself, wiring distortion between the semiconductor device and the wiring base material, Deformation can be prevented, and therefore problems such as wiring defects such as open / short (O / S) and dimensional deviation can be prevented. Further, since the formation of voids is prevented, a decrease in moisture absorption reflow heat resistance can be prevented, and finer wiring pitch can be achieved in a high-density and ultra-small three-dimensional mounting module. As a result, it is possible to improve the stability of the initial characteristics and operation characteristics of the semiconductor device and the wiring substrate, and to obtain a multilayer wiring board with a built-in semiconductor device that can improve the reliability of the semiconductor device and the wiring substrate.

また、開口部16の平面形状が、すべての角部17が曲線形状とされている多角形であると、積層・熱圧着・融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、半導体装置18と熱可塑性樹脂との間の空間が、半導体装置18の角部30と辺部とにおいて同程度に小さくなることにより、半導体装置18に対する熱可塑性樹脂の圧力がより均等になるので好ましい。   Further, when the planar shape of the opening 16 is a polygon in which all the corners 17 are curved, the heat constituting the perforated wiring substrate 3 at the time of lamination, thermocompression bonding, and fusion integration. In the process of changing the shape of the plastic resin and filling the space with the semiconductor device 18, the space between the semiconductor device 18 and the thermoplastic resin is as small as the corner 30 and the side of the semiconductor device 18. This is preferable because the pressure of the thermoplastic resin on the semiconductor device 18 becomes more uniform.

なお、この例で開口部16の平面形状が5箇所以上の凹み部10を持たない図形、例えば、五角形以上の多角形、前記多角形のすべての角部17が曲線形状とされている図形、楕円形等のいずれかである穴明き配線基材3を用いるのは、凹み部10を5箇所以上設けると、穴明き配線基材3において半導体装置の角部30に対応する部分以外に凹み部10を設けざるを得なくなり、積層・熱圧着・融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、開口部の辺部において熱可塑性樹脂が先に半導体装置に融着して、半導体装置18に対する熱可塑性樹脂の圧力が均等にならなくなるので好ましくないからである。   In this example, the shape of the opening 16 in which the planar shape does not have five or more dents 10, for example, a pentagon or more polygon, a figure in which all the corners 17 of the polygon are curved, The perforated wiring base material 3 which is either oval or the like is used in addition to the portion corresponding to the corner portion 30 of the semiconductor device in the perforated wiring base material 3 when five or more recessed portions 10 are provided. The process of filling the space with the semiconductor device 18 by changing the shape of the thermoplastic resin constituting the perforated wiring substrate 3 during the lamination, thermocompression bonding, and fusion integration. This is because the thermoplastic resin is first fused to the semiconductor device at the side of the opening, and the pressure of the thermoplastic resin on the semiconductor device 18 is not uniform.

また、本発明の半導体装置内蔵多層配線基板では、多角形の平面形状を有する半導体装置18と、穴明き配線基材3において半導体装置18を収納するように形成された開口部16との隙間20が半導体装置の角部30において最小であるとしている。
ここで、「隙間」とは、半導体装置18と開口部16の間にできる空間を上から見たときに、その空間を投射した平面内に内接する円の直径の長さとして規定することができる。そして、その内接円の直径が最小になるときを、「隙間が最小になる」という。
In the multilayer wiring board with a built-in semiconductor device of the present invention, the gap between the semiconductor device 18 having a polygonal planar shape and the opening 16 formed so as to accommodate the semiconductor device 18 in the perforated wiring substrate 3. 20 is the smallest at the corner 30 of the semiconductor device.
Here, the “gap” is defined as a length of a diameter of a circle inscribed in a plane in which the space is projected when the space between the semiconductor device 18 and the opening 16 is viewed from above. it can. And when the diameter of the inscribed circle is minimized, the gap is minimized.

図4(b)にこの穴明き配線基材3と半導体装置18を積層融着した半導体装置内蔵多層配線基板の一例を示す。この例では、開口部16の平面形状が八角形であり、半導体装置18の平面形状が四角形であるものを用いている。
この例では、半導体装置18と開口部16の間にできる空間を上から見たときに、その空間を投射した平面内に内接する円の直径の長さが半導体装置の角部30において最小である。
こうした構成をとることにより、融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、半導体装置18と熱可塑性樹脂との間の空間が、半導体装置18の角部30と辺部とにおいて同程度に小さくなることにより、半導体装置18に対する熱可塑性樹脂の圧力が均等になる。そのため、半導体装置を搭載した基材を含む複数の配線基材を積層し、熱圧着し、融着一体化する際に、半導体装置自体や、半導体装置と配線基材との間に配線歪みや変形が生じるのを防止することができ、したがって、オープン/ショート(O/S)等の配線不良や寸法のずれ等の不具合を防止することができる。また、ボイドの形成を防止するので、吸湿リフロー耐熱性の低下を防止することができ、高密度かつ超小型の3次元実装モジュールにおける配線ピッチのファイン化を達成することができる。その結果、半導体装置や配線基材の初期特性及び動作特性の安定性を向上させることができ、半導体装置や配線基材の信頼性を向上させることができる半導体装置内蔵多層配線基板を得られる。
FIG. 4B shows an example of a multilayer wiring board with a built-in semiconductor device in which the perforated wiring base material 3 and the semiconductor device 18 are laminated and fused. In this example, the opening 16 has an octagonal planar shape and the semiconductor device 18 has a rectangular planar shape.
In this example, when the space formed between the semiconductor device 18 and the opening 16 is viewed from above, the length of the diameter of a circle inscribed in the plane on which the space is projected is the smallest at the corner 30 of the semiconductor device. is there.
By adopting such a configuration, the thermoplastic resin constituting the perforated wiring base material 3 changes its shape and fills the space between the semiconductor device 18 and the thermoplasticity of the semiconductor device 18 during the fusion integration. The space between the resin and the corner portion 30 and the side portion of the semiconductor device 18 are reduced to the same extent, so that the pressure of the thermoplastic resin on the semiconductor device 18 becomes equal. Therefore, when laminating a plurality of wiring base materials including a base material on which a semiconductor device is mounted, thermocompression bonding, and fusing integration, the semiconductor device itself, wiring distortion between the semiconductor device and the wiring base material, Deformation can be prevented, and therefore problems such as wiring defects such as open / short (O / S) and dimensional deviation can be prevented. Further, since the formation of voids is prevented, a decrease in moisture absorption reflow heat resistance can be prevented, and finer wiring pitch can be achieved in a high-density and ultra-small three-dimensional mounting module. As a result, it is possible to improve the stability of the initial characteristics and operation characteristics of the semiconductor device and the wiring substrate, and to obtain a multilayer wiring board with a built-in semiconductor device that can improve the reliability of the semiconductor device and the wiring substrate.

一方、図4(c)に従来の穴明き配線基材3と半導体装置18を積層融着した半導体装置内蔵多層配線基板の一例を示す。この例では、開口部16の平面形状が四角形であり、半導体装置18の平面形状が四角形であるものを用いている。
この例では、融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、開口部の辺部において熱可塑性樹脂が先に半導体装置に融着して、半導体装置18に対する熱可塑性樹脂の圧力が均等にならず、特に半導体装置の角部30では圧力が不足する。その結果、この例の半導体装置内蔵多層配線基板においては、半導体装置と配線基材との間や、半導体装置同士の間に配線歪みや変形が生じ、したがって、オープン/ショート(O/S)等の配線不良や寸法のずれ等の不具合が生じ、また、ボイドが形成されやすく、したがって、吸湿リフロー耐熱性の低下が起こり、ひいては、半導体装置や配線基材の初期特性及び動作特性が不安定になり、半導体装置や配線基材の信頼性の向上を図ることができなくなっている。
On the other hand, FIG. 4C shows an example of a multilayer wiring board with a built-in semiconductor device in which a conventional perforated wiring substrate 3 and a semiconductor device 18 are laminated and fused. In this example, the opening 16 has a quadrangular planar shape and the semiconductor device 18 has a quadrangular planar shape.
In this example, the thermoplastic resin constituting the perforated wiring base material 3 changes its shape and fills the space with the semiconductor device 18 at the time of fusion integration, and the thermoplastic resin is formed at the side of the opening. However, the pressure of the thermoplastic resin on the semiconductor device 18 is not equalized first, and the pressure is insufficient at the corner portion 30 of the semiconductor device. As a result, in the multilayer wiring board with a built-in semiconductor device of this example, wiring distortion or deformation occurs between the semiconductor device and the wiring base material, or between the semiconductor devices, and therefore, open / short (O / S), etc. Insufficient wiring defects, dimensional deviations, etc. occur, and voids are easily formed, resulting in a decrease in moisture absorption reflow heat resistance, which in turn makes the initial characteristics and operating characteristics of semiconductor devices and wiring substrates unstable. Therefore, it is impossible to improve the reliability of semiconductor devices and wiring substrates.

[半導体装置内蔵多層配線基板の製造方法]
次に、本実施形態の半導体装置内蔵多層配線基板の製造方法について図5〜図8に基づき説明する。
ここでは、まず、個々の配線基材、即ち、最上層の配線基材、中実の内層基材、穴明き配線基材、半導体装置搭載内層基材の製造方法について説明し、次いで、これらの配線基材を用いた半導体装置内蔵多層配線基板の製造方法について説明する。
[Manufacturing method of multilayer wiring board with built-in semiconductor device]
Next, the manufacturing method of the semiconductor device built-in multilayer wiring board of this embodiment will be described with reference to FIGS.
Here, first, individual wiring base materials, that is, the uppermost wiring base material, the solid inner layer base material, the perforated wiring base material, and the manufacturing method of the semiconductor device mounting inner layer base material will be described. A method for manufacturing a multilayer wiring board with a built-in semiconductor device using the wiring substrate will be described.

(1)最上層の配線基材及び中実の内層基材
まず、図5(a)に示すように、表面及び裏面が平坦化された熱可塑性樹脂組成物からなる絶縁基材21を作製する。この絶縁基材21は、そのままで最上層基材となる。
次いで、図5(b)に示すように、この絶縁基材21の表面に、スタンパ22の凸部23を熱転写する。この熱転写の条件は、例えば、温度:175〜205℃、圧力:20〜60kg/cmである。
この熱転写により、図5(c)に示すように、絶縁基材21の表面に配線回路形成用溝部12が形成される。
(1) The uppermost wiring base material and the solid inner layer base material First, as shown in FIG. 5A, an insulating base material 21 made of a thermoplastic resin composition having a flattened front surface and back surface is prepared. . This insulating base material 21 becomes the uppermost layer base material as it is.
Next, as shown in FIG. 5B, the convex portion 23 of the stamper 22 is thermally transferred onto the surface of the insulating base material 21. Conditions for this thermal transfer are, for example, temperature: 175 to 205 ° C. and pressure: 20 to 60 kg / cm 2 .
By this thermal transfer, the wiring circuit forming groove 12 is formed on the surface of the insulating base material 21 as shown in FIG.

スタンパ22は、絶縁基材21に対して離型性の良好な材質、例えば、ガラス、セラミックス等により構成されたもので、特に、3〜5mmの厚みの耐熱ガラスが好適に用いられる。このスタンパ22は、耐熱ガラス板上にフォトリソグラフ法を用いてレジストマスクを形成し、その後、このレジストマスクを用いてサンドブラスト法により配線回路パターンに対応する凸部23を形成することにより作製される。   The stamper 22 is made of a material having good releasability with respect to the insulating base material 21, for example, glass, ceramics, and the like, and in particular, heat-resistant glass having a thickness of 3 to 5 mm is preferably used. The stamper 22 is produced by forming a resist mask on a heat-resistant glass plate using a photolithographic method, and then forming a convex portion 23 corresponding to the wiring circuit pattern by a sandblast method using the resist mask. .

次いで、図5(d)に示すように、絶縁基材21の所定位置に、レーザもしくは機械ドリル等を用いて絶縁基材21を貫通する貫通孔を形成し、バイアホール13とする。このバイアホール13は、スタンパにより配線回路形成用溝部12と同時に成形しても構わない。
次いで、図5(e)に示すように、スキージ印刷等により配線回路形成用溝部12及びバイアホール13内に導電性ペースト25を充填し、その後、この導電性ペースト25を120℃〜160℃で、30分〜60分加熱して硬化させ、導電材14とする。
次いで、図示しない研磨機を用いて絶縁基材21上に残っている導電材14aを研削して除去するとともに、絶縁基材21の表面を平坦化する。
以上により、中実の内層基材26を得ることができる。
Next, as shown in FIG. 5D, a through hole that penetrates the insulating base material 21 is formed at a predetermined position of the insulating base material 21 using a laser, a mechanical drill, or the like to form a via hole 13. The via hole 13 may be formed simultaneously with the wiring circuit forming groove 12 by a stamper.
Next, as shown in FIG. 5E, the conductive paste 25 is filled into the wiring circuit forming groove 12 and the via hole 13 by squeegee printing or the like, and then the conductive paste 25 is heated at 120 ° C. to 160 ° C. The conductive material 14 is cured by heating for 30 to 60 minutes.
Next, the conductive material 14a remaining on the insulating base 21 is removed by grinding using a polishing machine (not shown), and the surface of the insulating base 21 is flattened.
Thus, the solid inner layer base material 26 can be obtained.

(2)穴明き配線基材
図6(a)に示すように、その表面及び裏面が平坦化された熱可塑性樹脂組成物からなる絶縁基材31を作製する。
この絶縁基材31の厚みは、半導体装置18の厚みに対して1.05〜1.20倍とする。
(2) Perforated wiring base material As shown in FIG. 6A, an insulating base material 31 made of a thermoplastic resin composition whose front and back surfaces are flattened is prepared.
The thickness of the insulating base 31 is 1.05 to 1.20 times the thickness of the semiconductor device 18.

次いで、図6(b)に示すように、絶縁基材31の所定位置に、レーザもしくは機械ドリル等を用いて絶縁基材31を貫通する貫通孔を形成し、バイアホール13とする。
次いで、図6(c)に示すように、スキージ印刷等によりバイアホール13内に導電性ペースト25を充填し、その後、この導電性ペースト25を120℃〜160℃で、30分〜60分加熱して硬化させ、導電材14とする。
Next, as shown in FIG. 6B, a through hole penetrating the insulating base material 31 is formed at a predetermined position of the insulating base material 31 using a laser, a mechanical drill, or the like to form a via hole 13.
Next, as shown in FIG. 6C, the conductive paste 25 is filled in the via hole 13 by squeegee printing or the like, and then the conductive paste 25 is heated at 120 to 160 ° C. for 30 to 60 minutes. The conductive material 14 is then cured.

次いで、図6(d)に示すように、図示しない研磨機を用いて絶縁基材31上に残っている導電材14aを研削して除去するとともに、絶縁基材31の表面を平坦化する。
次いで、図6(e)に示すように、図示しない打ち抜き用の成型機を用いて、この絶縁基材31の所定箇所に半導体装置収納用の開口部32を打ち抜く。開口部32を打ち抜くための金型の平面形状は、5箇所以上の凹み部を持たない図形、例えば、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形であるとされるが、この金型の平面形状としては、八角形以上三十二角形以下で角部の数が4の倍数である多角形が好ましく、特に八角形、十二角形、十六角形、二十角形が好ましい。また、この金型の平面形状としてより好ましいのは、これらの多角形のすべての角部が曲線形状とされている図形である。こうして、穴明き配線基材33を得ることができる。
この開口部32の寸法・形状は、絶縁基材31が熱圧着される前では半導体装置18に対して所定の隙間が生じるように、また、絶縁基材31が熱圧着された際には半導体装置18の周囲に密着するように、その平面視の寸法・形状が設定される。例えば、半導体装置18の占有面積に対して1.01〜1.05倍とされる。
Next, as shown in FIG. 6D, the conductive material 14a remaining on the insulating base material 31 is ground and removed using a polishing machine (not shown), and the surface of the insulating base material 31 is flattened.
Next, as shown in FIG. 6 (e), an opening 32 for housing a semiconductor device is punched into a predetermined portion of the insulating base 31 using a punching molding machine (not shown). The planar shape of the mold for punching the opening 32 is a figure that does not have five or more recessed parts, for example, a polygon that is a pentagon or more, and a figure in which all corners of the polygon are curved. Although it is said that it is an ellipse, the planar shape of this mold is preferably an octagon or more and 32 or less and a polygon whose number of corners is a multiple of four, particularly an octagon, a dodecagon, A hexagonal shape and an icosahedron shape are preferable. More preferable as the planar shape of the mold is a figure in which all corners of these polygons are curved. In this way, a perforated wiring substrate 33 can be obtained.
The size and shape of the opening 32 is such that a predetermined gap is generated with respect to the semiconductor device 18 before the insulating base 31 is thermocompression-bonded. The size and shape in plan view are set so as to be in close contact with the periphery of the device 18. For example, the area occupied by the semiconductor device 18 is 1.01 to 1.05 times.

(3)半導体装置搭載内層基材
図7(a)に示すように、上記で得られた中実の内層基材26上の所定位置に、半導体装置18を配置し、この半導体装置18上にヒーター内蔵の熱圧着治具28を載置し、この熱圧着治具28を押下させることにより、半導体装置18を絶縁基材21に熱圧着する。熱圧着は、例えば、温度:180〜200℃、圧力:10〜100kg/cmの条件で行う。
(3) Semiconductor Device Mounted Inner Layer Base Material As shown in FIG. 7A, the semiconductor device 18 is disposed at a predetermined position on the solid inner layer base material 26 obtained as described above. A thermocompression bonding jig 28 with a built-in heater is placed, and the thermocompression bonding jig 28 is pressed down so that the semiconductor device 18 is thermocompression bonded to the insulating substrate 21. Thermocompression bonding is performed, for example, under conditions of temperature: 180 to 200 ° C. and pressure: 10 to 100 kg / cm 2 .

この熱圧着により、図7(b)に示すように、半導体装置18の端子19が絶縁基材21の導電材14、すなわち導電回路に電気的に接続されるとともに、半導体装置18と絶縁基材21とが融着一体化された半導体装置搭載内層基材29を得ることができる。   By this thermocompression bonding, as shown in FIG. 7B, the terminal 19 of the semiconductor device 18 is electrically connected to the conductive material 14 of the insulating base material 21, that is, the conductive circuit, and the semiconductor device 18 and the insulating base material are connected. Thus, a semiconductor device mounting inner layer base material 29 can be obtained.

(4)半導体装置内蔵多層配線基板
まず、図8に示すように、ヒーター内蔵の積層治具41内に、弾性及び離型性を有するクッションフィルム42、半導体装置搭載内層基材29、穴明き配線基材33、中実の内層基材26、絶縁基材21及び弾性及び離型性を有するクッションフィルム42をこの順に重ねる。
(4) Multilayer Wiring Board with Built-in Semiconductor Device First, as shown in FIG. 8, in a laminated jig 41 with a built-in heater, a cushion film 42 having elasticity and releasability, a semiconductor device mounting inner layer base material 29, a hole is formed. The wiring substrate 33, the solid inner layer substrate 26, the insulating substrate 21, and the cushion film 42 having elasticity and releasability are stacked in this order.

次いで、押圧治具43を押下させかつ加熱することにより、これら半導体装置搭載内層基材29〜絶縁基材21に熱圧着を施す。
この熱圧着の条件の一例を挙げると、温度:220〜300℃、圧力:10〜60kg/cmである。
こうして、熱圧着を施すことにより、各基材が融着一体化され本発明の半導体装置内蔵多層配線基板を得ることができる。
Subsequently, the pressing jig 43 is pressed down and heated to apply thermocompression to the semiconductor device mounting inner layer base material 29 to the insulating base material 21.
An example of the conditions for thermocompression bonding is as follows: temperature: 220 to 300 ° C., pressure: 10 to 60 kg / cm 2 .
Thus, by applying thermocompression bonding, the respective base materials are fused and integrated, and the semiconductor device built-in multilayer wiring board of the present invention can be obtained.

次に、本実施形態の半導体装置(ICチップ)内蔵多層配線基板40の実施例及び比較例について説明する。   Next, examples and comparative examples of the semiconductor device (IC chip) built-in multilayer wiring board 40 of the present embodiment will be described.

(実験例1)
実施例1においては、開口部16の平面形状が八角形である穴明き配線基材3を用いた。比較例1においては、開口部16の平面形状が四角形である穴明き配線基材3を用いた。これらの穴明き配線基材3と四角形の平面形状を有する半導体装置(ICチップ)を、熱圧着し、融着一体化させた。
実験例1では、図9に示すように、四角形の半導体装置(ICチップ)のひとつの角部がX軸方向には4.115の座標を有し、Y軸方向には3.045の座標を有している。そして、図9に示すような穴明き配線基材3の3つの節(node)の座標変化を測定した。この結果を、表1に示す。
(Experimental example 1)
In Example 1, the perforated wiring substrate 3 in which the planar shape of the opening 16 is an octagon was used. In Comparative Example 1, the perforated wiring base material 3 in which the planar shape of the opening 16 is a quadrangle was used. These perforated wiring base material 3 and a semiconductor device (IC chip) having a square planar shape were thermocompression bonded and fused and integrated.
In Experimental Example 1, as shown in FIG. 9, one corner of a rectangular semiconductor device (IC chip) has a coordinate of 4.115 in the X-axis direction and a coordinate of 3.045 in the Y-axis direction. have. And the coordinate change of three nodes (node) of the perforated wiring base material 3 as shown in FIG. 9 was measured. The results are shown in Table 1.

Figure 0004137739
Figure 0004137739

表1により、実施例1においては、物体の角部と辺部において、穴明き配線基材3の樹脂と半導体装置(ICチップ)との間にできる空間の差が小さいのに対し、比較例1では、穴明き配線基材3の樹脂の変形量が辺部において大きく、角部において小さくなることが分かった。これにより、実施例1の方が、配線基材としてより適していることが分かる。   According to Table 1, in Example 1, the difference between the space formed between the resin of the perforated wiring substrate 3 and the semiconductor device (IC chip) is small in the corners and sides of the object. In Example 1, it was found that the deformation amount of the resin of the perforated wiring base material 3 is large at the side portions and small at the corner portions. Thereby, it turns out that the direction of Example 1 is more suitable as a wiring base material.

(実験例2)
実施例2においては、開口部16の平面形状が八角形である穴明き配線基材3を用いた。実施例3においては、開口部16の平面形状は、実施例2における八角形のすべての角部17が円弧とされている図形である穴明き配線基材3を用いた。比較例2においては、開口部16の平面形状が四角形である穴明き配線基材3を用いた。これらの穴明き配線基材3を熱圧着して、形状を変化させた。なお、これらの例においては、開口部には何も収納しなかった。この結果を、図10から図12に示す。図10から図12は、それぞれ加熱後の穴明き配線基材のひとつの開口部16付近の形状を表しているが、それぞれの図中の破線は、加熱前の穴明き配線基材の形状を表している。また、図中、丸付きの数字はおよそ樹脂の変形量を表しており、数字が大きいところほど変形量が大きい。図10は実施例2に対するものであり、図11は実施例3に対するものであり、図12は比較例2に対するものである。
(Experimental example 2)
In Example 2, the perforated wiring substrate 3 in which the planar shape of the opening 16 is an octagon was used. In Example 3, the perforated wiring substrate 3 having a shape in which all the corners 17 of the octagon in Example 2 are arcs was used as the planar shape of the opening 16. In Comparative Example 2, a perforated wiring base material 3 in which the planar shape of the opening 16 is a quadrangle was used. These perforated wiring base materials 3 were thermocompression bonded to change the shape. In these examples, nothing was stored in the opening. The results are shown in FIGS. FIGS. 10 to 12 each show the shape near one opening 16 of the perforated wiring substrate after heating. The broken lines in each figure indicate the perforated wiring substrate before heating. Represents the shape. In the figure, the numbers with circles represent the deformation amount of the resin, and the larger the number, the larger the deformation amount. FIG. 10 is for Example 2, FIG. 11 is for Example 3, and FIG. 12 is for Comparative Example 2.

図10の実施例1と図11の実施例2では、開口部の角部の形状が直角に近いのに対して、図12の比較例1では、開口部の角部の形状がより尖っていることが分かる。これは、穴明き配線基材3の角部においては、辺部に比べて熱可塑性樹脂の変形量が少ないことに起因するものであると推測される。
また、図10の実施例1と図11の実施例2を比較すると、開口部のすべての角部に曲線をつけることにより、角部の形状をより直角に近くすることができることが分かる。
In Example 1 of FIG. 10 and Example 2 of FIG. 11, the shape of the corner of the opening is close to a right angle, whereas in Comparative Example 1 of FIG. 12, the shape of the corner of the opening is sharper. I understand that. This is presumed to be due to the fact that the amount of deformation of the thermoplastic resin is smaller at the corners of the perforated wiring substrate 3 than at the sides.
Further, comparing Example 1 in FIG. 10 with Example 2 in FIG. 11, it can be seen that the shape of the corner can be made closer to a right angle by providing a curve at all corners of the opening.

本実施形態の穴明き配線基材3及びこれを用いた半導体装置内蔵多層配線基板によれば、半導体装置搭載内層基材4、穴明き配線基材3、中実の内層基材2、最上層の配線基材1を順次積層し、熱圧着し、融着一体化する際に、半導体装置を収納するために形成された開口部16の平面形状が5箇所以上の凹み部10を持たない図形、例えば、五角形以上の多角形、前記多角形のすべての角部17が曲線形状とされている図形、楕円形等のいずれかである穴明き配線基材3を用いているので、積層・熱圧着・融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、半導体装置18と熱可塑性樹脂との間の空間が、半導体装置18の角部30と辺部とにおいて同程度に小さくなることにより、半導体装置18に対する熱可塑性樹脂の圧力が均等になる。そのため、半導体装置自体や、半導体装置と配線基材との間に配線歪みや変形が生じるのを防止することができ、したがって、オープン/ショート(O/S)等の配線不良や寸法のずれ等の不具合を防止することができる。また、ボイドの形成を防止するので、吸湿リフロー耐熱性の低下を防止することができ、高密度かつ超小型の3次元実装モジュールにおける配線ピッチのファイン化を達成することができる。その結果、半導体装置や配線基材の初期特性及び動作特性の安定性を向上させることができ、半導体装置や配線基材の信頼性を向上させることができる。   According to the perforated wiring substrate 3 of this embodiment and the semiconductor device built-in multilayer wiring substrate using the same, the semiconductor device mounting inner layer base material 4, the perforated wiring base material 3, the solid inner layer base material 2, When the uppermost wiring substrate 1 is sequentially laminated, thermocompression-bonded, and fused and integrated, the planar shape of the opening 16 formed to accommodate the semiconductor device has five or more recessed portions 10. Since there is no figure, for example, a polygon more than a pentagon, a figure in which all the corners 17 of the polygon are curved, an elliptical shape, etc., the perforated wiring substrate 3 is used. During the process of laminating, thermocompression bonding, and fusion integration, the thermoplastic resin constituting the perforated wiring substrate 3 changes its shape and fills the space between the semiconductor device 18 and the semiconductor device 18. The space between the corners 30 and the sides of the semiconductor device 18 is reduced to the same extent. By the pressure of the thermoplastic resin is equalized with respect to the semiconductor device 18. Therefore, it is possible to prevent wiring distortion and deformation from occurring between the semiconductor device itself and between the semiconductor device and the wiring base material, and therefore, wiring defects such as open / short (O / S), dimensional deviation, etc. Can be prevented. Further, since the formation of voids is prevented, a decrease in moisture absorption reflow heat resistance can be prevented, and finer wiring pitch can be achieved in a high-density and ultra-small three-dimensional mounting module. As a result, the stability of the initial characteristics and operation characteristics of the semiconductor device and the wiring substrate can be improved, and the reliability of the semiconductor device and the wiring substrate can be improved.

また、本実施形態の穴明き配線基材3及びこれを用いた半導体装置内蔵多層配線基板によれば、半導体装置搭載内層基材4、穴明き配線基材3、中実の内層基材2、最上層の配線基材1を順次積層し、熱圧着し、融着一体化する際に、多角形の平面形状を有する半導体装置18と、この半導体装置18が搭載された配線基材に隣接して配置された穴明き配線基材3においてこの半導体装置を収納するように形成された開口部16との隙間20が半導体装置の角部30において最小であるようにしているので、積層・熱圧着・融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、半導体装置18と熱可塑性樹脂との間の空間が、半導体装置18の角部30と辺部とにおいて同程度に小さくなることにより、半導体装置18に対する熱可塑性樹脂の圧力が均等になる。そのため、半導体装置自体や、半導体装置と配線基材との間に配線歪みや変形が生じるのを防止することができ、したがって、オープン/ショート(O/S)等の配線不良や寸法のずれ等の不具合を防止することができる。また、ボイドの形成を防止するので、吸湿リフロー耐熱性の低下を防止することができ、高密度かつ超小型の3次元実装モジュールにおける配線ピッチのファイン化を達成することができる。その結果、半導体装置や配線基材の初期特性及び動作特性の安定性を向上させることができ、半導体装置や配線基材の信頼性を向上させることができる。   In addition, according to the perforated wiring base material 3 and the semiconductor device built-in multilayer wiring substrate using the same according to the present embodiment, the semiconductor device mounting inner layer base material 4, the perforated wiring base material 3, the solid inner layer base material 2. When the uppermost wiring substrate 1 is sequentially laminated, thermocompression-bonded, and fused and integrated, the semiconductor device 18 having a polygonal planar shape and the wiring substrate on which the semiconductor device 18 is mounted Since the gap 20 with the opening 16 formed so as to accommodate the semiconductor device in the perforated wiring base material 3 arranged adjacently is minimized at the corner 30 of the semiconductor device, In the process in which the thermoplastic resin constituting the perforated wiring substrate 3 changes shape and fills the space with the semiconductor device 18 during thermocompression bonding and fusion integration, the semiconductor device 18 and the thermoplastic resin The space between the corners 30 and the sides of the semiconductor device 18 is the same. By smaller every time, the pressure of the thermoplastic resin is equalized with respect to the semiconductor device 18. Therefore, it is possible to prevent the wiring distortion or deformation from occurring between the semiconductor device itself or between the semiconductor device and the wiring base material. Therefore, wiring defects such as open / short (O / S), dimensional deviation, etc. Can be prevented. Further, since the formation of voids is prevented, a decrease in moisture absorption reflow heat resistance can be prevented, and finer wiring pitches can be achieved in a high-density and ultra-small three-dimensional mounting module. As a result, the stability of the initial characteristics and operation characteristics of the semiconductor device and the wiring substrate can be improved, and the reliability of the semiconductor device and the wiring substrate can be improved.

本実施形態の半導体装置内蔵多層配線基板の製造方法によれば、半導体装置搭載内層基材4、穴明き配線基材3、中実の内層基材2、最上層の配線基材1を順次積層し、熱圧着し、融着一体化する際に、半導体装置を収納するために形成された開口部16の平面形状が5箇所以上の凹み部10を持たない図形、例えば、五角形以上の多角形、前記多角形のすべての角部17が曲線形状とされている図形、楕円形等のいずれかである穴明き配線基材3を用いているので、積層・熱圧着・融着一体化時に、穴明き配線基材3を構成する熱可塑性樹脂が形状変化して半導体装置18との空間を埋めていく過程で、半導体装置18と熱可塑性樹脂との間の空間が、半導体装置18の角部30と辺部とにおいて同程度に小さくなることにより、半導体装置18に対する熱可塑性樹脂の圧力が均等になる。そのため、半導体装置自体や、半導体装置と配線基材との間に配線歪みや変形が生じるのを防止することができ、したがって、オープン/ショート(O/S)等の配線不良や寸法のずれ等の不具合を防止することができる。また、ボイドの形成を防止するので、吸湿リフロー耐熱性の低下を防止することができ、高密度かつ超小型の3次元実装モジュールにおける配線ピッチのファイン化を達成することができる。その結果、半導体装置や配線基材の初期特性及び動作特性の安定性を向上させることができ、半導体装置や配線基材の信頼性を向上させることができる。   According to the method for manufacturing a semiconductor device built-in multilayer wiring board of this embodiment, the semiconductor device mounting inner layer base material 4, the perforated wiring base material 3, the solid inner layer base material 2, and the uppermost wiring base material 1 are sequentially formed. When laminating, thermocompression bonding, and fusion integration, the planar shape of the opening 16 formed to accommodate the semiconductor device is a figure that does not have five or more recesses 10, for example, a pentagon or more Since the perforated wiring base material 3 which is either a square, a figure in which all the corners 17 of the polygon are curved, or an ellipse is used, lamination, thermocompression bonding and fusion integration Sometimes, the space between the semiconductor device 18 and the thermoplastic resin becomes the semiconductor device 18 in the process in which the shape of the thermoplastic resin constituting the perforated wiring substrate 3 changes and fills the space between the semiconductor device 18 and the semiconductor device 18. By reducing the size of the corner 30 and the side to the same extent, The pressure of the thermoplastic resin is equalized for 18. Therefore, it is possible to prevent wiring distortion and deformation from occurring between the semiconductor device itself and between the semiconductor device and the wiring base material, and therefore, wiring defects such as open / short (O / S), dimensional deviation, etc. Can be prevented. Further, since the formation of voids is prevented, a decrease in moisture absorption reflow heat resistance can be prevented, and finer wiring pitch can be achieved in a high-density and ultra-small three-dimensional mounting module. As a result, the stability of the initial characteristics and operation characteristics of the semiconductor device and the wiring substrate can be improved, and the reliability of the semiconductor device and the wiring substrate can be improved.

本発明の一実施形態の穴明き配線基材を示す断面図である。It is sectional drawing which shows the perforated wiring base material of one Embodiment of this invention. 本発明の一実施形態の穴明き配線基材を示す平面図である。It is a top view which shows the perforated wiring base material of one Embodiment of this invention. 本発明の一実施形態の半導体装置内蔵多層配線基板を示す断面図である。It is sectional drawing which shows the semiconductor device built-in multilayer wiring board of one Embodiment of this invention. 本発明の一実施形態の半導体装置内蔵多層配線基板の製造方法を示す過程図である。It is process drawing which shows the manufacturing method of the multilayer wiring board with a built-in semiconductor device of one Embodiment of this invention. 本発明の一実施形態に係る最上層の配線基材、及び、中実の内層基材の製造方法を示す過程図である。It is process drawing which shows the manufacturing method of the uppermost wiring base material which concerns on one Embodiment of this invention, and a solid inner layer base material. 本発明の一実施形態に係る穴明き配線基材の製造方法を示す過程図である。It is a process figure showing a manufacturing method of a perforated wiring substrate concerning one embodiment of the present invention. 本発明の一実施形態に係る半導体装置搭載内層基材の製造方法を示す過程図である。It is a process figure showing a manufacturing method of a semiconductor device loading inner layer base material concerning one embodiment of the present invention. 本発明の一実施形態の半導体装置内蔵多層配線基板の製造方法を示す過程図である。It is process drawing which shows the manufacturing method of the multilayer wiring board with a built-in semiconductor device of one Embodiment of this invention. 本発明の実施に係る穴明き配線基材の形状変化前の状態を示す図である。It is a figure which shows the state before the shape change of the perforated wiring base material based on implementation of this invention. 本発明の実施に係る穴明き配線基材の形状変化の状態を示す図である。It is a figure which shows the state of the shape change of the perforated wiring base material which concerns on implementation of this invention. 本発明の実施に係る穴明き配線基材の形状変化の状態を示す図である。It is a figure which shows the state of the shape change of the perforated wiring base material which concerns on implementation of this invention. 従来の穴明き配線基材の形状変化の状態を示す図である。It is a figure which shows the state of the shape change of the conventional perforated wiring base material.

符号の説明Explanation of symbols

1 最上層の配線基材
2 中実の内層基材
3 穴明き配線基材
4 半導体装置搭載内層基材
10 凹み部
11 絶縁基材
12 溝部
13 バイアホール
14 導電材
15 絶縁基材
16 開口部
17 角部
18 半導体装置
20 隙間
21 絶縁基材
26 中実の内層基材
29 半導体装置搭載内層基材
30 半導体装置の角部
31 絶縁基材
32 開口部
33 穴明き配線基材
DESCRIPTION OF SYMBOLS 1 Top layer wiring base material 2 Solid inner layer base material 3 Holed wiring base material 4 Semiconductor device mounting inner layer base material 10 Recessed part 11 Insulating base material 12 Groove part 13 Via hole 14 Conductive material 15 Insulating base material 16 Opening part DESCRIPTION OF SYMBOLS 17 Corner | angular part 18 Semiconductor device 20 Crevice 21 Insulating base material 26 Solid inner-layer base material 29 Semiconductor device mounting inner-layer base material 30 Semiconductor device corner | angular part 31 Insulating base material 32 Opening part 33 Perforated wiring base material

Claims (7)

熱可塑性樹脂組成物からなる絶縁基材に導体配線が形成された配線基材であって、半導体装置を収納するために形成された開口部の平面形状は、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形のいずれかであり、かつ、5箇所以上の凹み部を持たないことを特徴とする半導体装置内蔵多層配線基板用穴明き配線基材A wiring substrate in which conductor wiring is formed on an insulating substrate made of a thermoplastic resin composition, and the planar shape of an opening formed for housing a semiconductor device is a polygon that is a pentagon or more, the polygon A perforated wiring board for a multilayer wiring board with a built- in semiconductor device , wherein all of the corners of the circuit board are in the shape of a curve or an ellipse, and do not have five or more recesses. Wood . 前記熱可塑性樹脂組成物は、結晶融解ピーク温度が260℃以上である結晶性熱可塑性樹脂組成物、ガラス転移温度が260℃以上である非晶性熱可塑性樹脂組成物、液晶転移温度が260℃以上である液晶ポリマーから選択された1種以上を主成分とすることを特徴とする請求項1記載の半導体装置内蔵多層配線基板用穴明き配線基材The thermoplastic resin composition includes a crystalline thermoplastic resin composition having a crystal melting peak temperature of 260 ° C. or higher, an amorphous thermoplastic resin composition having a glass transition temperature of 260 ° C. or higher, and a liquid crystal transition temperature of 260 ° C. The perforated wiring base material for a multilayer wiring board with a built-in semiconductor device according to claim 1, wherein the main component is at least one selected from the above liquid crystal polymers. 熱可塑性樹脂組成物からなる絶縁基材に導体配線が形成されてなる配線基材が複数、積層され、これら複数の配線基材のうち、1つまたは2つ以上の配線基材に半導体装置が搭載され、この半導体装置が搭載された配線基材に隣接して配置された配線基材には、前記半導体装置を収納するための開口部が形成され、これらの配線基材同士が熱圧着により融着一体化されてなる半導体装置内蔵多層配線基板において、
前記開口部の平面形状は、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形のいずれかであり、かつ、5箇所以上の凹み部を持たないことを特徴とする半導体装置内蔵多層配線基板。
A plurality of wiring base materials in which conductor wiring is formed on an insulating base material made of a thermoplastic resin composition are laminated, and a semiconductor device is mounted on one or two or more wiring base materials among the plurality of wiring base materials. An opening for accommodating the semiconductor device is formed in the wiring substrate disposed adjacent to the wiring substrate on which the semiconductor device is mounted, and these wiring substrates are bonded to each other by thermocompression bonding. In a multilayer wiring board with a built-in semiconductor device formed by fusion,
The planar shape of the opening is a polygon that is a pentagon or more, a figure in which all corners of the polygon are curved, or an ellipse, and does not have five or more indentations. A multilayer wiring board with a built-in semiconductor device.
熱可塑性樹脂組成物からなる絶縁基材に導体配線が形成されてなる配線基材が複数、積層され、これら複数の配線基材のうち、1つまたは2つ以上の配線基材に半導体装置が搭載され、この半導体装置が搭載された配線基材に隣接して配置された配線基材には、前記半導体装置を収納するための開口部が形成され、これらの配線基材同士が熱圧着により融着一体化されてなる半導体装置内蔵多層配線基板において、
これらの配線基材を積層する際に、多角形の平面形状を有する半導体装置と前記開口部との隙間が半導体装置の角部において最小であることを特徴とする半導体装置内蔵多層配線基板。
A plurality of wiring base materials in which conductor wiring is formed on an insulating base material made of a thermoplastic resin composition are laminated, and a semiconductor device is mounted on one or two or more wiring base materials among the plurality of wiring base materials. An opening for accommodating the semiconductor device is formed in the wiring substrate disposed adjacent to the wiring substrate on which the semiconductor device is mounted, and these wiring substrates are bonded to each other by thermocompression bonding. In a multilayer wiring board with a built-in semiconductor device formed by fusion,
A multilayer wiring board with a built-in semiconductor device, wherein when the wiring substrates are laminated, a gap between the semiconductor device having a polygonal planar shape and the opening is minimum at the corner of the semiconductor device.
前記熱可塑性樹脂組成物は、結晶融解ピーク温度が260℃以上である結晶性熱可塑性樹脂組成物、ガラス転移温度が260℃以上である非晶性熱可塑性樹脂組成物、液晶転移温度が260℃以上である液晶ポリマーから選択された1種以上を主成分とする請求項3又は4記載の半導体装置内蔵多層配線基板。 The thermoplastic resin composition includes a crystalline thermoplastic resin composition having a crystal melting peak temperature of 260 ° C. or higher, an amorphous thermoplastic resin composition having a glass transition temperature of 260 ° C. or higher, and a liquid crystal transition temperature of 260 ° C. semiconductor device embedded multilayer wiring board according to claim 3 or 4, wherein a main component at least one selected from a liquid crystal polymer is higher. 熱可塑性樹脂組成物からなる絶縁基材に導体配線が形成されてなる配線基材が複数、積層され、これら複数の配線基材のうち、1つまたは2つ以上の配線基材に半導体装置が搭載され、この半導体装置が搭載された配線基材に隣接されして配置された配線基材には、前記半導体装置を収納するための開口部が形成され、これらの配線基材同士が熱圧着により融着一体化されてなる半導体装置内蔵多層配線基板の製造方法であって、
半導体装置搭載用の配線基材と、基材の一部に前記半導体装置を収納するための開口部が形成され、当該開口部の平面形状が、五角形以上の多角形、前記多角形のすべての角部が曲線形状とされている図形、楕円形のいずれかであり、かつ、5箇所以上の凹み部を持たない半導体装置内蔵多層配線基板用穴明き配線基材と、それ以外の配線基材を作製し、
次いで、前記半導体装置搭載用の配線基材に半導体装置を搭載し、
これらの配線基材を積層し、熱圧着により融着一体化することを特徴とする半導体装置内蔵多層配線基板の製造方法。
A plurality of wiring base materials in which conductor wiring is formed on an insulating base material made of a thermoplastic resin composition are laminated, and a semiconductor device is mounted on one or two or more wiring base materials among the plurality of wiring base materials. The wiring substrate that is mounted and disposed adjacent to the wiring substrate on which the semiconductor device is mounted has an opening for housing the semiconductor device, and the wiring substrates are thermocompression bonded together. A method of manufacturing a multilayer wiring board with a built-in semiconductor device that is fused and integrated by
A wiring substrate for mounting a semiconductor device, and an opening for housing the semiconductor device is formed in a part of the substrate, and a planar shape of the opening is a pentagon or more polygon, all of the polygons Perforated wiring base material for a multilayer wiring board with a built-in semiconductor device that is either a figure with a curved corner or an ellipse and does not have five or more recesses , and other wiring bases Make the material,
Next, the semiconductor device is mounted on the wiring substrate for mounting the semiconductor device,
A method of manufacturing a multilayer wiring board with a built-in semiconductor device, wherein these wiring substrates are laminated and fused and integrated by thermocompression bonding.
複数の前記配線基材を熱圧着により融着一体化する際の温度は、半導体装置搭載用の配線基材のガラス転移温度以上又は液晶転移温度以上であることを特徴とする請求項6記載の半導体装置内蔵多層配線基板の製造方法。 Temperature for fusing integrating a plurality of said wiring substrate by thermocompression bonding, according to claim 6, characterized in that the glass transition temperature or higher, or liquid crystal transition temperature higher than the wiring substrate for the semiconductor device mounted A method of manufacturing a multilayer wiring board with a built-in semiconductor device.
JP2003288083A 2003-08-06 2003-08-06 Perforated wiring base material for multilayer wiring board with built-in semiconductor device, multilayer wiring board with built-in semiconductor device, and manufacturing method thereof Expired - Fee Related JP4137739B2 (en)

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