JP4137774B2 - Driving circuit - Google Patents

Description

The present invention relates to a drive circuitry for emitting a plurality of light emitting elements.

  Conventionally, pachinko machines, which are a type of gaming machine, are used to display information related to gaming or to increase the effect of gaming effects, such as the number of reserved balls, electrical lamps, game board lamps, prize ball lamps, etc. Various light emitting display devices are provided. In these light emitting display devices, for example, light emitting diodes are used as light emitting elements. Recently, there is a tendency to use a large number of light-emitting diodes in combination with a combination of LEDs of a plurality of colors (for example, three colors of RGB (red, green, and blue)) in order to enhance the game effect. For this reason, a pachinko machine including a light emitting display device having a drive circuit of a dynamic drive system that can easily increase the number of light emission decoration patterns by causing multiple LEDs to emit light in multiple colors has been proposed (for example, Patent Document 1). .

Here, a driving circuit 100 of a conventional dynamic driving method (dynamic lighting method) will be described with reference to FIG.
The drive circuit 100 includes a plurality (four in FIG. 10) of pnp transistors TR101 to TR104, and a power supply VB is connected to the emitter side of the pnp transistors TR101 to TR104. Further, common signals COM101 to COM104 can be inputted to the base side of the pnp transistors TR101 to TR104 from a CPU (not shown), respectively. The pnp transistors TR101 to TR104 supply a power supply voltage to the collector side when the common signals COM101 to COM104 are input. Common lines CL101 to CL104 as scanning lines are respectively connected to the collector side of the pnp transistors TR101 to TR104, and a plurality (four in FIG. 10) of light emitting diodes LED101 are connected to each of the common lines CL101 to CL104. -The anode side of LED116 is connected. A plurality (four in FIG. 10) of signal lines SL101 to SL104 as signal lines are arranged in a lattice shape (matrix shape) with the light emitting diodes LED101 to LED116 as intersections. The signal lines SL101 to SL104 are connected to the cathode sides of the light emitting diodes LEDs 101 to 116. The signal lines SL101 to SL104 are connected to the collector side of the npn transistors TR105 to TR108 via resistors R101 to R104, respectively. The emitter sides of the npn transistors TR105 to TR108 are connected to a ground terminal, and segment signals SEG101 to SEG104 are input to the base side from a CPU (not shown).

Then, the CPU sequentially supplies the common signals COM101 to COM104 to the pnp transistors TR101 to TR104 within a predetermined period to supply a power supply voltage to the common lines CL101 to 104. Normally, the power supply voltage is supplied to the common lines CL101 to CL104 in a certain period (horizontal scanning period) alternately in one direction by line sequential scanning. Then, within each horizontal scanning period, the CPU inputs segment signals SEG101 to SEG104 to the npn transistors TR105 to TR108. Accordingly, the light-emitting diodes LED101 to LED116 of the common lines CL101 to CL104 that are fed are connected to the npn transistors TR105 to TR108 to which the segment signals SEG101 to SEG104 are input via the signal lines SL101 to SL104. The light emitting diodes LED101 to LED116 emit light.
JP 2003-24523 (paragraph numbers [0047] to [0049], FIG. 3)

  However, when the light emitting diodes LED101 to LED116 are controlled to emit light by the driving circuit 100 of the dynamic drive system, there is a problem that the light emitting diodes LED101 to LED116 that are not selected are erroneously turned on.

  The drive circuit 100 in FIG. 10 will be described in detail. First, assume that the segment signals SEG101 to SEG103 are input when the common signal COM101 is input. At this time, the light emitting diodes LED101 to LED103 emit light. On the other hand, the light emitting diode LED104 functions equivalently as a capacitor due to the potential difference between the common line CL101 and the signal line SL104. That is, since the power supply voltage is supplied to the anode side of the light emitting diode LED104, while the cathode side is placed in a floating state, negative charges on the signal line SL104 are collected on the cathode side and charged by the amount of the charge. The

  Next, when the common signal COM102 is input and the segment signal SEG104 is input, the light emitting diode LED108 emits light. At this time, since the npn transistor TR108 is in the on state, the negative charge accumulated on the cathode side of the light emitting diode LED104 moves to the ground terminal via the npn transistor TR108. On the other hand, since the pnp type transistor TR101 is in the OFF state, the escape line of the positive charge accumulated on the common line CL101, that is, the anode side of the light emitting diode LED104 is eliminated. For this reason, the potential difference between the anode side and the cathode side of the light emitting diode LED104 becomes large, and the light emitting diode LED104 that should not emit light originally is energized and erroneously lit.

  When such a light-emitting diode light-on occurs in a light-emitting display device that displays information related to a game, for example, a light-emitting light that should not be emitted due to a reserved-ball-number display that displays a stored value of the number of held balls. If the diode (lamp) is turned on erroneously and the stored value of the wrong number of reserved balls is expressed, there is a possibility of causing unnecessary confusion to the player. In addition, if a light-emitting diode of a light-emitting display device that performs a game effect is erroneously turned on, the light-emitting effect (game effect) is not performed vividly due to the flickering of the light-emitting diode, which may impair the interest of the player.

The present invention has been made to solve the above problems, its object is to provide a driving circuits to reliably prevent erroneous lighting of the plurality of light emitting elements.

In order to achieve the above object, the invention according to claim 1 is connected to each of the plurality of first switching elements that are turned on or off by the input of the first signal, and each of the first switching elements. A plurality of scanning lines to which a power supply voltage is supplied when the switching elements are switched on, a plurality of second switching elements that are switched on or off by the input of the second signal, and a connection for each of the second switching elements A plurality of signal lines respectively connected to a reference voltage terminal when the second switching element is switched on, and a plurality of light emitting elements connected between the scanning line and the signal line, Between the scanning line supplied with the power supply voltage by the input of the first signal and the signal line connected to the reference voltage terminal by the input of the second signal. The drive circuit that emits light by the generated potential difference includes a plurality of third switching elements that are turned on or off by the input of a third signal, and the third switching elements are connected in series for each of the scanning lines, and the scanning line switched from off to on by inputting a third signal connected to the reference voltage terminal while discharging the electric charge of the scan lines, the scan lines connected to the scan lines to the reference voltage terminal When the first switching element is turned on by inputting the first signal, it is switched off by inputting the third signal. .

  According to a second aspect of the present invention, in the first aspect of the invention, the third switching element is turned on by the input of the third signal when the signal line is not connected to the reference voltage terminal. The gist is to switch and connect the scanning line to the reference voltage terminal.

  According to a third aspect of the present invention, in the first aspect of the present invention, the third switching element is when a power supply voltage is not supplied to the scanning line, and the signal line is connected to the reference voltage terminal. When not connected, the gist is to switch on by the input of the third signal and connect the scanning line to the reference voltage terminal.

The invention according to claim 4 is the invention according to any one of claims 1 to 3 , wherein the third switching element is smaller than a potential difference required for current to flow through the light emitting element. The gist of the invention is that it has a characteristic of flowing a current from the scanning line to the reference voltage terminal by a potential difference.

  According to the present invention, it is possible to reliably prevent erroneous lighting of a plurality of light emitting elements.

Hereinafter, an embodiment in which the present invention is embodied in a pachinko gaming machine (hereinafter referred to as a “pachinko machine”) that is a kind of the present invention will be described with reference to FIGS.
In FIG. 1, the front side of the pachinko machine 10 is schematically shown, and a vertical rectangular middle frame 12 for setting various game components is opened and closed on the front side of the opening of the outer frame 11 that forms the outline of the machine body. And is detachably assembled. On the front side of the middle frame 12, a front frame 14 and a top ball tray 15 each having a glass frame for protecting the game board 13 disposed inside the machine in a see-through manner are assembled so as to be openable and closable in a laterally open state. . On the front side of the front frame 14, there is a frame lamp (light emitting display device) 16 a that is turned on (flashes) or turned off according to various game states (such as a big hit state) and performs a game effect (light emission effect) based on the light emission decoration. Is provided. The game area 13a of the game board 13 is turned on (flashing) or turned off according to various game states (such as a big hit state), and a game board lamp (light emission display) for performing a game effect (light emission effect) based on the light emission decoration. Device) 16b is provided. The frame lamp 16a and the game board lamp 16b are constituted by a plurality of light emitting diodes. In addition, a speaker 17 that outputs various sounds according to the state of the game and performs a game effect (sound effect) based on the sound output is disposed below the outer frame 11 (lower part of the pachinko machine 10). A lower ball tray 18 and a launching device 19 are attached to the lower part of the middle frame 12.

  In addition, a winning device 20 is disposed substantially at the center of the game area 13 a of the game board 13. Below the winning device 20, start winning ports 21, 22, and 23 are arranged. Behind each of the start winning ports 21 to 23, start winning switches SW1, SW2 and SW3 (shown in FIG. 5) for detecting a winning game ball are provided. And each said start winning opening 21-23 can provide the starting condition of the auxiliary game which opens the winning apparatus 20 in response to the detection of the winning game ball.

Next, the configuration of the winning device 20 will be described with reference to FIG.
The winning device 20 includes an attachment substrate 24 for attaching the winning device 20 to the game board 13. A housing 26 that forms a winning space 25 of the winning device 20 is attached to the mounting substrate 24. The housing 26 is provided with an upper ball receiving plate 27, a middle ball receiving plate 28 and a lower ball receiving plate 29. The housing 26 is equipped with various actuators (solenoids SOL1) that serve as driving sources for various movable devices disposed in the winning device 20.

  A pair of left and right opening / closing blades 30 and 31 are attached to the left and right sides of the upper ball receiving plate 27. The opening / closing blades 30 and 31 are opened and closed (opening and closing operations) by a solenoid SOL1. The opening operation of the opening and closing blades 30 and 31 is an operation that can take an open state (shown by a solid line in FIG. 2) from a closed state (shown by a two-dot chain line in FIG. 2), and the winning device 20 is opened by this opening operation. Thus, the game ball launched on the game board 13 can enter the winning device 20. The closing operation of the opening and closing blades 30 and 31 is an operation that can take the closed state from the open state, and the winning device 20 is closed by this closing operation, and it is impossible for the game ball to flow into the winning device 20. It becomes. Therefore, when the open / close blades 30 and 31 operate so as to be able to take a closed state → open state → closed state, one open / close operation is performed. Further, the upper ball receiving plate 27 is provided with count switches SW4 and SW5 for detecting a game ball flowing into the winning device 20. When the game balls are detected by the count switches SW4 and SW5, the number of game balls that have flowed into the winning device 20 is counted, and a predetermined number (for example, 10) of prize balls are paid out.

  In addition, a display device (light-emitting display device) 32 that performs a predetermined game effect (light-emitting effect) is provided above the upper ball receiving plate 27. The display device 32 is configured by arranging a plurality of light emitting diodes LED1 to LED20 in a matrix form (lattice form) of 5 rows by 4 rows (see FIG. 4). Further, on both the left and right sides of the display device 32, count lamps (light emitting display devices) 33 for notifying the number of game balls that have flowed into the winning device 20 are arranged (see FIG. 3). The count lamp 33 is configured by arranging a plurality (10 in this embodiment) of light emitting diodes LED31 to LED40 symmetrically.

  Further, the intermediate ball receiving plate 28 receives the game ball that has been detected by the count switches SW4 and SW5 and dropped, and guides the game ball toward the rear of the winning device 20. Further, the lower ball receiving plate 29 receives the game ball guided by the middle ball receiving plate 28 and guides the game ball toward the front of the winning device 20. In front of the lower ball receiving plate 29, a special winning opening 40 and a normal winning opening 41 are provided. The special winning opening 40 is disposed at the approximate center of the normal winning opening 41, and is provided in a guide member 40a having a passage shape so that the winning game ball can be guided to the rear of the winning apparatus 20. A special winning opening switch SW6 for detecting a winning game ball is provided behind the guide member 40a (shown in FIG. 5).

  In the pachinko machine 10 configured as described above, an auxiliary game that opens and closes the winning device 20 occurs by opening and closing the opening and closing blades 30 and 31 a predetermined number of times when a game ball is won at the start winning ports 21 to 23. It has come to be. In the auxiliary game, the winning device 20 is opened, and a game ball is allowed to flow into the winning device 20 to give the player a chance to generate a special game (big hit). In the present embodiment, when a game ball wins in the start winning ports 21 and 22, the opening and closing blades 30 and 31 are opened and closed based on the first opening pattern (one opening and closing operation). When a game ball wins the start winning opening 23, the opening / closing blades 30 and 31 are opened / closed based on a second opening pattern (intermittently two opening / closing operations) that is more advantageous than the first opening pattern. It is like that.

  Then, when a game ball that has flowed into the winning device 20 during the auxiliary game wins a special winning opening 40 and is detected, a big hit is generated. The big hit is made up of a predetermined number (for example, 15 times) of cycle games (round games), and gives a player a chance to win a large number of prize balls. In the cycle game, based on the third opening pattern which is more advantageous than the first and second opening patterns, the opening and closing blades 30 and 31 are opened and closed a predetermined number of times (for example, 18 times) or the game ball is won. The opening and closing blades 30 and 31 are repeatedly opened and closed until a predetermined number (for example, 10) flows into the device 20.

  In the display device 32, various display effects are performed. Specifically, during the auxiliary game, when a game ball wins a special winning opening 40, a big hit is generated, and a cycle game is started, a cycle effect is performed. In the cycle effect, an effect of displaying and notifying the display device 32 of the current number of cycle games (how many cycle games) is performed. In addition, the count lamp 33 emits (lights) the light emitting diodes LED31 to LED40 by the number corresponding to the number of game balls detected by the count switches SW4 and SW5 in one cycle game. The number of inflowing game balls is informed.

Hereinafter, the control configuration of the pachinko machine 10 in the present embodiment will be described in detail with reference to FIG.
A main control board 50 for controlling the entire gaming machine is mounted on the back side of the pachinko machine 10. The main control board 50 executes various processes for controlling the entire gaming machine, and outputs various control commands as predetermined control signals according to the processing results. In addition, a display device 32, a frame lamp 16a, a game board lamp 16b, a display lamp control board 52 for controlling the count lamp 33, and a sound control board 53 for controlling the speaker 17 are mounted on the back side of the machine. Each of the control boards 52 and 53 receives various control signals output from the main control board 50 and executes predetermined control based on the control signals.

  Next, the configuration of the main control board 50 will be described. The main control board 50 includes a main CPU (main control means) 50a, and a ROM 50b and a RAM 50c are connected to the main CPU 50a. Various control programs for controlling the pachinko machine 10 are stored in the ROM 50b. The RAM 50c stores (sets) various information that can be appropriately rewritten during the operation of the pachinko machine 10. The switches SW1 to SW6 and the solenoid SOL1 are connected to the main control board 50 (main CPU 50a). And main CPU50a inputs the detection signal from each said switch SW1-SW6, and controls an auxiliary | assistant game and a special game (each cycle game). For example, when a detection signal is input from the count switches SW4 and SW5 during a cycle game, the main CPU 50a displays a control signal for causing the count lamp 33 to emit light and performing a count effect. CPU 52a). Further, the main CPU 50a controls the solenoid SOL1 so that the opening / closing blades 30 and 31 can perform a predetermined opening / closing operation when the detection signals from the start winning switches SW1 to SW3 are input.

  Next, the configuration of the display lamp control board 52 will be described. The display lamp control board 52 includes a sub CPU (production control means) 52a, and a ROM 52b and a RAM 52c are connected to the sub CPU 52a. The ROM 52b stores control data for performing effects corresponding to the control signal output from the main CPU 50a. The control data is information for the sub CPU 52a to control the light emission mode of the frame lamp 16a, the game board lamp 16b, the display device 32, and the count lamp 33. When the sub CPU 52a receives a control signal from the main CPU 50a, Light emission control is performed based on control data for performing an effect associated with the control signal. The RAM 52c stores (sets) various information that can be appropriately rewritten during the operation of the pachinko machine 10. The sub CPU 52a is connected to a drive circuit 55 that emits light from the light-emitting diodes constituting the frame lamp 16a, the game board lamp 16b, the display device 32, and the count lamp 33 by a dynamic driving method (dynamic lighting method). . Then, the sub CPU 52a outputs various signals (common signal, segment signal, discharge signal) to the drive circuit 55 at a predetermined timing, so that the frame lamp 16a, the game board lamp 16b, the display device 32, and the count lamp 33 are output. The light emission is controlled.

  Here, the configuration of the drive circuit 55 will be described. In the present embodiment, the difference between the frame lamp 16a, the game board lamp 16b, the count lamp 33 and the display device 32 is only the arrangement of the light emitting diodes in the pachinko machine 10. Therefore, in the following description, only the configuration of the drive circuit 55 for controlling the light emission mode of the display device 32 will be described. That is, the drive circuit 55 is configured to control the light emission mode of the frame lamp 16a, the game board lamp 16b, and the count lamp 33, for example, connected to the light emitting diodes that constitute the frame lamp 16a, the game board lamp 16b, and the count lamp 33. The configuration of the segment driver is omitted. FIG. 6 is a block diagram showing the configuration of the drive circuit 55 for controlling the light emission mode of the display device 32.

  The drive circuit 55 includes a common driver 56, a discharge circuit 57, and a segment driver 58, and the light emitting diodes LED <b> 1 to LED <b> 20 constituting the display device 32 are connected to the drive circuit 55. As shown in FIG. 4, the light emitting diodes LED <b> 1 to LED <b> 20 constitute a display device 32 by being arranged in a matrix of 4 columns and 5 columns.

Next, the circuit configuration of the drive circuit 55 for controlling the light emission mode of the display device 32 will be described with reference to the circuit diagram of FIG.
The common driver 56 includes a plurality (four in this embodiment) of pnp transistors TR1 to TR4. The emitter sides of the pnp transistors TR1 to TR4 are connected to the positive terminal of the power supply VB, and the sub CPU 52a is connected to the base side so that common signals COM1 to COM4 are input. Common lines CL1 to CL4 as scanning lines are connected to the collector sides of the pnp transistors TR1 to TR4, respectively. Accordingly, the pnp transistors TR1 to TR4 are switched from off to on when the common signals COM1 to COM4 are input (the common signals COM1 to COM4 are changed to H level (high level, hereinafter the same)), and are connected to the collector side. A power supply voltage Vb (12 V in this embodiment) of the power supply VB is applied to each of the common lines CL1 to CL4.

  In addition, light emitting diodes LED1 to LED20 constituting the display device 32 are connected to the common lines CL1 to CL4. That is, the anode sides of a plurality of light emitting diodes LED1 to LED20 (5 in each embodiment) are connected to each common line CL1 to CL4. More specifically, the anode side of the light emitting diodes LED1 to LED5 is connected to the common line CL1. The anode side of the light emitting diodes LED6 to LED10 is connected to the common line CL2. The anode side of the light emitting diodes LED11 to LED15 is connected to the common line CL3. The anode side of the light emitting diodes LED16 to LED20 is connected to the common line CL4.

  Moreover, the cathode side of light emitting diode LED1-LED20 which comprises the display apparatus 32 is connected to signal line SL1-SL5 as a signal line. Specifically, the cathode sides of the light emitting diodes LED1, LED6, LED11, and LED16 are connected to the signal line SL1. Further, the cathode sides of the light emitting diodes LED2, LED7, LED12, and LED17 are connected to the signal line SL2. The cathode sides of the light emitting diodes LED3, LED8, LED13, and LED18 are connected to the signal line SL3. The cathode sides of the light emitting diodes LED4, LED9, LED14, and LED19 are connected to the signal line SL4. The cathode sides of the light emitting diodes LED5, LED10, LED15, and LED20 are connected to the signal line SL5.

  Next, the discharge circuit 57 connected to the common lines CL1 to CL4 will be described. The discharge circuit 57 includes a plurality (four in this embodiment) of npn transistors TR5 to TR8 and a plurality (four in this embodiment) of resistors R1 to R4.

  The collector side of the npn transistor TR5 is connected to a common line CL1 connected to the common driver 56 via a resistor R1. The emitter side of the npn transistor TR5 is connected to a ground terminal as a reference voltage terminal, and the sub CPU 52a is connected to the base side so that a discharge signal is input. The ground terminal applies a predetermined reference potential (in this embodiment, 0 V (zero volt)). Similarly, the collector sides of npn transistors TR6 to TR8 are connected to common lines CL2 to CL4 via resistors R2 to R4, respectively. The emitter sides of the npn transistors TR6 to TR8 are each connected to a ground terminal, and the sub CPU 52a is connected to the base side so that a discharge signal is input. Therefore, the npn transistors TR5 to TR8 are switched from OFF to ON when the discharge signal is input (the discharge signal becomes H level), and the common lines CL1 to CL4 connected to the collector side are grounded to the ground terminal. It becomes.

  Next, the segment driver 58 connected to the signal lines SL1 to SL5 will be described. The segment driver 58 includes npn transistors TR11 to TR15 and resistors R11 to R15.

  The collector side of the npn transistor TR11 is connected to a signal line SL1 connected to the display device 32 via a resistor R11. Further, the emitter side of the npn transistor TR11 is connected to the ground terminal, the base side is connected to the sub CPU 52a, and the segment signal SEG1 is inputted. Similarly, the collector sides of the npn transistors TR12 to TR15 are connected to signal lines SL2 to SL5 via resistors R12 to R15, respectively. The emitter sides of the npn transistors TR12 to TR15 are connected to the ground terminal, the base side is connected to the sub CPU 52a, and the segment signals SEG2 to SEG5 are input thereto. Therefore, when the segment signals SEG1 to SEG5 are input to the npn transistors TR11 to TR15 (the segment signals SEG1 to SEG5 are at the H level), the npn transistors TR11 to TR15 are switched from off to on, and the signal lines SL1 to SL5 connected to the collector side are connected. It will be grounded to the ground terminal.

  Accordingly, the common lines CL1 to CL4 are scanning lines to which power supply voltage is supplied, and the signal lines SL1 to SL4 are signal lines that are grounded to the ground terminal. The pnp transistors TR1 to TR4 are switching elements (first switching elements) that are turned on / off by the input of the common signals COM1 to COM4, and the npn transistors TR11 to TR15 are turned on by the input of the segment signals SEG1 to SEG4. A switching element (second switching element) that switches off. In addition, the npn transistors TR5 to TR8 serve as switching elements (third switching elements) that switch the scanning lines to be grounded to the ground terminal and discharge the scanning lines when a discharge signal is input. The light emitting diodes LED1 to LED20 serve as light emitting elements that emit light due to a potential difference generated between the scanning line and the signal line. Further, since the common signals COM1 to COM4 are input to the pnp transistors TR1 to TR4, they are the first signals, and the segment signals SEG1 to SEG5 are input to the npn transistors TR11 to TR15, and thus are the second signals. . Further, since the discharge signal is input to the npn transistors TR5 to TR8, it becomes the third signal.

Next, the operation of the drive circuit 55 will be described.
The sub CPU 52a receiving the control signal from the main CPU 50a reads out control data for performing an effect corresponding to the control signal from the ROM 52b, and sequentially outputs various signals to the drive circuit 55 based on the control data.

  More specifically, when the sub CPU 52a receives a control signal from the main CPU 50a, the sub CPU 52a reads control data for performing an effect corresponding to the control signal from the ROM 52b. Based on the control data, the sub CPU 52a sequentially inputs the common signals COM1 to COM4 in one direction to the pnp transistors TR1 to TR4 in a certain period (horizontal scanning period) (the common signals COM1 to COM4 are set to H). To level). Accordingly, the power supply voltage Vb is applied to the common lines CL1 to CL4 sequentially and selectively in one direction for a certain period. The sub CPU 52a sets the discharge signal to H level before setting the common signals COM1 to COM4 to H level, switches the npn transistors TR5 to TR8 from off to on, and grounds the common lines CL1 to CL4 to the ground terminal. The electric charges of the common lines CL1 to CL4 are discharged. Then, within each horizontal scanning period, the sub CPU 52a sets the segment signals SEG1 to SEG4 to the H level based on the control data. Accordingly, the signal lines SL1 to SL4 are connected to the npn transistors TR11 to TR15 of the light emitting diodes LED1 to LED20 of the common lines CL1 to CL4 to which the power supply voltage Vb is applied and the segment signals SEG1 to SEG4 are set to the H level. The light emitting diodes LED1 to LED20 connected via the light emit light. That is, the sub CPU 52a causes the desired light emitting diodes LED1 to LED20 to emit light.

  The operation of the drive circuit 55 will be described more specifically. In the following, when the main CPU 50a determines that the number “1” is to be displayed on the display device 32, and the sub CPU 52a displays “1” on the display device 32 (light emitting diodes LED3, LED7, LED8, LED13, LED17). , LED 18, LED 19) will be described with reference to FIGS. 4 and 8. In FIG. 4, the light emitting diodes LED 3, LED 7, LED 8, LED 13, LED 17, LED 18, and LED 19 that emit light when “1” is displayed on the display device 32 are shaded. FIG. 8 is a timing chart showing input timings of various signals when the light emitting diodes LED3, LED7, LED8, LED13, LED17, LED18, and LED19 are caused to emit light.

  First, the sub CPU 52a raises the discharge signal to H level (time A). At this time, the npn transistors TR5 to TR8 are switched from OFF to ON, and the common lines CL1 to CL4 are grounded to the ground terminal via the npn transistors TR5 to TR8, so that positive charges are accumulated in the common lines CL1 to CL4. If so, it will be discharged. Thereafter, the sub CPU 52a raises the common signal COM1 to H level (time B). Then, after the common signal COM1 becomes H level, the sub CPU 52a falls the discharge signal to L level (low level, the same applies hereinafter) (time C). At this time, the power supply voltage Vb is applied to the light emitting diodes LED1 to LED5. Note that when the discharge signal is at the H level, the common signal COM1 is raised to the H level, and then the discharge signal is set to the L level to improve the switching characteristics of the pnp transistor TR1 and to instantaneously set the power supply voltage Vb. This is because the light is applied to the light emitting diodes LED1 to LED5. That is, the rise of the power supply voltage Vb is improved.

  The sub CPU 52a sets the common signal COM1 to the H level and the discharge signal to the L level, and then raises the segment signal SEG3 to the H level (time D). The reason why the sub CPU 52a raises the segment signal SEG3 to H level after setting the common signal COM1 to H level is to prevent reverse current from flowing to the light emitting diodes LED1 to LED20. When the common signal COM1 and the segment signal SEG3 are set to the H level, the pnp transistor TR1 and the npn transistor TR13 are switched from OFF to ON. Then, the power supply voltage Vb is applied to the common line CL1, and the potential difference between the common line CL1 and the signal line SL3 becomes the same as the power supply voltage Vb (12V) applied from the power supply VB (that is, the power supply to the light emitting diode LED3). Voltage Vb is applied). Therefore, when the power supply voltage Vb (12 V) is applied to the light emitting diode LED3, a current flows and the light emitting diode LED3 emits light. The light-emitting diode is configured such that a current flows when the potential difference between the anode side and the cathode side is equal to or greater than a predetermined threshold value. The threshold values of the light-emitting diodes LED1 to LED20 of the present embodiment are individual even if they are the same product. Although there is a difference, it is approximately 1.8V to 2.2V.

  At this time, the anode side (common line CL1) of the light emitting diodes LED1, LED2, LED4, and LED5 is supplied with the power supply voltage Vb, while the cathode side (signal lines SL1, SL2, SL4, SL5) is connected to the ground terminal. It is not grounded and is left floating. For this reason, the light emitting diodes LED1, LED2, LED4, and LED5 are equivalently capacitors due to the potential difference between the common line CL1 and the signal lines SL1, SL2, SL4, and SL5. That is, negative charges on the signal lines SL1, SL2, SL4, and SL5 gather on the cathode side of the light emitting diodes LED1, LED2, LED4, and LED5, and are charged by the amount of the charge.

  After a lapse of a predetermined time after the light emitting diode LED3 emits light, the sub CPU 52a lowers the common signal COM1 to L level (time E). That is, the pnp transistor TR1 is switched from on to off. At this time, since the power supply voltage Vb is not applied, the potential difference between the common line CL1 and the signal line SL3 becomes small, and the voltage applied to the light emitting diode LED3 becomes equal to or less than the threshold value of the light emitting diodes LED1 to LED20. That is, no current flows through the light emitting diode LED3, and the light emitting diode LED3 is turned off. Next, the sub CPU 52a causes the segment signal SEG3 to fall to the L level (time F). That is, the npn transistor TR13 is switched from on to off. Then, after turning off the npn transistor TR13, the sub CPU 52a raises the discharge signal to H level (time G). That is, the sub CPU 52a changes the common signal COM1 and the segment signal SEG3 to the L level and changes the discharge signal from the L level to the H level with all the pnp transistors TR1 to TR4 and the npn transistors TR11 to TR15 turned off. . At this time, the npn transistors TR5 to TR8 are switched from OFF to ON, and the common lines CL1 to CL4 are grounded to the ground terminal via the npn transistors TR5 to TR8, so that the positive charges accumulated in the common line CL1 are stored. Is discharged. That is, the positive charge accumulated on the anode side of the light-emitting diodes LED1, LED2, LED4, and LED5 equivalent to capacitors due to the negative charge collected on the cathode side is transferred to the ground terminal via the npn transistor TR5. Inflow and discharge. The reason why the sub CPU 52a sets the segment signal SEG3 to the L level and then raises the discharge signal to set the H level is to discharge the charges accumulated in the common line CL1 and to light-emitting diodes LED1 to LED20. This is to prevent a reverse current from flowing through. The sub CPU 52a raises both the common signal COM1 and the segment signal SEG3 to the L level, and then raises the discharge signal to the H level, in addition to the above reason, the power source VB applied to the common line CL1. This is to reduce current consumption.

  Incidentally, when the npn transistors TR5 to TR8 are turned on, in order to pass a current from the collector side to the emitter side of the npn transistors TR5 to TR8, the characteristics of the npn transistors TR5 to TR8 cause the collector side and the emitter side to change. A potential difference of about 0.6 V or more (this also varies depending on the individual. In experimental values, 0.56 to 0.66 V) or more is necessary. For this reason, a maximum potential of 0.66 V may remain on the anode side (on the common line CL1) of the light emitting diodes LED1, LED2, LED4, and LED5. Therefore, when the npn transistors TR11 to TR15 are turned on from off and the cathode side of the light emitting diodes LED1, LED2, LED4, and LED5 (signal lines SL11, SL12, SL14, SL15) is grounded, the electric charge that could not be discharged A voltage of 0.66 V at maximum is applied to the light emitting diodes LED1, LED2, LED4, and LED5. However, since a voltage of at least a threshold value (1.8 to 2.2 V) must be applied in order to pass a current through the light emitting diodes LED1 to LED20, the light emitting diodes LED1, LED2, LED4, and LED5 are required after discharge. Current does not flow through. That is, in the npn transistors TR5 to TR8, current flows with a potential difference (0.56 to 0.66V) smaller than the potential difference (1.8 to 2.2V) necessary for the current to flow through the light emitting diodes LED1 to LED20. Due to the characteristics, after discharging, the electric charge does not remain so that the light emitting diodes LED1 to LED20 emit light on the common lines CL1 to CL4. Therefore, after the discharge, the light emitting diodes LED1 to LED20 are surely prevented from erroneous lighting.

  Subsequently, the sub CPU 52a raises the common signal COM2 to H level (time H), and then lowers the discharge signal to L level (time I). Then, the sub CPU 52a raises the segment signals SEG2 and SEG3 to H level (time J). For this reason, the pnp transistor TR2 and the npn transistors TR12 and TR13 are turned on from off, a potential difference is generated between the common line CL2 and the signal lines SL2 and SL3, and the power supply voltage Vb is applied to the light emitting diodes LED7 and LED8. . That is, current flows through the light emitting diodes LED7 and LED8, and the light emitting diodes LED7 and LED8 emit light. At this time, since the electric charges of the common lines CL1 to CL4 are discharged from the time G to the time I by the discharge circuit 57, the light emitting diode LED2 does not emit light even if the signal line SL2 is grounded. When the common signal COM2 and the segment signals SEG2 and SEG3 become H level, negative charges are collected on the cathode side of the light emitting diodes LED6, LED9, and LED10, and the light emitting diodes LED6, LED9, and LED10 are equivalently capacitors.

  Thereafter, the sub CPU 52a causes the common signal COM2 to fall to the L level (time K). At this time, the pnp transistor TR2 is turned from on to off, the potential difference between the common line CL2 and the signal lines SL2 and SL3 becomes equal to or less than the threshold value of the light emitting diodes LED1 to LED20, and no current flows through the light emitting diodes LED7 and LED8. Accordingly, the light emitting diodes LED7 and LED8 are turned off. Next, the sub CPU 52a causes the signal lines SL2 and SL3 to fall to the L level (time L). That is, the npn transistors TR12 and TR13 are switched from on to off. After the common signal COM2 and the segment signals SEG2 and SEG3 are all set to the L level, the sub CPU 52a raises the discharge signal to the H level and is equivalent to a capacitor due to the negative charges collected on the cathode side. The positive charges on the anode side of the light emitting diodes LED6, LED9, and LED10 are discharged (time M).

  Subsequently, the sub CPU 52a raises the common signal COM3 to H level (time N), and then lowers the discharge signal to L level (time O). Then, the sub CPU 52a raises the segment signal SEG3 to H level (time P). Therefore, the pnp transistor TR3 and the npn transistor TR13 are turned on from off, a potential difference is generated between the common line CL3 and the signal line SL3, and the power supply voltage Vb is applied to the light emitting diode LED13. That is, a current flows through the light emitting diode LED13, and the light emitting diode LED13 emits light. When the common signal COM3 and the segment signal SEG3 become H level, negative charges are collected on the cathode side of the light emitting diodes LED11, LED12, LED14, and LED15, and the light emitting diodes LED11, LED12, LED14, and LED15 are equivalently capacitors.

  Thereafter, the sub CPU 52a causes the common signal COM3 to fall to the L level (time Q). At this time, the pnp-type transistor TR3 is turned off from on, the potential difference between the common line CL3 and the signal line SL3 becomes less than the threshold value of the light emitting diodes LED1 to LED20, and no current flows through the light emitting diode LED13. Accordingly, the light emitting diode LED13 is turned off. Next, the sub CPU 52a causes the signal line SL3 to fall to L level (time R). That is, the npn transistor TR13 is switched from on to off. Then, after setting both the common signal COM3 and the segment signal SEG3 to the L level, the sub CPU 52a raises the discharge signal to the H level, and the light emitting diode that has become an equivalent capacitor due to the negative charge collected on the cathode side The positive charge on the anode side of LED11, LED12, LED14, and LED15 is discharged (time S).

  Subsequently, the sub CPU 52a raises the common signal COM4 to H level (time T), and then lowers the discharge signal to L level (time U). Then, the sub CPU 52a raises the segment signals SEG2, SEG3 and SEG4 to H level (time V). For this reason, the pnp transistor TR4 and the npn transistors TR12, TR13, TR14 are turned on from off, and a potential difference is generated between the common line CL4 and the signal lines SL2, SL3, SL4, and the light emitting diodes LED17, LED18, LED19 are supplied with power. A voltage Vb is applied. That is, current flows through the light emitting diodes LED17, LED18, and LED19, and the light emitting diodes LED17, LED18, and LED19 emit light. At this time, since the electric charges of the common lines CL1 to CL4 are discharged by the discharge circuit 57 between the time S and the time U, the light emitting diodes LED12 and LED14 do not emit light even if the signal lines SL2 and SL4 are grounded. When the common signal COM4 and the segment signals SEG2, SEG3, and SEG4 become H level, negative charges are collected on the cathode side of the light emitting diodes LED16 and LED20, and the light emitting diodes LED16 and LED20 are equivalently capacitors.

  Thereafter, the sub CPU 52a causes the common signal COM4 to fall to the L level (time W). At this time, the pnp-type transistor TR4 is turned off from on, the potential difference between the common line CL4 and the signal lines SL2, SL3, SL4 becomes less than the threshold value of the light emitting diodes LED1 to LED20, and current flows to the light emitting diodes LED17, LED18, LED19. No longer flows. Accordingly, the light emitting diodes LED17, LED18, and LED19 are turned off. Next, the sub CPU 52a causes the signal lines SL2, SL3, and SL4 to fall to the L level (time X). That is, the npn transistors TR12, TR13, TR14 are switched from on to off. After the common signal COM4 and the segment signals SEG2, SEG3, and SEG4 are all set to the L level, the sub CPU 52a raises the discharge signal again to the H level (time A), and the negative charge collected on the cathode side The positive charges on the anode side of the light-emitting diodes LED16 and LED20 that are equivalently capacitors are discharged. Thereafter, the operation from time A to time X is repeated until the next control signal is input from the main CPU 50a.

  These operations from the time A to the time X are performed in a very short time, and the operations from the time A to the time X are repeatedly performed. It can be recognized as an image. That is, for human vision, the light emitting diodes LED3, LED7, LED8, LED13, LED17, LED18, and LED19 can be recognized to be lit at the same time, and the display device 32 emits the number “1”. It is possible to visually recognize as displayed. A driving method in which the light-emitting diodes LED1 to LED20 are recognized to be simultaneously turned on by the afterimage phenomenon by repeating the lighting / light-off operation in this way is called a dynamic driving method (dynamic lighting method).

  In this embodiment, at time A, time G, time M, and time S, the discharge signal is raised to H level to turn on the npn transistors TR5 to TR8 and discharge the charges on the common lines CL1 to CL4. This process is the first step. Further, at time B, time H, time N, and time T, the process of setting the common signals COM1 to COM4 to H level and turning on the pnp transistors TR1 to TR4 is a second step. In addition, at time C, time I, time O, and time U, the process of setting the discharge signal to the L level and switching off the npn transistors TR5 to TR8 is the third step. Further, at time D, time J, time P, and time V, the process of setting the segment signals SEG1 to SEG5 to the H level to turn on the npn transistors TR11 to TR15 and causing the light emitting diodes LED1 to LED20 to emit light is the fourth step. Become. Further, at time E and time F, time K and time L, time Q and time R, time W and time X, the common signals COM1 to COM4 and the segment signals SEG1 to SEG5 are set to L level, and the pnp transistors TR1 to TR4 are set. And the process which switches off the npn-type transistors TR11-TR15 and turns off the light-emitting diodes LED1-LED20 is the fifth step.

  Further, the difference between the frame lamp 16 a, the game board lamp 16 b and the count lamp 33 and the display device 32 is only the arrangement of the light emitting diodes in the pachinko machine 10. Therefore, although the detailed description is omitted, the sub CPU 52a performs the same sequence for the drive circuit 55 having the same circuit configuration with respect to the light emitting diodes constituting the frame lamp 16a, the game board lamp 16b, and the count lamp 33. The light emission is controlled by outputting various signals.

Therefore, according to the present embodiment, the following effects can be obtained.
(1) The drive circuit 55 that controls the light emission of the light emitting diodes LED1 to LED20 is provided with a discharge circuit 57 connected to the common lines CL1 to CL4 so as to discharge the charges of the common lines CL1 to CL4. For this reason, it is possible to prevent erroneous lighting of the light emitting diodes LED1 to LED20, which are generated due to accumulation of excess charges on the common lines CL1 to CL4 (more specifically, the anode side of the light emitting diodes LED1 to LED20). That is, flickering of the display device 32, the frame lamp 16a, the game board lamp 16b, and the count lamp 33 can be prevented.

  (2) When a discharge signal is input (set to H level), the pnp transistors TR1 to TR4 are switched from OFF to ON, and the common lines CL1 to CL4 are grounded to the ground terminal and stored in the common lines CL1 to CL4. The charge is discharged. Therefore, by controlling the timing at which the discharge signal is input, it is possible to reliably remove excess charges accumulated in the common lines CL1 to CL4, and to prevent erroneous lighting of the light emitting diodes LED1 to LED20. .

  (3) Since the discharge circuit 57 discharges the charges on the common lines CL1 to CL4 when the signal lines SL1 to SL4 are not grounded to the ground terminal, the discharge circuit 57 reliably discharges the charges accumulated on the common lines CL1 to CL4. can do. Moreover, it is possible to prevent a reverse current from flowing through the light emitting diodes LED1 to LED20 by discharging the charges accumulated in the common lines CL1 to CL4 when the signal lines SL1 to SL4 are not grounded. Therefore, it is possible to prevent erroneous lighting of the light emitting diodes LED <b> 1 to LED <b> 20 caused by the reverse current flowing. Moreover, since generation | occurrence | production of a reverse current is prevented, failure (breakage | damage) of light emitting diode LED1-LED20 by a reverse current can be suppressed.

  (4) When the npn transistors TR5 to TR8 are turned on, the potential difference (0.56 to 0.66 V) required to flow current from the collector side to the emitter side is from the anode side of the light emitting diodes LED1 to LED20. It was made smaller than the potential difference (1.8 to 2.2 V) necessary for flowing current to the cathode side. For this reason, when the discharge circuit 57 discharges the charges of the common lines CL1 to CL4, the potential difference between the anode side and the cathode side of the light emitting diodes LED1 to LED20 is changed between the collector side and the emitter side of the pnp transistors TR1 to TR4. It becomes the same as the potential difference between. Accordingly, even after the discharge, even if the cathode side of the light emitting diodes LED1 to LED20 to which the power supply voltage Vb is not applied to the anode side is grounded to the ground terminal, the voltage applied to the light emitting diodes LED1 to LED20 is The voltage is not high enough to allow current to flow through the LED 20. For this reason, after the discharge, the unselected light emitting diodes LED1 to LED20 do not emit light, and flickering (incorrect lighting) of the frame lamp 16a, the game board lamp 16b, the display device 32, and the count lamp 33 can be suppressed.

  (5) The light emitting diodes LED1 to LED20 constituting the display device 32 are arranged and connected in a matrix. For this reason, it becomes possible to express a number, a character, etc. by selecting light emitting diode LED1-LED20 made to light-emit.

  (6) Since the pachinko machine 10 is provided with the drive circuit 55 that prevents the light emitting diodes LED1 to LED20 from being erroneously turned on, the frame lamp 16a, the game board lamp 16b, the display device 32, and the count lamp 33 are used in the light emission effect during the game. Flickering can be suppressed. Therefore, it is possible to prevent discomfort caused by flickering to the player and confusion caused by erroneous lighting of the display device 32 and the count lamp 33 that provide information related to the game. Further, since flickering is eliminated, the light emission effect can be performed vividly and the player's interest can be improved.

  (7) While the discharge signal is set to H level and the npn transistors TR5 to TR8 of the discharge circuit 57 are turned on, the common signals COM1 to COM4 are set to H level and the pnp transistors TR1 to TR4 of the common driver 56 are turned on. Then, after turning on the pnp transistors TR1 to TR4, the discharge signal was set to L level. For this reason, the switching characteristics of the pnp transistors TR1 to TR4 are improved, and the power supply voltage Vb is instantaneously applied to the light emitting diodes LED1 to LED20 (that is, the rising of the power supply voltage Vb is improved). The LEDs 1 to 20 can be switched quickly. Further, since the pnp transistors TR1 to TR4 are discharged when they are off, power consumption can be suppressed.

  (8) Since the driving circuit 55 causes the light emitting diodes LED1 to LED20 constituting the display device 32 to emit light by the dynamic driving method, the light emitting diodes LED1 to LED20 can easily emit light to increase the pattern of the light emitting decoration. be able to. For this reason, a player's interest can be improved.

  (9) Before the light emitting diodes LED1 to LED20 are caused to emit light, a discharge signal is always input to discharge excess electric charges accumulated in the common lines CL1 to CL4, thereby reliably preventing erroneous lighting of the light emitting diodes LED1 to LED20. be able to. That is, even in the state where excess charges are accumulated in the common lines CL1 to CL4, since the light emitting diodes LED1 to LED20 are discharged before light emission, flickering of the light emitting diodes LED1 to LED20 can be reliably prevented. .

  (10) After all the common signals COM1 to COM4 and the segment signals SEG1 to SEG5 are set to L level and the pnp transistors TR1 to TR4 and npn transistors TR11 to TR15 are turned off, the discharge signal is set to H level and npn The type transistors TR5 to TR8 were turned on, and the charges on the common lines CL1 to CL4 were discharged. For this reason, it is possible to reliably discharge the charges accumulated in the common lines CL1 to CL4 and prevent a reverse current from flowing through the light emitting diodes LED1 to LED20, and to supply the current of the power source VB applied to the common lines CL1 to CL4. Consumption can be suppressed.

  (11) An npn transistor TR5 in which a current flows from the collector side to the emitter side with a potential difference smaller than a potential difference (1.8 to 2.2 V) necessary for flowing a current from the anode side to the cathode side of the light emitting diodes LED1 to LED20. -TR8 was connected to each of the common lines CL1-CL4, and the discharge circuit 57 was comprised. For this reason, it is possible to provide the discharge circuit 57 that can reliably prevent erroneous lighting and can contribute to the reduction of the manufacturing cost.

  For example, in the case of the discharge circuit 71 in which the anode sides of the discharge diodes LED21 to LED24 are connected to the common lines CL1 to CL4 and the npn transistor TR21 is connected to the cathode side (see FIG. 9), the discharge diodes LED21 to LED24 are connected. Manufacturing cost can be reduced by using the same product as the light emitting diodes LED1 to LED20.

  However, there are individual differences in the threshold value of the voltage required to flow the currents of the light emitting diodes LED1 to LED20, even if the product is the same. If the same product is used, erroneous lighting may not be prevented. For example, when the threshold value of the discharging diode LED21 is 2.2V, even if the npn transistor TR21 is turned on and discharged, a potential of 2.2V remains on the common line CL1. If the threshold value of the light emitting diode LED1 is 1.8V, when the cathode side of the light emitting diode LED1 is grounded to the ground terminal, a voltage higher than the threshold value of the light emitting diode LED1 of 2.2V is applied to the light emitting diode LED1. As a result, the light emitting diode LED1 may be erroneously lit. In order to prevent this, apart from the light emitting diodes LED1 to LED20, special discharging diodes LED21 to LED24 having a threshold value smaller than 1.8 V must be prepared. Therefore, in the discharge circuit 71, if it is intended to prevent erroneous lighting, special discharge diodes LED21 to LED24 are required as described above, and the type of parts and labor for assembly increase, which increases the manufacturing cost. . That is, the discharge circuit 71 shown in FIG. 9 has a configuration like the discharge circuit 57 of the present embodiment because it can surely prevent erroneous lighting and cannot contribute to a reduction in manufacturing cost.

In addition, the said embodiment can be changed into the following embodiment (another example).
The light emitting diodes LED1 to LED20 constituting the display device 32 of the above embodiment are arranged and connected in a matrix of 5 rows and 4 columns, but are not limited to 5 rows and 4 columns. It may be arranged and connected in a matrix of 16 columns and 16 columns vertically.

  In the above embodiment, the common signals COM1 to COM4 are set to the H level while the discharge signal is at the H level, and then the discharge signal is set to the L level. However, after the discharge signal is changed from the H level to the L level, the common signal COM1 ˜COM4 may be set to H level.

In the above embodiment, the light emitting diodes LED1 to LED20 are employed as the light emitting elements, but the present invention is not limited thereto, and for example, EL elements may be used.
In the above embodiment, the frame lamp 16a, the game board lamp 16b, the count lamp 33, and the drive circuit 55 of the display device 32 are integrally configured, and the frame lamp 16a, the game board lamp 16b, the count lamp 33, and the display device 32 are provided. A drive circuit 55 that can be driven entirely is provided. As another example, separate drive circuits may be provided for the frame lamp 16a, the game board lamp 16b, the count lamp 33, and the display device 32, respectively.

  In the above embodiment, when discharging, the sub CPU 52a sets all the npn transistors TR5 to TR8 constituting the discharge circuit 57 from OFF to ON and outputs a discharge signal H so as to discharge all the common lines CL1 to CL4. I was on the level. As another example, the sub CPU 52a may set the discharge signal to the H level so that only the common lines CL1 to CL4 in which the power supply voltage Vb is applied and the positive charges are accumulated in the previous horizontal scanning period are discharged.

  In the above embodiment, the ground terminal is a reference voltage terminal that gives a predetermined reference potential. However, the ground terminal may not be a ground terminal as long as the charges accumulated in the common lines CL1 to CL4 can be discharged. For example, a voltage terminal that applies a potential of 0.1 V as the predetermined reference potential may be used as the reference voltage terminal.

  The above embodiment is embodied in the drive circuit 55 of the light emitting display device provided in the pachinko machine 10 (so-called feather mono) classified as the second type, but the pachinko machine (so-called digital patch) classified as the first type. ) Or a driving circuit of a light emitting display device provided in a pachinko machine (so-called right property) classified as the third type. Further, the present invention may be embodied in a drive circuit of a light emitting display device provided in a pachislot machine (rotating game machine).

  In the above embodiment, the discharge signal and the common signals COM1 to COM4 may be simultaneously set to the H level, or the common signals COM1 to COM4 may be set to the H level and then the discharge signal may be set to the H level. Even in this case, when the discharge signal and the common signals COM1 to COM4 are at the H level, the switching characteristics of the pnp transistors TR1 to TR4 are improved by setting the discharge signal to the L level, and the power supply is instantaneously supplied. The voltage Vb is supplied to the common lines CL1 to CL4.

Next, the creation of a technical idea that can be grasped from the above embodiment and another example will be added below.
(A) While the third switching element connects the scanning line to the reference voltage terminal and discharges the scanning line, the first switching element inputs the first signal and switches it on. It is after supplying the supply voltage to the scan line, the third switching element as claimed in any one of claims 1 to 4, characterized in that switched off by an input of the third signal Driving circuit.

(B) In a light-emitting display device including a plurality of light-emitting elements arranged and connected in a matrix, the plurality of light-emitting elements emit light by the drive circuit according to any one of claims 1 to 4. And a light-emitting display device.

(C) A gaming machine in which a game effect is performed by light emission of the light emitting display device, comprising the light emitting display device described in the technical concept (b).
(D) A plurality of first switching elements that are turned on or off by the input of the first signal and connected to each of the first switching elements, and a power supply voltage is supplied when the first switching element is turned on. A plurality of scanning lines, a plurality of second switching elements that are turned on or off by the input of a second signal, and the second switching elements are connected to each other, and the second switching elements are turned on. A plurality of signal lines respectively connected to a reference voltage terminal and each of the scanning lines are connected in series, and turned on or off by the input of a third signal, and the scanning line is turned on when turned on. A third switching element connected to a reference voltage terminal for discharging the charge of the scan line, the scan line and the signal A plurality of light emitting devices connected between the scanning line to which a power supply voltage is supplied by the input of the first signal and the signal line connected to a reference voltage terminal by the input of the second signal. In the method of controlling the drive circuit that emits light due to the potential difference generated in the first step, when the second switching element is off, the first step of turning on the third switching element to discharge the charge of the scanning line; A second step of turning on the first switching element while the third switching element is on; and a third step of turning off the third switching element after the first switching element is turned on. And after the third switching element is turned off, while the first switching element is on, Control method of a driver circuit which is characterized in that a fourth step of emitting the light emitting element by switching the second switching element is turned on.

  (E) The drive circuit control method described in the technical idea (d) includes a fifth step of turning off the light emitting element by turning off the first switching element and the second switching element, A method of controlling a drive circuit, wherein the fifth step is repeatedly executed in order from step to step.

The front view of a pachinko machine. The front view of a winning device. The enlarged front view for demonstrating a display apparatus and a count lamp. Explanatory drawing which shows the arrangement | sequence of the light emitting diode in a display apparatus. The block diagram for demonstrating the connection of a main control board and a display lamp control board. The block diagram which shows the structure of a drive circuit. The circuit diagram which shows the circuit structure of a drive circuit. The timing chart explaining the timing which a common signal, a discharge signal, and a segment signal output. The circuit diagram which shows the circuit structure of another drive circuit. The circuit diagram which shows the circuit structure of the conventional drive circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Pachinko machine (game machine), 16a ... Frame lamp (light emitting display device), 16b ... Game board lamp (light emitting display device), 32 ... Display device (light emitting display device), 33 ... Count lamp (light emitting display device) 55 ... Drive circuit, 56 ... Common driver, 57 ... Discharge circuit, 58 ... Segment driver, TR1 to TR4 ... pnp transistor ((first) switching element), TR5 to TR8 ... npn transistor ((third) switching) Element), TR11 to TR15 ... npn transistor ((second) switching element), CL1 to CL4 ... common line (scanning line), SL1 to SL4 ... signal line (signal line), LED1 to LED20, LED31 to LED40 ... light emission. Diode (light emitting element).

Claims (4)

A plurality of first switching elements that are turned on or off in response to an input of the first signal, and a plurality of first switching elements that are connected to each of the first switching elements and that are supplied with a power supply voltage when the first switching element is turned on. Scanning lines, a plurality of second switching elements that are turned on or off by the input of a second signal, and a reference voltage terminal connected to each of the second switching elements when the second switching elements are turned on. A plurality of light emitting elements connected between the scanning line and the signal line, the scanning line to which a power supply voltage is supplied by the input of the first signal In the drive circuit that emits light by a potential difference generated between the signal line connected to a reference voltage terminal by the input of the second signal,
A plurality of third switching elements that are switched on or off in response to an input of the third signal;
The third switching element is connected in series to each of the scanning lines, the scanning lines are connected to the scanning line to said reference voltage terminal switched from off to on by inputting the third signal While the electric charge is discharged , the scanning line is connected to the reference voltage terminal to discharge the electric charge of the scanning line, and the first switching element is turned on by inputting the first signal. Sometimes, the driving circuit is switched off by inputting the third signal . The third switching element is turned on by the input of the third signal when the signal line is not connected to the reference voltage terminal, and connects the scanning line to the reference voltage terminal. The drive circuit according to claim 1. The third switching element is switched on by the input of the third signal when a power supply voltage is not supplied to the scanning line and the signal line is not connected to the reference voltage terminal. The drive circuit according to claim 1, wherein the scanning line is connected to the reference voltage terminal. The third switching element has a characteristic of flowing a current from the scanning line to the reference voltage terminal with a potential difference smaller than a potential difference necessary for a current to flow through the light emitting element. Item 4. The drive circuit according to any one of Items 3 to 3 .

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