JP4139893B2 - Inverter device and multiphase inverter device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an inverter device composed of a power switching element connected between main power supply terminals, and more particularly, a high voltage level shift-up circuit that transmits a control signal from a low voltage side circuit to a high voltage side circuit at high speed and a low voltage from the high voltage side circuit. The present invention relates to an inverter device including a high voltage level shift down circuit that transmits a state detection signal to a side circuit at high speed. The present invention is used for, for example, an inverter device for automobiles, home appliances or industrial use.
[Prior art]
Conventionally, in an inverter device including a first power switching element (upper arm switching element) and a second power switching element (lower arm switching element) connected in series between main power supply terminals, an upper arm switching element is A MOS transistor or the like has been used for a level shift circuit for transmitting a control signal to be controlled. In this level shift circuit, a high voltage MOS transistor is used because a surge voltage at the time of switching is applied in addition to the main power supply voltage, but the high voltage MOS transistor is not suitable for high-speed circuit operation. For this reason, there is a method in which several low-breakdown-voltage MOS transistors are cascaded in series to share the voltage applied to the circuit (see, for example, “Level Shift Circuit” in Patent Document 1).
[0002]
An example is shown in FIG. MOS transistors M2, M9 and M4 are connected in series between the positive voltage side power supply terminal 121 and the negative voltage side power supply terminal 123, and a voltage half the power supply voltage Vdd is applied from the terminal 112 to the gate terminal of the MOS transistor M9. Has been. Similarly, the MOS transistors M1, M8, and M3 are connected in series between the power supply voltage terminals, and a voltage half the power supply voltage Vdd is applied from the terminal 112 to the gate terminal of the MOS transistor M8. The MOS transistor M5 is an output MOS transistor of this level shift circuit. When the MOS transistor M2 is turned on, the MOS transistor M9 is also turned on, and the gate terminal of the MOS transistor M3 becomes the GND level. As a result, the MOS transistor M3 is turned on, the gate terminal of the MOS transistor M5 becomes the Vdd level, and the MOS transistor M5 is turned off. On the other hand, when the MOS transistor M2 is turned off, no current flows through the MOS transistors M2 and M9, and a voltage of Vdd / 2 is equally applied to the source terminal and the drain terminal of both elements. At the same time, since the MOS transistors M1 and M8 are on, the gate terminal of the MOS transistor M5 becomes the GND level, and the MOS transistor M5 is turned on. In the case of this circuit, the MOS transistor M9 clamps at half the power supply voltage Vdd, so that the withstand voltage of the MOS transistor M2 may be half of Vdd as compared to the case without the MOS transistor M9.
[0003]
[Patent Document 1]
JP 11-205123 A
[0004]
[Problems to be solved by the invention]
In the above prior art, when the power switching element (IBGT in this example) is switched, a pulse voltage that changes from 0 V to the main power supply voltage VBB is applied to the output terminal of the inverter. Therefore, when the upper arm power supply voltage is Vc, the power supply Vdd of this level shift circuit changes from Vc to VBB + Vc. When the MOS transistor M2 is off, when the potential of the main power supply Vdd falls, the voltage between the gate and the source of the MOS transistor M9 becomes a negative bias and the gate may be destroyed. This is because when the MOS transistor M2 is off, the impedance of the source of the MOS transistor M9 becomes high, and the fall time of the source of the MOS transistor M9 is delayed from the fall time of the gate of the MOS transistor M9.
[0005]
An object of the present invention is to eliminate the above-mentioned problems, and to provide an inverter device provided with a level shift circuit having high-speed switching operation and high breakdown voltage characteristics of a voltage clamping MOS transistor.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, high speed means is provided between the gate and the source of the voltage clamping MOS transistor. As a specific example of the speed-up means, a capacitor or a series circuit of a capacitor and a resistor can be considered. As another speed-up means, a diode or Zener diode in which the cathode is connected to the gate of the MOS transistor and the anode is connected to the source can be considered.
[0007]
According to the above means, since the impedance between the gate and the source of the MOS transistor is lowered, the source potential follows the voltage fluctuation of the gate of the voltage clamping MOS transistor. As a result, the switching speed is increased and the negative bias of the voltage between the gate and the source is eliminated and the gate breakdown is prevented, so that the reliability of the inverter device is improved. Further, this level shift circuit can be operated up to a power supply voltage twice the withstand voltage of the voltage clamping MOS transistor.
[0008]
Further, according to the above-described another speed-up means, even if the gate potential of the MOS transistor falls below the source potential, the diode is turned on at about 0.7 V (diode VF), and the gate and source of the MOS transistor have low impedance. become. As a result, the switching speed is increased, and the negative bias of the gate-source voltage is eliminated and the gate breakdown can be prevented, so that the reliability of the inverter device is improved. Further, the level shift circuit can be operated up to a power supply voltage that is twice the withstand voltage of the voltage clamping MOS transistor.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a configuration of an inverter device according to a first embodiment of the present invention. In FIG. 1, the inverter device includes an upper arm power switching element 101, a lower arm power switching element 102, an upper arm driving device 103, a lower arm driving device 104, an upper arm state detecting device 105, a lower arm state detecting device 106, A level shift-up device 125 comprising a first resistor 107, a first n-type MOS transistor 108, a first speed-up means 109, and a second n-type MOS transistor 110, a second resistor 111, and a midpoint potential terminal 112 In addition, a midpoint potential power source (Vdd / 2) 126 comprising the third resistor 113, the first p-type MOS transistor 114, the second p-type MOS transistor 116, the second speed-up means 115, and the fourth resistor 117 Level shift down device 127, upper arm power supply 118, lower Over arm power supply 119, controller 120, a positive potential terminal 121 of the main power supply, an inverter output terminal 122, GND terminal 123, Vdd terminal 124, which are connected as shown.
[0010]
The upper arm driving device 103 is means for driving the upper arm power switching element 101. The lower arm driving device 104 is means for driving the lower arm power switching element 102. The upper arm state detection device 105 is a means for monitoring the operating state of the upper arm power switching element 101. The lower arm state detection device 106 is means for monitoring the operation state of the lower arm power switching element 102 and the like. The first speed-up means 109 is connected between the gate and source of the first n-type MOS transistor 108, and is constituted by a device whose source potential varies so as to follow the potential variation of the gate. The second speed-up means 115 is connected between the gate and source of the second p-type MOS transistor 116, and is constituted by a device whose source potential varies so as to follow the potential variation of the gate. The GND terminal 123 is connected to the negative potential terminal of the main power supply. The Vdd terminal 124 is connected to the positive potential terminal of the upper arm power supply 118.
[0011]
In FIG. 1, the upper arm power switching element 101 and the lower arm power switching element 102 are n-type MOS transistors, but other elements such as insulated gate bipolar transistors may be used. The main power source positive potential terminal 121 is connected to the main power source positive potential VB, and the main power source negative potential terminal 123 is connected to the main power source negative potential GND. For convenience of explanation, the GND terminal 123 is grounded (0 V). The potential difference of the upper arm power supply 118 is VU, and the inverter output terminal 122 is used as a reference. The potential difference of the lower arm power supply 119 is VL, and the negative potential terminal 123 of the main power supply is used as a reference. The second resistor 111 and the third resistor 113 are connected in series between the Vdd terminal 124 and the GND terminal 123, and assuming that the resistance values are the same, the potential of the midpoint potential terminal 112 is Vdd / 2.
[0012]
The control device 120 controls the upper arm power switching element 101 and the lower arm power switching element 102 not to be simultaneously turned on. When the upper arm power switching element 101 is on and the lower arm power switching element 102 is off, the potential of the inverter output terminal 122 is VB, and the potential of the Vdd terminal 124 is VB + VU. Further, when the upper arm power switching element 101 is turned off and the lower arm power switching element 102 is turned on, the potential of the inverter output terminal 122 is 0 V, and the potential of the Vdd terminal 124 is VU. Therefore, the potential of the Vdd terminal 124 changes from VU to VB + VU.
[0013]
First, operations related to each device of the upper arm will be described. The level shift-up device 125 according to the present invention includes a first n-type MOS transistor 108, a second n-type MOS transistor 110, a first resistor 107, and a first speed-up means 109. In this inverter device, a control signal for controlling on / off of the switching element 101 for the upper arm power from the control device 120 is voltage-converted to the upper arm. The converted control signal enters the upper arm driving device 103, is voltage amplified to a pulse signal of the potential difference VU with the inverter output terminal 122 as a reference, and is applied to the gate terminal of the upper arm power switching element 101.
[0014]
The level shift down device 127 of the present invention includes a first p-type MOS transistor 114, a second p-type MOS transistor 116, a fourth resistor 117, and a second speed-up means 115. In this inverter apparatus, the detection signal from the upper arm state detection device 105 is converted into a voltage on the lower arm side and transmitted to the control device 120. The upper arm state detection device 105 detects the state of each device of the upper arm such as an overcurrent and overtemperature of the upper arm power switching element 101 or an overvoltage and undervoltage of the upper arm power supply. The detection output also enters the upper arm driving device 103, and stops the upper arm power switching element 101 when an abnormality such as overcurrent or overtemperature occurs.
[0015]
Next, operations related to each device of the lower arm will be described. A signal for controlling on / off of the lower arm power switching element 102 from the control device 120 enters the lower arm drive device 104, and is amplified to a pulse signal having a potential difference VL with the GND terminal 123 as a reference to switch the lower arm power. Applied to the gate terminal of the element 102. The lower arm state detection device 106 detects lower arm device states such as overcurrent and overtemperature of the lower arm power switching element 102, or overvoltage and undervoltage of the lower arm power supply, and transmits them to the control device 120. The detection output also enters the lower arm driving device 104, and stops the lower arm power switching element 102 when an abnormality such as overcurrent or overtemperature occurs.
[0016]
Next, a detailed circuit operation of the level shift up device 125 will be described. For convenience of explanation, the level shift up device 125 of FIG. 1 will be described with reference to FIG.
[0017]
FIG. 2 is a diagram for explaining the configuration of the level shift up device 125 according to the first embodiment of the present invention. In this embodiment, the first speed increasing means 109 in FIG. 1 is replaced with a series circuit of a capacitor 201 and a resistor 202. In FIG. 2, a terminal 204 is a signal input terminal, and a terminal 205 is a signal output terminal. Other components are the same as those of the level shift up device of FIG. For the explanation of the operation, the pulse voltage source 203 is connected between the Vdd terminal 124 and the GND terminal 123. The low level of this pulse voltage is VU, which is equal to or higher than the voltage at which the first n-type MOS transistor 108 and the second n-type MOS transistor 110 operate. The high level of this pulse voltage is VU + VB, which does not exceed the breakdown voltage of each MOS transistor. Further, in order to generate the potential Vdd / 2 of the midpoint potential terminal 112, a resistor 206 is connected between the Vdd terminal 124 and the midpoint potential terminal 112, and further between the midpoint potential terminal 124 and the GND terminal 123. A resistor 207 is connected.
[0018]
First, the operation when the pulse voltage source 203 is a constant voltage (VU at low level or VU + VB at high level) will be described. When the threshold voltage of the second n-type MOS transistor 110 is input to the signal input terminal 204, the second n-type MOS transistor 110 is turned on, and the source potential of the first n-type MOS transistor 108 is lowered to near the ground level. Then, the first n-type MOS transistor 108 is turned on, a current flows through the first resistor 107, and a potential difference is generated between the signal output terminal 205 and the Vdd terminal 124. On the other hand, when a voltage smaller than the threshold voltage of the second n-type MOS transistor 110 is input to the signal input terminal 204, the second n-type MOS transistor 110 is turned off. Assuming that the first n-type MOS transistor 108 and the second n-type MOS transistor 110 have the same electrical characteristics, the pulse power supply voltage Vdd is evenly distributed between the source and drain of each MOS transistor. The source potential of the type MOS transistor 108 is about Vdd / 2 (VU / 2 or VU / 2 + VB / 2). Therefore, the first n-type MOS transistor 108 is turned off, no current flows through the first resistor 107, and no potential difference is generated between the signal output terminal 205 and the Vdd terminal 124. As a result, the voltage pulse signal input to the signal input terminal 204 is level shifted, and the voltage pulse signal is output from the signal output terminal 205.
[0019]
Next, a transient operation when the voltage of the pulse voltage source 203 rises (low level to high level) and falls (high level to low level) will be described. When the second n-type MOS transistor 110 is on, the source potential of the first n-type MOS transistor 108 is approximately near the ground level. Therefore, the first n-type MOS transistor 108 is turned on, and a potential difference is generated between both ends of the first resistor 107. On the other hand, when the second n-type MOS transistor 110 is off, the source impedance of the first n-type MOS transistor 108 is only about the parasitic capacitance between the source and drain of the second n-type MOS transistor 110, Pretty expensive.
[0020]
Without the first speed-up means of the present invention (capacitor 201 and resistor 202 in the figure), the gate potential of the first n-type MOS transistor 108 rises almost simultaneously when this pulse voltage rises. The source potential of the n-type MOS transistor 108 rises with a delay due to high impedance. As a result, the source and gate potential difference of the first n-type MOS transistor 108 tends to widen.
[0021]
Also, when the pulse voltage falls, the gate potential of the first n-type MOS transistor 108 falls almost simultaneously, but the source potential of the first n-type MOS transistor 108 falls late. As a result, a region in which the gate potential of the first n-type MOS transistor 108 is lower than the source potential is generated (gate negative bias), and the first n-type MOS transistor 108 is broken down.
[0022]
On the other hand, when there is the first speed-up means (capacitor 201 and resistor 202), the impedance between the gate and the source of the first n-type MOS transistor 108 becomes low. Therefore, the gate potential and the source potential of the first n-type MOS transistor 108 rise almost simultaneously when this pulse voltage rises. When the pulse voltage falls, the gate potential and the source potential of the first n-type MOS transistor 108 fall almost simultaneously. As a result, the source potential of the first n-type MOS transistor 108 becomes Vdd / 2 which is substantially the same as the gate potential, and the above gate breakdown does not occur.
[0023]
This speed-up means is more effective as the capacitance value of the capacitor 201 is larger, and more effective as the resistance value of the resistor 202 is smaller. Further, when the resistance value is zero ohms, that is, when only the capacitor 201 is used, the same operation is performed and the same effect can be obtained.
[0024]
With the above speed-up means, the level shift up device 125 of the present invention speeds up the switching of the first n-type MOS transistor 108 and prevents gate breakdown, thereby improving the reliability of the inverter device. Further, it can be operated with a power supply voltage twice the breakdown voltage of the first n-type MOS transistor 108.
[0025]
Next, a detailed circuit operation of the level shift down device will be described. For convenience of explanation, the level shift down device 127 of FIG. 1 will be described with reference to FIG.
[0026]
FIG. 3 is a block diagram for explaining the configuration of the level shift down device 127 according to the first embodiment of the present invention. In this embodiment, the second speed-up means 115 in FIG. 1 is replaced with a series circuit of a capacitor 301 and a resistor 302. In FIG. 3, a terminal 304 is a signal input terminal, and a terminal 305 is a signal output terminal. Other components are the same as those of the level shift down device 127 of FIG. For the explanation of the operation, the pulse voltage source 203 is connected between the Vdd terminal 124 and the GND terminal 123. Note that the low level of this pulse voltage is VU, which is equal to or higher than the voltage at which the first p-type MOS transistor 114 and the second p-type MOS transistor 116 operate. The high level of this pulse voltage is VU + VB, which is a voltage that does not exceed the breakdown voltage of each MOS transistor. Further, in order to generate the potential Vdd / 2 of the midpoint potential terminal 112, a resistor 306 is connected between the Vdd terminal 124 and the midpoint potential terminal 112, and further between the midpoint potential terminal 124 and the GND terminal 123. A resistor 307 is connected.
[0027]
First, the operation when the pulse voltage source 203 is a constant voltage (VU at low level or VU + VB at high level) will be described. When the threshold voltage of the first p-type MOS transistor 114 is input to the signal input terminal 304, the first p-type MOS transistor 114 is turned on and the source potential of the second p-type MOS transistor 116 rises to near Vdd. Then, the second p-type MOS transistor 116 is turned on, a current flows through the fourth resistor 117, and a potential difference is generated between the signal output terminal 305 and the GND terminal 123.
[0028]
On the other hand, when a voltage smaller than the threshold voltage of the first p-type MOS transistor 114 is input to the signal input terminal 304, the first p-type MOS transistor 114 is turned off. Assuming that the first p-type MOS transistor 114 and the second p-type MOS transistor 116 have the same electrical characteristics, the pulse power supply voltage Vdd is evenly distributed between the source and drain of each MOS transistor. The source potential of the type MOS transistor 116 is about Vdd / 2 (VU / 2 or VU / 2 + VB / 2).
[0029]
Therefore, the second p-type MOS transistor 116 is turned off, no current flows through the fourth resistor 117, and no potential difference is generated between the signal output terminal 305 and the GND terminal 123. As a result, the voltage pulse signal input to the signal input terminal 304 is level shifted, and the voltage pulse signal is output from the signal output terminal 305.
[0030]
Next, a transient operation when the voltage of the pulse voltage source 203 rises (low level to high level) and falls (high level to low level) will be described. When the first p-type MOS transistor 114 is on, the source potential of the second p-type MOS transistor 116 is approximately near Vdd. Therefore, the second p-type MOS transistor 116 is turned on, and a potential difference is generated between both ends of the fourth resistor 117. On the other hand, when the first p-type MOS transistor 114 is off, the source impedance of the second p-type MOS transistor 116 is only about the parasitic capacitance between the source and drain of the first p-type MOS transistor 114. Is quite expensive. Without the second speed-up means of the present invention (capacitor 301 and resistor 302 in this figure), the gate potential of the second p-type MOS transistor 116 rises almost simultaneously when this pulse voltage rises. The source potential of the p-type MOS transistor 116 rises with a delay due to high impedance. As a result, a region where the gate potential of the second p-type MOS transistor 116 is higher than the source potential is generated (gate positive bias), and the second p-type MOS transistor 116 is gate-destructed.
[0031]
When the pulse voltage falls, the gate potential of the second p-type MOS transistor 116 falls almost simultaneously, but the source potential of the second p-type MOS transistor 116 falls late. As a result, the source and gate potential difference of the second p-type MOS transistor 116 tends to widen. On the other hand, when the second speed-up means (capacitor 301 and resistor 302) is provided, the impedance between the gate and the source of the second p-type MOS transistor 116 is lowered. Therefore, when the pulse voltage rises, the gate potential and the source potential of the second p-type MOS transistor 116 rise almost simultaneously. Further, when this pulse voltage falls, the gate potential and the source potential of the second p-type MOS transistor 116 fall almost simultaneously.
[0032]
As a result, the source potential of the second p-type MOS transistor 116 becomes Vdd / 2 which is substantially the same as the gate potential, and the above gate breakdown does not occur. This speed-up means is more effective as the capacitance value of the capacitor 301 is larger, and more effective as the resistance value of the resistor 302 is smaller. Further, when the resistance value is zero ohms, that is, when only the capacitor 301 is used, the same operation is performed and the same effect can be obtained.
[0033]
With the above speed-up means, the level shift down device 127 of the present invention speeds up the switching of the second p-type MOS transistor 116 and prevents gate breakdown, thereby improving the reliability of the inverter device. Further, it can be operated with a power supply voltage that is twice the breakdown voltage of the second p-type MOS transistor 116.
[0034]
As described above, when the inverter device shown in FIG. 1 is applied, the level shift-up circuit and the level shift-down circuit can be speeded up, and gate breakdown of the voltage clamping MOS transistor in the circuit does not occur. The withstand voltage of the voltage clamping MOS transistor may be (VB + VU) / 2.
[0035]
FIG. 4 is a block diagram of the level shift up device 125 according to the second embodiment of the present invention. In this embodiment, the first speed-up means 109 in FIG. In this figure, a terminal 402 is a signal input terminal, and a terminal 403 is a signal output terminal. Other components are the same as those of the level shift up device of FIG. For the explanation of the operation, the pulse voltage source 203 is connected between the Vdd terminal 124 and the GND terminal 123. The low level of this pulse voltage is VU, which is equal to or higher than the voltage at which the first n-type MOS transistor 108 and the second n-type MOS transistor 110 operate. The high level of this pulse voltage is VU + VB, which is a voltage that does not exceed the breakdown voltage of each MOS transistor. Further, in order to generate the potential Vdd / 2 of the midpoint potential terminal 112, a resistor 404 is connected between the Vdd terminal 124 and the midpoint potential terminal 112, and further between the midpoint potential terminal 124 and the GND terminal 123. A resistor 405 is connected.
[0036]
First, the operation when the pulse voltage source 203 is a constant voltage (VU at the low level or VU + VB at the high level) is the same as FIG.
[0037]
Next, a transient operation when the voltage of the pulse voltage source 203 rises (low level to high level) and falls (high level to low level) will be described. When the second n-type MOS transistor 110 is on, the source potential of the first n-type MOS transistor 108 is approximately near the ground level. Therefore, the first n-type MOS transistor 108 is turned on, and a potential difference is generated between both ends of the first resistor 107. On the other hand, when the second n-type MOS transistor 110 is off, the source impedance of the first n-type MOS transistor 108 is only about the parasitic capacitance between the source and drain of the second n-type MOS transistor 110, Pretty expensive. Without the first speed-up means of the present invention (Zener diode 401 in the figure), the gate potential of the first n-type MOS transistor 108 rises almost simultaneously when this pulse voltage rises, but the first n-type The source potential of the MOS transistor 108 rises with a delay due to high impedance. As a result, the source and gate potential difference of the first n-type MOS transistor 108 tends to widen.
[0038]
Also, when the pulse voltage falls, the gate potential of the first n-type MOS transistor 108 falls almost simultaneously, but the source potential of the first n-type MOS transistor 108 falls late. As a result, a region in which the gate potential of the first n-type MOS transistor 108 is lower than the source potential is generated (gate negative bias), and the first n-type MOS transistor 108 is broken down. On the other hand, when there is the first speed-up means (Zener diode 401), the gate potential of the first n-type MOS transistor 108 rises almost simultaneously when the pulse voltage rises, and the first n-type MOS transistor 108 rises. The source potential rises with a momentary delay. As a result, the source and gate potential difference of the first n-type MOS transistor 108 tends to widen, but is clamped by the Zener voltage VZ.
[0039]
When this pulse voltage falls, the gate potential of the first n-type MOS transistor 108 falls almost simultaneously, and the source potential of the first n-type MOS transistor 108 falls with a momentary delay. However, when the gate potential of the first n-type MOS transistor 108 falls by about 0.7 V (about VF of the Zener diode) from the source potential, the Zener diode 401 is turned on and the gate of the first n-type MOS transistor 108 is turned on. The impedance between the potential and the source potential decreases. As a result, the source potential of the first n-type MOS transistor 108 becomes Vdd / 2 that is substantially the same as the gate potential (there is a slight difference of about 0.7 V), and the aforementioned gate breakdown does not occur. In the case of this means, the same effect of preventing gate breakdown can be obtained with a diode.
[0040]
With the above speed-up means, the level shift-up device of the present invention speeds up switching of the first n-type MOS transistor 108 and prevents gate breakdown, thereby improving the reliability of the inverter device. Further, it can be operated with a power supply voltage twice the breakdown voltage of the first n-type MOS transistor 108. Further, when the present embodiment is integrated into an integrated circuit (IC), the speed-up means is a Zener diode, so that the IC area can be reduced as compared with the case of the capacity as shown in FIG.
[0041]
FIG. 5 is a block diagram of a level shift down apparatus according to a second embodiment of the present invention. In this embodiment, the second speed-up means 115 in FIG. 1 is replaced with a Zener diode 501. In FIG. 5, a terminal 502 is a signal input terminal, and a terminal 503 is a signal output terminal. Other components are the same as those of the level shift up device 127 of FIG. For the explanation of the operation, the pulse voltage source 203 is connected between the Vdd terminal 124 and the GND terminal 123. Note that the low level of this pulse voltage is VU, which is equal to or higher than the voltage at which the first p-type MOS transistor 114 and the second p-type MOS transistor 116 operate. The high level of this pulse voltage is set to VU + VB, and the voltage does not exceed twice the breakdown voltage of each MOS transistor. Further, in order to generate the potential Vdd / 2 of the midpoint potential terminal 112, a resistor 504 is connected between the Vdd terminal 124 and the midpoint potential terminal 112, and further, between the midpoint potential terminal 124 and the GND terminal 123. A resistor 505 is connected.
[0042]
First, the operation when the pulse voltage source 203 is at a constant voltage (VU at low level or VU + VB at high level) is the same as FIG.
[0043]
Next, a transient operation when the voltage of the pulse voltage source 203 rises (low level to high level) and falls (high level to low level) will be described. When the first p-type MOS transistor 114 is on, the source potential of the second p-type MOS transistor 116 is approximately near Vdd. Therefore, the second p-type MOS transistor 116 is turned on, and a potential difference is generated between both ends of the fourth resistor 117. On the other hand, when the first p-type MOS transistor 114 is off, the source impedance of the second p-type MOS transistor 116 is only about the parasitic capacitance between the source and drain of the first p-type MOS transistor 114, Pretty expensive.
[0044]
Without the second speed-up means (Zener diode 501 in the figure) of the present invention, the gate potential of the second p-type MOS transistor 116 rises almost simultaneously when the pulse voltage rises, but the first n-type The source potential of the MOS transistor 108 rises with a delay due to high impedance. As a result, a region where the gate potential of the second p-type MOS transistor 116 is higher than the source potential is generated (gate positive bias), and the second p-type MOS transistor 116 is gate-destructed. When the pulse voltage falls, the gate potential of the second p-type MOS transistor 116 falls almost simultaneously, but the source potential of the second p-type MOS transistor 116 falls late. As a result, the source and gate potential difference of the first n-type MOS transistor 108 tends to widen.
[0045]
On the other hand, when there is the second speed-up means (Zener diode 501), the gate potential of the second p-type MOS transistor 116 rises almost simultaneously when this pulse voltage rises, and the second p-type MOS transistor 116 is raised. The source potential rises with a momentary delay. However, when the gate potential of the second p-type MOS transistor 116 increases by about 0.7 V (about VF of the Zener diode) from the source potential, the Zener diode 501 is turned on and the gate of the second p-type MOS transistor 116 is turned on. The impedance between the potential and the source potential decreases. As a result, the source potential of the second p-type MOS transistor 116 is approximately the same as the gate potential Vdd / 2 (there is a slight difference of about 0.7 V), and the aforementioned gate breakdown does not occur. When the pulse voltage falls, the gate potential of the second p-type MOS transistor 116 falls almost simultaneously, and the source potential of the second p-type MOS transistor 116 falls with a momentary delay. As a result, the source and gate potential difference of the second p-type MOS transistor 116 tends to widen, but is clamped by the Zener voltage VZ. In the case of this speed-up means, the same gate breakdown prevention effect can be obtained even with a diode.
[0046]
With the above speed-up means, the level shift-up device of the present invention speeds up the switching of the second p-type MOS transistor 116 and prevents gate breakdown, thereby improving the reliability of the inverter device. Further, it can be operated with a power supply voltage that is twice the breakdown voltage of the second p-type MOS transistor 116. Further, when the present embodiment is integrated into an integrated circuit (IC), the speed-up means is a Zener diode, so that the IC area can be reduced as compared with the case of the capacity as shown in FIG.
[0047]
FIG. 6 is a block diagram of an inverter device using means according to the second embodiment of the present invention. The basic configuration of the inverter device of FIG. 6 is almost the same as that of FIG. 1, but the difference from FIG. 1 is the configuration of the midpoint potential power supply 126 that generates the midpoint potential. In FIG. 6, a series circuit of a first capacitor 601 and a fifth resistor 602 is connected to both terminals of the second resistor 111, and a second capacitor 603 and a sixth resistor are connected to both terminals of the third resistor 113. 604 series circuits were connected. The purpose of this embodiment is to speed up the potential change response of the midpoint potential terminal 112 when the resistance values of the second resistor 111 and the third resistor 113 are increased in order to reduce power consumption. . When this inverter device is applied to a product field where the power supply voltage VB is high, the resistance values of the second resistor 111 and the third resistor 113 must be increased to reduce power consumption. However, when the Vdd terminal 124 is switched, since the impedance of the second resistor 111 and the third resistor 113 is high, the potential change of the midpoint potential terminal 112 is delayed. As a result, the change in the gate potential of the first n-type MOS transistor of the level shift-up device 125 and the change in the gate potential of the second p-type MOS transistor of the level shift-down device 127 are delayed, and FIGS. The gate breakdown as described in FIG. 5 occurs.
[0048]
For this reason, a first capacitor 601, a fifth resistor 602, a second capacitor 603, and a sixth resistor 604 are added as speed-up means. Note that the capacitance value of these capacitors and the resistance value of the resistors are determined to be lower than the impedances of the second resistor 111 and the third resistor 113.
[0049]
In FIG. 6, the upper arm power switching element 101 and the lower arm power switching element 102 are n-type MOS transistors, but other elements such as insulated gate bipolar transistors may be used. The positive potential terminal 121 of the main power supply is connected to the positive potential VB of the main power supply, and the negative potential terminal 123 of the main power supply is connected to the negative potential GND of the main power supply. For convenience of explanation, the GND terminal 123 is grounded (0 V). The potential difference of the upper arm power supply 118 is VU, and the inverter output terminal 122 is used as a reference. The potential difference of the lower arm power supply 119 is VL, and the negative potential terminal 123 of the main power supply is used as a reference. The control device 120 controls the upper arm power switching element 101 and the lower arm power switching element 102 not to be simultaneously turned on.
[0050]
When the upper arm power switching element 101 is on and the lower arm power switching element 102 is off, the potential of the inverter output terminal 122 is VB, and the potential of the Vdd terminal 124 is VB + VU. Further, when the upper arm power switching element 101 is turned off and the lower arm power switching element 102 is turned on, the potential of the inverter output terminal 122 is 0 V, and the potential of the Vdd terminal 124 is VU. Therefore, the potential of the Vdd terminal 124 changes from VU to VB + VU.
[0051]
6, the operations of the level shift up device 125, the level shift down device 127, the upper arm drive device 103, the lower arm drive device 104, the upper arm state detection device 105, and the lower arm state detection device 106 are the same as those in FIG. However, since the operation of the midpoint potential power supply 126 is different, the operation of this power supply will be described.
[0052]
First, when the Vdd terminal 124 is at a constant voltage (VU at low level or VU + VB at high level), if the resistance values of the second resistor 111 and the third resistor 113 are the same, the potential of the midpoint potential terminal 112 is Vdd. / 2. (When the potential at the Vdd terminal is VU, the potential at the midpoint potential terminal is VU / 2, and when the potential at the Vdd terminal is VB + VU, the potential at the midpoint potential terminal is VB / 2 + VU / 2). The operation of is the same as FIG.
[0053]
Next, a transient operation when the potential of the Vdd terminal 124 is rising (low level to high level) and falling (high level to low level) will be described. The impedance of the series circuit of the first capacitor 601 and the fifth resistor 602 is lower than the impedance of the second resistor 111, and the impedance of the second capacitor 603 and the sixth resistor 604 is less than the impedance of the third resistor 113. Therefore, the potential of the midpoint potential terminal 112 rises simultaneously with the rise of the potential of the Vdd terminal 124, and the potential of the midpoint potential terminal 112 falls simultaneously with the fall of the potential of the Vdd terminal 124. Therefore, the response of the potential change at the midpoint potential terminal 112 becomes faster than when there is no main capacitor and resistor.
[0054]
As described above, when the inverter device shown in FIG. 6 is applied, even when the resistance values of the second resistor 111 and the third resistor 113 are increased to reduce power consumption, the speed and level of the midpoint potential power source are increased. The shift-up circuit and the level shift-down circuit can be speeded up, and the gate of the voltage clamping MOS transistor in the circuit does not break down. The withstand voltage of the voltage clamping MOS transistor may be (VB + VU) / 2.
[0055]
FIG. 7 is a block diagram of an inverter device according to a third embodiment of the present invention. FIG. 7 is an example of a three-phase inverter device using the single-phase inverter device of FIG.
[0056]
The three-phase inverter device includes a first upper arm power switching element 704, a first upper arm reflux diode 705, a second upper arm power switching element 706, a second upper arm reflux diode 707, a third Upper arm power switching element 708, third upper arm return diode 709, first lower arm power switching element 710, first lower arm return diode 711, and second lower arm power switching element 712. , A second lower arm return diode 713, a third lower arm power switching element 714, a third lower arm return diode 715, a first upper arm drive device 716, a second upper arm drive device 717, A third upper arm drive 718, a first lower arm drive 719, a second lower arm drive 720, Lower arm driving device 721, first upper arm state detecting device 722, second upper arm state detecting device 723, third upper arm state detecting device 724, first lower arm state detecting device 725, second Lower arm state detector 726, third lower arm state detector 727, first upper arm power source 728, second upper arm power source 729, third upper arm power source 730, lower arm power source 731, first level Shift-up device 732, second level shift-up device 733, third level shift-up device 734, first resistor 735, second resistor 736, third resistor 737, fourth resistor 738, fifth Resistor 739, sixth resistor 740, first level shift down device 741, second level shift down device 742, third level shift down device 743, control device 12 Configured to include a.
[0057]
Terminal 701 is a first inverter output terminal, terminal 702 is a second inverter output terminal, terminal 703 is a third inverter output terminal, terminal 121 is a positive potential terminal of the main power supply, and terminal 123 is a negative potential terminal of the main power supply. The connected GND terminal, terminal 744 is a first Vdd terminal, terminal 745 is a second Vdd terminal, and terminal 746 is a third Vdd terminal.
[0058]
In FIG. 7, a first upper arm power switching element 704, a second upper arm power switching element 706, a third upper arm power switching element 708, a first lower arm power switching element 710, a second Although the lower arm power switching element 712 and the third lower arm power switching element 714 are n-type MOS transistors, other elements such as insulated gate bipolar transistors may be used. The main power source positive potential terminal 121 is connected to the main power source positive potential VB, and the main power source negative potential terminal 123 is connected to the main power source negative potential GND. For convenience of explanation, the GND terminal 123 is grounded (0 V).
[0059]
The first resistor 735 and the second resistor 736 are connected in series between the first Vdd terminal 744 and the GND terminal 123, and are connected to the first level shift up device 732 and the first level shift down device 741. A necessary potential Vdd1 / 2 is generated. Note that the potential of the first Vdd terminal 744 is Vdd1.
[0060]
The third resistor 737 and the fourth resistor 738 are connected in series between the second Vdd terminal 745 and the GND terminal 123, and are connected to the second level shift up device 733 and the second level shift down device 742. A necessary potential Vdd2 / 2 is generated. Note that the potential of the second Vdd terminal 745 is Vdd2.
[0061]
The fifth resistor 739 and the sixth resistor 740 are connected in series between the third Vdd terminal 746 and the GND terminal 123, and are connected to the third level shift up device 734 and the third level shift down device 743. A necessary potential Vdd3 / 2 is generated. Note that the potential of the third Vdd terminal 746 is Vdd3.
[0062]
The present embodiment has a configuration in which three single-phase inverters of FIG. 1 are connected in parallel, and the operation of each single-phase inverter device is the same as that of FIG. The control device 120 sends a control signal to each single-phase inverter to control on / off of the upper arm power switching element and the lower arm power switching element of each phase. Further, the control device 120 receives detection values of the upper arm state detection device and the lower arm state detection device from each single phase inverter device, and sets a control pattern of each single phase inverter device.
[0063]
FIG. 8 shows a fourth embodiment of the inverter device using the present invention. FIG. 8 shows an example in which the driving device, the state detection device, the level shift up device, the level shift down device, and the midpoint potential power supply of each phase are integrated into an integrated circuit (monolithic IC) in the three-phase inverter device of FIG. .
[0064]
In this embodiment, a first upper arm drive circuit 802, a first upper arm state detection circuit 803, a second upper arm drive circuit 804, a second upper arm state detection circuit 805, and a third upper arm drive circuit 806, a third upper arm state detection circuit 807, a first lower arm drive circuit 808, a first lower arm state detection circuit 809, a second lower arm drive circuit 810, a second lower arm state detection circuit 811, Third lower arm drive circuit 812, third lower arm state detection circuit 813, first level shift up circuit 814, first level shift down circuit 815, second level shift up circuit 816, second level Shift down circuit 817, third level shift up circuit 818, third level shift down circuit 819, first midpoint potential power supply 820, second midpoint potential power supply 821 It is equipped with third midpoint potential power source 822 to the monolithic IC801.
[0065]
The monolithic IC 801 is connected to a first upper arm power source 823, a second upper arm power source 824, a third upper arm power source 825, and a lower arm power source 826.
[0066]
The operation of FIG. 8 is the same as that of FIG. In the case of the present embodiment, the number of parts can be greatly reduced and the cost can be reduced by using an IC.
[0067]
An example in which the inverter device according to the present invention is applied to a motor will be described with reference to the block diagram of FIG.
[0068]
The inverter device 901 of this embodiment corresponds to the inverter device of FIG. 7 or FIG. A three-phase motor 902 is connected to a first inverter output terminal 701, a second inverter output terminal 702, and a third inverter output terminal 703 of the inverter device 901 controlled by the control device 120. The first current detection device 903, the second current detection device 904, and the third current detection device 905 detection signals are input to the control device 120. Further, the main power source 906 is connected to the positive potential terminal 121 of the main power source of the inverter device 901 and the GND terminal 123 connected to the negative potential terminal of the main power source.
[0069]
The output current flowing through the first inverter output terminal 701 of the inverter device 901 is detected by the first current detection device 903 and sent to the control device 120. The control device 120 sends a control signal corresponding to the detected value to the inverter device 901 of the present invention. The operation of other current detection devices is the same. Further, the control device 120 receives the detection values of the upper arm state detection device and the lower arm state detection device from the inverter device 901 of the present invention, and sets the control pattern of each single-phase inverter device.
[0070]
In the case of this application example, the reliability of the entire motor system is improved, and the number of parts can be greatly reduced and the cost can be reduced by using an IC as shown in FIG.
[0071]
【The invention's effect】
According to the present invention, it is possible to increase the speed of the level shift up circuit and the level shift down circuit of the inverter device, and it is possible to prevent gate breakdown of the voltage clamping MOS transistor in the circuit, thereby improving the reliability of the inverter device. Further, since the level shift up circuit and the level shift down circuit can be operated up to a power supply voltage that is twice the withstand voltage of the voltage clamping MOS transistor, the withstand voltage of the inverter device can be increased.
[Brief description of the drawings]
FIG. 1 shows a first embodiment of an inverter device using the present invention.
FIG. 2 shows a first embodiment of the level shift up device of the present invention.
FIG. 3 shows a first embodiment of a level shift down apparatus according to the present invention.
FIG. 4 shows a second embodiment of the level shift up device of the present invention.
FIG. 5 shows a second embodiment of the level shift down apparatus of the present invention.
FIG. 6 shows a second embodiment of an inverter device using the present invention.
FIG. 7 shows a third embodiment of an inverter device using the present invention.
FIG. 8 shows a fourth embodiment of an inverter device using the present invention.
FIG. 9 shows an application example of the inverter device of the present invention to a motor.
FIG. 10 shows an example of a level shift circuit used in a conventional inverter device.
[Explanation of symbols]
101 Upper arm power switching element
102 Switching element for lower arm power
103 Upper arm drive device
104 Lower arm drive device
105 Upper arm state detection device
106 Lower arm state detection device
107 first resistor
108 First n-type MOS transistor
109 First speed-up means (device whose source potential fluctuates so as to follow the potential fluctuation of the gate)
110 Second n-type MOS transistor
111 Second resistor
112 Midpoint potential terminal
113 Third resistor
114 First p-type MOS transistor
116 Second p-type MOS transistor
115 Second speed-up means (device whose source potential fluctuates so as to follow gate potential fluctuation dV / dt)
117 fourth resistance
118 Upper arm power supply
119 Lower arm power supply
120 controller
121 Main power supply positive potential terminal
122 Inverter output terminal
123 GND terminal
124 Vdd end
125 level shift up device
126 Midpoint potential power supply (Vdd / 2)
127 Level shift down device
201 capacity
202 resistance
203 Pulse voltage source
204 Signal input terminal
205 Signal output terminal
206 Resistance
207 resistance
301 capacity
302 resistance
304 signal input terminal
305 Signal output terminal
306 resistance
307 resistance
401 Zener diode
402 Signal input terminal
403 Signal output terminal
404 resistance
405 resistance
501 Zener diode
502 Signal input terminal
503 Signal output terminal
504 resistance
505 resistance
601 first capacity
602 fifth resistor
603 second capacity
604 Sixth resistor
701 First inverter output terminal
702 Second inverter output terminal
703 Third inverter output terminal
704 First upper arm power switching element
705 First upper arm return diode
706 Second upper arm power switching element
707 Second upper arm return diode
708 Third upper arm power switching element
709 Third upper arm return diode
710 First lower arm power switching element
711 First lower arm return diode
712 Second lower arm power switching element
713 Second lower arm return diode
714 Third lower arm power switching element
715 Third lower arm return diode
716 First upper arm driving device
717 Second upper arm driving device
718 Third upper arm drive
719 First lower arm drive device
720 Second lower arm driving device
721 Third lower arm driving device
722 First upper arm state detection device
723 Second upper arm state detection device
724 Third upper arm state detection device
725 First lower arm state detection device
726 Second lower arm state detection device
727 Third lower arm state detection device
728 First upper arm power supply
729 Second upper arm power supply
730 Third upper arm power supply
731 Lower arm power supply
732 First level shift-up device
733 Second level shift up device
734 Third level shift up device
735 First resistor
736 Second resistance
737 Third resistor
738 Fourth resistor
739 5th resistor
740 Sixth resistor
741 First level shift down device
742 Second level shift down device
743 Third level shift down device
744 First Vdd terminal
745 Second Vdd terminal
746 Third Vdd terminal
801 Monolithic IC
802 First upper arm drive circuit
803 First upper arm state detection circuit
804 Second upper arm drive circuit
805 Second upper arm state detection circuit
806 Third upper arm drive circuit
807 Third upper arm state detection circuit
808 First lower arm drive circuit
809 First lower arm state detection circuit
810 Second lower arm drive circuit
811 Second lower arm state detection circuit
812 Third lower arm drive circuit
813 Third lower arm state detection circuit
814 First level upshift
815 First level shift down circuit
816 Second level shift up circuit
817 Second level shift down circuit
818 Third level shift-up circuit
819 Third level shift down circuit
820 First midpoint potential power supply
821 Second midpoint potential power supply
822 Third midpoint potential power supply
823 First upper arm power supply
824 Second upper arm power supply
825 Third upper arm power supply
826 Lower arm power supply
901 FIG. 7 or FIG. 8 corresponds to the inverter device of the present invention.
902 Three-phase motor
903 First current detection device
904 Second current detection device
905 Third current detection device
906 Main power supply

Claims (10)

High-arm terminal for main power supply, low-potential terminal for main power supply, output terminal connected to external load, switching for upper arm power with drain connected to high-potential terminal for main power supply and source connected to output terminal A lower arm power switching element having a drain connected to the output terminal and a source connected to the low potential terminal for main power, an upper arm driving means connected to a control terminal of the upper arm power switching element, Lower arm driving means connected to the control terminal of the arm power switching element, upper arm state detecting means for detecting the upper arm operating state, lower arm state detecting means for detecting the lower arm operating state, and control of the entire apparatus Control means for operating the upper arm power source with the lower arm side operated and the lower potential side connected to the output terminal, and the lower arm side operated with the lower potential side connected to the output terminal A lower arm power supply connected to the low potential terminal; a level shift up means connected between the high potential side of the upper arm power supply and the low potential side of the lower arm power supply to transmit the control signal of the control means to the upper arm drive means; Level shift down means connected between the high potential side of the upper arm power supply and the low potential side of the lower arm power supply for transmitting the detection signal of the upper arm state detection means to the control means; the high potential of the upper arm power supply and the lower arm It consists of a midpoint potential power supply that generates a low potential intermediate potential of the power supply and a midpoint potential terminal that is the output terminal of the midpoint potential power supply
In the level shift-up means, one terminal has a first resistor connected to the high potential side of the upper arm power supply, a drain connected to the other terminal of the first resistor, and a gate connected to the midpoint potential terminal. A first nMOS transistor, a second nMOS transistor having a drain connected to the source of the first nMOS transistor, a source connected to the main power supply low potential terminal, and a gate receiving a control signal of the control means; The level shift down means comprises a first speed-up means having a terminal connected to the gate of the first nMOS transistor and the other terminal connected to the source of the first nMOS transistor. A first pMOS transistor connected to the potential side and having a detection signal of the upper arm state detection means input to the gate, and a source connected to the first pMOS transistor A second pMOS transistor connected to the drain of the transistor and having a gate connected to the midpoint potential terminal, one terminal connected to the drain of the second pMOS transistor, and the other terminal connected to the low potential terminal for main power supply An inverter comprising: a second resistor; and a second speed-up means having one terminal connected to the gate of the second pMOS transistor and the other terminal connected to the source of the second pMOS transistor. apparatus. 2. The inverter device according to claim 1, wherein the first speed-up means and the second speed-up means are a series circuit composed of a capacitor and a resistor. 2. The inverter apparatus according to claim 1, wherein the first speed-up means and the second speed-up means are capacitors. 2. The inverter device according to claim 1, wherein the first speed-up means and the second speed-up means are Zener diodes. 2. The inverter device according to claim 1, wherein the first speed-up means and the second speed-up means are diodes. 3. The inverter device according to claim 1, wherein the middle point potential power source has a third resistor in which one terminal is connected to the high potential side of the upper arm power source and the other terminal is connected to the middle point potential terminal, and one terminal. Is connected to the midpoint potential terminal and the other terminal is connected to the low potential side of the lower arm power supply, and the first capacitor is connected to the high potential side of the upper arm power supply. A fifth resistor having one terminal connected to the other terminal of the first capacitor and the other terminal connected to the midpoint potential terminal; and a second capacitor having one terminal connected to the midpoint potential terminal; An inverter device comprising: a sixth resistor having one terminal connected to the other terminal of the second capacitor and the other terminal connected to the low potential side of the lower arm power supply. In multi-phase inverter device which is connected in parallel with the main power supply higher potential terminal and the main power supply low potential terminal of the plurality of inverter device, wherein the plurality of inverter devices is an inverter apparatus according to claim 1 respectively Multi-phase inverter device. In multi-phase inverter device which is connected in parallel with the main power supply higher potential terminal and the main power supply low potential terminal of the plurality of inverter device, wherein the plurality of inverter devices is an inverter apparatus according to claim 6, respectively Multi-phase inverter device. 2. The inverter device according to claim 1, wherein the upper arm driving means, the lower arm driving means, the upper arm state detecting means, the lower arm state detecting means, the level shift up means, the level shift down means, and the midpoint potential power source are combined into one. An inverter device characterized by being integrated in a semiconductor substrate. 8. The multiphase inverter device according to claim 7, wherein the upper arm driving means, the lower arm driving means, the upper arm state detecting means, the lower arm state detecting means, the level shift up means, the level shift down means, and the midpoint of each phase. A multiphase inverter device in which a potential power source is integrated in a single semiconductor substrate.

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