JP4142210B2 - Semiconductor memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a write-only precharge circuit that is effective in reducing recovery time after writing to an SRAM and reducing cycle time.
[0002]
[Prior art]
In SRAM (Static Random Access Memory), a recovery time (a time during which the potential of the bit line is set to a high potential and the potential difference is set to 0 after the write operation) is one of the factors governing the cycle time. FIG. 2 shows an example of a conventional SRAM write circuit and bit line precharge circuit. In the figure, W1 and W2 indicate word lines, BL1 and BR1, BL2 and BR2 indicate bit line pairs, and memory cells MC1 to MC4 are arranged at the intersections of the word lines and bit line pairs. Reference numerals WR1 and WR2 denote write circuits, an NMOS transistor MNL provided between the bit line BL1 and the power supply VSS, an NMOS transistor MNR provided between the bit line BR1 and the power supply VSS, and a write control signal. It is composed of NAND gates NW1 and NW2 to which WP and data inputs DL and DR are input, and inverters IN1 and IN2 for receiving outputs of NW1 and NW2. The output signals NL and NR of the inverters IN1 and IN2 are connected to the gates of MNL and MNR. PR1 and PR2 denote bit line precharge circuits, which include a PMOS transistor MP0 provided between the power supply VDD and the bit line BL1, a PMOS transistor MP1 provided between the power supply VDD and BR1, and a bit line. It consists of MP2 provided between BR1 and BL1. A precharge control signal PU is input to the gates of MP0, MP1, and MP2. Hereinafter, these PMOSs are referred to as precharge PMOSs.
[0003]
FIG. 3 shows a schematic operation diagram of a conventional example. The operation of the conventional circuit will be described below with reference to FIGS. During standby, all the word lines, the precharge control signal PU, and the write control signal WP are at a low potential. As a result, the precharge PMOS is conductive, the bit lines BL1 and BR1 are both at high potential, and the potential difference (signal amplitude) is zero. In the read operation, first, the precharge control signal PU is set to a high potential, and all the precharge PMOSs are made nonconductive. Only one of the word lines corresponding to the address signal is set to a high potential to select a memory cell. Accordingly, a current (cell current) flows from one of the bit lines BL1 and BR1 toward the memory cell according to the stored data, and a potential difference (signal amplitude) is generated between the bit lines. Since the above cell current is very small, the signal amplitude of the bit line at the time of read operation is small and is generally amplified and output by a sense amplifier or the like.
[0004]
During the write operation, as in the read operation, the precharge control signal PU is set to a high potential to shut off the precharge PMOS, and only one of the word lines corresponding to the address signal is set to a high potential. One of the data inputs DL and DR is at a high potential and the other is at a low potential according to the data to be written. Here, when the write signal WP is set to a high potential, one of NL and NR becomes a high potential. As a result, one of the NMOS transistors NML and NMR becomes conductive, and only one of the bit lines BL1 and BR1 is pulled down to a low potential, so that data in the memory cell is rewritten. After completion of the write operation and the read operation, all the word lines, the write control signal WP, and the precharge control signal PU are returned to a low potential, and the memory cell and the write circuit are shut off. Further, the precharge PMOS is turned on, and both the bit lines BL1 and BR1 are precharged to a high potential within a certain time, and the signal amplitude becomes 0 (hereinafter, this time is referred to as a recovery time).
[0005]
[Problems to be solved by the invention]
Here, when the read operation is performed after the write operation, the minimum cycle time is regulated by the recovery time. In this case, when the cycle time is reduced, the read operation of the next cycle starts before the bit line potential difference returns to 0 at a certain point. At the time of reading, data is read by the signal amplitude of the bit line, but the signal amplitude is very small. For this reason, if the bit line potential difference does not return to 0 at the start of reading, normal data cannot be read due to this potential difference, and the access time may be delayed, or in the worst case, erroneous data may be read. . Thus, the timing at which the read operation of the next cycle starts immediately after the potential difference of the bit line returns to 0 in the recovery period after the end of the write operation is the minimum cycle time. Thus, the recovery time is one of the factors governing the cycle time. Here, in order to reduce the recovery time and the cycle time, it is only necessary to increase the size of the precharge PMOS. In this case, however, the load capacity driven by the precharge control signal increases and the read operation starts. Occasionally, if the precharge PMOS is made non-conductive, the delay time increases and the access time increases.
[0006]
It is an object of the present invention to provide an SRAM having a bit line precharge circuit that shortens the cycle time without increasing the access time.
[0007]
[Means for Solving the Problems]
As means for achieving the above object, typical ones specified by the present invention are shown below.
[0008]
(1) a plurality of word lines, a plurality of bit lines, a memory cell arranged at the intersection of the word line and the bit line, a writing circuit for rewriting data in the memory cell by reducing the potential of the bit line; In the semiconductor memory including the first precharge circuit that returns the bit line potential to a high potential at least after the read operation, the semiconductor memory operates by detecting the end of writing and detects that the bit line potential is precharged to a high potential. A second precharge circuit for ending the operation is provided.
[0009]
(2) In the above means (1), the second precharge circuit includes a first NAND gate for inputting a bit line signal, a first inverter for inputting a write control signal, and an output of the first NAND gate. A first NAND gate for inputting a signal and an output signal of the first inverter, and a first NAND gate disposed between a power line and a bit line on the high potential side and connected to an output of the second NAND gate; A second PMOS transistor and a third PMOS transistor provided between the bit lines and having a gate connected to the output of the second NAND gate.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In this embodiment, in addition to the bit line precharge circuits PR1 and PR2, another new bit line precharge circuit PW1 and PW2 is added to the conventional circuit. Hereinafter, for distinction, PW1 and PW2 are referred to as write-only precharge circuits, and PR1 and PR2 are referred to as precharge circuits. The write-only precharge circuits PW1 and PW2 include the bit lines BL1 and BR1 and the precharge control circuit WRC that receives the write control signal, the power supply VDD and the PMOS transistor MP3 provided on the bit line BR1, the power supply VDD and the bit line BL1. PMOS transistor MP4 provided between the bit lines BR1 and BL1, and a PMOS transistor MP5 provided between the bit lines BR1 and BL1. The output signal PWR of the precharge control circuit WRC is input to the gates of the PMOS transistors MP3, MP4, and MP5. The precharge control circuit WRC is configured to output a low potential only when the write control signal is at a low potential and at least one of the bit line signals is at a low potential.
[0011]
FIG. 4 shows a schematic operation diagram of the present embodiment. Here, the operation waveforms of the word line signals W1, W2, the write control signal WP, and the precharge control signal PU are the same as those in the conventional example, and the memory cells MC1 to MC2, precharge circuits PR1, PR2, and write circuits WR1, WR2 The operation is the same as in the conventional example. On the other hand, the write-only precharge circuit operates as described below. The output PWR of the precharge control circuit WRC outputs a low potential only when the write control signal is at a low potential and at least one of the bit line signals is at a low potential. That is, the output PWR becomes a low potential only from the end of the write operation until the bit line is precharged to a high potential, and the PMOS transistors MP3, MP4, and MP5 of the write-only precharge circuit PW1 are conducted only during that period. . Thus, only the precharge PMOS, MP0, MP1, and MP2 conduct and precharge during the recovery period after the read operation, but the recovery period after the write operation includes MP3, MP3, MP4 and MP5 are also conducted to precharge the bit line at high speed. As a result, this embodiment can shorten the recovery time and the cycle time compared to the conventional example.
[0012]
MP3, MP4, and MP5 are conducted only during the recovery period after writing, and are not conducted during the read operation and standby. For this reason, it is not necessary to drive the precharge PMOS when it is turned off at the start of the read operation. Thus, in the conventional example, when the precharge PMOS is increased in order to reduce the recovery time, there is a problem that the delay time for shutting off the precharge PMOS at the start of the read operation is increased and the access time is delayed. In this embodiment, the cycle time can be reduced without increasing the access time.
[0013]
FIG. 5 is a circuit diagram showing a second embodiment of the present invention, showing a specific circuit configuration of the precharge control circuit WRC in the write-only precharge circuits PW1 and PW2 in the first embodiment. It is. The precharge control circuit includes a NAND gate NA1 to which the bit lines BR1 and BL1 are input, an inverter INV1 to which the write control signal WP is input, an output signal P2 from the NAND gate NA1 and an output signal P1 from the inverter INV1. The output PWR of the NAND gate NA2 is connected to the gates of PMOS transistors MP3 and MP4 provided between the power supply VDD and the bit line and the PMOS transistor MP5 provided between the bit lines.
[0014]
FIG. 7 shows operation waveforms of this embodiment. Hereinafter, the operation of this embodiment will be described with reference to FIG. The present embodiment is a circuit specifically showing the precharge control circuit WRC of the first embodiment, and the basic operation is the same as that of the first embodiment. Thus, only the operation of the precharge control circuit will be described. The output P2 of the NAND gate NA1 to which the bit line signal is input becomes a low potential only when the potentials of the left and right bit lines are both high. Here, the logic threshold value of NA1 is set lower than the bit line potential at the time of reading. As a result, the output P2 of NA1 is at a high potential only from the start of the write operation to the end of recovery of the bit line. Further, the output P1 of the inverter INV1 is an inverted signal of the write control signal WP, and becomes a high potential at times other than the write operation. Thus, the output PWR of the NAND gate NA2 to which P1 and P2 are input becomes a low potential only from the end of the write operation until the bit line is precharged to a high potential.
[0015]
FIG. 8 is a circuit diagram showing a third embodiment of the present invention. In the second embodiment, the complementary signal of the write control signal WP is generated by the inverter INV1 provided for each of the write-only precharge circuits PW1 and PW2, but in this embodiment, it is provided in common for all the precharges. Further, the complementary signal / WP of the write control signal WP is generated and inputted by one inverter INV. As a result, the number of elements of the write-only precharge circuits PW1, PW2 can be reduced as compared with the second embodiment.
[0016]
【The invention's effect】
According to the present invention, the recovery time after the write operation can be shortened and the cycle time can be shortened without increasing the delay time for turning off the precharge PMOS during the read operation, that is, the access time. For example, as shown in FIG. 5, in the circuit of FIG. 1 to which the present invention is applied, the recovery time after writing can be reduced by about 25% compared to the conventional circuit of FIG.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of the present invention.
FIG. 2 is a diagram showing a conventional example.
FIG. 3 is a schematic operation diagram of a conventional example.
FIG. 4 is an operation schematic diagram of the first embodiment of the present invention.
FIG. 5 is a diagram showing the effect of the present invention.
FIG. 6 is a diagram showing a second embodiment of the present invention.
FIG. 7 is an operation schematic diagram of the second embodiment of the present invention.
FIG. 8 is a diagram showing a third embodiment of the present invention.
[Explanation of symbols]
W1, W2 ... Word lines BL1, BR1, BL2, BR2 ... Bit lines MC1, MC2, MC3, MC4 ... Memory cells WR1, WR2 ... Write circuits PR1, PR2 ... Bit line precharge circuit PU ... Precharge control signal, WP ... Write control signals PW1, PW2... Write-only bit line precharge circuit WRC... Precharge control circuit.

Claims (2)

Multiple word lines,
Multiple bit lines,
A memory cell located at the intersection of each word line and bit line;
A write circuit for rewriting data of a desired memory cell by lowering the potential of the bit line;
A first precharge circuit that returns the potential of the bit line to a high potential at least after a read operation;
Operates by detecting the completion of writing, possess a second precharge circuit potential of the bit line is completed detected and operation that are precharged to a high potential, the
The second precharge circuit includes:
A first NAND gate for inputting a bit line signal;
A first inverter for inputting a write control signal;
A second NAND gate for inputting the output signal of the first NAND gate and the output signal of the first inverter;
First and second PMOS transistors disposed between a high-potential-side power supply line and a bit line and having a gate connected to an output of the second NAND gate;
A semiconductor memory which is characterized in that chromatic provided between the bit line, a third PMOS transistor having a gate connected to an output of said second NAND gate, a. Multiple word lines,
Multiple bit lines,
A memory cell located at the intersection of each word line and bit line;
A write circuit for rewriting data of a desired memory cell by lowering the potential of the bit line;
A first precharge circuit that returns the potential of the bit line to a high potential at least after a read operation;
A second precharge circuit that operates by detecting the end of writing, detects that the potential of the bit line has been precharged to a high potential, and ends the operation.
Before Stories second precharge circuit,
A first NAND gate for inputting a bit line signal ;
A second NAND gate for inputting a complementary signal of the output signal of the first NAND gate and a write control signal;
First and second PMOS transistors disposed between a high-potential-side power supply line and a bit line and having a gate connected to an output of the second NAND gate;
And a third PMOS transistor provided between the bit lines and having a gate connected to the output of the second NAND gate .

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