JP4149151B2 - Input/Output Buffer Circuit - Google Patents

Description

[0001]
[Technical field to which the invention pertains]
The present invention relates to an input/output buffer circuit, and more particularly to an input/output buffer circuit including a PMOS transistor to which a voltage signal having a voltage level higher than its own power supply voltage is directly input.
[0002]
2. Description of the Related Art
An input/output buffer circuit is a buffer circuit that can output a signal to the outside of a semiconductor integrated circuit (hereinafter referred to as LSI) and input a signal from the outside, thereby propagating a signal in both directions. As an example, an input/output buffer circuit 1 is shown in FIG. 9. A signal input from an input/output terminal PAD, which is a connection part with the outside of the LSI, is input to an input buffer section BI in an input/output buffer section B. At this time, an output buffer section BO is inactivated by an output enable signal (not shown). A signal is output from the input/output terminal PAD by the output buffer section BO activated by the output enable signal. Here, the output buffer section BO has a drive stage of a CMOS configuration, and in FIG. 9, a PMOS transistor BM1 is illustrated.
[0003]
In addition, in FIG. 9, the input/output buffer circuit 1 includes, in addition to the input/output buffer section B, an electrostatic breakdown protection section D for preventing electrostatic breakdown of internal elements due to a surge voltage such as static electricity from the external input/output terminal PAD, and a clamp section C for clamping the input voltage level on the high voltage side to a predetermined voltage level in the input mode.
[0004]
The electrostatic breakdown protection unit D is composed of diode elements DU and DL for absorbing a surge voltage input from the input/output terminal PAD to the power supply voltage VDD1 and the ground voltage GND. These diode elements DU and DL can be composed of PN junctions, or can be composed of diode-connected MOS transistors. For example, to configure the diode element DU with a PMOS transistor, the source terminal, gate terminal, and back gate terminal are connected to the power supply voltage VDD1, and the drain terminal is connected to the input/output terminal PAD. When a surge voltage equal to or greater than a voltage obtained by adding the threshold voltage of a diode-connected PMOS transistor from the power supply voltage VDD1 is applied to the input/output terminal PAD, the diode element DU composed of a PMOS transistor becomes conductive, forming a path for discharging the surge voltage to the power supply voltage VDD1 side, thereby protecting the internal circuits such as the input/output buffer unit B from the surge voltage.
[0005]
The clamp unit C is a circuit for clamping the voltage level when the input/output terminal PAD is in a floating state. The PMOS transistor CM1 controlled by the pull-up control circuit C1 is turned on as necessary to clamp the input/output terminal PAD to the power supply voltage VDD1.
[0006]
With the recent progress in miniaturization of LSIs, the driving power supply voltage of LSIs has been decreasing, and there are cases where a system is constructed by combining multiple LSIs that operate on different power supply voltages. In this case, it would be convenient if the input/output terminals of the LSIs that operate on different power supply voltages could be directly connected to each other, and proposals to realize this have been made in the past. This proposal provides an N-well potential control unit A that biases the N-well potential of a PMOS transistor to the higher voltage side of the power supply voltage and the input voltage signal, and specifically, there are the following methods.
[0007]
The N-well potential control unit A100 shown in FIG. 10 is composed of a first PMOS transistor PM1 having a source terminal connected to the power supply voltage VDD1, a drain terminal and a back gate terminal connected to the N-well NW, and a gate terminal connected to the input/output terminal PAD (the voltage signal VIN to be input/output), and a second PMOS transistor PM2 having a source terminal connected to the input/output terminal PAD, a drain terminal and a back gate terminal connected to the N-well NW, and a gate terminal connected to the power supply voltage VDD1.
[0008]
If the threshold voltage of the PMOS transistors PM1 and PM2 is VthP, when VIN<VDD1-VthP, the voltage signal VIN applied to the gate terminal of the first PMOS transistor PM1 is lower than the power supply voltage VDD1 applied to the source terminal, and the potential difference is equal to or greater than the threshold voltage VthP. Therefore, the first PMOS transistor PM1 operates linearly and becomes conductive, connecting the N-well NW to the power supply voltage VDD1. On the other hand, in the second PMOS transistor PM2, the voltage relationship between the gate terminal and the source terminal is the opposite relationship to that of the first PMOS transistor PM1, so the non-conductive state is maintained. Therefore, the potential VNW of the N-well NW is biased to the power supply voltage VDD1.
[0009]
When VIN>VDD1+VthP, the voltage relationship between the gate terminals and the source terminals of the first and second PMOS transistors PM1 and PM2 is the opposite to that described above. That is, the first PMOS transistor PM1 is in a non-conductive state, while the second PMOS transistor PM2 operates linearly and is conductive. Therefore, the potential VNW of the N-well NW is biased to the voltage signal VIN.
[0010]
10, the N-well NW is biased to the power supply voltage VDD1 when VIN<VDD1-VthP, and is biased to the voltage signal VIN when VIN>VDD1+VthP. In these regions, the N-well NW is biased to the higher voltage of the power supply voltage VDD1 and the voltage signal VIN.
[0011]
[Problem to be solved by the invention]
However, in the N-well potential control unit A100, in the region of VDD1-VthP<VIN<VDD1+VthP, the N-well NW becomes in a floating state, which is a problem.
[0012]
As described above, when the potential VNW of the N-well NW is in a floating state, the backgate bias in PMOS transistors such as the drive stage PMOS transistor BM1 of the output buffer unit BO in FIG. 9, the PMOS transistor CM1 of the clamp unit C, and the diode element DU composed of the PMOS transistor of the electrostatic breakdown protection unit D, becomes unstable, which may cause various malfunctions in the circuit operation, such as instability of the driving capability due to instability in the threshold voltage caused by the backgate bias effect, instability of switching control, or an increase in the forward current in the PN junction from the drain terminal to the N-well NW, which is problematic.
[0013]
The present invention has been made to solve the problems of the prior art, and has an object to provide an input/output buffer circuit including PMOS transistors, which can reliably bias the N-well potential even if a voltage signal having a voltage different from its own power supply voltage is directly input to an input/output terminal, and which has an N-well potential control section that prevents the N-well potential from floating over the entire voltage range of the voltage signal.
[0014]
[Means for solving the problem]
In order to achieve the above object, an input/output buffer circuit according to claim 1 is an input/output buffer circuit in which a voltage signal having a voltage level higher than its own power supply voltage is directly input to an input/output terminal, and which includes an N-well potential control section which sets an N-well potential of a PMOS transistor to whose drain terminal the voltage signal is applied to the power supply voltage in a first region where the voltage signal is a voltage equal to or lower than a first predetermined voltage value compared to the power supply voltage, to a voltage signal in a second region where the voltage signal is a voltage equal to or higher than a second predetermined voltage value compared to the power supply voltage, and to the power supply voltage or a voltage signal in a third region where the voltage signal is a voltage between the first and second regions. The N-well potential control unit includes a first PMOS transistor having a source terminal connected to a power supply voltage and a drain terminal and a back gate terminal connected to the N-well, a second PMOS transistor having a source terminal connected to an input/output terminal, a drain terminal and a back gate terminal connected to the N-well, and a gate terminal connected to the power supply voltage, and a PMOS transistor control unit that sets a second predetermined voltage value as a threshold voltage value of the second PMOS transistor, and makes the first PMOS transistor conductive in the first and third regions and makes the first PMOS transistor non-conductive in the second region .
[0015]
In the input/output buffer circuit of the first aspect, the N-well potential control unit appropriately switches the N-well potential of the PMOS transistor, to which a voltage signal is applied at the drain terminal, between the power supply voltage and the voltage signal according to the voltage level of the voltage signal at the input/output terminal. The voltage level of the voltage signal to be switched is performed according to the magnitude relationship with the power supply voltage. That is, the voltage signal is set to the power supply voltage in the first region where the voltage is equal to or lower than a first predetermined voltage value compared to the power supply voltage, and is set to the voltage signal in the second region where the voltage is equal to or higher than a second predetermined voltage value compared to the power supply voltage. Then, in the intermediate third region, the voltage signal is set to one of the two voltage levels. In this case, since the source terminal of the second PMOS transistor is connected to the input/output terminal and the gate terminal is connected to the power supply voltage, when the voltage level of the voltage signal is boosted to a voltage equal to or higher than the voltage obtained by adding the threshold voltage of the second PMOS transistor to the power supply voltage, the second PMOS transistor becomes conductive and supplies the voltage signal to the N-well. Meanwhile, the first PMOS transistor is controlled by the PMOS transistor control unit. The voltage level of the voltage signal is the power supply voltage plus the threshold voltage of the second PMOS transistor, and in the first and third regions below this voltage, the PMOS transistor is conductive to supply the power supply voltage to the N-well, and in the second region above this voltage, the PMOS transistor is non-conductive. Usually, the threshold voltages of the first and second PMOS transistors are the same. Therefore, in the first and third regions, the second PMOS transistor is non-conductive and the first PMOS transistor is conductive to set the N-well potential to the power supply voltage, and in the second region, the first PMOS transistor is non-conductive and the second PMOS transistor is conductive to set the N-well potential to the voltage signal.
According to a fourth aspect of the present invention, there is provided an input/output buffer circuit in which a voltage signal at a voltage level higher than its own power supply voltage is directly input to an input/output terminal, the input/output buffer circuit comprising an N-well potential control section for setting an N-well potential of a PMOS transistor to whose drain terminal the voltage signal is applied to the power supply voltage in a first region where the voltage signal is a first predetermined voltage value or less compared to the power supply voltage, to the voltage signal in a second region where the voltage signal is a second predetermined voltage value or more compared to the power supply voltage, and to the power supply voltage or to the voltage signal in a third region where the voltage signal is a voltage sandwiched between the first and second regions, the N-well potential control section comprising first and second PMOS transistors, and each of whose source terminals, drain terminals and backgate terminals have a connection relationship similar to that of the first aspect, with the gate terminal of the first PMOS transistor being connected to the input/output terminal. The second PMOS transistor includes a PMOS transistor control unit that sets the first predetermined voltage value as a threshold voltage value of the first PMOS transistor, and renders the second PMOS transistor non-conductive in the first region and renders the second PMOS transistor conductive in the second and third regions.
In the input/output buffer circuit of claim 4, the N-well potential of the PMOS transistor, to whose drain terminal a voltage signal is applied, is appropriately switched between the power supply voltage and the voltage signal by the N-well potential control unit according to the voltage level of the voltage signal at the input/output terminal. The voltage level of the voltage signal to be switched is performed according to the magnitude relationship with the power supply voltage. That is, the voltage signal is set to the power supply voltage in a first region where the voltage is equal to or lower than a first predetermined voltage value compared to the power supply voltage, and is set to the voltage signal in a second region where the voltage is equal to or higher than a second predetermined voltage value compared to the power supply voltage. Then, in an intermediate third region, the voltage signal is set to one of the two voltage levels. In this case, the connections to the gate terminals of the first and second PMOS transistors have an opposite relationship to the connections in claim 1. The first PMOS transistor is conductive when the voltage level of the voltage signal is lowered below the power supply voltage to the threshold voltage of the first PMOS transistor, and supplies the power supply voltage to the N-well. On the other hand, the second PMOS transistor is controlled by the PMOS transistor control unit. The voltage level of the voltage signal is set to a threshold voltage, which is a voltage lower than the power supply voltage by the threshold voltage of the first PMOS transistor, and is non-conductive in a first region below this voltage, and is conductive in second and third regions above this voltage to supply a voltage signal to the N-well. Normally, the threshold voltages of the first and second PMOS transistors are the same, so in the first region, the first PMOS transistor is conductive and the second PMOS transistor is non-conductive, making the N-well potential the power supply voltage, and in the second and third regions, the first PMOS transistor is non-conductive and the second PMOS transistor is conductive, making the N-well potential the voltage signal.
[0016]
As a result, the N-well potential of the PMOS transistor is set to an appropriate voltage according to the voltage level of the voltage signal applied to the input/output terminal, and therefore does not become floating at a predetermined voltage level. Therefore, the N-well potential can be reliably set for all voltage levels of the voltage signal at the input/output terminal, and the input/output buffer circuit can always achieve stable circuit operation regardless of the input state or output state.
By utilizing the threshold voltage of the PMOS transistor, the N-well potential can be switched between the power supply voltage and the voltage signal, with the voltage level of the voltage signal being the threshold voltage away from the power supply voltage as the boundary.
[0017]
According to a second aspect of the present invention, in the input/output buffer circuit of the first aspect, the N-well potential control section fixes the N-well potential to the power supply voltage in the third region.
[0018]
[0019]
[0020]
[0021]
[0022]
[0023]
According to a third aspect of the present invention, in the input/output buffer circuit of the first or second aspect, the PMOS transistor control unit includes an NMOS transistor having a source terminal connected to the gate terminal of the first PMOS transistor, a drain terminal connected to the input/output terminal, and a gate terminal to which a predetermined voltage lower than the power supply voltage is applied, and a third PMOS transistor having a source terminal connected to the input/output terminal, a drain terminal connected to the gate terminal of the first PMOS transistor, a gate terminal connected to the power supply voltage, and a back gate terminal connected to the N-well.
[0024]
In the input/output buffer circuit of claim 3 , as a PMOS transistor control section for controlling the first PMOS transistor, an NMOS transistor is connected between the input/output terminal and the gate terminal of the first PMOS transistor, with a predetermined voltage lower than the power supply voltage applied to the gate terminal. A voltage with an upper limit equal to a voltage obtained by subtracting the threshold voltage of the NMOS transistor from the predetermined voltage lower than the power supply voltage is applied to the gate terminal of the first PMOS transistor to make the first PMOS transistor conductive. On the other hand, when the voltage level of the voltage signal is boosted to the power supply voltage plus the threshold voltage of the third PMOS transistor or higher, the third PMOS transistor is made conductive, and a voltage signal is applied to the gate terminal of the first PMOS transistor to make the NMOS transistor non-conductive. Normally, the thresholds of the first to third PMOS transistors are the same, so the third PMOS transistor makes the NMOS transistor non-conductive and also makes the first PMOS transistor non-conductive. Since the second PMOS transistor is made conductive, the N-well potential is switched.
[0025]
According to a fifth aspect of the present invention, in the input/output buffer circuit of the fourth aspect, the PMOS transistor control section includes an NMOS transistor having a source terminal connected to the gate terminal of the second PMOS transistor and a drain terminal connected to a power supply voltage, and having a gate terminal to which a voltage signal or a predetermined voltage lower than the voltage signal is applied, and a third PMOS transistor having a source terminal connected to the power supply voltage, a drain terminal connected to the gate terminal of the second PMOS transistor, a gate terminal connected to the input/output terminal, and a back gate terminal connected to the N-well.
[0026]
In the input/output buffer circuit of claim 5 , as a PMOS transistor control section for controlling the second PMOS transistor, an NMOS transistor is connected between a power supply voltage and the gate terminal of the second PMOS transistor, with a voltage signal or a predetermined voltage lower than the voltage signal applied to the gate terminal. A voltage with an upper limit equal to a voltage obtained by subtracting the threshold voltage of the NMOS transistor from the voltage signal or the predetermined voltage lower than the voltage signal is applied to the gate terminal of the second PMOS transistor to make the second PMOS transistor conductive. On the other hand, when the voltage level of the voltage signal is lowered from the power supply voltage to the threshold voltage of the third PMOS transistor or lower, the third PMOS transistor is made conductive, and the power supply voltage is applied to the gate terminal of the second PMOS transistor to make the NMOS transistor non-conductive. Normally, the thresholds of the first to third PMOS transistors are the same, so the third PMOS transistor makes the NMOS transistor non-conductive and also makes the second PMOS transistor non-conductive. Since the first PMOS transistor is conductive, the N-well potential is switched.
[0027]
As a result, when the first or second PMOS transistor is made conductive by the NMOS transistor, the voltage applied to the gate terminal of the first or second PMOS transistor is limited to an upper limit voltage obtained by subtracting the threshold voltage of the NMOS transistor from the voltage applied to the gate terminal of the NMOS transistor, so that a voltage equal to or higher than the threshold voltage can be reliably applied between the gate terminal and source terminal of the first or second PMOS transistor. In particular, if the voltage applied to the gate terminal of the NMOS transistor is set to a predetermined voltage lower than the power supply voltage or the voltage signal, the upper limit of the voltage applied to the gate terminal of the first or second PMOS transistor can be lowered by the predetermined voltage. The first or second PMOS transistor is made conductive by linear operation, and the N well can be reliably biased to the power supply voltage or the voltage signal.
[0028]
In the input/output buffer circuit according to the third aspect of the present invention, the predetermined voltage applied to the gate terminal of the NMOS transistor can utilize one of the multiple power supply systems.
[0029]
Furthermore, if a second voltage step-down unit is provided that receives a power supply voltage or a voltage signal as input and outputs a predetermined voltage, the predetermined voltage to be applied to the gate terminal of the NMOS transistor can be provided by appropriately stepping down the power supply voltage or the voltage signal.
[0030]
Furthermore, if a first voltage step-down unit is provided that receives a signal from the source terminal of the NMOS transistor, steps down this signal, and outputs the stepped-down signal to the gate terminal of the first or second PMOS transistor, then when the first or second PMOS transistor is made conductive, the voltage applied to the gate terminal of the first or second PMOS transistor can be appropriately stepped down, thereby ensuring that the first or second PMOS transistor is made conductive.
[0031]
Here, the first and second voltage step-down sections can easily obtain an appropriately stepped-down output by using a resistive element or a step-down at a junction.
[0032]
[0023]
Hereinafter, an embodiment of the input/output buffer circuit of the present invention will be described in detail with reference to the drawings based on FIGS. 1 to 8. FIG. 1 is a circuit diagram showing an N-well potential control section in an input/output buffer circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a first specific example of the N-well potential control section. FIG. 3 is a circuit diagram showing a second specific example of the N-well potential control section. FIG. 4 is a circuit diagram showing a third specific example of the N-well potential control section. FIG. 5 is a circuit diagram showing a fourth specific example of the N-well potential control section. FIG. 6 is a circuit diagram showing a fifth specific example of the N-well potential control section. FIG. 7 is a waveform diagram showing how the well potential is switched by the N-well potential control section of the embodiment. FIG. 8 is a waveform diagram showing how the well potential is switched by the N-well potential control section of another embodiment. FIG. 9 is a circuit block diagram showing an input/output buffer circuit. FIG. 10 is a circuit diagram showing an N-well potential control section of the prior art.
[0033]
In the input/output buffer circuit of the embodiment of the present invention shown in FIG. 1, in addition to the conventional N-well potential control unit A100, a PMOS transistor control unit is provided to control the conduction/non-conduction of the first PMOS transistor PM1. The PMOS transistor control unit includes an NMOS transistor NM1, a third PMOS transistor PM3, and first and second voltage step-down units 11 and 12. Between the gate terminal of the first PMOS transistor PM1 and the input/output terminal PAD, a third PMOS transistor PM3 is provided, the gate terminal of which is connected to the power supply voltage VDD1 and the back gate terminal of which is connected to the N-well NW. Furthermore, the NMOS transistor NM1 is provided with a drain terminal connected to the input/output terminal PAD and a source terminal connected to the gate terminal P1 of the first PMOS transistor PM1 via the first voltage step-down unit 12 as necessary. The gate terminal of this third PMOS transistor PM3 is biased by the second voltage step-down unit 11.
[0034]
The second voltage step-down unit 11 outputs a predetermined voltage lower than the power supply voltage VDD1, and biases the gate terminal of the NMOS transistor NM1 to the predetermined voltage. When the voltage signal VIN from the input/output terminal PAD input to the drain terminal of the NMOS transistor NM1 is equal to or lower than the voltage value obtained by subtracting the threshold voltage VthN of the NMOS transistor NM1 from the predetermined voltage, the NMOS transistor NM1 operates linearly and becomes conductive, and the voltage signal VIN is output as is to the source terminal of the NMOS transistor NM1. On the other hand, when the voltage signal VIN is boosted and exceeds the voltage value obtained by subtracting the threshold voltage VthN from the predetermined voltage, the NMOS transistor NM1 operates in saturation. That is, the voltage obtained by subtracting the threshold voltage VthN from the predetermined voltage is output to the source terminal of the NMOS transistor NM1. This output voltage does not change even if the voltage signal VIN is boosted, and is fixed to the voltage obtained by subtracting the threshold voltage VthN from the predetermined voltage.
[0035]
As a result, when the first PMOS transistor PM1 is turned on, the voltage applied to the gate terminal P1 is limited to a voltage value equal to or lower than the predetermined voltage minus the threshold voltage VthN before being stepped down by the first voltage step-down unit 12. Therefore, if the predetermined voltage is set to a voltage appropriately stepped down from the power supply voltage VDD1, a voltage equal to or higher than the threshold voltage VthP is reliably applied between the gate terminal P1 and the source terminal of the first PMOS transistor PM1 even if the first voltage step-down unit 12 is not provided and the source terminal of the NMOS transistor NM1 and the gate terminal P1 of the first PMOS transistor PM1 are directly connected. In other words, if the predetermined voltage is set according to the magnitude relationship between the threshold voltage VthN of the NMOS transistor NM1 and the threshold voltage VthP of the first PMOS transistor PM1, the voltage applied to the gate terminal P1 of the first PMOS transistor PM1 can be a voltage stepped down from the power supply voltage VDD1, which is the voltage of the source terminal, to a voltage equal to or higher than the threshold voltage VthP. Since the first PMOS transistor PM1 operates linearly and is conductive, the N-well NW can be reliably biased to the power supply voltage VDD1.
[0036]
The first voltage step-down unit 12 steps down the voltage from the source terminal of the NMOS transistor NM1 and biases the gate terminal P1 of the first PMOS transistor PM1. As a result, regardless of the presence or absence of the second voltage step-down unit 11 described above, the first voltage step-down unit 12 can apply a voltage obtained by appropriately stepping down the voltage from the source terminal of the NMOS transistor NM1 to the gate terminal P1 of the first PMOS transistor PM1. Regardless of the voltage value, a voltage equal to or higher than the threshold voltage VthP is reliably applied between the gate terminal P1 and the source terminal of the first PMOS transistor PM1, and the first PMOS transistor PM1 operates linearly to become conductive, so that the N well NW can be reliably biased to the power supply voltage VDD1.
[0037]
This state continues until the voltage signal VIN reaches a voltage value equal to or greater than the threshold voltage VthP relative to the power supply voltage VDD1. After the voltage signal VIN reaches a voltage value equal to or greater than the threshold voltage VthP relative to the power supply voltage VDD1, the third PMOS transistor PM3 becomes conductive, biasing the gate terminal P1 of the first PMOS transistor PM1 to the voltage signal VIN and making the first PMOS transistor PM1 non-conductive. At the same time, the second PMOS transistor PM2 becomes conductive, so that the N-well NW is biased to the voltage signal VIN instead of the power supply voltage VDD1.
[0038]
1, the potential VNW of the N-well NW of the PMOS transistor provided in the input/output buffer circuit 1 is biased seamlessly to the power supply voltage VDD1 when VIN<VDD1+VthP, and to the voltage signal VIN when VIN>VDD1+VthP, in response to the voltage signal VIN applied to the input/output terminal PAD, and therefore does not enter a floating state. Therefore, the potential VNW of the N-well NW can be reliably set for all voltage values of the voltage signal VIN of the input/output terminal PAD, and the input/output buffer circuit 1 can always obtain stable circuit operation regardless of the input state or output state.
[0039]
2 to 6, specific examples of the second voltage step-down section 11 and the first voltage step-down section 12 will be shown as first to fifth specific examples. Here, the first to third specific examples (FIGS. 2 to 4) are specific examples of the second voltage step-down section 11, and the fourth and fifth specific examples (FIGS. 5 and 6) are specific examples of the first voltage step-down section 12.
[0040]
First, a specific example of the second voltage step-down unit 11 will be shown. In the N-well potential control unit A11 of the first specific example in FIG. 2, a second power supply voltage VDD2, which is one of a plurality of power supply systems, is used as a predetermined voltage lower than the power supply voltage VDD1 output from the second voltage step-down unit 11. In recent LSIs and electronic application product boards, a plurality of power supply voltages for circuit operation may be prepared. Among these power supply systems, the second power supply voltage VDD2, which is lower than the power supply voltage VDD1 used for the circuit operation of the input/output buffer circuit 1, can be used as a voltage for biasing the gate terminal of the NMOS transistor NM1. As a result, when the first PMOS transistor PM1 is made conductive, a voltage with an upper limit equal to the voltage obtained by subtracting the threshold voltage VthN from the second power supply voltage VDD2 is applied to the source terminal of the NMOS transistor NM1 directly connected to the gate terminal P1 of the first PMOS transistor PM1. Here, since VDD2<VDD1, a voltage equal to or higher than the threshold voltage VthP is applied between the gate and source of the first PMOS transistor PM1, and the first PMOS transistor PM1 operates linearly and becomes conductive. Therefore, the power supply voltage VDD1 is reliably biased to the N-well NW.
[0041]
3, the N-well potential control unit A12 of the second specific example is configured to apply a predetermined voltage obtained by dividing the power supply voltage VDD1 to the gate terminal of the NMOS transistor NM1 by inserting resistance elements R1 and R2 between the power supply voltage VDD1 and the ground voltage GND as the second voltage step-down unit 11. By appropriately setting the voltage division ratio of the resistance elements R1 and R2, a voltage obtained by subtracting the threshold voltage VthN from this predetermined voltage is applied to the gate terminal P1 of the first PMOS transistor PM1, reliably turning on the first PMOS transistor PM1 and reliably biasing the power supply voltage VDD1 to the N-well NW.
[0042]
4, the N-well potential control unit A13 applies a step-down voltage generated by a diode group D1, which is made up of a predetermined number of diodes connected in series, to the gate terminal of the NMOS transistor NM1 as the second voltage step-down unit 11. By appropriately setting the step-down value of the diode group D1, the first PMOS transistor PM1 can be made conductive reliably, and the power supply voltage VDD1 can be reliably biased to the N-well NW.
[0043]
Next, a specific example of the first voltage step-down unit 12 will be described. In the N-well potential control unit A14 of the fourth specific example in FIG. 5, the first voltage step-down unit 12 uses a diode group D2 in which a predetermined number of diodes are connected in series to step down the voltage output from the source terminal of the NMOS transistor NM1 and apply it to the gate terminal P1 of the first PMOS transistor PM1. Since the voltage output from the source terminal of the NMOS transistor NM1 has an upper limit of a voltage value obtained by subtracting the threshold voltage VthN from the power supply voltage VDD1, by appropriately setting the step-down value of the diode group D2, when the first PMOS transistor PM1 is made conductive, a voltage equal to or lower than the voltage obtained by subtracting the threshold voltage VthP from the power supply voltage VDD1 can be applied to the gate terminal P1 of the first PMOS transistor PM1. The first PMOS transistor PM1 is made conductive by linear operation, and the power supply voltage VDD1 is reliably biased to the N-well NW.
[0044]
6, the N-well potential control unit A15 of the fifth specific example is configured to apply a predetermined voltage obtained by dividing the voltage from the source terminal of the NMOS transistor NM1 to the gate terminal P1 of the PMOS transistor PM1 by inserting resistance elements R3 and R4 between the source terminal of the NMOS transistor NM1 and the ground voltage GND as the first voltage step-down unit 12. By appropriately setting the voltage division ratio of the resistance elements R3 and R4, the first PMOS transistor PM1 can be reliably brought into conduction, and the power supply voltage VDD1 can be reliably biased to the N-well NW.
[0045]
7 shows the switching waveform of the potential VNW of the well NW with respect to the voltage signal VIN, together with the voltage value VP1 of the gate terminal P1 of the first PMOS transistor PM1, in the N-well potential control unit A1 of the embodiment (first to fifth specific examples A11 to A15). In FIG. 7, the case where the power supply voltage VDD1 is 3.3 V and the absolute values of the threshold voltages of the NMOS/PMOS transistors are approximately equal (VthN≈VthP) is shown as an example.
[0046]
When the voltage signal VIN is equal to or higher than the voltage obtained by adding the threshold voltage VthP to the power supply voltage VDD1 (region (2) in FIG. 7: VIN>VDD1+VthP), the third PMOS transistor PM3 is conductive and biases the voltage value VP1 of the gate terminal P1 of the first PMOS transistor PM1 to the voltage signal VIN, so that the first PMOS transistor PM1 is non-conductive. On the other hand, the second PMOS transistor PM2 is conductive and the potential VNW of the N-well NW becomes the voltage signal VIN.
[0047]
When the voltage signal VIN drops to a voltage equal to or lower than the power supply voltage VDD1 plus the threshold voltage VthP (regions (1) and (3) in FIG. 7: VIN<VDD1+VthP), the second and third PMOS transistors PM2 and PM3 become non-conductive. On the other hand, the NMOS transistor NM1 is conductive. However, until the voltage signal VIN drops to a voltage obtained by subtracting the threshold voltage VthN from the voltage of the gate terminal of the NMOS transistor NM1, the NMOS transistor NM1 operates in saturation, so that the voltage of the source terminal is substantially fixed to the voltage obtained by subtracting the threshold voltage VthN from the voltage of the gate terminal. This voltage is applied to the gate terminal P1 of the first PMOS transistor PM1, and the potential difference between the gate and source is biased to the threshold voltage VthP or higher, so that the first PMOS transistor PM1 operates linearly and becomes conductive, and the N-well NW is biased to the power supply voltage VDD1.
[0048]
7, the waveform when the voltage VP1 of the gate terminal P1 is stepped down from the power supply voltage VDD1 (3.3 V) by approximately the threshold voltage VthN is the same as the waveform when the second voltage step-down unit 11 and the first voltage step-down unit 12 are not present and the gate terminal of the NMOS transistor NM1 is connected to the power supply voltage VDD1 in Fig. 1. A voltage stepped down from the source terminal by the threshold voltage VthN is applied to the gate terminal P1 of the first PMOS transistor PM1, but since the absolute values of the threshold voltages VthN and VthP are approximately equal, there is a risk that the first PMOS transistor PM1 cannot be operated linearly enough to be conductive.
[0049]
Therefore, in order to further step down the voltage VP1 of the gate terminal P1 of the first PMOS transistor PM1, it is preferable to provide at least one of the second voltage step-down unit 11 and the first voltage step-down unit 12.
[0050]
By providing the second voltage step-down unit 11, the predetermined voltage applied to the gate terminal of the NMOS transistor NM1 can be lowered from the power supply voltage VDD1, and the voltage value of the source terminal in saturation operation can be further lowered. As a result, the total step-down value V1, V2 from the power supply voltage VDD1 at the voltage VP1 of the gate terminal P1 is a voltage obtained by adding the step-down value of the predetermined voltage at the gate terminal by the second voltage step-down unit 11 to the threshold voltage VthN. When the second voltage step-down unit 11 is provided, the voltage applied to the gate terminal of the NMOS transistor NM1 is stepped down, so that the saturation operation of the NMOS transistor NM1 is maintained even in region (1) according to the total step-down value V1, V2 (waveform indicated by I in FIG. 7).
[0051]
Furthermore, by providing the first voltage step-down unit 12, the voltage VP1 of the gate terminal P1 can be stepped down uniformly. The total step-down values V1 and V2 from the power supply voltage VDD1 are the voltages obtained by adding the step-down value by the first voltage step-down unit 12 to the threshold voltage VthN. When the first voltage step-down unit 12 is provided, the voltage applied to the gate terminal of the NMOS transistor NM1 can be, for example, the power supply voltage VDD1, so that the saturation operation of the NMOS transistor NM1 is maintained only in region (3) regardless of the total step-down values V1 and V2. Furthermore, the step-down by the first voltage step-down unit 12 is a constant voltage value, so that the step-down of a predetermined voltage is maintained even in region (1) in which the NMOS transistor NM1 operates linearly (waveform indicated by II in FIG. 7).
[0052]
In the above, the case where the second voltage step-down unit 11 and the first voltage step-down unit 12 are provided separately has been described, but if both the second voltage step-down unit 11 and the first voltage step-down unit 12 are provided, the respective step-down voltages are added together, and the voltage VIN applied to the gate terminal P1 when the first PMOS transistor PM1 is conductive can be effectively stepped down. That is, the same effect can be achieved whether both the second voltage step-down unit 11 and the first voltage step-down unit 12 are provided together or each is provided separately.
[0053]
In the embodiment, the NMOS transistor NM1 and the third PMOS transistor PM3 are provided between the gate terminal P1 of the first PMOS transistor PM1 and the input/output terminal PAD, but in another embodiment, the connection relationship may be reversed to achieve the same effect. That is, the NMOS transistor NM1 and the third PMOS transistor PM3 are provided between the gate terminal P2 of the second PMOS transistor PM2 and the power supply voltage VDD1, and the gate terminal of the NMOS transistor NM1 is connected to the input/output terminal PAD. Also, the gate terminals of the first and third PMOS transistors PM1 and PM3 are connected to the input/output terminal PAD. In this case, the second voltage step-down unit 11 and the first voltage step-down unit 12 can be connected in the same manner as in the embodiment, and achieve the same action and effect. That is, the second voltage step-down unit 11 can be connected to the gate terminal of the NMOS transistor NM1 to apply a predetermined voltage, and can be set to step down the voltage signal VIN of the input/output terminal PAD. The first voltage step-down unit 12 may be provided between the NMOS transistor NM1 and the gate terminal P2 of the second PMOS transistor PM2.
[0054]
In another embodiment, waveforms showing the relationship of the voltage VP2 of the gate terminal P2 of the second PMOS transistor PM2 and the potential VNW of the N-well NW to the voltage signal VIN are shown in Fig. 8. In region (1'), the first and third PMOS transistors PM1 and PM3 are conductive and the second PMOS transistor PM2 is non-conductive, so that the N-well NW is biased to the power supply voltage VDD1.
[0055]
In the case where the second voltage step-down unit 11 and the first voltage step-down unit 12 are not provided, in the region (3') where the NMOS transistor NM1 operates in saturation, the voltage VP2 of the gate terminal P2 of the second PMOS transistor PM2 is biased to a voltage obtained by subtracting the threshold voltage VthN from the voltage signal VIN. In this state, if the absolute values of the threshold voltages of the NMOS and PMOS are approximately equal (VthN ≈ VthP), there is a risk that the second PMOS transistor PM2 will not operate linearly enough and will not be conductive, as in the case of the embodiment shown in FIG.
[0056]
In addition, in region (2'), the NMOS transistor NM1 enters a region in which it operates linearly, so that the power supply voltage VDD1 is applied to the voltage VP2 of the gate terminal P2 of the second PMOS transistor PM2, and the second PMOS transistor PM2 operates linearly to bias the N-well NW to the voltage signal VIN.
[0057]
Next, when the second voltage step-down unit 11 is provided, the voltage applied to the gate terminal of the NMOS transistor NM1 is stepped down, and the saturated operating region of the NMOS transistor NM1 is extended by the amount of this step-down (waveform indicated by I in FIG. 8).
[0058]
Furthermore, when the first voltage step-down unit 12 is provided, the voltage VP2 of the gate terminal P2 can be stepped down uniformly (waveform indicated by II in FIG. 8).
[0059]
Incidentally, the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications are possible without departing from the spirit and scope of the present invention.
For example, in this embodiment, the threshold voltages VthN and VthP of the MOS transistors are used to set the voltage signal VIN for switching the bias voltage of the potential VNW of the N-well NW, but the present invention is not limited to this and can be applied to any configuration that can detect a voltage signal. It is sufficient to detect whether the voltage signal is equal to or lower than a first predetermined voltage value or equal to or higher than a second predetermined voltage value compared to the power supply voltage.
[0060]
Specifically, the detection can be performed by configuring a comparator or the like that uses the first and second predetermined voltage values as offset voltages. In this case, in order to reliably control the first or second PMOS transistor to be non-conductive by the output signal of the comparator or the like, it is necessary to control the signal level of the output signal at the higher voltage level of the power supply voltage and the voltage signal input to the input/output terminal. Therefore, the first PMOS transistor becomes non-conductive when the voltage signal is equal to or higher than the output inversion voltage set in the comparator or the like, and includes a higher voltage region than the power supply voltage. Therefore, it is preferable that the comparator or the like that outputs a signal that makes the first PMOS transistor non-conductive is driven by a voltage signal. Conversely, the second PMOS transistor becomes non-conductive when the voltage signal is equal to or lower than the output inversion voltage set in the comparator or the like, and includes a lower voltage region than the power supply voltage. Therefore, it is preferable that the comparator or the like that outputs a signal that makes the second PMOS transistor non-conductive is driven by the power supply voltage.
[0061]
(Note 1) In an input/output buffer circuit in which a voltage signal having a voltage level higher than the power supply voltage of the circuit itself is directly input to an input/output terminal,
The N-well potential of a PMOS transistor to which the voltage signal is applied at the drain terminal is
In a first region where the voltage signal is equal to or lower than a first predetermined voltage value compared to the power supply voltage,
In a second region where the voltage signal is equal to or greater than a second predetermined voltage value compared to the power supply voltage,
an N-well potential control unit that sets the voltage signal to the power supply voltage or the voltage signal in a third region where the voltage signal is a voltage sandwiched between the first and second regions;
(Additional Note 2) The N-well potential control unit includes:
a first PMOS transistor having a source terminal connected to the power supply voltage and a drain terminal and a back gate terminal connected to the N-well;
a second PMOS transistor having a source terminal connected to the input/output terminal, a drain terminal and a back gate terminal connected to the N-well, and a gate terminal connected to the power supply voltage;
a PMOS transistor control unit that sets the second predetermined voltage value as a threshold voltage value of the first PMOS transistor, and makes the first PMOS transistor conductive in the first and third regions and makes the first PMOS transistor non-conductive in the second region.
(Additional Note 3) The PMOS transistor control unit is
an NMOS transistor having a source terminal connected to the gate terminal of the first PMOS transistor, a drain terminal connected to the input/output terminal, and a gate terminal to which a predetermined voltage lower than the power supply voltage is applied;
and a third PMOS transistor having a source terminal connected to the input/output terminal, a drain terminal connected to a gate terminal of the first PMOS transistor, a gate terminal connected to the power supply voltage, and a back gate terminal connected to the N-well.
(Supplementary Note 4) The input/output buffer circuit according to Supplementary Note 3, wherein the predetermined voltage utilizes one of a plurality of power supply systems.
(Additional Note 5) The PMOS transistor control unit is
an NMOS transistor having a drain terminal connected to the input/output terminal;
a first voltage step-down unit that steps down a voltage signal from a source terminal of the NMOS transistor and inputs the step-down voltage to a gate terminal of a first PMOS transistor;
and a third PMOS transistor having a source terminal connected to the input/output terminal, a drain terminal connected to a gate terminal of the first PMOS transistor, a gate terminal connected to the power supply voltage, and a back gate terminal connected to the N-well.
(Additional Note 6) The N-well potential control unit includes:
a first PMOS transistor having a source terminal connected to the power supply voltage, a drain terminal and a back gate terminal connected to the N-well, and a gate terminal connected to the input/output terminal;
a second PMOS transistor having a source terminal connected to the input/output terminal and a drain terminal and a back gate terminal connected to the N-well;
a PMOS transistor control unit that sets the first predetermined voltage value as a threshold voltage value of the second PMOS transistor, makes the second PMOS transistor non-conductive in the first region, and makes the second PMOS transistor conductive in the second and third regions.
(Additional Note 7) The PMOS transistor control unit is
an NMOS transistor having a source terminal connected to the gate terminal of the second PMOS transistor, a drain terminal connected to the power supply voltage, and a gate terminal to which the voltage signal or a predetermined voltage lower than the voltage signal is applied;
and a third PMOS transistor having a source terminal connected to the power supply voltage, a drain terminal connected to a gate terminal of the second PMOS transistor, a gate terminal connected to the input/output terminal, and a back gate terminal connected to the N-well.
(Additional Note 8) The PMOS transistor control unit includes:
an NMOS transistor having a drain terminal connected to the power supply voltage;
a first voltage step-down unit that steps down a voltage signal from a source terminal of the NMOS transistor and inputs the voltage signal to a gate terminal of a second PMOS transistor;
and a third PMOS transistor having a source terminal connected to the power supply voltage, a drain terminal connected to a gate terminal of the second PMOS transistor, a gate terminal connected to the input/output terminal, and a back gate terminal connected to the N-well.
(Supplementary Note 9) The input/output buffer circuit according to Supplementary Note 3 or 7, further comprising a second voltage step-down section that steps down a voltage level of the power supply voltage or the voltage signal and outputs the predetermined voltage.
(Supplementary Note 10) The input/output buffer circuit according to at least one of Supplementary Note 5, 8, or 9, wherein the first or second voltage step-down unit utilizes a voltage step-down using a resistive element.
(Supplementary Note 11) The input/output buffer circuit according to at least one of Supplementary Note 5, 8, and 9, wherein the first or second voltage drop section utilizes a voltage drop at a junction.
[0062]
Effect of the Invention
According to the present invention, in an input/output buffer circuit including a PMOS transistor, even if a voltage signal with a voltage level different from the power supply voltage of the input/output terminal is directly input, the N-well potential can be reliably biased, and it is possible to provide an input/output buffer circuit equipped with an N-well potential control section that prevents the N-well potential from being in a floating state in all voltage level ranges.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an N-well potential control unit in an input/output buffer circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a first specific example of an N-well potential control unit.
FIG. 3 is a circuit diagram showing a second specific example of an N-well potential control unit.
FIG. 4 is a circuit diagram showing a third specific example of an N-well potential control unit.
FIG. 5 is a circuit diagram showing a fourth specific example of an N-well potential control unit.
FIG. 6 is a circuit diagram showing a fifth specific example of an N-well potential control unit.
7 is a waveform diagram showing how a well potential is switched by an N-well potential control unit according to the embodiment. FIG.
FIG. 8 is a waveform diagram showing how the well potential is switched by an N-well potential control unit according to another embodiment.
FIG. 9 is a circuit block diagram showing an input/output buffer circuit.
FIG. 10 is a circuit diagram showing an N-well potential control section of the prior art.
[Explanation of symbols]
1 Input/Output Buffer Circuit 11 Second Voltage Step-Down Unit 12 First Voltage Step-Down Unit A1, A11, A12, A13, A14, A15, A100
N-well potential control units D1, D2 Diode group NM1 NMOS transistor NW N-well PAD Input/output terminal PM1 First PMOS transistor PM2 Second PMOS transistor PM3 Third PMOS transistor R1, R2, R3, R4 Resistor element VDD1 Power supply voltage VDD2 Second power supply voltage

Claims (5)

In an input/output buffer circuit in which a voltage signal having a voltage level higher than the power supply voltage of the circuit itself is directly input to an input/output terminal,
The N-well potential of a PMOS transistor to which the voltage signal is applied at the drain terminal is
In a first region where the voltage signal is equal to or lower than a first predetermined voltage value compared to the power supply voltage,
In a second region where the voltage signal is equal to or greater than a second predetermined voltage value compared to the power supply voltage,
an N-well potential control unit that sets the voltage signal to the power supply voltage or the voltage signal in a third region where the voltage signal is a voltage between the first and second regions ;
The N-well potential control unit includes:
a first PMOS transistor having a source terminal connected to the power supply voltage and a drain terminal and a back gate terminal connected to the N-well;
a second PMOS transistor having a source terminal connected to the input/output terminal, a drain terminal and a back gate terminal connected to the N-well, and a gate terminal connected to the power supply voltage;
a PMOS transistor control unit that sets the second predetermined voltage value as a threshold voltage value of the second PMOS transistor, and makes the first PMOS transistor conductive in the first and third regions and makes the first PMOS transistor non-conductive in the second region . 2. The input/output buffer circuit according to claim 1, wherein the N-well potential control section fixes the N-well potential to the power supply voltage in the third region. The PMOS transistor control unit is
3. The input/output buffer circuit according to claim 1, further comprising: an NMOS transistor having a source terminal connected to the gate terminal of the first PMOS transistor, a drain terminal connected to the input/output terminal, and a gate terminal to which a predetermined voltage lower than the power supply voltage is applied; and a third PMOS transistor having a source terminal connected to the input/output terminal, a drain terminal connected to the gate terminal of the first PMOS transistor, a gate terminal connected to the power supply voltage , and a back gate terminal connected to the N-well. In an input/output buffer circuit in which a voltage signal having a voltage level higher than the power supply voltage of the circuit itself is directly input to an input/output terminal,
The N-well potential of a PMOS transistor to which the voltage signal is applied at the drain terminal is
In a first region where the voltage signal is equal to or lower than a first predetermined voltage value compared to the power supply voltage,
In a second region where the voltage signal is equal to or greater than a second predetermined voltage value compared to the power supply voltage,
an N-well potential control unit that sets the voltage signal to the power supply voltage or the voltage signal in a third region where the voltage signal is a voltage between the first and second regions;
The N-well potential control unit includes:
a first PMOS transistor having a source terminal connected to the power supply voltage, a drain terminal and a back gate terminal connected to the N-well, and a gate terminal connected to the input/output terminal;
a second PMOS transistor having a source terminal connected to the input/output terminal and a drain terminal and a back gate terminal connected to the N-well;
a PMOS transistor control unit that sets the first predetermined voltage value as a threshold voltage value of the first PMOS transistor, makes the second PMOS transistor non-conductive in the first region, and makes the second PMOS transistor conductive in the second and third regions. The PMOS transistor control unit is
an NMOS transistor having a source terminal connected to the gate terminal of the second PMOS transistor, a drain terminal connected to the power supply voltage, and a gate terminal to which the voltage signal or a predetermined voltage lower than the voltage signal is applied;
5. The input/output buffer circuit according to claim 4, further comprising: a third PMOS transistor having a source terminal connected to the power supply voltage, a drain terminal connected to a gate terminal of the second PMOS transistor, a gate terminal connected to the input/output terminal, and a back gate terminal connected to the N -well.

Images