JP4151783B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective for use in an A / D conversion circuit using a chopper type voltage comparison circuit.
[0002]
[Prior art]
The chopper type voltage comparator first stores the input signal (or reference voltage) as a charge in the capacitance of the input unit, and then applies the reference voltage (or other input signal) to the input unit to apply the input signal and the reference voltage (or A voltage comparison is performed by amplifying the difference from other input signals. At this time, if the reset is performed by short-circuiting the input terminal and output terminal of the amplifier during charge accumulation, the influence of the offset voltage of the amplifier due to manufacturing variation or the like can be removed, so that the voltage used in the A / D converter Often used as a comparator. It is known that a chopper type voltage comparator is effective for high-speed operation by connecting multiple pairs of capacitors and amplifiers as in Non-Patent Document 1 in order to obtain a necessary gain to obtain a required resolution. ing.
[0003]
As the amplifier used for the chopper type voltage comparator, in addition to the differential amplifier shown on page 313 of Non-Patent Document 1, an inverter circuit used in a digital circuit is used to simplify the circuit and reduce the area. Often used as. Non-Patent Document 2 describes an offset error study of a chopper type voltage comparator using an inverter circuit.
[0004]
In the capacitor array type digital / analog conversion circuit, a reset field effect transistor provided between the inverting input terminal and the output terminal is turned on by an undershoot or overshoot generated at the output terminal of the operational amplifier circuit. It is found that an offset occurs due to the leakage current generated between the source and drain, and in order to prevent this, two field effect transistors are connected in series between the inverting input terminal and the output terminal, and the connection point Patent Document 1 discloses that a field effect transistor is provided between a constant voltage and a constant voltage.
[Non-Patent Document 1]
David A. Johns, Ken Martin, "Analog Integrated Circuit Design," John Wiley & Sons, Inc., Chapter 7
[Non-Patent Document 2]
Toshiro Tsukada, Eigame Imaizumi, Tatsuharu Matsuura “Offset Error Study of CMOS Chopper Type Voltage Comparator” IEICE Transactions C-II Vol.J77-C-II No.11 pp516-524 November 1994
[Patent Document 1]
JP 11-298329 A
[0005]
[Problems to be solved by the invention]
When using a circuit that handles a high voltage internally, such as a flash memory, it is necessary to keep the element breakdown voltage of a MOS transistor or the like high. In order to increase the element breakdown voltage, it is generally necessary to increase the element size and increase the threshold voltage of the MOS transistor, and the performance of the MOS transistor decreases. That is, a MOS transistor that prioritizes element breakdown voltage has a high threshold voltage Vth and a low current driving capability (transconductance gm). A voltage comparator using such an element has a high operable lower power supply voltage limited by the threshold voltage Vth, and the operation speed can be kept low even when it operates.
[0006]
The mainstream of LSI operating power supply voltage tends to decrease due to miniaturization of the manufacturing process. The problem of lowering the lower limit power supply voltage may be solved if a MOSFET (low VthMOS) with a lowered threshold voltage Vth can be used. However, as shown in the characteristic diagram of FIG. 12, the low Vth MOSFET generates a relatively large leakage current even when the gate-source voltage Vgs = 0. FIG. 13A is a measurement circuit diagram thereof.
[0007]
Therefore, in the chopper type voltage comparator of the successive approximation A / D converter as shown in FIG. 14, the inputs and outputs of the amplifier circuits A1, A2, and A3 are short-circuited as shown in FIG. Then, the input signal Vin is supplied, and the capacitors Cin, C1 and C2 provided at the inputs of the respective amplifier circuits A1 to A3 hold charges corresponding to variations in the input signal Vin and the logic threshold voltages of A2 and A3. In order to compare the magnitude of the input signal Vin with respect to a plurality of reference voltages Vref, when a circuit is configured using a low Vth MOSFET as shown in FIG. 14B, 0 V is applied to the gate. As a result, the leakage current leak flowing through the MOSFET in the off state causes the capacitors Cin, C1, and C2 to lose their charge, resulting in an error in the subsequent comparison operation.
[0008]
In a semiconductor integrated circuit device such as a one-chip microcomputer equipped with a flash memory and an A / D converter, a high threshold voltage with a high withstand voltage used for the nonvolatile memory cell and its write and erase circuits. 12 and a low threshold voltage MOSFET used for a circuit element such as a control circuit, as shown in the characteristic diagram of FIG. 12, substantial leakage occurs even when the gate-source voltage Vgs = 0. If a standard Vth (threshold voltage) MOSFET that does not generate current is used, the manufacturing process of the semiconductor integrated circuit device becomes complicated only for that reason, resulting in high cost.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device including a chopper type voltage comparison circuit and a local DAC that enable a highly accurate voltage comparison operation with a simple configuration. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a chopper type voltage comparison circuit and a local DAC that realize high-speed operation with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. First and second switch MOSFETs that are on / off controlled by the first voltage and the ground potential of the circuit between the input terminal and the output terminal of the first inverter circuit that operates based on the first voltage and the ground potential of the circuit. And a third switch MOSFET that is turned on when the first and second switch MOSFETs are controlled to be turned off between the interconnection point of the series circuit and the first voltage. In the state where the first and second switch MOSFETs are turned on, an input signal is taken into the input of the first inverter circuit via a capacitor to constitute a chopper type amplifier circuit.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a circuit diagram of an embodiment of a chopper type voltage comparison circuit according to the present invention. The input signal Vin and the reference voltage Vref are selectively supplied to one electrode of the capacitor Cin as an input capacitance via the switches S1 and S2. The other electrode of the capacitor Cin is connected to the input terminal of the CMOS inverter circuit A1 that constitutes the amplifier circuit. The output terminal of the inverter circuit A1 is connected to one electrode of a capacitor C1 as a coupling capacitor. The other electrode of the capacitor C1 is connected to the input terminal of the CMOS inverter circuit A2 that constitutes the amplifier circuit. The output terminal of the inverter circuit A2 is connected to one electrode of a capacitor C2 as a coupling capacitor. The other electrode of the capacitor C2 is connected to the input terminal of a similar CMOS inverter circuit A3.
[0012]
In this embodiment, when a low threshold voltage MOSFET is used as a reset switch for short-circuiting the input terminal and the output terminal of the inverter circuit A1 constituting the amplifier circuit, it is generated between the source and the drain. In order to prevent a part of the electric charge held in the input capacitance Cin from being lost due to a leakage current (so-called threshold leakage current) leak in the off state, N-channel MOSFETs Q1 and Q2 connected in series are Used. A P-channel MOSFET Q5 is provided between the interconnection point of these MOSFETs Q1 and Q2 and the power supply voltage Vcc. Although not particularly limited, the P-channel MOSFET Q5 is a high threshold voltage (high withstand voltage) MOSFET.
[0013]
A switch control signal φ1 is supplied to the gates of the MOSFETs Q1, Q2 and Q3, Q4, and a switch control signal φ2 is supplied to the gate of the MOSFET Q5. These switch control signals φ1 and φ2 are set to a high level such as the power supply voltage Vcc and a low level such as the circuit ground potential 0V.
[0014]
As shown in FIG. 2, the switch control signals φ1 and φ2 are set to a high level, the N-channel MOSFETs Q1, Q2, Q3, and Q4 are turned on, the P-channel MOSFET Q5 is turned off, and the switch S1 is turned on. A signal Vin is supplied. Thus, the logic threshold voltage V formed by short-circuiting the input and output of the inverter circuit A1. _LT The signal charge corresponding to the input signal Vin with reference to is taken into the input capacitor Cin.
[0015]
When the switch S1 is turned off, the switch control signal φ1 is set to the low level, the MOSFETs Q1, Q2, Q3 and Q4 are turned off, the switch S2 is turned on and the reference voltage Vref is supplied. The difference voltage Vref−Vin between the input signal Vin and the input signal Vin is the logic threshold voltage V _TL Compare the magnitude (positive and negative). By amplifying the output signal of the inverter circuit by the inverter circuits A2 and A3, a high-level / low-level voltage comparison output can be obtained.
[0016]
In this embodiment, when the reset is completed and the comparison operation is started as shown in FIG. 2, the MOSFET Q5 for fixing the potential at the interconnection point between the switch MOSFETs Q1 and Q2 is turned on before the reset switches MOSFETQ1 and Q2 are turned off. Then, charge flows into the input capacitor Cin that should hold the logic threshold voltage of the first-stage inverter circuit A1, and an error occurs in the subsequent comparison operation. In order to avoid this problem, first, the reset switches MOSFETs Q1 and Q2 are turned off by the control signal φ1, and then the switch MOSFET Q5 for fixing the potential between the reset switches MOSFETs Q1 and Q2 is turned on by the control signal φ2.
[0017]
In the embodiment of FIG. 1, two MOSFETs Q1 and Q2 are connected in series to a reset switch of a first stage inverter circuit (amplifier circuit) A1 using a MOSFET having a low threshold voltage Vth, and when the reset switch is off, MOSFETs Q1 and Q2 are connected. The intermediate node of the switch, which is the interconnection point, is connected to the power supply Vcc via the P-channel MOSFET Q5. In the configuration using a single switch MOSFET as shown in FIG. 12, under the condition that the output of the first-stage inverter circuit A1 is 0V, the leak current leak is transferred from the input capacitance Cin via the reset switch MOSFET to the inverter circuit. A leakage voltage comparison error occurs at the output of A1.
[0018]
In the configuration of the embodiment of FIG. 1, even when the output of the first-stage inverter circuit A1 is 0V, the leakage current leak is supplied from the power source Vcc via the MOSFET Q3, and the leakage current leak from the input capacitance Cin does not occur. The accuracy of the comparison operation is not degraded. However, when the input terminal of the inverter circuit A1 is near 0V, the leak current leak generated in the MOSFET Q1 flows into the input capacitance Cin and causes a determination error. Therefore, it is necessary to always satisfy the condition of the input signal that can suppress the leakage current of the low threshold voltage MOSFET Q1 used for the reset switch to be sufficiently small.
[0019]
In other words, referring to the characteristic diagram of FIG. 12, if a negative bias voltage such as −Vc is supplied between the gate and the source, the leakage current is reduced to a level that does not cause a problem substantially equivalent to that of a standard Vth MOSFET. be able to. In order to operate the low-th MOSFET at the operating point c at its Id-Vgs, as shown in FIG. 13B, a positive voltage such as the voltage Vc is applied to the source S with respect to the substrate B of the MOSFET. Supply it.
[0020]
In FIG. 1, assuming that the condition that the leakage current leak of the low Vth MOSFET Q1 is sufficiently small as described above is expressed by the gate-source voltage Vgs <−Va <0V, the input voltage of the inverter circuit A1 is always Va. As long as it is kept higher. The logic threshold voltage of the inverter circuit A1 is V _TL V _TL + Vref −Vin>Va> 0 so that V> 0 always holds _TL By adjusting the value of V and the control of Vref, it is possible to prevent deterioration in accuracy due to charge loss of the input section capacitance Cin.
[0021]
The switch S1 is turned on, and the logic threshold voltage is applied to the input capacitor Cin. _TL When the input signal Vin is supplied with reference to the input capacitor Vin, the input capacitance Cin has Vin−V. _TL Is maintained. When the reference voltage Vref is supplied by switching from the switch S1 to the switch S2, Vin−Vref> V _TL When the reference voltage as described above is supplied, the potential Va of the input terminal of the inverter circuit A1 becomes Va <0V, and a large leak current flows through the MOSFET Q1.
[0022]
Specifically, when the logic threshold voltage of the inverter circuit operating at the power supply voltage Vcc of 3V is 1.5V and the input signal Vin of 3V is supplied, the input capacitor holds the voltage of 1.5V. When the input switch is switched and a reference voltage Vref of 1.5 V or less is supplied, the potential of the input terminal of the inverter circuit A1 becomes 0 V or less, and a leak current similar to that of the MOSFET Q2 is generated. It will be done.
[0023]
However, when used in an A / D conversion circuit, a constant voltage is formed from the power supply voltage Vcc, and is divided to form a reference voltage Vref. Therefore, the reference voltage (digital conversion signal selected first) is selected as the voltage comparison order. The most significant bit) is generally selected to correspond to the midpoint voltage of the constant voltage. Therefore, the logic threshold voltage V of the inverter circuit A1. _TL Is set to Vcc / 2, the inevitably the midpoint voltage Vref <V _TL Therefore, it is not difficult to satisfy the above condition by limiting the positive maximum value of the input signal Vin so as not to exceed Vcc, and the A / D conversion operation is not particularly limited. It does not affect.
[0024]
FIG. 3 is a circuit diagram showing another embodiment of the chopper type voltage comparison circuit according to the present invention. In this embodiment, the interstage capacitors C1 and C2 and the reset switch MOSFET Q3 that short-circuits the input and output of the inverter circuit A2 are omitted. Other configurations are the same as those of the embodiment of FIG.
[0025]
That is, the input signal Vin and the reference voltage Vref are selectively supplied to one electrode of the input capacitor Cin via the switches S1 and S2, and the other electrode of the input capacitor Cin is the first-stage CMOS inverter constituting the amplifier circuit. Connected to the input terminal of the circuit A1. The output terminal of the inverter circuit A1 is connected to the input terminal of the CMOS inverter circuit A2 constituting the amplifier circuit. The output terminal of the inverter circuit A2 is connected to the input terminal of a similar CMOS inverter circuit A3. Further, reset switch MOSFETs Q1, Q2 and switch MOSFET Q5 similar to those in the embodiment of FIG. 1 are provided between the input terminal and the output terminal of the inverter circuit A1, and the input terminal and the output terminal of the inverter circuit A3 are connected. A reset switch MOSFET Q4 is provided between them.
[0026]
By eliminating the interstage capacitance as described above, it is not necessary to consider the accuracy degradation due to the leakage current as described above, but it is possible to accurately match the logic threshold voltages of the adjacent inverter circuits A1 and A2 and A2 and A3. Necessary. In order to match the logic threshold voltage, it is effective to use a layout technique such as a common centroid with a MOS having a relatively large element size as shown in FIG. In order to reduce the influence of the error of the logic threshold voltage, it is effective to increase the voltage gain of the first-stage inverter circuit A1.
[0027]
In FIG. 4, four M1, two M2, and two M5 are formed in the P-type well P-WELL as N-channel MOSFETs having a relatively large channel width, and the channel width is formed in the N-type well N-WELL. As a P-channel MOSFET with a large length, four M2, two M4, and two M6 are formed. The N-channel MOSFETs M1 to M5 have the same size, and a total of eight are linearly arranged in the channel length direction. The P-channel MOSFETs M2 to M6 have the same size, and a total of 8 are linearly arranged in the channel length direction. The P-channel MOSFET is formed larger than the N-channel MOSFET so that the conductance characteristic is the same as that of the N-channel MOSFET so that the logic threshold voltage is approximately ½ of the operating voltage.
[0028]
The one N-channel MOSFET and the P-channel MOSFET are paired so that the gate electrodes G are linearly arranged. That is, they are arranged linearly in the channel width direction of the MOSFET. Although not particularly limited, a dummy MOSFET (dummy NMOS, dummy PMOS) is provided at an end portion in the channel length direction of the MOSFET in order to prevent influence with other circuits. In order to accurately match the logic threshold voltages of the first-stage inverter circuit A1 and the next-stage inverter circuit A2, the end MOSFETs constituting part of the first-stage inverter circuit A1 are provided with dummy NMOS and dummy PMOS as described above. It is done.
[0029]
On the other hand, the dummy MOSFET is not provided in the end MOSFET constituting the inverter circuit A3 unlike the first-stage inverter circuit. This is because the inverter circuit A3 is supplied with the input signal supplied to its input amplified by the inverter circuits A1 and A2, and has a relatively large signal amplitude, so that the logic threshold voltage of the inverter circuits A3 and A2 This is because the difference does not significantly affect the accuracy of the voltage comparison operation.
[0030]
As shown in FIG. 4 as an equivalent circuit, the first stage inverter circuit is composed of four N-channel MOSFETs M1 and four P-channel MOSFETs M2, and has a large voltage gain. That is, the second-stage inverter circuit is composed of two N-channel MOSFETs M3 and M4 and two P-channel MOSFETs M4, and the third-stage inverter circuit is composed of two N-channel MOSFETs M5 and two P-channel MOSFETs. Since the channel MOSFET M6 is used, the first-stage inverter circuit is twice as large in terms of element size.
[0031]
In FIG. 4, although the wiring layout is omitted, as shown in the figure, in the first stage inverter circuit, the gates G, drains D and sources S of the four MOSFETs M1 and M2 are connected to each other, and the gate G is input. Terminal IN and drain D are output terminals and are connected to the gate G of the next-stage inverter circuit. The ground potential of the circuit is applied to the source S of the N-channel MOSFET M1, and the power supply voltage is applied to the source S of the P-channel MOSFET M2. Also in the second-stage and third-stage inverter circuits, the gates G, drains D, and sources S of the two MOSFETs M3 and M4, M5, and M6 are connected to each other. The ground potential of the circuit is applied to the sources S of the N-channel MOSFETs M3 and M5, and the power supply voltage is applied to the sources S of the P-channel MOSFETs M4 and M6. The output terminal of the second stage inverter circuit is connected to the input terminal of the third stage inverter circuit, and the third stage inverter circuit is used as the output terminal OUT.
[0032]
When removing the interstage capacitors C1 and C2, it is also necessary to remove the reset switch MOSFET Q3 of the second stage inverter circuit A2. Second stage inverter circuit A2 If the reset switch MOSFET Q3 remains, the second stage inverter circuit when the logic threshold voltage of the first stage inverter circuit A1 to be held in the input capacitor Cin at the time of reset is slightly different from the logic threshold voltage. Influenced by A2. At the time of comparison, the logic threshold voltage of the first stage inverter circuit A1 is not affected by the threshold voltage of the second stage inverter circuit A2, so this difference causes a comparison error. Therefore, as described above, the second-stage inverter circuit A2 reset switch MOSFET Q3 is omitted, and the influence can be eliminated even if the logic-threshold voltage of the second-stage inverter circuit A2 is different.
[0033]
The presence / absence of the reset switch MOSFET Q4 in the third-stage (and subsequent) inverter circuit A3 does not directly cause an error in the comparator like the logic threshold voltage of the inverter circuit A2. However, generally, a finite resistance (parasitic resistance) exists in the power supply / ground wiring of the inverter circuit, and a voltage drop (IR drop) corresponding to the current consumption occurs.
[0034]
At the time of resetting, a through current flows through the first-stage inverter circuit A1 and the second-stage inverter circuit A2, and also at the time of comparison, when the input voltage Vin requiring a high-precision comparison operation is close to the comparison voltage Vref, the through-current Flows. When the difference between Vin and Vref to be compared is sufficiently small, a through current flows through the first-stage inverter circuit A1 and the second-stage inverter circuit A2 as well as the third-stage inverter circuit A3. When the through current flows in the circuit A3, the operation conditions at the time of reset and comparison are more accurately matched, so the accuracy of the comparison result is also accurate.
[0035]
A reset switch MOSFET Q4 is provided in the third stage inverter circuit A3 so that a required through current flows through the third stage inverter circuit A3 even if the logic threshold voltages of the first stage inverter circuit A1 and the second stage inverter circuit A2 are slightly shifted. Thus, it is beneficial to perform the comparison operation with high accuracy by allowing the through current to flow as described above.
[0036]
FIG. 5 shows an element cross-sectional view of one embodiment of the interstage capacitance of the embodiment of FIG. For the interstage capacitors C1 and C2, a capacitive element using an upper electrode, a lower electrode, and an insulating film provided therebetween as a dielectric is used. However, the parasitic capacitance Cs is always connected between the well and the substrate on the lower electrode side. FIG. 6 shows a load circuit of the inverter circuit in consideration of the influence of the parasitic capacitance (bottom capacitance). The load capacity of the first stage inverter circuit A1 is obtained by adding the bottom capacity Cs in parallel to the series capacity of the input capacity Cg and the interstage capacity C1 of the next stage inverter circuit A2.
[0037]
Since the gain of the signal path transmitted from the output of the inverter circuit A1 to the input of the inverter circuit A2 is expressed by C1 / (C1 + Cg), it is general that C1 is sufficiently large with respect to Cg so that the gain is not reduced too much. It is. In this case, since the combined capacitance value of the series circuit of C1 and Cg is almost equal to Cg, the load capacitance of the inverter circuit A1 is approximately expressed as Cg + Cs. Therefore, if the interstage capacitances C1 and C2 are removed under these conditions, the load capacity of the inverter circuits A1 and A2 is always reduced, and high-speed operation is possible. For example, when C1 is 5 times Cg and Cs is about 20% of C1, the values of Cg and Cs are almost equal. Therefore, the speed can be increased about twice by removing the interstage capacitance.
[0038]
When a CMOS switch is configured using a MOSFET having a high breakdown voltage and a high threshold voltage, the on-resistance is remarkably increased. The increase in the on-resistance deteriorates the settling time of the input signal and the settling time of the DAC that forms the reference voltage, resulting in deterioration of absolute accuracy. That is, when a low voltage operation is performed using a high breakdown voltage (high Vth) MOS, not only the reset switch MOSFET of the chopper type voltage comparison circuit but also the switches S1 and S2 for switching between the input signal and the reference voltage become a problem. In particular, when the threshold voltage Vth rises due to low temperature operation in addition to process variations, the on-resistance of the switch for an intermediate signal in the vicinity of 1/2 Vcc becomes very high.
[0039]
In a known CMOS switch configured by connecting an N-channel MOSFET and a P-channel MOSFET in parallel, the back gates of the N-channel MOSFET and the P-channel MOSFET are normally connected to the ground / power supply Vcc, respectively. Here, when the input signal is about 1/2 Vcc, the effective threshold voltage Vth of the N-channel MOSFET and the PMOSFET rises due to the substrate bias effect. Under the condition that the original true threshold voltage Vth0 is high (process variation, low temperature), the on-resistance is extremely increased as the power supply voltage Vcc is lowered. As one means for avoiding an increase in on-resistance, it is conceivable to use a low Vth MOS for the switch. However, a leakage current generated under conditions where Vth is low (process variation, high temperature) deteriorates conversion accuracy. In addition, the switches S1 and S2 cannot adopt the circuit configuration such as the reset MOSFETs Q1, Q2 and Q5.
[0040]
FIG. 7 shows a circuit diagram of an embodiment of the CMOS switch used in the present invention. In this embodiment, a CMOS switch is configured by connecting in parallel a high breakdown voltage and high threshold voltage P-channel MOSFET Q6 and an N-channel MOSFET Q7. The voltage of the input signal IN is transmitted to the substrate (channel) of the N-channel MOSFET Q7 through the N-channel MOSFET Q8 in order to reduce the resistance value in the on state.
[0041]
In the CMOS switch of this embodiment, a positive potential corresponding to the input signal IN is supplied to the substrate (P-WELL) of the N-channel MOSFET Q7 in the on state, and the effective threshold voltage Vth is lowered by the substrate bias effect. Thus, the on-resistance is reduced. Further, in order to prevent leakage of current when the CMOS switch is turned off, the N channel MOSFET Q9 controls the potential of the substrate (P-WELL) of the N channel MOSFET Q7 to 0V. As a result, the effective threshold voltage of MOSFET Q7 in the off state becomes larger than that in the on state due to the substrate potential, and the threshold leak current flowing between the source and drain in the off state is greatly reduced. Can do.
[0042]
The inventor of the present application uses a MOSFET having a large on-resistance value of about 163 KΩ in a state where a bias voltage such as 0 V is supplied to the substrate of the MOSFET Q7 of the CMOS switch as in the conventional CMOS switch. It has been confirmed that when the MOSFET Q8 is added to have the same voltage as the input signal to be transmitted, a significant on-resistance value can be reduced to about 2.3 KΩ.
[0043]
In order to switch the MOSFETs Q8 and Q9 as described above in accordance with the on / off state of the CMOS switch as described above, the gate of the MOSFET Q8 is supplied to the gate of the N-channel MOSFET Q7 of the CMOS switch. A non-inverted switch control signal Vsw is supplied, and an inverted switch control signal / Vsw supplied to the gate of the P-channel MOSFET Q6 of the CMOS switch is supplied to the gate of the N-channel MOSFET Q9.
[0044]
In this embodiment, by using a substrate bias control type circuit as shown in FIG. 7 as the input / reference voltage changeover switches S1 and S2 of the chopper type voltage comparison circuit, the influence of such an increase in on-resistance is mitigated. . In the embodiment circuit of FIG. 7, the back gate (substrate) of the N-channel MOSFET Q7 constituting the CMOS analog switch is biased by the input signal by the switch MOSFET Q8 when the switch is on, and the switch MOSFET Q9 when the switch is off. Connect to ground with. As a result, an increase in on-resistance due to the substrate bias effect can be avoided without increasing the off-state leakage current.
[0045]
The embodiment circuit of FIG. 7 can be realized by an n-substrate / P-WELL process as shown in FIG. 5 or a triple well (deep well) which has become common in recent years. In the p-substrate / N-WELL process, the P-channel MOSFET 6 of the CMOS switch can be made a substrate bias control type, and in the triple well process, both the P-channel MOSFET Q6 and the N-channel MOSFET Q7 of the CMOS switch are of the substrate bias control type. I can do it.
[0046]
The increase in the on-resistance of the CMOS analog switch becomes a problem in the local DAC which is an important circuit element of the successive approximation A / D converter together with the chopper type voltage comparison circuit. A resistor string type DAC generally used as a local DAC is 2 for an n-bit DAC. ⁿ Since the unit resistors are connected in series, and the voltage at each node is selected and output by the switch, the switch for selecting the voltage near 1/2 Vcc is the input / reference voltage changeover switch of the previous chopper type voltage comparison circuit and The exact same problem occurs. Although it is possible to solve in principle by making all the switches with on-resistance problems a substrate bias control type, the back gate to be controlled (P-WELL in FIG. 7) needs to be separated by each switch. When applied to a large number of switches, the occupied area increases drastically and is not practical in terms of cost.
[0047]
Since the CMOS switch of this embodiment controls the substrate (P-WELL) of the N-channel MOSFETs Q7 and Q8 to 0V in the off state, the output voltage VOUT can be used in the range of 0 to AVCC (analog circuit power supply voltage). is there. However, it is necessary to separate the P-WELL from other N-channel MOSFETs, and the layout size is increased. For example, if an n-bit DAC is used as described above, 2 ⁿ Unit resistors are connected in series, and the voltage at each node is selected and output by a switch. Of these, a switch that selects a voltage near 1/2 Vcc is the input / reference voltage of the previous chopper type voltage comparison circuit. Since the same problem as that of the changeover switch occurs, it is limitedly used to select the intermediate reference voltage Vref so as to prevent an increase in the occupied area to the minimum necessary.
[0048]
FIG. 8 shows a circuit diagram of another embodiment of the CMOS switch used in the present invention. In the CMOS switch of this embodiment, a local DAC switch as will be described later has a two-stage serial configuration of a lower bit side and an upper bit side, and the on-resistance value among those controlled by the lower bit decoder becomes a problem. Used for. That is, when a CMOS switch is configured with a MOSFET having a high breakdown voltage and a high Vth as described above, the on-resistance value becomes about 210 KΩ, but the on-resistance value is reduced to about 4 by using the N-channel MOSFET Q11 having a low Vth. It can be reduced to 4 KΩ.
[0049]
However, if the low Vth MOSFET Q11 is used as described above, the leakage current when it is turned off increases. Therefore, among those provided at each node of the resistor string, for example, it is used for selecting an intermediate voltage in the vicinity of 0.7V to 2.2V. When applied to a CMOS switch that selects such an intermediate voltage, the source potential with respect to the substrate (channel) becomes 0.7 V to 2.2 V as described above, and the effective threshold voltage Vth increases due to the substrate effect. , Leakage current can be reduced.
[0050]
9 and 10 are circuit diagrams showing an embodiment of the local DAC according to the present invention. FIG. 9 shows a circuit diagram of the left half of the local DAC, and FIG. 10 shows a circuit diagram of the right half of the local DAC. This local DAC is combined with the chopper type voltage comparison circuit to constitute a successive approximation type A / D converter.
[0051]
The local DAC is a resistor string type DAC, and if it is an 8-bit DAC, it is 2 ⁸ = 256 unit resistors are connected in series between the constant voltage Vr and the ground potential avss of the circuit, and 256 voltages at each node are selected by a switch and output. In this embodiment, the upper bit side is 3 bits and the lower bit side is 5 bits, and one of the 256 voltages is selected. Of the 256 nodes, 32 series resistors are divided into 8 groups and selected by switches SW1 to SW8 controlled by the higher 3 bits of decoding output.
[0052]
32 nodes of each of the 8 groups are selected by a switch controlled by a middle 5-bit decode output. In this embodiment, as shown in FIG. 10, four intermediate potentials are taken out and selected by the lower 2-bit decode output. That is, the 256 reference voltages are formed, and the first reference voltage supplied to the chopper type voltage comparison circuit by selecting each of the 256 potentials by the upper bit 3 bit decode output and the middle 5 bit decode output. Output as Vref1. Then, the potentials of the four nodes in the above 256 are selected by the lower 2-bit decode output and output as the second reference voltage Vref2 supplied to the other chopper type voltage comparison circuit.
[0053]
By making the capacitance ratio of the input capacitance Cin to which the second reference voltage Vref2 is input with the input capacitance Cin to which the first reference voltage Vref1 is input four times, the input signal and the reference voltage Vref2 are each The signal voltage supplied to the chopper type voltage comparison circuit receiving the potential can be reduced to ¼, and the output results of the two chopper type voltage comparison circuits are combined to obtain a 10-bit A / D conversion output as a whole. be able to.
[0054]
In the local DAC of this embodiment, among the eight switches SW1 to SW8 corresponding to the upper 3-bit decode output, the analog switches as shown in FIG. The switches SW7 and SW8 for selecting are configured by P-channel MOSFETs, and the switches SW1 and SW2 for selecting low voltage are configured by N-channel MOSFETs. Although omitted in the figure, a low threshold voltage as shown in FIG. 8 is used to select an intermediate potential among CMOS switches that are switch-controlled by the lower bit and middle bit decode outputs. It is comprised by using this MOSFET.
[0055]
As described above, the low Vth MOS is used for selecting the intermediate potential among the CMOS switches that are switch-controlled by the lower bit side switch and the middle bit decode output. However, in this configuration, the low Vth MOS is always 1 / Since a voltage in the vicinity of 2 Vr is applied to the source / drain, the leakage current at the off time does not matter.
[0056]
FIG. 11 is a block diagram showing an embodiment of a single chip microcomputer to which the present invention is applied. Although not particularly limited, the single-chip microcomputer MCU of this embodiment is incorporated in an automobile or an industrial machine and functions as its control device.
[0057]
The microcomputer MCU shown in the figure is a central processing unit CPU of a so-called stored program system. Although not particularly limited, the central processing unit CPU is coupled with a flash memory FEEPROM, a random access memory RAM, an analog / digital conversion circuit ADC, a watchdog timer WDT, a timer circuit TIM, and a serial communication interface SCI via an internal bus IBUS. The A predetermined clock signal CLK is supplied from the clock generation circuit CLKG to each part of the microcomputer MCU including the central processing unit CPU, and the microcomputer MCU further controls the operation of the clock generation circuit CLKG. CLKC and a power-on reset circuit POR for resetting each part of the microcomputer MCU to the initial state when the power is turned on.
[0058]
The watchdog timer WDT is supplied with the internal signal PR from the central processing unit CPU, and its output signal, that is, the abnormality detection signal TD is supplied to the clock controller CLKC. One input terminal of the clock generation circuit CLKG is coupled to one electrode of the crystal oscillator XTAL via the external terminal EXTAL, and the clock output signal CG of the clock controller CLKC is supplied to the other input terminal. The other electrode of the crystal oscillator XTAL is coupled to the clock controller CLKC via the external terminal XTAL.
[0059]
The power-on reset circuit POR is supplied with the power supply voltage VCC and the ground potential VSS, which are the operation power supply of the single-chip microcomputer MCU, via the external terminals VCC and VSS, respectively. It is supplied to the controller CLKC. The clock controller CLKC is further supplied with an output signal RSTP of the complete stop control register RSTP and an output signal RCMD of the mode control register RCMD from the central processing unit CPU. The output signal, that is, the normal reset signal RS is sent to the central processing unit CPU. It is supplied to each part of the microcomputer MCU.
[0060]
The central processing unit CPU performs step operations according to a user program stored in the flash memory FEEPROM, executes predetermined arithmetic processing, and controls and supervises each part of the microcomputer. In this embodiment, the central processing unit CPU includes a complete stop control register and a mode control register which can be written by an instruction, and output signals RSTP and RCMD are supplied to the clock controller CLKC as described above. Further, the internal signal PR indicating the program execution status of the central processing unit CPU is constantly monitored by the watchdog timer WDT and used for detecting an abnormality of the microcomputer MCU.
[0061]
The flash memory FEEPROM stores programs and fixed data necessary for control of the central processing unit CPU. The random access memory RAM is composed of, for example, a static RAM having a predetermined storage capacity, and temporarily stores calculation results and control data of the central processing unit CPU.
[0062]
In such a single-chip microcomputer, the analog / digital conversion circuit ADC converts an analog input signal input from various sensors connected to the outside into a digital signal of a predetermined bit, and the central processing unit via the internal bus IBUS. It can be used for transmission to a CPU or the like. In this embodiment, the local DAC and the chopper type voltage comparison circuit as described above are used. The timer circuit TIM measures time according to the clock signal supplied from the clock generation circuit CPG, and the serial communication interface SCI is a high-speed connection between the serial input / output device coupled to the outside of the microcomputer and the random access memory RAM, for example. Support data transfer.
[0063]
The watchdog timer WDT monitors the internal signal PR output from the central processing unit CPU. In response to the fact that the internal signal PR is not formed over a predetermined time, in other words, the instruction fetch by the central processing unit CPU is long. In response to not being performed over a period of time, an abnormality of the central processing unit, that is, the microcomputer is detected, and its output signal, that is, the abnormality detection signal TD is selectively set to the high level. The power-on reset circuit POR monitors the potential of the power supply voltage VCC and the ground potential VSS supplied via the external terminals VCC and VSS, and when the operation power is turned on, its output signal, that is, the power-on reset signal POR. Is temporarily set to the high level for a predetermined period. The abnormality detection signal TD from the watchdog timer WDT and the power-on reset signal POR from the power-on reset circuit POR are supplied to the clock controller CLKC.
[0064]
As a result, in a single-chip microcomputer or the like incorporated in an automobile or industrial machine, the operation of the clock generation circuit is selectively stopped in response to detection of an abnormality by a watchdog timer or writing of a predetermined register by a command from the central processing unit. By providing a clock controller that can be released, this complete stop state can be released only by the power-on reset signal when the power is turned on again. When an abnormality occurs, the operating power is turned off and then turned on again. The operation of the computer or the like can be completely stopped.
[0065]
The above single-chip microcomputer is configured by using a manufacturing process of a flash memory FEEPROM. In other words, there are two types of MOSFETs: a high breakdown voltage and high threshold voltage MOSFET that constitutes the memory cell of the flash memory FEEPROM and its peripheral circuits, and a low threshold voltage MOSFET that constitutes a logic circuit such as the central processing unit CPU. The threshold voltage is constituted by a MOSFET. When the analog / digital conversion circuit ADC is configured in such a single chip microcomputer composed of two types of MOSFETs, a switch or CMOS used for the local DAC and chopper type voltage comparison circuit that configure the analog / digital conversion circuit ADC. By applying the present invention to the switch, the same thing as the low threshold voltage MOSFET of the above logic circuit is used to reduce the cost, while suppressing the leakage current in the analog / digital conversion circuit ADC and achieving high speed and high accuracy. An A / D conversion operation can be performed.
[0066]
According to the embodiment described above, it is possible to reduce the operable power supply voltage by using the low Vth MOS for the reset switch of the inverter circuit used in the chopper type voltage comparison circuit. In order to prevent accuracy degradation due to leakage current generated in the low Vth MOSFET, two reset switches of the first-stage inverter circuit are connected in series, and the intermediate node is set to an appropriate potential when the switch is turned off to prevent leakage current. can do. In addition, by eliminating the interstage capacitance, accuracy deterioration due to the leakage current of the reset switch of the inverter circuit after the second stage is prevented, and by removing the parasitic capacitance (bottom plate capacity) of the interstage capacitance that becomes the load of the inverter circuit High speed operation is possible.
[0067]
When removing the interstage capacitance, if there is a reset switch for the second-stage inverter circuit, the offset voltage of the first-stage inverter circuit will deviate from the original value at the time of reset. Remove the reset switch for the second-stage inverter circuit and remove it. Can be prevented. On the other hand, by leaving the third-stage (and subsequent) reset switch, the current consumption at the time of reset and comparison is almost equal, and the offset error is caused by the voltage drop (IR drop) caused by the parasitic resistance of the power supply wiring. It can be prevented from occurring.
[0068]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the inverter circuit may have a low threshold voltage or a high threshold voltage. In the present invention, once the input signal is stored, various chopper type voltage comparison circuits for comparing the magnitudes of a plurality of different reference voltages, a local DAC, and a successive approximation A / D converter configured by combining them, or The present invention can be widely used in various semiconductor integrated circuit devices including a resistor string type DAC.
[0069]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. First and second switch MOSFETs that are on / off controlled by the first voltage and the ground potential of the circuit between the input terminal and the output terminal of the first inverter circuit that operates based on the first voltage and the ground potential of the circuit. And a third switch MOSFET that is turned on when the first and second switch MOSFETs are controlled to be turned off between the interconnection point of the series circuit and the first voltage. In a state in which the first and second switch MOSFETs are turned on, an input signal is taken into the input of the first inverter circuit via a capacitor to constitute a chopper type amplifier circuit. An accurate and high-speed voltage comparison operation can be performed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a chopper type voltage comparison circuit according to the present invention.
FIG. 2 is an explanatory diagram of a reset switch according to the embodiment of FIG.
FIG. 3 is a circuit diagram showing another embodiment of the chopper type voltage comparison circuit according to the present invention.
FIG. 4 is an element layout diagram showing one embodiment of an inverter circuit used in a chopper type voltage comparison circuit used in the present invention.
FIG. 5 is a device cross-sectional view showing one embodiment of the interstage capacitance of the embodiment of FIG. 1;
6 is a load circuit diagram of the inverter circuit of the embodiment of FIG. 1; FIG.
FIG. 7 is a circuit diagram showing one embodiment of a CMOS switch used in the present invention.
FIG. 8 is a circuit diagram showing another embodiment of the CMOS switch used in the present invention.
FIG. 9 is a partial circuit diagram showing one embodiment of a local DAC according to the present invention.
FIG. 10 is a remaining partial circuit diagram showing an embodiment of a local DAC according to the present invention.
FIG. 11 is a block diagram showing an embodiment of a single chip microcomputer to which the present invention is applied.
FIG. 12 is a characteristic diagram of a MOSFET for explaining the present invention.
FIG. 13 is a measurement circuit diagram of a MOSFET for explaining the present invention.
FIG. 14 is a circuit diagram showing an example of a chopper type voltage comparison circuit studied prior to the present invention.
[Explanation of symbols]
Q1-Q11 ... MOSFET, S1, S2 ... Switch, A1-A3 ... Inverter circuit, M1-M6 ... Unit MOSFET, SW1-SW8 ... Analog switch, MCU ... Single-chip microcomputer, CPU ... Central processing unit, IBUS ... Internal bus , FEEPROM ... Flash memory, RAM ... Random access memory, ADC ... Analog / digital conversion circuit, WDT ... Watch dog timer, TIM ... Timer circuit, SCI ... Serial communication interface, POR ... Power on reset circuit, CLKC ... Clock controller, CLKG ... Clock generation circuit, XTAL ... Crystal oscillator.

Claims (8)

It has a chopper type amplifier circuit,
The chopper type amplifier circuit is
A first inverter circuit operating with a first voltage and a ground potential of the circuit;
First and second switches which are provided in series between an input terminal and an output terminal of the first inverter circuit and are on / off controlled by a first control signal which is set to the first voltage and the ground potential of the circuit. MOSFET,
A capacitor having one end connected to the input terminal of the first inverter circuit and supplied with first and second input signals from the other end;
Provided between the connection point of the first and second switch MOSFETs and a second voltage having the same polarity as the first voltage, and turned on by a second control signal that is set to the first voltage and the ground potential of the circuit. A third switch MOSFET which is controlled to be turned off ;
A second inverter circuit for amplifying the output signal of the first inverter circuit,
The first input signal is supplied from the other end of the capacitor when the first and second switch MOSFETs are turned on by the first control signal.
The second input signal is supplied from the other end of the capacitor when the first and second switch MOSFETs are turned off by the first control signal ,
After the first and second switch MOSFETs are turned off by the first control signal, the third switch MOSFET is turned on by the second control signal,
The first switch when a difference voltage between a voltage obtained by adding the second input signal to the logic threshold voltage of the first inverter circuit and the first input signal is applied to the source of the first switch MOSFET. The first input signal, the second input signal, and the logic threshold voltage are set so that the leakage current flowing through the MOSFET is less than or equal to a desired current,
The threshold voltages of the first and second switch MOSFETs have a first threshold voltage corresponding to the first voltage,
A threshold voltage of the third switch MOSFET is set higher than the first threshold voltage ;
The semiconductor integrated circuit device, wherein the first and second inverter circuits are constituted by MOSFETs having the first threshold voltage . In claim 1,
The semiconductor integrated circuit device includes a nonvolatile memory circuit that can be electrically erased and written,
The third switch MOSFET is configured using a high voltage MOSFET used in the nonvolatile memory circuit,
The semiconductor integrated circuit device according to claim 1, wherein the first and second switch MOSFETs are constituted by MOSFETs having a low threshold voltage used for the nonvolatile memory circuit. In claim 2,
The other end of the capacitor, further comprising a first analog switch for supplying the first input signal, a second analog switch for supplying the second input signal,
The first input signal is an analog input voltage signal;
The second input signal is a reference voltage;
The chopper amplifier circuit performs a voltage comparison operation between the analog input voltage signal and the reference voltage when the first and second switch MOSFETs are turned off by the first control signal. Circuit device. In claim 3,
A third inverter circuit;
The output signal of the second inverter circuit is amplified by the third inverter circuit ,
A wiring capacitance between the input terminals of the output terminal and the second inverter circuit of the first inverter circuit, the input capacitance of the second input inverter circuit is set to be equal to,
A semiconductor integrated circuit device, wherein a wiring capacitance between an output terminal of the second inverter circuit and an input terminal of the third inverter circuit and an input capacitance of the third input inverter circuit are set to be equal . In claim 3,
A semiconductor integrated circuit device characterized in that a low threshold voltage MOS switch is provided in parallel with an input terminal and an output terminal of the third inverter circuit. In claim 5,
The reference voltage input through the second analog switch is sequentially switched corresponding to the voltage comparison result, and a digital signal corresponding to the analog input voltage signal is obtained from the relationship between the voltage comparison result and the switched reference voltage. A semiconductor integrated circuit device further comprising a circuit for obtaining a conversion signal. In claim 6,
The reference voltage is composed of a plurality of voltages obtained by dividing a constant voltage that is lower than the first voltage with reference to the ground potential.
The second analog switch for selecting the reference voltage on the ground potential side of the circuit is composed of an N-channel MOSFET,
The second analog switch for selecting the reference voltage on the constant voltage side is composed of a P-channel MOSFET,
The second analog switch that selects an intermediate reference voltage between the ground potential of the circuit and the constant voltage is a CMOS switch in which a P-channel MOSFET and an N-channel MOSFET are connected in parallel,
A first bias switching circuit that supplies a positive bias voltage to the N-channel substrate gate when the N-channel MOSFET is in an on state and supplies a ground potential of the circuit when the N-channel MOSFET is in an off state, or the P One of the second bias switching circuits for supplying a positive bias voltage to the substrate gate of the channel MOSFET when the P-channel MOSFET is on and supplying the first voltage when the P-channel MOSFET is off. A semiconductor integrated circuit device, which is provided. In claim 7,
The first bias switching circuit includes an N-channel type fourth switch MOSFET that transmits the reference voltage to the substrate gate when the N-channel MOSFET is turned on, and the ground potential when the N-channel is turned off. Consisting of an N-channel fifth MOSFET that transmits the above to the substrate gate,
The second bias switching circuit includes a P-channel type sixth switch MOSFET that transmits the reference voltage to the substrate gate and a first P-channel MOSFET when the P-channel is in an OFF state. A semiconductor integrated circuit device comprising a seventh P-channel MOSFET for transmitting a voltage to the substrate gate.

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