JP4152116B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a nonvolatile semiconductor device, and more particularly, to improve the shape of a floating gate in a split gate flash memory.
[0002]
[Prior art]
There are various types of nonvolatile semiconductor devices, and there are devices that can be electrically written and erased. The split gate type flash memory is one of them.
[0003]
In recent years, the need for miniaturization and integration of semiconductor devices has increased greatly, and even a nonvolatile semiconductor device is no exception. Under such circumstances, other elements (for example, a resistance element and a capacitance element) are formed on the same substrate for the split gate type flash memory which is one of the nonvolatile semiconductor devices, and there is a demand for miniaturization and integration. It is natural that there is.
[0004]
FIG. 11 is a cross-sectional view showing a conventional split gate flash memory, a semiconductor device having a polysilicon resistor and a capacitive element in the same substrate.
[0005]
See FIG. In the figure, the semiconductor device includes a split gate flash memory 101, a resistor element 102a, and a capacitor element 102b. Here, the split gate flash memory 101, the resistance element 102a, and the capacitor element 102b are all formed on the same semiconductor layer 103.
[0006]
The split gate flash memory 101 includes a first insulating film 104, a floating gate 105, a mini-LOCOS oxide film 106, a second insulating film 107, a control gate 108a, and an interlayer insulating film 109. A floating gate 105 is formed at a desired position of the first insulating film 104 on the semiconductor layer 103. The mini-LOCOS oxide film 106 is an inactive region formed on the floating gate 105. The second insulating film 107 covers the first insulating film 104, the side of the floating gate 105, and the surface of the mini LOCOS oxide film 106. A control gate 108 a is formed from the upper part to the side part of the floating gate 105 through the second insulating film 107.
[0007]
The interlayer insulating film 109 is an insulating film that covers the entire split gate flash memory 101, the resistor element 102a, and the capacitor element 102b. 11 indicates a protruding tip portion of the floating gate 105 adjacent to the bird's beak at the tip of the mini-LOCOS oxide film 106. In FIG.
[0008]
The resistance element 102 a is a polysilicon resistance 112 a formed on the LOCOS oxide film 111 as an element isolation film formed on the semiconductor layer 103. The polysilicon resistor 112a is made of a polysilicon material. The resistance element 102a is formed on the same continuous semiconductor layer 103 as the split gate type flash memory.
[0009]
The capacitor element 102 b is a capacitor formed on the LOCOS oxide film 111 as an element isolation film formed on the semiconductor layer 103. The capacitive element 102b is formed on the same continuous semiconductor layer 103 as the split gate type flash memory.
[0010]
In addition, these mixed split gate flash memories have a semiconductor layer 103 formed on a semiconductor substrate (not shown), and a large number of cells having a source region and a drain region (both not shown) inside the semiconductor layer 103. Exists.
[0011]
Next, the operation of a general split gate flash memory will be described.
[0012]
At the time of writing: In the split gate type flash memory described above, the charge (electrons) using the hot electron phenomenon generated between the source and drain regions (not shown) when the transistor of the memory cell to be written is turned on is supplied to the floating gate 105 To write data to the floating gate 105.
[0013]
At the time of erasing: By applying a high voltage to the control gate 108a, the electric field concentration at the protrusion 110 of the floating gate 105 is utilized to move the charge (electrons) in the floating gate 105 from the floating gate 105 to the control gate 108a. To remove data from the program state. That is, in order to realize low voltage erasing, it is necessary that the tip of the protrusion 110 is sharper.
[0014]
Hereinafter, a method for manufacturing a polysilicon resistor and a capacitor element formed in the same substrate as a split gate type flash memory which is a nonvolatile semiconductor device according to a conventional example will be described with reference to the drawings.
[0015]
FIG. 8 to FIG. 10 are cross-sectional views showing the steps of manufacturing the split gate flash memory, the resistance element 102a, and the capacitance element 102b of FIG. 11 in time series. 8 to 10, the same components are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, these will be sequentially described.
[0016]
See FIG. A LOCOS oxide film 111 is formed on the semiconductor layer 103 at a position where the polysilicon resistor 112a and the capacitor 112b are to be formed. Then, a first insulating film 104 made of a SiO ₂ film is formed on the entire surface, and a polysilicon film 113 is laminated on those surfaces.
[0017]
See FIG. Next, a silicon nitride film (not shown), which is an oxidation resistant film, is formed so that the polysilicon film 113 serving as the formation region of the floating gate 105 is exposed, and the mini-LOCOS oxide film 106 is formed using this as a mask. Next, after etching the silicon nitride film, a resist 114 is formed at a desired position where the resistance element 102a and the capacitor element 102b are formed by exposure and development.
[0018]
See FIG. Using the mini-LOCOS oxide film 106 and the resist 114 as a mask, the polysilicon film 113 is etched and removed to form the floating gate 105, the polysilicon resistor 112a, and the capacitor lower electrode 112b. Thereafter, impurities are introduced into the polysilicon resistor 112a and the capacitor lower electrode 112b simultaneously or separately.
[0019]
Subsequent to FIG. 10, a second insulating film 107 made of silicon oxide is formed on the entire surface. A polysilicon film is formed on the second insulating film 107 and patterned so as to extend from the top to the side of the floating gate 105, thereby forming the control gate 108a. At the same time, the capacitor upper electrode 108b is formed on the capacitor 102b. Impurities are ion-implanted into the semiconductor layer 103 to form both source and drain regions (both not shown).
[0020]
Thereafter, the interlayer insulating film 109 is attached to the entire split gate flash memory 101, the resistor element 102a, and the capacitor element 102b, thereby completing the semiconductor device shown in FIG.
[0021]
[Problems to be solved by the invention]
In FIG. 9 of the semiconductor device manufacturing method described above, when etching the polysilicon film 113 using the mini-LOCOS oxide film 106 and the resist 114 as a mask, appropriate etching conditions are set (etching gas species, temperature, It was extremely difficult to select the appropriate concentration.
[0022]
This is because carbon (C) exists in the resist 114 when forming the resistance element 102a and the capacitance element 102b, and is combined with oxygen (O) in the oxide film, thereby increasing the etching rate of the mini-LOCOS oxide film 106. This is because the etching selection ratio of the floating gate 105 to the polysilicon is lowered.
[0023]
For example, in the conventional example as described above, when the gas type for etching the polysilicon film 113 is selected, the etching of the mini LOCOS oxide film 106 proceeds as compared with the case without the resist due to the influence of the resist 114, and the protrusion just below it. The polysilicon film 113 in the portion 110 is etched more than necessary. Further, the first insulating film 104 is etched off during the overetching of the polysilicon film 113, and the semiconductor layer 103 is etched. Further, the formation state of the polysilicon side wall surface of the floating gate 105 also changes, and the vertical state cannot be maintained. These examples will be described later with reference to FIG.
[0024]
In the presence of a resist, it is very difficult to find an etching condition for obtaining a floating shape equivalent to that without a resist. Even if an appropriate etching condition is found, the required polysilicon resistance and capacitance vary, and the resist area varies depending on the design pattern. Therefore, the etching condition is not versatile. In other words, it is obvious that the etching gas and the etching conditions must be searched one by one for each design pattern, which is inefficient.
[0025]
Hereinafter, the case where the above-described oxide film is etched and the polysilicon film is also etched will be described with reference to FIG. FIG. 12 is an enlarged view of the vicinity of the protrusion 110 in FIG.
[0026]
This figure compares a circle A in an ideal protruding state (the floating gate 105 including the ideal protruding portion 110 is indicated by a dotted line) and a protruding state circle B found in the conventional example. If the etching is excessive, the mini-LOCOS oxide film 106 proceeds from the state of the circle A to the state of the circle B. Along with this, the polysilicon film corresponding to the floating gate 105 of the mini-LOCOS oxide film 106 is also etched.
[0027]
As a result, due to the shape of the tip of the bird's beak of the mini-LOCOS oxide film 106, the protrusion of the circle B is less sharp (not steep) than the protrusion of the circle A. That is, the erase characteristic (extraction of electrons) at the time of data erasure is deteriorated.
[0028]
The present invention has been made in view of the above disadvantages, and provides a mixed split gate flash memory in which the floating gate 105 is not etched more than necessary.
[0029]
[Means for Solving the Problems]
According to a first aspect of the present invention, a step of forming an element isolation film and a first insulating film on a semiconductor layer, a step of sequentially forming a polysilicon film and a second insulating film on the entire surface, and the second Forming a mask at a desired position on the insulating film and etching the insulating film to form a first remaining portion and a second remaining portion made of a second insulating film on the polysilicon film; A silicon nitride film is formed on the silicon film and the remaining portion, an opening is provided at a desired position of the silicon nitride film, and the polysilicon film is thermally oxidized through the opening to form a mini-LOCOS oxide film. A step of removing the silicon nitride film, and etching the polysilicon film using the remaining portions of the mini-LOCOS oxide film and the second insulating film as a mask to form a floating gate under the mini-LOCOS oxide film. Forming a polysilicon resistor under the first remaining portion, and forming a lower electrode of a capacitor element under the second remaining portion, a surface of the first insulating film, and a polysilicon film A step of covering a side surface, a surface of the mini LOCOS oxide film, a side surface and a surface of the first and second remaining portions with a third insulating film, and forming a control gate from the top to the side of the floating gate; And a step of forming the upper electrode of the capacitor element at a desired position on the lower electrode of the capacitor element.
[0030]
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, characterized in that the semiconductor device is formed by at least one of the polysilicon resistor and the capacitive element.
[0031]
A third aspect of the present invention includes the step of forming the second insulating film and the polysilicon film in the capacitor element through the third insulating film. A method for manufacturing a semiconductor device is provided.
[0032]
According to a fourth aspect of the present invention, there is provided the semiconductor device manufacturing method according to the first, second, or third aspect, wherein the thickness of the second insulating film is 50 to 500 mm.
[0033]
According to a fifth aspect of the present invention, the ratio of the thickness of the polysilicon film to the thickness of the second insulating film is 24: 1 to 12: 5, or A method for manufacturing a semiconductor device according to 3 or 4 is provided.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 to FIG. 6 are cross-sectional views showing the invention showing the manufacturing method according to the first embodiment of the present invention in time series. In all the drawings, the same components are denoted by the same reference numerals.
[0035]
The semiconductor device manufactured by the manufacturing method of this embodiment is shown in FIG. In the present embodiment, the split gate flash memory 1, the resistance element 2a, and the capacitive element 2b are formed on the same semiconductor substrate as in the conventional example shown in FIG. However, the method of forming the resistive element 2a and the capacitive element 2b and the effect after anisotropic etching are greatly different from the conventional example.
[0036]
Hereinafter, the manufacturing method according to the present embodiment will be sequentially described with reference to FIGS.
[0037]
See Figure 1:
A semiconductor substrate (not shown) is prepared, and a P-type semiconductor layer 3 is formed on the semiconductor substrate. Next, a silicon oxide film, a silicon nitride film, and a resist (both not shown) are applied to the entire surface of the semiconductor layer 3, exposed and developed, and the silicon nitride film is etched using the resist as a mask to open an opening (not shown). The LOCOS oxide film 5 as an element isolation film is formed by thermal oxidation or the like. Thereafter, thermal oxidation, chemical vapor deposition, or the like is performed on the entire surface to form about 82 mm of a first silicon oxide film (SiO ₂ ) for forming the first insulating film 4.
[0038]
Next, on the first insulating film 4 and the LOCOS oxide film 5, silane (SiH ₄ ) or the like using chemical vapor deposition is thermally decomposed in a nitrogen (N ₂ ) or hydrogen (H ₂ ) atmosphere. As a result, a polysilicon film 6 is formed to a thickness of about 1200 mm.
[0039]
Thereafter, a second silicon oxide film 8 is formed on the polysilicon film 6 by about 50 to 500 mm by thermal oxidation, chemical vapor deposition or the like.
[0040]
See Figure 2:
Next, in order to form the resistive element 2a and the capacitive element 2b, a resist is applied, and mask exposure and development processing are performed. Then, anisotropic etching is performed to etch the second silicon oxide film 8 and leave the second silicon oxide film 8 just below the resist 7 (hereinafter, this portion is referred to as a second silicon oxide film 8a). ).
[0041]
See FIG.
[0042]
Thereafter, the resist 7 is removed, and a silicon nitride film 9 is formed on the surface of the polysilicon film 6 and the second silicon oxide film 8a by about 800 mm. The silicon nitride film 9 is an oxidation resistant film for forming the mini LOCOS oxide film 10 of the split gate flash memory 1.
[0043]
Subsequently, a resist (not shown) is applied, mask exposure and development are performed, and an opening 11 is provided at a desired location where the mini-LOCOS oxide film 10 is formed so that the polysilicon film 6 is exposed.
[0044]
See FIG.
[0045]
Next, the mini LOCOS oxide film 10 is formed in the opening 11 by thermally oxidizing the polysilicon film 6. Thereafter, the silicon nitride film 9 existing on the surface is removed.
[0046]
See FIG.
[0047]
Thereafter, anisotropic etching is performed on the polysilicon film 6 using the mini-LOCOS oxide film 10 and the second silicon oxide film 8a as a mask. Here, the present invention is characterized in that the second insulating film 8a, which is a silicon oxide film (SiO ₂ ) of the same quality as the mini-LOCOS oxide film 10, is left on the resistor element 2a and the capacitor element 2b, and polysilicon is used as a mask. The film 6 is subjected to anisotropic dry etching. The above etching conditions generally use the same etching gas (CF ₄ , HBr, etc.) as that used to etch polysilicon.
[0048]
The polysilicon film 6 left immediately after the etching immediately below the second silicon oxide film 8a is defined as a polysilicon film 6a. The polysilicon film 6a becomes a lower electrode of the resistance element 2a and the capacitance element 2b, respectively.
[0049]
Here, it is necessary to maintain a desired resistance value and capacitance value in the polysilicon film 6a. There are the following two methods.
[0050]
As a first method, after forming the element shape of the resistive element 2a or the capacitive element 2b (two polysilicon films 6a in FIG. 5), a resist is applied in an arbitrary process, and the resist is used as a mask. Impurities are implanted into the two polysilicon films 6a simultaneously or separately. At this time, the resistance element 2a is implanted with an impurity so as to have an arbitrary resistance value, and the lower electrode of the capacitance element 2b is about 5 × 10 ¹⁵ (pieces / cm ² ) in order to prevent depletion of the electrode. Impurities are implanted.
[0051]
As a second method, ion implantation is performed on the polysilicon film 6a of the resistance element 2a simultaneously with ion implantation performed when forming a source / drain of a transistor in the semiconductor layer 3 to be described later. In this case, there is an advantage that the number of steps can be reduced by the amount that the resist is not formed as compared with the first method.
[0052]
See FIG.
[0053]
Thereafter, the third insulating film 13 is coated on the entire surface of the split gate flash memory 1, the resistor element 2a, and the capacitor element 2b. Next, a polysilicon film is coated on the third insulating film 13. A resist (not shown) is formed on the polysilicon film, and exposure / development processing is performed to provide an opening at a desired position. Then, the control gate 14a and the capacitor upper electrode 14b are formed by etching.
[0054]
Here, the polysilicon film for forming the control gate 14a and the capacitor upper electrode 14b may be a laminate of polysilicon and tungsten silicide.
[0055]
Next, using the formed floating gate 12 and control gate 14 as a mask, impurities are ion-implanted into the semiconductor layer 3 to form both source and drain regions (both not shown). Here, as described above, the impurity may be implanted into the polysilicon film 6a in order to obtain a desired resistance value.
[0056]
Then, an interlayer insulating film 15 is attached to the entire split gate flash memory 1, resistance element 2a, and capacitive element 2b. Then, a hybrid semiconductor device having the split gate flash memory 1, the resistance element 2a, and the capacitance element 2b shown in FIG. 6 is completed.
[0057]
FIG. 7 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. The difference from the first embodiment (FIG. 6) is the shape of the capacitive element 2b. The same components as those in the first embodiment are denoted by the same reference numerals, and the description of the same contents is omitted.
[0058]
The feature of this embodiment is that the capacitor upper electrode 14b is present on the capacitor lower electrode 12b via the third insulating film 13 in the capacitor element 2b. In general, the capacitance value of the capacitive element 2b depends on the distance between the capacitive upper electrode 14b and the capacitive lower electrode 12b. That is, in this embodiment, the distance is only the thin third insulating film 13 and can have a high capacitance value.
[0059]
The manufacturing method of the present embodiment is not significantly different from the manufacturing method of the first embodiment of the present invention, but in the step shown in FIG. 5, the silicon oxide film 8a of the capacitive element 2b may be selectively etched.
[0060]
A feature of the present invention (first and second embodiments) is that a second silicon oxide film 8a is formed when the lower electrodes of the resistance element 2a and the capacitor element 2b are formed, and the second silicon oxide film 8a is masked. As shown, by etching the polysilicon film 6, the etching shape of the polysilicon film 6 of FIG. 4 is stabilized regardless of the area of the resistance element 2a and the capacitance element 2b.
[0061]
As described above, in the manufacturing method of the present invention, since the lower electrodes of the resistance element 2a and the capacitive element 2b have the second silicon oxide film 8 made of the same material as the mini-LOCOS oxide film 10 thereabove, no resist is required. Therefore, it is not necessary to consider the influence of the resist when the polysilicon film 6 is etched.
[0062]
As a result, the mini-LOCOS oxide film 10 and the floating gate 12 existing immediately below are not etched more than necessary, and the protrusion of the floating gate 12 immediately below the bird's beak at the tip of the mini-LOCOS oxide film 10 is sharp. Can be maintained. In addition, the data erasing characteristics (such as electron extraction efficiency) of the split gate flash memory 1 are not deteriorated.
[0063]
In the above-described embodiment, the example in which the resistor element 2a and the capacitor element 2b are formed on the LOCOS oxide film 6 on the semiconductor layer 3 is disclosed, but the LOCOS oxide film 6 is not necessarily an element necessary for the present invention. .
[0064]
Further, the present invention includes those in which sidewall spacers are formed around the resistance element 2a and those in which a part of the second silicon oxide film 8 is converted into sidewall spacers.
[0065]
As a result, in the present invention, the ratio of the thickness of the polysilicon film 6 to the thickness of the second insulating film 8a is 24: 1 to 12: 5.
[0066]
【The invention's effect】
The polysilicon film 6 immediately below the floating gate 12 is not etched more than necessary during etching. As a result, the protrusion at the tip of the floating gate 12 is kept sharp, and the erase characteristic (extraction of electrons) at the time of data erasure is not deteriorated.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.
FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.
FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.
FIG. 5 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention. FIG.
FIG. 7 is a cross-sectional view showing a semiconductor device of a semiconductor device according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a manufacturing method according to a conventional semiconductor device.
FIG. 9 is a cross-sectional view showing a manufacturing method according to a conventional semiconductor device.
FIG. 10 is a cross-sectional view showing a manufacturing method according to a conventional semiconductor device.
FIG. 11 is a cross-sectional view showing a manufacturing method according to a conventional semiconductor device.
FIG. 12 is a cross-sectional view showing a manufacturing method according to a conventional semiconductor device.

Claims (4)

Forming an element isolation film and a first insulating film on the semiconductor layer;
Sequentially forming a first conductive film and a second insulating film on the entire surface;
A mask is formed at a desired position on the second insulating film, and the insulating film is etched to form a first remaining portion and a second remaining portion made of the second insulating film on the first conductive film. And a process of
A silicon nitride film is formed on the first conductive film and the remaining part, an opening is provided at a desired position of the silicon nitride film, the first conductive film is thermally oxidized through the opening, Forming a LOCOS oxide film;
Removing the silicon nitride film;
Using the remaining portions of the mini-LOCOS oxide film and the second insulating film as a mask, the first conductive film is etched to form a floating gate under the mini-LOCOS oxide film and below the first remaining portion. Forming a polysilicon resistor and a lower electrode of a capacitive element under the second remaining portion, respectively;
Coating a third insulating film on each of the surface of the first insulating film, the side surface of the first conductive film, the surface of the mini-LOCOS oxide film, and the side surfaces and the surface of the first and second remaining portions; When,
Forming a control gate with a second conductive film from the top to the side of the floating gate, and forming an upper electrode of the capacitive element at a desired position on the lower electrode of the capacitive element. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the capacitive element includes a step of selectively removing the second insulating film . The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film has a thickness of 50 to 500 mm . The ratio of the film thickness of the said 1st electrically conductive film and the film thickness of the said 2nd insulating film is 24: 1-12: 5, The manufacturing of the semiconductor device of Claim 1 thru | or 3 characterized by the above-mentioned Method.

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