JP4153679B2 - Sampling frequency converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sampling frequency converter, and in particular, converts data sampled at a specific sampling frequency into data sampled at a different sampling frequency in a system such as an AV (Audio Visual) amplifier to which a digital audio signal is input. The present invention relates to a sampling frequency converter.
[0002]
[Prior art]
In a system such as an AV (Audio Visual) amplifier to which a digital audio signal supplied from a device such as a DVD (Digital Video Disk or Digital Versatile Disk), CD (Compact Disk), or DAT (Digital Audio Tape) is input, A sampling frequency converter that converts data sampled at a sampling frequency into data sampled at a different sampling frequency is used.
[0003]
An example of such a sampling frequency converter is a sampling frequency converter using a digital signal processor (DSP: Digital Signal Processor).
FIG. 5 is a block diagram showing the configuration of a conventional sampling frequency converter using a DSP in this way.
[0004]
As shown in FIG. 5, a conventional sampling frequency converter 50 includes a digital interface receiver (DIR) 51, a frequency divider 52, a DSP 53, and a switch means, which are input / output circuits. 55.
[0005]
The DIR 51 receives externally supplied digital audio signals (for example, left and right (LR) digital audio signals), and outputs a master clock 62 from the PLL unit 56 in the DIR 51. Further, the normal clock group 64 and the data signal 67 are output.
[0006]
The frequency divider 52 receives the master clock 62 and divides it by the bit clock frequency divider 521 to generate an LR (left / right) discrimination clock LRCK2. Further, the frequency is divided by the LR discrimination clock divider 522 to generate the bit clock BCK2. These LRCK2 and BCK2 are output as an upsampling clock group 63.
[0007]
The DSP 53 receives the normal clock group 64 (LR discrimination clock LRCK1 and bit clock BCK1) output from the DIR 51 and the data signal 67.
The switch means 55 inputs the upsampling clock group 63 (LRCK1 and BCK1) and the normal clock group 64 (LRCK2 and BCK2), and selects and outputs one of the clock groups.
Further, the DSP 53 outputs the data signal 68 sampled by the data output clock group 66 selected by the switch means 55 to the outside.
[0008]
When upsampling is not necessary, the normal clock group 64 (LRCK1 and BCK1) is used as the data output clock group 66 of the DSP 53 by switching the switch means 55.
[0009]
Next, in the conventional sampling frequency converter 50, for example, the sampling frequency fs is converted to a sampling frequency of fs = 48 KHz at the time of data input and converted to a sampling frequency of fs = 96 KHz at the time of data output (upsampling). Will be described.
[0010]
In the sampling frequency converter 50, a digital signal of fs = 48 kHz is input to the DIR 51, and the normal clock group 64 (LR discrimination clock LRCK1 and bit clock BCK1) generated by the PLL unit 56 in the DIR 51 and the sampling frequency fs = A data signal 67 sampled at 48 KHz is output from the DIR 51. The output data signal 67 is input to the DSP 53.
The normal clock group 64 (LRCK1 and BCK1) is used as a data input clock for the DSP 53.
[0011]
The LR discrimination clock LRCK1 is a clock for discriminating whether a stereo digital audio signal is a left (L) channel signal or a right (R) channel signal. For example, when the LR discrimination clock LRCK1 is at a high level. This indicates that the data of the stereo digital audio signal is data of the right channel (R). Conversely, when it is at a low level, it indicates data of the left channel (L).
The relationship between the frequencies of the LR discrimination clock LRCK1 and the bit clock BCK1 is BCK = 64 × fs with respect to LRCK = fs.
[0012]
The 24.576 MHz master clock 62 output from the PLL unit 56 of the DIR 51 is input to the frequency dividing circuit 52, and is divided by the 1/4 frequency divider 521 to a frequency of 1/4 to generate the bit clock BCK2. The
Further, the 1/256 frequency divider 522 divides the frequency to 1/256 to generate the LR discrimination clock LRCK2.
The bit clock BCK2 and the LR discrimination clock LRCK2 are an upsampling clock group 63 for the sampling frequency fs = 96 KHz, are selected by the switch means 55, and are used as the data output clock group 66 of the DSP 53.
[0013]
[Problems to be solved by the invention]
As described above, the conventional sampling frequency converter separates the master clock 62 separately from the normal clock group 64 (LR determination clock LRCK1 and bit clock BCK1) for data input to the DSP 53 when upsampling is performed. The upsampling clock group 63 (the LR discrimination clock LRCK2 and the bit clock BCK2) newly created by the rotation is used as the data output clock group 66 from the DSP 53.
For this reason, the phase of the data input clock to the DSP 53 and the data output clock from the DSP 53 are shifted.
[0014]
In addition, the phase difference of the clock cannot be kept constant, and the phase changes due to turning on / off of the power supply of the apparatus and is unstable.
As described above, there is a problem that correct data cannot be output from the DSP 53 unless the phase of the clock for input clock output matches (see the conventional example of the timing chart of FIG. 4).
[0015]
In order to solve this problem, asynchronous buffer circuits are provided between the data input clock and the DSP 53 and between the data output clock and the DSP 53, and the phase of the clock is controlled by these buffer circuits. A method of adjusting to fit is also conceivable.
However, the circuit scale increases by the buffer circuit, and the manufacturing cost increases. Further, it is difficult to make the phases completely coincide with each other only by adjustment with the buffer circuit, and the reliability is lacking.
[0016]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a highly reliable sampling frequency converter capable of outputting correct data by matching the phases of sampling clocks.
[0017]
[Means for Solving the Problems]
In order to achieve the above-described object, a sampling frequency conversion device according to the present invention receives a digital signal supplied from the outside and a first selected clock group supplied from the outside as described in claim 1. An input / output circuit that outputs a first data signal and a master clock; a master clock that is input; the first clock group that corresponds to the first sampling frequency; and the second clock that corresponds to the second sampling frequency. A frequency dividing circuit that outputs two clock groups, a first clock group that is output from the frequency dividing circuit, and the second clock group, and a first selected clock group that is output. Switch means, second switch means for selecting the first clock group and the second clock group output from the frequency divider circuit, and outputting a second selected clock group; And the first selected clock group used as the sampling clock group for input of the first data signal are input, and the second selected clock group is input and used as the output sampling clock group. And a digital signal processor for outputting the second data signal.
As a result, clock groups having different sampling frequencies are generated from one master clock by the frequency dividing circuit, so that the phase of the sampling clock for input and the sampling clock for output of the digital signal processor (DSP) is changed. Since the data can be adjusted and correct data can be output, the reliability can be improved.
[0018]
The sampling frequency converter according to the present invention is characterized in that, as described in claim 2, the input / output circuit includes third switch means and fourth switch means, and the first input from the outside. The selected clock group and the internally generated sampling clock group are configured to be selectable by the third switch means and the fourth switch means.
Thereby, the sampling clock input from the outside and the sampling clock generated inside can be selected.
[0019]
The sampling frequency converter according to the present invention is characterized in that, as described in claim 3, the third switch means and the fourth switch means can be automatically switched by a control signal. .
Thereby, the sampling clock input from the outside and the sampling clock generated inside can be automatically switched by the control signal.
[0020]
The sampling frequency converter according to the present invention is characterized in that the second sampling frequency is higher than the first sampling frequency.
Thereby, upsampling can be performed.
[0021]
The sampling frequency converter according to the present invention is characterized in that, as described in claim 5, the first clock group and the second clock group are sampling clocks for a digital audio signal.
Thereby, the sampling frequency can be converted with respect to the digital audio signal.
[0022]
In the sampling frequency converter according to the present invention, the first clock group and the second clock group are signals of a left (L) channel with respect to the digital audio signal. It includes an LR discriminating clock for discriminating whether the signal is a right (R) channel signal and a bit clock for fetching each data of the digital audio signal.
As a result, it is possible to determine whether the digital audio signal is a left (L) channel signal or a right (R) channel signal, and each data of the digital audio signal can be captured.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments according to the present invention will be described in detail based on the drawings.
(First embodiment)
A first embodiment according to the present invention will be described below.
FIG. 1 is a block diagram showing the configuration of the first embodiment.
As shown in FIG. 1, the sampling frequency converter 10 of the first embodiment includes an DIR (digital interface receiver) 11 that is an input / output circuit, a frequency divider 12, a DSP 13, a first switch means 14, Second switch means 15 is provided.
[0024]
The DIR 11 receives a digital signal 21 (for example, left and right (LR) digital audio signal) supplied from the outside, and outputs a master clock 22 from the PLL unit 16 in the DIR 11. Further, the first selected clock group 25 is input from the outside of the DIR 11 and the first data signal 27 is output.
[0025]
The internal configuration and function of the DIR 11 will be described below with reference to FIG. FIG. 2 is a block diagram showing the configuration of the DIR.
As shown in FIG. 2, the digital signal 21 supplied from the outside is input to the DIF decoder and also to the synchronization detection unit 32. The output from the synchronization detection unit 32 is input to the phase comparison unit 33 of the PLL unit 16, and the master clock 22 is generated through an LPF (low pass filter) 34 and a VCO (voltage controlled oscillator) 35.
[0026]
Further, the output of the VCO 35 can be fed back to the phase comparison unit 33 via the frequency divider 36 so that the phase can be synchronized with the input signal.
Further, the VCO 35 output can be input to the clock generation unit 37, and the LR discrimination clock LRCK1 and the bit clock BCK1 can be generated inside the DIR11.
[0027]
Further, the first selected clock group 25 can be inputted from the outside, and the sampling clock generated internally by the third switch means 38 and the fourth switch means 39 or the clock inputted from the outside is used. You can choose to use.
[0028]
These switch means 38 and 39 can be switched by a control signal 40 from an external microcomputer or the like.
Then, the clocks LRCK1 and BCK1 are input to a DIF (digital interface) decoder, and the first data signal 27 is output.
[0029]
The frequency dividing circuit 12 shown in FIG. 1 is composed of, for example, a plurality of stages of D flip-flops as shown in FIG. 6A, and the inverted output of each D flip-flop is connected to the data input terminal. By inputting the inverted output of the preceding D flip-flop to the clock input terminal, it is possible to use a circuit in which the output of each D flip-flop is divided by half that of the preceding stage.
[0030]
In the example shown in (a) of FIG. 6, the clock is composed of 9 stages of D flip-flops, and outputs a clock divided by 1/2 to 1/512 of the master clock input via the buffer. It can be done.
[0031]
Then, as shown in the timing chart of each divided clock with respect to the master clock 22 as shown in FIG. 6B, a divided clock having the same phase can be obtained.
[0032]
A circuit configuration other than that shown in FIG. 6A may be used as long as it can receive the master clock 22 and obtain a divided clock having the same phase.
[0033]
Such a frequency dividing circuit 12 receives the master clock 22 output from the DIR 11 and is composed of a 1/4 frequency clock (BCK2) for bit clock and a 1/256 frequency divided clock (LRCK2) for LR discrimination clock. A normal clock group 24 composed of an upsampling clock group 23, a bit clock 1/8 frequency-divided clock (BCK1) and an LR discrimination clock 1/512 frequency-divided clock (LRCK1) is output.
[0034]
The first switch means 14 inputs the upsampling clock group 23 (LRCK2 and BCK2) and the normal clock group 24 (LRCK1 and BCK1), selects one of the clock groups, and selects the selected clock group 25. Output. The selected clock group 25 is input to the DIR 11 and the DSP 13.
[0035]
The second switch means 15 receives the upsampling clock group 23 (LRCK2 and BCK2) and the normal clock group 24 (LRCK1 and BCK1), selects one of the clocks, and selects the second selected clock group. 26 is output. The second selected clock group is input to the DSP 13 as an output sampling clock group.
[0036]
Further, the DSP 13 outputs the second data signal 28 sampled by this output sampling clock group to the outside.
[0037]
Next, in the sampling frequency converter 10, an operation when data is output (upsampling) with the sampling frequency fs set to, for example, the sampling frequency of fs = 48 KHz at the time of input and the sampling frequency of fs = 96 KHz will be described. .
[0038]
A digital signal of fs = 48 KHz is input to DIR11.
The 24.576 MHz master clock 22 output from the PLL section of the DIR 11 is input to the frequency divider circuit 12.
[0039]
Next, the 24.576 MHz master clock 22 is frequency-divided by the frequency dividing circuit 12 to 1/4 frequency to generate the bit clock BCK2, or is frequency-divided to 1/256 frequency and LR discrimination clock. LRCK2 is generated (see FIG. 6).
[0040]
Further, the 24.576 MHz master clock 22 is frequency-divided by the frequency dividing circuit 12 to a frequency of 1/8 to generate the bit clock BCK1, or is frequency-divided to a frequency of 1/512 and the LR discrimination clock. LRCK1 is generated (see FIG. 6).
[0041]
Next, the normal clock group 24 (LRCK1, BCK1) of the sampling frequency fs = 48 KHz selected by the first switch means 14 is input to the DIR 11 and the first data signal sampled at this sampling frequency fs = 48 KHz. 27 is output from the DIR 11 (at this time, the switch means 38 and 39 in the DIR 11 are preset to use a clock input from the outside).
[0042]
Next, the normal clock group 24 (LRCK1, BCK1) with the sampling frequency fs = 48 KHz is also used as a data input clock for the DSP 13, and the first data signal 27 is input to the DSP 13.
[0043]
Next, the upsampling clock group 23 (LRCK2 and BCK2) of the sampling frequency fs = 96 KHz selected by the second switch means 15 is used as the sampling clock group for output from the DSP 13 (second selected clock group 26). And the second data signal 28 sampled at the sampling frequency fs = 96 KHz is output from the DSP 13.
[0044]
Refer to FIG. 4 for the timing of each signal (LRCK1, BCK1, first data signal 27) on the DSP input side and each signal (LRCK2, BCK2, second data signal 28) on the DSP output side in the above operation. Will be explained.
FIG. 4 is a diagram showing a comparison of timing charts of the conventional sampling frequency conversion device and the sampling frequency conversion device according to the embodiment (the first embodiment or the second embodiment) according to the present invention.
[0045]
The LR discriminating clocks (LRCK1, LRCK2) are clocks for discriminating between a left (L) channel signal and a right (R) channel signal in a stereo digital audio signal. It indicates that the data of the digital audio signal is right channel (R) data. Conversely, when it is at a low level, it indicates data of the left channel (L).
[0046]
The bit clocks (BCK1, BCK2) are clock signals for taking in one bit of data, have a frequency 64 times that of the LR discrimination clocks (LRCK1, LRCK2), and the LR discrimination clocks (LRCK1, LRCK2) are at a high level. Alternatively, 32-bit data is captured while the level is low.
[0047]
The DSP output side has a sampling frequency (fs = 96 KHz) twice that of the DSP input side (fs = 48 KHz).
In the conventional sampling frequency converter, as shown in FIG. 4, the falling edge of LRCK1 on the DSP input side is shifted from the falling edge of LRCK2 on the DSP output side, and the phases do not match.
[0048]
On the other hand, in the sampling frequency converter of this embodiment, as shown in FIG. 4, the timing of the falling edge of LRCK1 on the DSP input side matches the timing of the falling edge of LRCK2 on the DSP output side. Match.
[0049]
As described above, the sampling frequency converter of the present embodiment divides one master clock to generate the normal clock and the upsampling clock, so that the phases of the respective clocks coincide with each other from the DSP input side. Data can be transferred normally to the output side.
[0050]
(Second Embodiment)
A second embodiment according to the present invention will be described below.
FIG. 3 is a block diagram showing the configuration of the second embodiment.
As shown in FIG. 3, the sampling frequency converter 20 of the second embodiment is a case where the master clock 22 is different from the first embodiment, and only the difference will be described and the same as the first embodiment. A description of the portion is omitted.
[0051]
In the present embodiment, the master clock 22 output from the PLL unit of the DIR 11 has a half frequency of the first embodiment. For example, when the master clock 22 of the first embodiment is 24.576 MHz. The master clock 22 of this embodiment is 12.288 MHz.
[0052]
The normal clock group 24 (LRCK1, BCK1) output from the frequency divider circuit 12 is fs = 48 KHz, and the upsampling clock group 23 (LRCK2, BCK2) is fs = 96 KHz.
[0053]
As described above, the present embodiment can output data (upsampling) in the same manner as the first embodiment with the sampling frequency of fs = 48 KHz at the time of input set to the sampling frequency of fs = 96 KHz.
[0054]
In each embodiment of the present invention, upsampling at an arbitrary magnification with respect to an arbitrary sampling frequency can be performed by changing the frequency dividing ratio of the clock extracted from the frequency dividing circuit 12 to a different one.
[0055]
Further, downsampling can be easily performed by changing the frequency division ratio and setting the sampling frequency of the DSP output sampling clock lower than the sampling frequency of the input sampling clock.
[0056]
Further, by changing the frequency dividing ratio, it can be used as a sampling frequency conversion device for digital signals other than the left and right (LR) digital audio signals.
[0057]
【The invention's effect】
As described above, according to the present invention, as described in claim 1, the digital signal supplied from the outside and the first selected clock group supplied from the outside are input, and the first data An input / output circuit for outputting a signal and a master clock, a first clock group corresponding to the first sampling frequency to which the master clock is input, and a second clock group corresponding to the second sampling frequency. A frequency dividing circuit for outputting, a first switch means for selecting the first clock group and the second clock group outputted from the frequency dividing circuit, and outputting a first selected clock group; Second switch means for selecting the first clock group and the second clock group output from the frequency dividing circuit and outputting a second selected clock group, a first data signal, and the first data signal Data signal The first selected clock group used as an input sampling clock group is input, and the second selected clock group is input and used as an output sampling clock group to output a second data signal. By having a signal processor, clock groups having different sampling frequencies are generated from one master clock by the frequency dividing circuit, so that the phase of the sampling clock for DSP input and the sampling clock for output Therefore, it is possible to provide a sampling frequency converter that can improve reliability because it can output correct data.
[0058]
According to the present invention, as described in claim 2, the digital interface receiver includes third switch means and fourth switch means, and the first selected clock group inputted from outside and the internal The sampling clock group generated in the above can be selected by the third switch means and the fourth switch means, so that the sampling clock input from the outside and the sampling clock generated internally can be selected. It is possible to provide a sampling frequency conversion device that can perform the above.
[0059]
According to the present invention, as described in claim 3, the third switch means and the fourth switch means can be automatically switched by the control signal, so that the sampling clock input from the outside It is possible to provide a sampling frequency converter capable of automatically switching between internally generated sampling clocks by a control signal.
[0060]
According to the present invention, as described in claim 4, when the second sampling frequency is higher than the first sampling frequency, it is possible to provide a sampling frequency converter capable of upsampling.
[0061]
According to the present invention, as described in claim 5, the first clock group and the second clock group are sampling clocks for the digital audio signal, so that the sampling frequency is converted for the digital audio signal. It is possible to provide a sampling frequency conversion device that can perform the above.
[0062]
According to the present invention, as described in claim 6, the first clock group and the second clock group are either a left (L) channel signal or a right (R) channel signal with respect to a digital audio signal. LR discriminating clock for discriminating between the digital audio signal and a bit clock for capturing each data of the digital audio signal. Therefore, it is possible to provide a sampling frequency converter that can determine whether the signal is a digital audio signal and can capture each data of the digital audio signal.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention.
FIG. 2 is a block diagram showing a DIR configuration according to the first or second embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a second embodiment.
FIG. 4 is a diagram illustrating a timing chart between a conventional sampling frequency conversion device and a sampling frequency conversion device according to an embodiment (first embodiment or second embodiment) of the present invention.
FIG. 5 is a block diagram showing the configuration of a conventional sampling frequency converter.
6A and 6B are a circuit diagram (a) and a timing chart (b) showing an example of a frequency dividing circuit used in the first embodiment or the second embodiment according to the present invention.
[Explanation of symbols]
10,20 Sampling frequency converter
11 DIR (Digital Interface Receiver)
12 divider circuit
13 DSP (Digital Signal Processor)
14, 15 Switch means
16 PLL section
21 Digital signal
22 Master clock
23 Upsampling clocks
24 Normal clock group
25, 26 Selected clock group
27, 28 Data signal
32 Synchronization detector
33 Phase comparator
36 divider
37 Clock generator
38,39 switch means
40 Control signal
BCK1, BCK2 bit clock
LRCK1, LRCK2 LR discrimination clock

Claims (6)

An input / output circuit for inputting a digital signal supplied from the outside and a first selected clock group supplied from the outside, and outputting a first data signal and a master clock;
A frequency divider that receives the master clock and outputs a first clock group corresponding to a first sampling frequency and a second clock group corresponding to a second sampling frequency;
First switch means for selecting the first clock group and the second clock group output from the frequency divider circuit and outputting the first selected clock group;
Second switch means for selecting the first clock group and the second clock group output from the frequency divider and outputting a second selected clock group;
A first data signal and the first selected clock group used as a sampling clock group for input of the first data signal are input, and the second selected clock group is input as an output sampling clock group. A digital signal processor that, when used, outputs a second data signal;
A sampling frequency conversion device characterized by comprising: The sampling frequency converter according to claim 1,
The input / output circuit includes third switch means and fourth switch means,
The first selection clock group input from the outside and the sampling clock group generated internally are configured to be selectable by the third switch means and the fourth switch means. Sampling frequency converter. The sampling frequency converter according to claim 2,
The sampling frequency converter according to claim 3, wherein the third switch means and the fourth switch means can be automatically switched by a control signal. In the sampling frequency converter according to any one of claims 1 to 3,
The sampling frequency converter characterized in that the second sampling frequency is higher than the first sampling frequency. In the sampling frequency converter according to any one of claims 1 to 4,
The sampling frequency converter according to claim 1, wherein the first clock group and the second clock group are sampling clocks for a digital audio signal. In the sampling frequency converter according to claim 5,
The first clock group and the second clock group are:
An LR discrimination clock for discriminating whether the digital audio signal is a left (L) channel signal or a right (R) channel signal;
A bit clock for capturing each data of the digital audio signal;
A sampling frequency conversion device comprising:

Images