JP4159197B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an insulated gate FET (field effect) having a stacked source and drain region that can reduce a capacitance between a gate electrode and a source and drain and suppress a short channel effect. The present invention relates to a method for manufacturing a transistor.
[0002]
[Prior art]
  In most semiconductor integrated circuits, an insulated gate FET (MISFET) is used as a basic element. In recent years, as semiconductor device dimensions are further miniaturized, variations in threshold voltage due to variations in gate length due to the short channel effect, an increase in leakage current due to degradation of subthreshold characteristics, and the like have become problems.
[0003]
  In order to solve these problems, it is known that it is effective to reduce the depth of the junction between the source / drain and the semiconductor substrate (hereinafter simply referred to as source / drain junction). However, if the source / drain junction is simply shallowed, the short channel effect can be suppressed. However, since the resistance value of the source / drain diffusion layer increases, the metal oxide semiconductor FET (MOSFET) There is a problem that the current driving force decreases.
[0004]
  Therefore, in order to solve the decrease in the current driving force, the source and drain regions existing on both sides of the channel region immediately below the gate electrode are stacked up to the upper side of the semiconductor substrate, in other words, the gate electrode sidewall insulating film is interposed on both sides of the gate electrode. A so-called stacked diffusion layer structure for forming source and drain diffusion layers reaching the semiconductor substrate is proposed. In this way, by stacking the source and drain regions above the semiconductor substrate, the source and drain diffusion layers can be effectively increased in thickness to reduce the resistance, and the depth of the source and drain junctions can be reduced. It is.
[0005]
  FIG. 9 shows a process of forming a conventional stacked diffusion layer disclosed in Japanese Patent Application Laid-Open No. 61-196577. As shown in FIG. 9A, an active region 3 is formed by forming and partitioning an element isolation region (silicon oxide film) 2 on a silicon substrate 1. A gate oxide film 4 is formed on the active region 3, and a gate electrode 6 whose side wall and upper part are covered with an insulating film 5 is formed.
[0006]
  Next, as shown in FIG. 9B, a silicon layer 8 is selectively epitaxially grown on the exposed source / drain formation region 7 in the silicon substrate 1. Then, impurities are ion-implanted into the silicon layer 8 to form impurity layers (source / drain diffusion layers) 9.
[0007]
  Next, as shown in FIG. 9C, an interlayer insulating film 10 is grown on the entire surface of the wafer, and an upper wiring 12 formed on the interlayer insulating film 10 is connected to a source / drain diffusion layer (via a contact wiring 11). Source and drain regions) 9.
[0008]
  The FET having the above-described stacked diffusion layer 9 thus obtained has a source / drain diffusion layer 9 below the gate electrode 6 because the source / drain region 9 is above the boundary between the gate oxide film 4 and the active region. Is suppressed, and the short channel effect is suppressed. Further, the length of the gate electrode 6 can be shortened without increasing the layer resistance of the source / drain diffusion layer 9.
[0009]
  FIG. 10 shows a process of forming a conventional stacked diffusion layer disclosed in Japanese Patent Publication No. 8-2576506. First, as shown in FIG. 10A, an oxide film 22 that forms an element isolation region is formed on a P-type substrate 21. Next, a gate oxide film 23 and a gate electrode 24 are sequentially formed in the active region on the P-type substrate 21, and thermal oxidation is performed to form an oxide film 25 having a sufficient thickness on the surface of the gate electrode 24. Next, as shown in FIG. 10B, after the oxide film 22 around the gate electrode 24 is removed, a polycrystalline silicon layer is formed, and the polycrystalline silicon layer is made N-type by phosphorus diffusion, and at the same time N-type A low concentration region 26 is formed. Next, the sidewall 27 is formed by an etch back method. Next, arsenic is implanted into the sidewall 27 by ion implantation to form the N-type high concentration region 28. The N-type low concentration region 26, the sidewall 27, and the N-type high concentration region 28 thus formed serve as the source and drain regions.
[0010]
  Next, as shown in FIG. 10C, an interlayer insulating film 29 is formed on the entire surface of the wafer, and contact holes are formed at the positions of the source and drain regions 26 and 27 so as to include a part of the sidewall 27 by photolithography and etching. 30, and the source / drain regions 26, 27, 28 are connected to the upper wiring 32 through the contact wiring 31.
[0011]
[Problems to be solved by the invention]
  However, the FET having the stacked diffusion layer formed by the conventional stacked diffusion layer forming method has the following problems. That is, in the case of the method of forming a stacked diffusion layer disclosed in any of JP-A-61-196577 and JP-B-8-2576506, the direction perpendicular to the longitudinal direction of the gate electrode (that is, the gate length) Contact holes are formed in the source and drain regions from the gate electrode to the element isolation region in the direction). The lengths of the source and drain regions are determined as follows.
[0012]
  FIG. 8 is a diagram showing the relationship among the gate electrode, the active region, and the contact hole. In the figure, p represents an alignment margin between the gate electrode 61 and the contact hole 63, o represents the width of the contact hole 63, and q represents an alignment margin between the contact hole 63 and the element isolation region 62. Represents. In the FET (FIG. 9) disclosed in Japanese Patent Application Laid-Open No. 61-196577, the length of the source / drain region 9 cannot be made shorter than (p + o + q). Therefore, in such an FET, it is not easy to reduce the area occupied by the source / drain regions 9.
[0013]
  Further, when the source and drain regions are stacked on the semiconductor substrate, the occupied area portion of the source and drain regions and the well region which are also present in the case of the normal (non-stacked) MISFET shown in FIG. As shown in FIG. 6B, parasitic capacitance is also generated between the stacked diffusion layers (source and drain regions) and the gate electrode. Therefore, in the FET as disclosed in Japanese Patent Application Laid-Open No. 61-196577 and Japanese Patent Publication No. 8-2576506, the operation speed of the element becomes slow.
[0014]
  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a high-speed semiconductor device with a small occupied area and parasitic capacitance of source and drain regions.
[0015]
[Means for Solving the Problems]
  In order to achieve the above object, a method for manufacturing a semiconductor device of the present invention includes:
  Forming an element isolation region on a silicon substrate or silicon well region with a material having etching selectivity with respect to silicon etching, and dividing the silicon substrate or silicon well region into the element isolation region and an active region;
  Sequentially forming a gate insulating film, a gate electrode and a gate sidewall insulating film on the active region;
  Forming a first polycrystalline silicon film so as to cover the entire surface including the element isolation region and the active region;
  Anisotropic etching is performed on the first polycrystalline silicon film so that the polycrystalline silicon film is adjacent to the gate sidewall insulating film.FirstForming a sidewall;
  Of the above polycrystalline siliconFirstForming a second polycrystalline silicon film so as to cover the sidewall;
  By performing anisotropic etching on the second polycrystalline silicon film and the first sidewall, the polycrystalline film is adjacent to the gate sidewall insulating film and extends to the element isolation region. Forming a second sidewall of silicon;
  the aboveSecondProcess of forming source and drain regions by implanting impurity ions into sidewalls
WithIn a method for manufacturing a semiconductor device,
  The height of the second sidewall formed by the above process from the surface of the silicon substrate or silicon well region at the portion in contact with the gate sidewall insulating film in the second sidewall is the silicon of the gate electrode. Less than the height from the surface of the substrate or silicon well region,
  In addition, the change in the height of the second sidewall from the surface of the silicon substrate or the silicon well region in the direction perpendicular to the longitudinal direction of the gate electrode decreases from the gate electrode side toward the side edge. Have
It is characterized by that.
[0016]
  According to the above configuration, the boundary between the active region and the element isolation region extends from the side edge of the gate electrode in the direction perpendicular to the longitudinal direction of the gate electrode.SecondIt is located between the side edges. Therefore, the junction area between the source / drain regions and the silicon substrate or silicon well region is sufficiently smaller than the surface area of the source / drain regions. As a result, most of the contact region between the source / drain region and the upper wiring is secured in the junction region formed in the active region of the silicon substrate or the silicon well region. Compared with a conventional semiconductor device having the same junction area on the surface, the area occupied by the source / drain junction region on the surface of the active region is reduced. That is, the junction capacitance between the source / drain regions and the semiconductor substrate is reduced.
[0017]
  Further, the source and drain regions (aboveSecondThe height of the side wall increases in the direction perpendicular to the longitudinal direction of the gate electrode from the side edge of the source / drain region toward the gate electrode. Therefore, the contact surface between the source / drain region and the contact wiring is inclined with respect to the axis of the contact wiring, and the area of the contact surface is increased. Therefore, the contact resistance between the source / drain regions and the contact wiring is lowered.
[0018]
  Furthermore, the height of the portion of the source / drain region that is in contact with the gate sidewall insulating film is lower than the height of the gate electrode. Therefore, the capacitance between the source / drain region and the gate electrode is reduced as compared with the conventional semiconductor device in which the height of the source / drain region in the vicinity of the gate electrode is approximately the same as the height of the gate electrode. .
[0019]
  Further, as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 61-196777, an expensive epitaxial growth apparatus is not required for forming the stacked diffusion layer, and the source and drain regions of the above-mentioned stacked structure are very low cost. Is formed.
[0020]
  Thus, the area occupied in the source and drain regions and the parasitic capacitance can be reduced without sacrificing the contact resistance to the upper wiring.
[0021]
  Further, the method of manufacturing a semiconductor device according to the present invention provides the length from the side edge of the source / drain region to the gate electrode in the direction perpendicular to the longitudinal direction of the gate electrode, and the gate sidewall insulation of the source / drain region. It is desirable that the height of the portion in contact with the film is longer than the height from the surface of the silicon substrate or silicon well region.
[0022]
  According to the above configuration, the source and drain regions (the aboveSecondThe overlap region between the side wall) and the gate electrode is made as small as possible, and the lengths of the source and drain regions are sufficiently secured. Therefore, a contact region between the source / drain region and the upper wiring is sufficiently secured while reducing a parasitic resistance between the source / drain region and the gate electrode.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
<First embodiment>
  FIG. 1 shows a longitudinal section of a semiconductor device formed by the semiconductor device manufacturing method of the present embodiment, which is cut perpendicular to the longitudinal direction of the gate electrode. Hereinafter, the distance in the direction perpendicular to the longitudinal direction of the gate electrode is referred to as “length”, and the distance in the longitudinal direction of the gate electrode is referred to as “width”.
[0024]
  The semiconductor device according to the present embodiment is a MISFET having a stacked source / drain region, a semiconductor substrate or a well region (hereinafter referred to as a semiconductor substrate) 41 provided in the semiconductor substrate, and an element isolation region 42. , A gate insulating film 43, a gate electrode 44, and a gate electrode side wall insulating film 45. Furthermore, it has a polycrystalline silicon side wall 48 constituting source and drain regions, and at least one of the polycrystalline silicon side walls 48 in the source and drain regions is connected to the upper wiring 52 via a contact wiring 51. Yes. Reference numeral 50 denotes an interlayer insulating film.
[0025]
  In the source and drain regions, impurities are implanted into the polysilicon side wall 48 adjacent to the gate electrode side wall insulating film 45 and above the interface between the gate insulating film 43 and the active region of the semiconductor substrate 41. And the shallow junction region 53 between the impurity layer 48 and the semiconductor substrate 41. In the present embodiment, the silicide film 49 is formed on the surfaces of the gate electrode 44 and the source / drain regions 48 in a self-aligning manner.
[0026]
  Further, the distance a between the side wall of the gate electrode 44 and the element isolation region 42 includes the film thickness b of the gate electrode side wall insulating film 45, the alignment margin c between the gate electrode 44 and the element isolation region 42, and a> It is designed so that the relationship b + c is established. The height e of the conductive layer of the gate electrode 44 is designed so that the relationship of e> g is established with the height g of the source / drain region 48 in the vicinity of the gate electrode 44.
[0027]
  A value obtained by multiplying the distance a by the gate width of the transistor (W in FIG. 7) corresponds to the area occupied by the source / drain junction region 53 on the surface of the semiconductor substrate 41. Here, the length of the source / drain junction region 53 (the value obtained by subtracting the film thickness b of the gate electrode sidewall insulating film 45 from the distance a) is determined by diffusing impurities serving as donors or acceptors from the accumulated impurity layer 48. As long as the junction can be formed in the semiconductor substrate 41, it is better that the junction resistance is reduced from the viewpoint of reducing the junction capacitance as long as the parasitic resistance is not significantly increased.
[0028]
  That is, in the present embodiment, the position of the boundary between the element isolation region 42 and the active region 54 so that a <d between the distance a and the length d of the stacked source / drain regions 48. Is set. As a result, the surface area of the source / drain region 48 is larger than the area occupied by the source / drain junction region 53 in the active region surface AA ′.
[0029]
  In the stacked structure MISFET in the present embodiment, as described above, the surface area of the source / drain region 48 is made larger than the occupied area of the source / drain junction region 53 in the active region surface AA ′. Therefore, the area occupied by the source / drain junction region 53 on the active region surface AA ′ can be reduced as compared with the conventional semiconductor device. That is, the junction area between the source / drain region 48 and the semiconductor substrate 41 can be reduced without sacrificing the contact resistance of the contact wiring 51 connected to the source / drain region 48 having a large surface area. The junction capacity can be effectively reduced.
[0030]
  In the present embodiment, the source / drain regions 48 are wide so that the length d of the stacked source / drain regions 48 and the height g in the vicinity of the gate electrode 44 have a relationship of d> g. Are stacked. By doing so, the overlap region between the source / drain region 48 and the gate electrode 44 can be made as small as possible, and a sufficient contact region between the source / drain region 48 and the upper wiring 52 can be secured.
[0031]
  As a result, as described above, the relationship between the height g of the source / drain region 48 and the height e of the conductive layer of the gate electrode 44 can be easily set to g <e. The capacitance between the gate electrode 44 and the source / drain region 48 is determined by the height g of the source / drain region 48, the film thickness b of the gate electrode sidewall insulating film 45, and the film quality (dielectric constant). Therefore, the parasitic capacitance between the gate electrode 44 and the source / drain region 48 can be made smaller than in the conventional case where the height of the stacked diffusion layer and the gate electrode is substantially equal, which is determined by the height of the gate electrode. is there.
[0032]
  Furthermore, in the present embodiment, the height of the source / drain region 48 is increased from the side edge of the source / drain region 48 toward the gate electrode 44 in a direction perpendicular to the longitudinal direction of the gate electrode 44. In this way, the surface of the source / drain region 48 is inclined. Therefore, the contact surface between the source / drain region 48 and the contact wiring 51 is inclined with respect to the axis of the contact wiring 51, and the area of the contact surface becomes larger. Therefore, the contact resistance between the source / drain region 48 and the contact wiring 51 is lowered.
[0033]
  That is, in the stacked structure MISFET according to the present embodiment, the area occupied by the source and drain regions, the parasitic capacitance, and the parasitic resistance can be reduced without sacrificing the contact resistance.
[0034]
  FIG. 8 shows a layout of a conventional stacked structure MISFET. In this stacked structure MISFET, the margin between the gate electrode 61 and the element isolation region 62 includes an opening width o of the contact hole 63, an alignment margin p for preventing the contact hole 63 from contacting the gate electrode 61, and a contact hole. 63 is the total width of the alignment margin q that does not reach the element isolation region 62. Therefore, assuming that the gate length of the stacked structure MISFET of FIG. 8 is L (generally, the gate length L is the minimum processing dimension) and the gate width is W, a margin between the gate electrode 61 and the element isolation region 62 is obtained. Requires about 2.5 L to 3 L, and the area occupied by the active region 64 is 6 LW to 7 LW (= (2.5 L × 2 + L) × W to (3L × 2 + L) × W).
[0035]
  FIG. 7 shows the layout of the stacked structure MISFET in this embodiment. Since the alignment margin is about 1/3 of the minimum processing dimension L that is the gate length, the alignment margin between the gate electrode 44 and the element isolation region 42 is about 2 / 3L (= 1 / 3L × 2). It will be good. That is, the area occupied by the active region 54 in the present embodiment is 7/3 LW (= (2 / 3L × 2 + L) × W). That is, according to the present embodiment, the occupied area of the active region 54 can be suppressed to about 1/3 to 7/18 of the occupied area of the active region 64 in FIG. Therefore, the junction parasitic capacitance per element can be reduced to about 2/9 to 4/15 as compared with the conventional stacked structure MISFET element.
[0036]
  Specifically, in the present embodiment, a stacked structure MISFET is created based on a 0.18 μm processing rule. In this case, the length a of the active region 54 is a = 0.12 μm, which can be designed to be very small compared to 0.45 μm to 0.54 μm in the case of the conventional stacked structure MISFET, and the junction parasitic capacitance is 2 It can be reduced to about / 9 to 4/15. More specifically, the well concentration is 1.0 × 10.¹⁸cm^-3The junction capacitance per 1 μm of the gate width when set to about can be reduced to about 0.7 fF, compared with about 2.6 fF to 3.1 fF in the case of the conventional stacked structure MISFET.
[0037]
  Further, the gate sidewall insulating film 45 is formed of a silicon oxide film having a thickness of 10 nm and a silicon nitride film having a thickness of 30 nm, and the total thickness b is 40 nm. The alignment margin c between the gate electrode 44 and the element isolation region 42 is about 0.07 μm (70 nm). The height e of the conductor layer of the gate electrode 44 is 200 nm, and the height g of the source / drain regions 48 is 100 nm.
[0038]
  In this case, the source and drain regions 48 and the gate electrode 44 are compared with the conventional stacked structure MISFET in which the height of the source and drain regions represented by the above-mentioned Japanese Patent Publication No. 8-2576506 is approximately the same as the height of the gate electrode. Therefore, the capacitance value per 1 μm of gate width can be reduced from about 0.24 fF to about 0.12 fF.
[0039]
  As described above, in the present embodiment, in the stacked structure MISFET, the source and drain regions 48 stacked above the surface of the active region in the semiconductor substrate 41 are perpendicular to the longitudinal direction of the gate electrode. The boundary between the active region 54 and the element isolation region 42 is located. Therefore, the area occupied by the source / drain junction region 53 on the surface AA ′ of the semiconductor substrate 41 can be reduced without reducing the surface area of the source / drain region 48. Therefore, the capacitance (junction capacitance) between the source / drain junction region 53 and the semiconductor substrate 41 can be reduced without sacrificing the contact resistance with the upper wiring 52.
[0040]
  Further, the height g of the stacked source / drain regions 48 near the gate electrode 44 is lower than the height e of the gate electrode 44. Therefore, the capacitance between the source / drain region 48 and the gate electrode 44 can be reduced as compared with the conventional stacked structure MISFET in which the height of the stacked diffusion layer in the vicinity of the gate electrode is approximately the same as the height of the gate electrode.
[0041]
  The length d of the stacked source / drain regions 48 in the direction perpendicular to the longitudinal direction of the gate electrode is longer than the height g in the vicinity of the gate electrode 44. Therefore, a sufficient contact region between the source / drain region 48 and the upper wiring 52 can be secured while reducing the parasitic resistance between the source / drain region 48 and the gate electrode 44. Further, the surface of the source / drain region 48 is inclined from the gate electrode 44 side toward the side edge. Therefore, the contact surface between the source / drain region 48 and the contact wiring 51 can be inclined with respect to the axis of the contact wiring 51 to increase the area of the contact surface. As a result, the contact resistance between the source / drain region 48 and the contact wiring 51 can be reduced.
[0042]
  That is, according to the present embodiment, it is possible to reduce the occupied area in the source and drain regions and reduce the parasitic capacitance and parasitic resistance without sacrificing the contact resistance. Therefore, the capacity required for charging the stacked structure MISFET according to the present embodiment is reduced, and the operation speed of the circuit designed using the stacked structure MISFET according to the present embodiment can be improved.
[0043]
  The length a of the active region 54, the thickness b of the gate sidewall insulating film 45, the alignment margin c between the gate electrode 44 and the element isolation region 42, the height e of the conductor layer of the gate electrode 44, the source, The value of the height g of the drain region 48 only needs to satisfy a> b + c and g <e, and is not limited to the value of the present embodiment.
[0044]
  In the present embodiment, the presence of the polycrystalline silicon sidewall 48 alleviates the vertical step by the gate electrode 44. Therefore, the planarization of the interlayer insulating film 50 on the gate electrode 44 is facilitated, and the formation of multilayer wiring is facilitated. Furthermore, there is no problem of a decrease in the selection ratio with the base stopper layer during the etching in the contact 51 formation process.
[0045]
  Further, after the source and drain regions 48 and 53 are formed by implanting impurities serving as donors or acceptors into the stacked polycrystalline silicon sidewall 48, the active region 54 is not exposed. Therefore, the active region 54 is not damaged by etching or ion implantation.
[0046]
  <Second Embodiment>
  The present embodiment relates to a method for manufacturing a semiconductor device according to the first embodiment. 2 to 5 are longitudinal sectional views of a stacked structure MISFET for explaining a method of manufacturing a semiconductor device in the present embodiment. Hereinafter, the manufacturing method of the stacked structure MISFET in the present embodiment will be described in detail with reference to FIGS. Hereinafter, the distance in the direction perpendicular to the longitudinal direction of the gate electrode is referred to as “length”, and the distance in the longitudinal direction of the gate electrode is referred to as “width”.
[0047]
  First, as shown in FIG. 2 (a), by a well-known MOS-FET process, a semiconductor substrate or a well region (hereinafter referred to as a semiconductor substrate) 41 provided on the semiconductor substrate is separated into element isolation regions 42, A gate insulating film 43, a gate electrode 44, and a gate sidewall insulating film 45 are sequentially stacked. Here, a silicon oxide film 46 is formed on the gate electrode 44 which is a polycrystalline silicon film. The gate electrode sidewall insulating film 45 is formed of a silicon oxide film and a silicon nitride film. The gate electrode side wall insulating film 45 may be composed of a single layer.
[0048]
  Next, as shown in FIG. 2B, a polycrystalline silicon film 47 is grown by chemical vapor deposition (CVD). When the polycrystalline silicon film 47 is grown, it is important to grow the polycrystalline silicon film 47 by a method that eliminates as much as possible the natural oxide film at the interface with the active region surface of the semiconductor substrate 41. This is because an impurity which becomes a donor or an acceptor is introduced into the polycrystalline silicon film 47 later, and the impurity in the polycrystalline silicon film 47 is diffused into the semiconductor substrate 41 by thermal diffusion. If an oxide film is formed at the interface between the surface and the polycrystalline silicon film 47, this oxide film acts as a diffusion barrier to inhibit uniform impurity diffusion (that is, the source / drain junction depth becomes non-uniform). This is because transistor characteristics vary.
[0049]
  Next, as shown in FIG. 3C, anisotropic etching back is performed on the polycrystalline silicon film 47 by dry etching to form a polycrystalline silicon sidewall 48 '. Next, as shown in FIG. 3D, a polycrystalline silicon film 47 ′ is formed so as to cover the polycrystalline silicon sidewall 48 ′. In that case, for the same reason as when the polycrystalline silicon film 47 is formed, polycrystalline silicon is removed by a method of eliminating the natural oxide film between the polycrystalline silicon side wall 48 ′ and the polycrystalline silicon film 47 ′ as much as possible. A film 47 ′ is formed.
[0050]
  Next, anisotropic etching back is performed until the height g of the polycrystalline silicon side wall 48 ′ becomes lower than the height e of the gate electrode 44. Finally, as shown in FIG. 4E, the length d of the polycrystalline silicon sidewall 48 is designed so that the relationship of (2p−b) <d <(2p−b + o) is established. The Here, b is the thickness of the gate electrode sidewall insulating film 45, p is an alignment margin between the gate electrode 44 and the contact hole, and o is the opening width of the contact hole (see FIG. 8).
[0051]
  When the length d of the polycrystalline silicon sidewall 48 is shorter than (2p−b) (d <2p−b), the contact hole is most misaligned with respect to the gate electrode 44 (the displacement amount of the contact hole). In the case of p), the contact wiring cannot be connected to the source region or the drain region. On the other hand, when the length d of the polycrystalline silicon sidewall 48 is longer than (2p−b + o) (d> 2p−b + o), the occupied area of the element becomes larger than that of the conventional stacked structure FET, which is not preferable.
[0052]
  Here, the length d of the polycrystalline silicon sidewall 48 is determined by the thickness h of the polycrystalline silicon film 47 (see FIG. 2B) and the height f of the step due to the gate electrode 44 (gate polycrystalline silicon film 44). The height including the upper silicon oxide film 46 (see FIG. 2A) is determined by the etching amount at the time of the etching back.
[0053]
  When the polycrystalline silicon 47 is grown by the film thickness h, as can be seen from FIGS. 2B and 4E, the length d and the height g of the formed polycrystalline silicon sidewall 48 are determined. The ratio is approximately the same as the ratio between the growth thickness h of the polycrystalline silicon 47 and the step f due to the gate electrode 44. Actually, since the shape of the polycrystalline silicon side wall 48 is convex upward, the height g of the polycrystalline silicon side wall 48 is slightly lower than the relationship of the above ratio. Considering this, the growth film thickness h of the polycrystalline silicon 47 is determined.
[0054]
  In this embodiment, when the minimum processing dimension is 0.18 μm (180 nm), the thickness b of the gate sidewall insulating film 45 is 40 nm, and the alignment margin p between the gate electrode 44 and the contact hole is 0. 0.07 μm (70 nm), the length d of the polycrystalline silicon side wall 48 is set to about 300 nm to 350 nm, the height g of the polycrystalline silicon side wall 48 is set to about 100 nm, and the height of the polycrystalline silicon layer of the gate electrode 44 e is about 200 nm, and the height f of the step due to the gate electrode 44 is about 300 nm.
[0055]
  As described above, in order to form the polycrystalline silicon sidewall 48 having a height g of about 100 nm and a length d of about 300 nm to 350 nm, the growth thickness of the polycrystalline silicon film 47 needs to be about 1000 nm. It is. Therefore, in the present embodiment, the growth thickness h of the first polycrystalline silicon film 47 is set to 700 nm, and the growth thickness of the second polycrystalline silicon film 47 ′ is set to 300 nm. In this way, the polycrystalline silicon films 47 and 47 ′ are deposited in two steps, and anisotropic etching is performed in two steps, whereby the height g of the polycrystalline silicon side wall 48 can be easily set to the gate electrode 44. The height d can be made sufficiently lower than the height e, and the length d of the polycrystalline silicon side wall 48 can be made sufficiently longer than the height g.
[0056]
  The height g of the polycrystalline silicon side wall 48 suppresses the parasitic capacitance between the gate electrode 44 and the source / drain regions, so that the metal silicide layer is formed when forming the metal silicide in a later step. Is as low as possible without reaching the surface of the active region on the semiconductor substrate 41 and destroying the shallow junction with the semiconductor substrate 41 in the source and drain regions, and is not limited to the numerical values in the present embodiment.
[0057]
  Incidentally, after forming the polycrystalline silicon film, anisotropic etching is performed by performing a photolithography process, so that the local wiring can be formed simultaneously with the formation of the polycrystalline silicon side wall. However, when the polycrystalline silicon film is grown at a time, a local wiring having a height three times as high as that of the gate electrode 44 is formed, so that it is difficult to form the upper wiring. However, in this embodiment, the polycrystalline silicon film is grown a plurality of times, and anisotropic etching back is performed for each growth. Therefore, the height of the local wiring can be suppressed by setting the growth thickness of the last polycrystalline silicon film 47 ′ to be thin.
[0058]
  The semiconductor device manufactured in the present embodiment is characterized by a structure in which the length d of the polycrystalline silicon side wall 48 that becomes the stacked source and drain regions is longer than the height g (d> g). The crystalline silicon side wall 48 has a height g lower than the height f of the conductor layer of the gate electrode 44 while ensuring a length d that can be reliably connected to the contact wiring. Therefore, as a result, it is possible to prevent an increase in the resistance of the contact for connecting the upper wiring and the source / drain region while suppressing the parasitic capacitance between the gate electrode 44 and the source / drain region. Further, since the height g of the polycrystalline silicon side wall 48 is lower than the height f of the gate electrode 44, when the metal silicide layer is formed on the surface of the source / drain region later, the reaction between the metal and polycrystalline silicon. It is possible to prevent a short circuit between the gate electrode 44 and the source / drain regions above the gate electrode 44 due to the volume expansion in the layer.
[0059]
  The anisotropic etching back for the polycrystalline silicon side wall 48 'is performed using a TCP type etching apparatus.₂= 130 sccm, pressure was 10 mTorr, TCP power was 350 W, Bottom power was 50 W.
[0060]
  Next, as shown in FIG. 4F, after the silicon oxide film 46 on the gate electrode 44 is removed by wet etching using, for example, diluted hydrofluoric acid, impurity ions are implanted to form source and drain regions. Is called. In the present embodiment, the doping of the gate electrode 44 ′ and the source / drain region 48 ″ is performed simultaneously.
[0061]
  Hereinafter, the conditions for the impurity ion implantation in this embodiment will be described. Here, the film thickness e of the polycrystalline silicon serving as the gate electrode 44 is set to about 200 nm, and the maximum height g of the polycrystalline silicon sidewall 48 is set to about 100 nm. First, in ion implantation for an n-channel transistor, phosphorus ions are implanted at an energy of about 20 keV to 80 keV and 1 × 10 6.¹⁵cm^-2~ 1x10¹⁶cm^-2Inject at a moderate dose. On the other hand, in the ion implantation for the p-channel transistor, boron ions are implanted at an energy of about 10 keV to 40 keV and 1 × 10 6.¹⁵cm^-2~ 1x10¹⁶cm^-2Inject at a moderate dose.
[0062]
  In the present embodiment, the active region of the semiconductor substrate 41 is covered with a polycrystalline silicon sidewall 48. Therefore, there is an advantage that the active region is not directly ion-implanted and the active region is hardly damaged.
[0063]
  Next, heat treatment is performed to activate the implanted impurities, and the impurities implanted into the polycrystalline silicon sidewall 48 are diffused to the semiconductor substrate 41 to form shallow source / drain junction regions 53. In this case, the standard of the heat treatment is such that impurities can be diffused to the extent that the source and drain regions 53 are not offset with respect to the gate electrode 44. Specifically, the impurity is diffused in the lateral direction by the thickness b of the gate electrode sidewall insulating film 45. In order to suppress the short channel effect and secure the driving current, it is necessary to make the junction depth as shallow as possible and to form the junction region 53 so as not to be offset with respect to the gate electrode 44.
[0064]
  Next, as shown in FIG. 4G, a refractory metal silicide film 49 is selectively formed on the source and drain regions 48 ″ and the gate electrode 44 ′ by a known silicide process. In this embodiment, the entire upper part of the source electrode 48 ″, the drain electrode 48 ″ and the gate electrode 44 ′ is silicided.
[0065]
  Next, as shown in FIG. 5H, an interlayer insulating film 50 is formed on the entire surface by a known method. Next, as shown in FIG. 5I, the contact hole 55 is opened at a desired position in the interlayer insulating film 50, and then the upper wiring 52 is formed. Thus, the source / drain region 48 ″ is connected to the upper wiring 52 through the contact wiring 51.
[0066]
  As described above, in the present embodiment, the length d of the source / drain region 48 ″, the film thickness b of the gate electrode sidewall insulating film 45, and the alignment margin between the gate electrode 44 ′ and the contact hole 55. The relationship of (2p−b) <d <(2p−b + o) is established between p and the width o of the contact hole 55. Therefore, the alignment of the contact hole 55 with respect to the gate electrode 44 ′ is established. Even in the case of the most misalignment (when the misalignment amount of the contact hole 55 is p), the contact wiring 51 and the source / drain region 48 "are reliably connected. Further, the occupied area of the element does not increase more than necessary. Further, the height g of the source / drain region 48 ″ and the height e of the gate electrode 44 ′ satisfy the relationship g <e. Therefore, the gate electrode 44 ′ and the source / drain region The capacity between 48 "can be made smaller than that of the conventional semiconductor device.
[0067]
【The invention's effect】
  As is apparent from the above, the semiconductor device manufacturing method according to the present invention has a MIS type semiconductor device having source and drain regions formed adjacent to the gate sidewall insulating film and above the surface of the silicon substrate or silicon well region. In this manufacturing method, the boundary between the active region and the element isolation region in the silicon substrate or silicon well region is perpendicular to the longitudinal direction of the gate electrode from the side edge of the gate electrode.SecondSince it is located between the side edges of the sidewalls (the source and drain regions), the area occupied by the source and drain junction regions can be made sufficiently smaller than the surface area of the source and drain regions. Therefore, the junction capacitance between the source / drain regions and the semiconductor substrate can be reduced.
[0068]
  Further, since the height of the source / drain region is increased in the direction perpendicular to the longitudinal direction of the gate electrode toward the gate electrode, the contact surface between the source / drain region and the contact wiring is formed on the contact surface. Can be tilted with respect to the wiring axis. Therefore, the contact area between the source / drain regions and the contact wiring can be increased to reduce the contact resistance.
[0069]
  Further, the height of the portion of the source / drain region in contact with the gate sidewall insulating film is made lower than the height of the gate electrode. Therefore, the capacitance between the source / drain regions and the gate electrode can be reduced.
[0070]
  Further, as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 61-196577, an expensive epitaxial growth apparatus is not required for forming the stacked diffusion layer. Therefore, the source and drain regions of the stacked structure can be formed at a very low cost.
[0071]
  That is, according to the present invention, it is possible to reduce the occupied area and the parasitic capacitance in the source and drain regions without sacrificing the contact resistance with the upper wiring. Therefore, the capacity required for charging can be reduced, and the operation speed of the circuit designed using this semiconductor device can be improved.
[0072]
  The method of manufacturing a semiconductor device according to the present invention is characterized in that a length from a side edge of the source / drain region to a gate electrode in a direction perpendicular to a longitudinal direction of the gate electrode is determined by a gate sidewall of the source / drain region. If the height from the surface of the silicon substrate or silicon well region in the portion in contact with the insulating film is longer, the parasitic resistance between the source / drain region and the gate electrode is reduced, and the source / drain region is reduced. A sufficient contact area between the upper wiring and the upper wiring can be secured.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view in a direction perpendicular to a longitudinal direction of a gate electrode in a stacked structure MISFET formed by a method of manufacturing a semiconductor device according to the present invention;
2 is a cross-sectional view showing a manufacturing method of the stacked structure MISFET shown in FIG. 1;
3 is a cross-sectional view showing a manufacturing method subsequent to FIG. 2; FIG.
4 is a cross-sectional view showing a manufacturing method subsequent to FIG. 3; FIG.
5 is a cross-sectional view showing a manufacturing method subsequent to FIG. 4; FIG.
FIG. 6 is an explanatory diagram of parasitic capacitances of a normal MISFET and a stacked structure MISFET.
7 is a diagram showing a layout of a stacked structure MISFET shown in FIG. 1; FIG.
FIG. 8 is a diagram showing a layout of a conventional stacked structure MISFET.
FIG. 9 is a diagram showing a method for manufacturing a conventional stacked structure MISFET.
10 is a diagram showing a method of manufacturing a stacked structure MISFET different from FIG. 9; FIG.
[Explanation of symbols]
  41 ... Semiconductor substrate,
42 ... element isolation region, 43 ... gate insulating film,
44 ... gate electrode, 45 ... gate electrode sidewall insulating film,
46 ... Silicon oxide film, 47, 47 '... Polycrystalline silicon film,
48,48 "... source and drain regions (polycrystalline silicon sidewalls),
48 '... polycrystalline silicon sidewall,
49 ... Silicide film, 50 ... Interlayer insulating film,
51 ... Contact wiring, 52 ... Upper wiring,
53 ... Source / drain junction region, 54 ... Active region,
55: Contact hole.

Claims (2)

Forming an element isolation region on a silicon substrate or silicon well region with a material having etching selectivity with respect to silicon etching, and dividing the silicon substrate or silicon well region into the element isolation region and an active region;
Sequentially forming a gate insulating film, a gate electrode, and a gate sidewall insulating film on the active region;
Forming a first polycrystalline silicon film so as to cover the entire surface including the element isolation region and the active region;
Performing anisotropic etching on the first polycrystalline silicon film to form a first sidewall of polycrystalline silicon adjacent to the gate sidewall insulating film;
Forming a second polycrystalline silicon film so as to cover the first sidewall of the polycrystalline silicon;
By performing anisotropic etching on the second polycrystalline silicon film and the first sidewall, the polycrystalline film is adjacent to the gate sidewall insulating film and extends to the element isolation region. Forming a second sidewall of silicon;
In a method for manufacturing a semiconductor device, comprising the step of implanting impurity ions into the second sidewall to form source and drain regions ,
The height of the second sidewall formed by the above process from the surface of the silicon substrate or silicon well region of the portion of the second sidewall that is in contact with the gate sidewall insulating film is the silicon of the gate electrode. Less than the height from the surface of the substrate or silicon well region,
In addition, the change in the height of the second sidewall from the surface of the silicon substrate or the silicon well region in the direction perpendicular to the longitudinal direction of the gate electrode decreases from the gate electrode side toward the side edge. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The length from the side edge of the source / drain region to the gate electrode in the direction perpendicular to the longitudinal direction of the gate electrode is the silicon substrate or silicon in the portion in contact with the gate sidewall insulating film of the source / drain region. A method of manufacturing a semiconductor device, wherein the height of the well region is longer than the height from the surface.

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