JP4159260B2 - Charged particle beam scanning system - Google Patents

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となる。ここで、Ｋは入力ステップ信号の振幅であり、ｔはステップ入力からの時刻を表す。図1の検査装置では、上記のステップ信号の振幅Ｋは図５のステップ電圧ΔＨであり、このステップ信号が制御出力周期Ｔ１（信号３３の周期）ごとに次々とアナログ回路に加えられ（図５の波形４４デジタル制御信号）、遅れ成分１の影響を受けたアナログ信号が出力される。そこで１つのステップ信号に対する応答出力信号ｅ１の値がｔ＝Ｔ１経過したときにとる値が、あるべき値Ｋ＝ΔＨに対して例えば誤差１％以内に収まっていれば、アナログ化された偏向制御信号１００はほぼ図５の波形４５となり、少なくとも取り込みタイミング信号３３の位よりでほぼ理想的な走査位置を指定できる。しかしｔ＝Ｔ１に於る振幅誤差１％を実現するには、信号３３の周波数の３／４倍以上の周波数帯域がアナログ回路に要求される。例えば信号３３の周波数、つまり制御出力周波数が４００ＭＨｚときアナログ回路は３００ＭＨｚ帯域が要求され、回路の実現性からも、前述したノイズ対策からも無理な条件である。
【００３８】
そこで遅れ成分１が時定数Ｔ２の１次遅れである場合の、制御周期Ｔ１の階段波４４の応答出力信号ｅ２を、スキャン開始からｔ＝ｎ・Ｔ１（ｎ＝１，２，）経過した時点で算出すると、これは（数１）のｅ１の時刻ｔ＝Ｔ１，２・Ｔ１，…，ｎ・Ｔ１に於る値を加算して得られるので、
【数２】

となる。図５の波形４６は、デジタル制御信号４４に対する遅れ成分１の応答信号波形で、（数２）はこの波形４６のｔ＝ｎ・Ｔ１（ｎ＝１，２，…）に於る値を示している。但し図５では、遅れ成分１の通過帯域は、制御出力周波数（１／Ｔ１）の１／３０倍程度の場合である。例えば、制御出力周波数が１００ＭＨｚの場合、波形４５を得るアナログ回路の帯域は７５ＭＨｚであり、アナログ回路の帯域が３．２ＭＨｚの場合は波形４６となる。
【００３９】
図５の波形４６は、（数２）からわかるように、デジタル制御信号の印加開始時刻ｔ₀（＝０）から徐々に波形４５と離れていき、時刻ｔｓ以降は波形４５との差はほぼ一定となる。また時刻ｔｓまでは直線からのずれ、即ち非直線歪みが大きい領域Ｚがあり、その後はほぼ直線となる。ここで領域Ｚは非直線歪みが許容誤差を越える領域であり、その後の波形４５との差ΔＶはｔｓ以降ほぼ一定値Ｋα／（１−α）となって、偏向位置の目標位置からの一定のずれを生じる。例えば、制御出力周波数が１００ＭＨｚ（Ｔ１＝１０ns）、アナログ回路の帯域が３．２ＭＨｚ（波形４６）かつ許容誤差が５％以内の場合は、前記誤差ΔＶによる位置ずれは、４．４９画素分であり、領域Ｚは２４画素分であることが算出できる。（数２）の第２項から分かるように、前記偏向位置ずれは、走査速度つまり各ステップ電圧ΔＨ（＝Ｋ）が大きいほど大きくなり、また、制御出力周波数（１／Ｔ１）が大きくなるか、アナログ回路の通過帯域（１／Ｔ２に比例）が小さくなる程、（数２）のαは大きくなって１に近づき、前記位置ずれをもたらす誤差電圧ΔＶと領域Ｚは大きくなる。
【００４０】
以上のように、遅れ成分１が一次遅れ系とみなせるときは、（数２）の右辺第２項が遅れ成分により生じる誤差の原因となっている。この第２項は（数１）でｔ＝ｎ・Ｔ１とおき、振幅Ｋを振幅−Ｋα／（１−α）で置き換えた値に等しいから、振幅−Ｋα／（１−α）のステップ信号を時定数Ｔ２の１次遅れ回路、即ち遅れ成分１へ印加したときのｔ＝ｎＴ１に於る値に等しい。従って本発明では、ｔ０＝０の時点に振幅が＋Ｋα（１−α）のステップ信号を補正信号として最初のデジタル基本走査信号入力時点にアナログ回路へ入力する。そうすると（数２）のｅ２はＫｎとなり、誤差項である第２項は現れない。図６（ａ）は、この補正信号を図示したものである。また図６（ｂ）は、デジタル基本走査信号と補正信号を予めデジタル的に加算したときの制御信号を示しており、最初の段差はＫ／（１−α）である。
【００４１】
ここで、遅れ成分の時定数Ｔ２は、前述した遅れ成分を含むアナログ回路特性の測定により得られる値であり、図１のシステム制御手段１０内の遅れ補正パラメータ算出手段２０にて算出される。また各ステップ電圧Ｋ＝ΔＨと制御出力周期Ｔ１は、装置定数もしくは走査パラメータとして図１のシステム制御手段１０より与えられる値であるから、補正信号の振幅Ｋα／（１−α）は容易に求まり、遅れ成分による歪みや誤差を補正できる。従って、デジタル方式のビーム走査式検査装置において、ノイズ除去フィルタを意図的に挿入することによるノイズ低減で高精度化を図り、それにより生じた遅れ成分による波形歪みおよび位置ずれを正確に補正することができ、集積回路のデザインルールの微細化等による微細欠陥検出の要求に従う分解能の向上および高精度化と、微細化および検査面積の大型化による検査時間の増大に伴なう検査時間短縮を同時に実現できる。なお、図５の領域Ｚが無視できる用途においては、走査条件の変更により変化する誤差電圧ΔＶのみを算出し、これにより生じる位置ずれのみを補正するようにしてもよい。
【００４２】
次に、バイアホール検査のように、より多くの画素データを高速読み取りする場合の動作を述べる。前記のように補正信号を加えると、得られたアナログ偏向制御信号の波形は、広帯域特性を持つアナログ回路で得られた波形４５とは時刻ｔ＝ｎ・Ｔ１（ｎ＝１，２…）で一致するが、その他の時刻では異なってくる。今図７に示したように、補正後の出力波形４６の、時刻ｎ・Ｔ１＋ｃ（０≦ｃ≦１）に於る値Ｖ３から、この時点の理想的出力値Ｖ１を差引いたリプル電圧ｅ３を求めると次式となる。
【数３】

この（数３）でα＝０とおいたときのｅ３の値は、広帯域特性を持つアナログ回路で得られた波形４５の場合に相当し、この波形４５の方が補償したときよりリプル電圧は大きいことを示している。また（数３）のリプル電圧ｅ３は、ｎの値が変っても変らない。そこでこのリプルの最大電圧を許容誤差以内に収めれば、制御出力周期Ｔ１に関係無く、画像取り込みタイミング信号３３の画像取り込み周期を自由に設定できる。この場合、図７の電圧Ｖ１が画素間隔の制御電圧となり、その誤差はｅ３である。
【００４３】
以上から、平滑化に必要な遅れ成分の時定数が算出できる。いま、高速動作時の画像取り込み周期Ｔ１を制御出力周期Ｔ１の１／２、かつ誤差が画素間隔の５％以内の条件の場合、平滑化に必要な遅れ成分の時定数は制御出力周期Ｔ１の約５倍である。正確に５倍である場合、その誤差は４．９９％である。この場合、（遅れ成分周波数）＝１／２π（時定数）の関係があるので、例えば、制御出力周波数を１００ＭＨｚとすると、３．２ＭＨｚ以下の遅れ成分が必要となる。また、リプルにより正方向に誤差があることを考慮して、画像取り込みタイミング信号を制御出力周期のタイミングよりも数％程度早く出力すると精度向上につながる。前記パーセンテージは、正確には（数３）を利用して算出できる。このようにして、デジタル偏向走査信号を平滑化するためのフィルタ（遅れ成分）を意図的に挿入し、平滑化された滑らかな波形の状態で、遅れ成分による波形歪みおよび位置ずれを前記のようにして補正信号により補正すれば、偏向制御出力タイミングに関係なく、所定の画素の取り込み周期を自由に設定できるので、超高速検査が要求されるバイアホール検査も容易に行えるようになる。
【００４４】
以上に述べた図１の構成と動作では、主にノイズ除去を行うためのフィルタ挿入を前提としていたが、ここでこのフィルタについて改めて述べる。一般に、オペアンプの出力雑音電圧ｅ４は、（数４）により求められる。
【数４】

ここで、ＥNは入力雑音電圧密度、ＧNはゲイン、ＢＷは周波数帯域である。ＥNはトータルの入力雑音電圧密度であり、電流ノイズ、電圧ノイズ、抵抗の熱雑音の２乗平均により求められる。これらを総合した入力雑音電圧密度Ｅｎは、低ノイズタイプの高速アンプでは通常、数ｎV／√（Ｈｚ）である。ここで例えば、入力電圧雑音密度を１ｎV／√（Ｈｚ）、帯域を４００ＭＨｚ、ゲインを２倍とすると、オペアンプの出力雑音電圧は４０μＶとなる。前記検査装置において、電子ビームを０．０５μｍ間隔で検出を行い、４００μｍの偏向範囲を振幅４Ｖで走査し、かつ許容誤差が検査間隔の１０分の１以下である場合、許容誤差は５０μＶである。これは前記オペアンプの出力雑音電圧４０μＶにほぼ等しく、許容誤差の限界を示している。さらに、前記オペアンプの出力雑音電圧ｅ４は実効値を示しており、ピーク値としては０．１％の確率でその±３．３倍のノイズが存在することになる。従ってアナログ回路の周波数帯域幅を制限せざるとえず、遅れ成分１としてフィルタを挿入することになる。入力電圧雑音密度Ｅｎを常識的な値である５ｎV／√（Ｈｚ）程度にしたときには、上記の許容誤差５０μＶに十分収まるフィルタ帯域を前記実効係数も考慮に入れ算出すると、その帯域は数ＭＨｚとなる。以上より、上記検査装置の要求仕様レベルの場合、数ＭＨｚ〜数１０ＭＨｚの帯域を持つフィルタが望まれる。また、従来技術で述べたように、比較的低い周波数の外来ノイズの混入も考えられ、これらのノイズ対策上からもこのような帯域制限が望ましい。そしてこの帯域制限を行った上で、前述の補正を行うことで、高精度かつ高速な検査装置が実現可能となる。
【００４５】
次に、遅れ成分１が１次遅れではなく、２次以上の遅れ要素である場合について述べる。例えば、時定数Ｔ２の遅れ成分が２つ結合した２次遅れの場合、制御周期Ｔ１の階段波の応答出力信号ｅ５は、（数５）となる。
【数５】

ここで右辺第２項は、階段波の１段目の段差が生じるタイミング（図５のｔ₀＝０）に加えられた振幅−Ｋα／（１−α）のステップ信号が、時定数Ｔ２の遅れ成分が２つ結合した２次遅れ回路を通過した場合の、時刻ｔ＝ｎ・Ｔ１に於ける値に等しい。また、（数５）の右辺第３項は、階段波の１段目の段差が生じるタイミングｔ₀＝０に加えられた振幅−Ｋ（Ｔ１／Ｔ２）α／（１−α）²のステップ信号が、遅れ成分が時定数Ｔ２の１次遅れ回路を通過した場合の、時刻ｔ＝ｎ・Ｔ１に於ける値に等しい。従って補正信号としては、前記第２項を打ち消すため、振幅＋Ｋα／（１−α）のステップ信号をｔ₀＝０の時点で２次遅れ回路へ入力し、また、前記第３項を打ち消すため、振幅＋Ｋ（Ｔ１／Ｔ２）α／（１−α）²のステップ信号をｔ₀＝０の時点で後段の１次遅れ回路へ入力すればよい。
【００４６】
時定数Ｔ２とＴ３の遅れ成分が２つ結合した２次遅れの場合、制御周期Ｔ１の階段波の応答出力信号ｅ６は、（数６）となる。
【数６】

この右辺第２項は、ｔ₀＝０のタイミングに加えられた振幅−Ｋα／（１−α）・Ｔ２／（Ｔ２−Ｔ３）のステップ信号が、遅れ成分が時定数Ｔ２の１次遅れ回路を通過した場合の、時刻がｔ＝ｎ・Ｔ１に於ける値と等しく、また（数６）の右辺第３項は、ｔ₀＝０のタイミングに加えられた振幅−Ｋβ／（１−β）・Ｔ３／（Ｔ３−Ｔ２）のステップ信号が、遅れ成分が時定数Ｔ３の１次遅れ回路を通過した場合の、時刻がｔ＝ｎ・Ｔ１に於ける値と等しい。従って補正信号としては、前記第２項を打ち消すため、振幅＋Ｋα／（１−α）・Ｔ２／（Ｔ２−Ｔ３）のステップ信号を、ｔ₀＝０の時点で前段の時定数Ｔ２の１次遅れ回路へ入力し、また、前記第３項を打ち消すため、振幅＋Ｋβ／（１−β）・Ｔ３／（Ｔ３−Ｔ２）のステップ信号を、ｔ₀＝０の時点で後段の時定数Ｔ３の１次遅れ回路へ入力すればよい。
【００４７】
同様な手法によって、より高次の遅れについてもその補正を行うことができる。但し、誤差範囲内の成分は省略したり、または、近似関数を求め、その関数にしたがった補正方法を選択してもよい。また高次フィルタの特性には、チェビシェフ特性、バタワース特性、ベッセル特性などがあるが、入力信号が階段波であることを考慮すると、リンギングが生じるため、チェビシェフ特性となる構成は避けるべきである。バタワース特性となる場合はリンギングが生じにくく、ベッセル特性となる場合は全くリンギングが生じない。このように高次の遅れ成分は、構成によってピークを持つ場合があり、波形を乱すことがあるため、あまり複雑な構成の遅れ成分は好ましくない。さらに一般に高次の遅れ補正は、その補正手段が複雑になり、またそれらの補正手段は予め用意する必要があるため、可能な限り、挿入する遅れ成分は１次遅れ程度になるようにすべきである。また、回路の設計指針としては、大部分は挿入する遅れ成分の１桁以上広帯域の設計を行い、最終段に１次程度の大きな遅れ成分を挿入することが望ましい。
【００４８】
次に、図１の遅れ成分補正手段１８を含む偏向制御手段１１の具体的な構成例を説明する。図８は、図６（ａ）に示した方法で補正を行う時の偏向制御手段１１を示したブロック図で、補正量演算部１１３は、走査管理部１１１から階段波の段差量Ｋ＝ ΔＨ、制御出力周期Ｔ１、遅れ成分の時定数Ｔ２を含むパラメータＰMを受け取り、図６（ａ）の補正信号の振幅、即ち
【数７】

を算出する。ＤＡ変換部１１４はこれをアナログ補正量に変換し、走査管理部１１１からの走査開始信号ＴＭが入力された時点より出力する。こうして生成されたステップ状の補正信号ＡＭはＤＡ変換部１１２から出力された補正前の偏向制御信号とアナログ加算器１１５で加算され、こうして図６（ａ）に示した方法で遅れ成分に対する補正が行われる。
【００４９】
図９は、図８の構成の変形例で、図６（ｂ）に示した補正方法に該当する。補正量演算部１１３は図８と同じ（数７）の補正量ＭＤを算出するが、これを内蔵するレジスタへ保持し、走査開始信号ＴＭの入力時点より出力する。このデジタル値と補正前のデジタル偏向制御信号とがデジタル加算器１１５Ｂで加算された後、ＤＡ変換部１１２でアナログ化され、補正信号を含むアナログ信号が遅れ成分１へ入力される。
【００５０】
ここで補正信号自体の演算誤差を考える。まず補正信号の電圧精度の影響は、ステップ信号の振幅ＭＤの大きさに関連する。例えば、ステップ信号の振幅ＭＤが１０画素間隔の量と同じ場合位置ずれの許容誤差を１０％（１／１０画素）とすると振幅ＭＤには１％の誤差が許容できる。補正信号の時刻精度の影響は、誤差時間をａ、階段数をｎとすると、誤差電圧ｅ７は次式となる。
【数８】

ここで制御出力周波数が１／Ｔ１＝１００ＭＨｚ、遅れ成分が１／（２π）Ｔ２＝１．６ＭＨｚ、許容誤差が１／１０画素の場合、制御出力周期（１０ns）の１／１０程度許容できる。従って補正信号には特に高い精度が求められることはない。
【００５１】
図１０は、時定数Ｔ２を持つ２つの遅れ成分１Ａ、１Ｂが存在する２次遅れの場合の遅れ成分補正手段１８の構成例である。この場合は、補正量演算部１１３Ｂは２つの補正信号の振幅ＭＤ１、ＭＤ２を算出する。
【数９】

ＤＡ変換部１１４Ｂ、１１４Ｃはこれらのデジタル値ＭＤ１、ＭＤ２をアナログ信号に変換しアナログ補正信号の振幅ＭＡ１、ＭＡ２を生成し、これを走査開始信号ＴＭの入力時点より出力する。このうち信号ＭＡ１は補正前のアナログ制御信号と加算器１１５Ｃで加算されたのち初段の１次遅れ成分１Ａへ入力され、この出力と信号ＭＡ２とが加算器１１５Ｄで加算されて後段の一次遅れ成分１Ｂへ入力され、こうして２次遅れ成分による歪み等の補正が行われる。なお、２つの１次遅れ成分の間での加算が困難な回路構成の場合は、別に時定数Ｔ２の遅れ成分を用意してこれに補正信号ＭＡ２を入力し、その出力を遅れ成分１Ｂの出力と加算するようにしてもによい。
【００５２】
図１１は、時定数Ｔ２とＴ３の遅れ成分１Ｃ、１Ｄの２つが結合した２次遅れの場合の遅れ成分補正手段１８の構成例である。この場合は、補正量演算部１１３Ｃは次式により２つ振幅ＭＤ３、ＭＤ４を算出する。
【数１０】

そしてＤＡ変換部１１４Ｂでアナログ化した信号ＭＡ３は後段の遅れ成分１Ｄへ入力し、ＤＡ変換部１１４Ｃでアナログ化した信号ＭＡ４は、補正用に別に設けた１次遅れ成分（時定数Ｔ２）１１６へ入力する。この遅れ成分１１６出力は遅れ成分１Ｄ出力と加算される。２つのＤＡ変換器１１４Ｂ、１１４Ｃが出力開始するのは走査開始信号ＴＡの入力以降である。なお、２つの遅れ成分１Ｃ、１Ｄの間での加算が困難なときは、もう１つの時定数Ｔ３の遅れ成分を用意してこれに信号ＭＡ３を入力し、その出力を遅れ成分１Ｄの出力点で加算するようにしてもよい。
【００５３】
同様にして、遅れ成分の次数が更に高くなったときでもそのために生じる誤差を補正する信号を導くことができ、正確な補正が可能である。但し、あまり特殊な構成の遅れ成分を挿入すると、対応した複雑な補正手段を用意することが必要となる。遅れ成分の挿入はノイズ低減や平滑化が目的であることから、遅れ成分をあまり複雑にすることは補正手段をも複雑にすることになり好ましくない。
以上、上記構成により、補正手段は走査条件に従い逐次正確な補正信号を生成でき、走査条件の変更により変化する遅れ成分の歪みが補正可能となる。
【００５４】
以上で本発明の特徴とする補正方法とその具体的な構成を詳細に述べたが、最後に装置全体の動作に関連した操作について述べる。まず、遅れ成分の測定および補正手段へのパラメータ転送等を行う測定モードと通常の検査時に補正を実施する補正モードは、システム全体の系で実施するものであり、かつ全ての装置に実施するものであるので、一連のシーケンスを実施するシステムコマンドを用意する必要があり、また作業マニュアルを用意する必要がある。
【００５５】
上述の測定もしくは補正時に発生する作業は、測定モードでは、システム制御部に対し走査を行う既知パターンの位置やパターンデータのロードや、既知パターンが描かれている試料の試料室へのロード（既にロードされている場合やステージに備え付けられている場合は必要ない）、走査条件の入力、測定実行入力、遅れ成分の特性算出演算実行入力などがある。
【００５６】
補正モードでは、システム制御手段１０から偏向制御手段１１への補正データの転送、遅れ補正の実行コマンド入力などがあり、また、測定自身をシステム的に行わない場合などは、補正手段にパラメータを渡すためのロード作業が必要となる。この場合、前記システムコマンドを用意すると、全てを自動で短時間に行うことができる。あらかじめシステム制御部にコマンド登録をしておくと、各補正アライメント時やキャリブレーション時に容易に自動実行することも可能である。
【００５７】
操作パネルを用いると、走査条件が変更された時に、実行確認が提示され、実行を選択するなど、操作パネルの指示に従って行うことで作業者のミスをなくす効果がある。また、測定結果の視覚的表示、履歴データとしての記録を行うことで、全体管理が容易となる。
【００５８】
なお、以上では電子ビーム走査によるウエハ等の検査装置について詳細を述べたが、本発明は、ビーム光源からのビームを偏向してビーム走査を行うすべての装置、例えば描画装置、顕微鏡（ＳＥＭ）などを含む荷電粒子ビーム走査式装置にも応用可能であることは明らかである。
【００５９】
【発明の効果】
本発明によれば、以下の効果がある。
（１）走査条件を容易に可変設定可能なデジタル偏向制御方式を用いて高精度かつ高速走査が可能な荷電粒子ビーム走査式装置が実現でき、これをウエハ等の検査装置に用いれば、集積回路のデザインルールの微細化等による微細欠陥検出が高い精度で行え、かつ微細化および検査面積の大型化に対しても検査時間の短縮をはかれる効果がある。
（２）偏向位置の誤差を生じさせずに、デジタル偏向走査信号の平滑化が可能となり、制御出力周期より短い周期での走査位置指定が容易に行え、ウエハ等の検査装置で例えばバイアホール（スルーホール）底の残留物検査などを高速かつ十分な精度行える効果がある。
（３）走査信号の非直線部分を用いないときは、位置ずれの補正のみを行えばよく、より簡単な構成で高速かつ高精度な走査が可能になる。
【図面の簡単な説明】
【図１】 本発明の荷電粒子ビーム走査式装置の構成例を示す概略ブロック図である。
【図２】遅れ成分測定モードの処理手順を示すフローチャートである。
【図３】遅れ成分測定系の説明図である。
【図４】アナログ走査信号の説明図である。
【図５】デジタル式偏向回路の走査信号説明図である。
【図６】 １次遅れ成分補正方法の説明図である。
【図７】遅れ成分補正時の走査信号の詳細説明図である。
【図８】１次遅れ成分に対する補正回路の例である。
【図９】図８の変形例である。
【図１０】同じ時定数の２つの１次遅れ成分があるときの補正回路の例である。
【図１１】時定数の異なる２つの１次遅れ成分があるときの補正回路の例である。
【符号の説明】
１ 遅れ成分
１０ システム制御手段
１１ 偏向制御手段
１２ 偏向器
１３ 荷電粒子ビーム
１４ 試料
１５ 画像処理手段
１６ ビーム照射タイミング信号
１７ 遅れ成分測定手段
１８ 遅れ成分補正手段
１９ 走査制御手段
２０ 遅れ補正パラメータ算出手段
２１ 基準信号発生手段
３２ 画像取り込み開始信号
３３ 画像取り込みタイミング信号
３４ 画像取り込み有効信号
１１１ 走査管理部
１１２、１１４、１１４Ｂ、１１４Ｃ ＤＡ変換部
１１３、１１３Ｂ、１１３Ｃ 補正量演算部
１１５、１１５Ｂ、１１５Ｃ、１１５Ｄ 加算器[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charged particle beam scanning apparatus for irradiating a predetermined position with a charged particle beam, and more particularly to a charged particle beam scanning apparatus suitable for an automatic inspection apparatus that needs to control the beam irradiation position at high speed and with high accuracy. .
[0002]
[Prior art]
The charged particle beam scanning type automatic inspection device deflects the charged particle beam and scans the inspection object such as a wafer or mask to obtain an image showing the physical properties of the inspection object, and obtains the acquired image pattern. It is known to test by comparing or evaluating. As for this charged particle beam scanning type automatic inspection apparatus, Japanese Patent Laid-Open No. 5-258703 discloses a deflection control apparatus in which a deflection circuit section for generating a charged particle beam scanning signal is constituted by an analog integration circuit. The signal generated by this analog method is a ramp waveform, and the controllable state quantities are a slope value that is a ramp wave inclination amount and a retrace value that is a ramp wave return amount. The slope of the analog signal specified by the slope value is compared with the line size value that is the adjustment value, and the offset specified by the retrace value is compared with the offset value that is the adjustment value. The signal is kept constant. The slope of the ramp wave is preferably a constant straight line, but in such an analog system, the ramp wave slope has a non-linear portion called linear distortion. If this non-linear part is used as a deflection signal, an error in the deflection position will occur. Therefore, only the part that maintains the linearity accuracy near the center of the ramp slope part is used as a deflection signal by using an analog voltage comparison circuit. I use it.
[0003]
In the deflecting device of the charged particle scanning apparatus, there are many factors that cause the positional deviation of the beam irradiation position in addition to the non-linearity error of the ramp wave inclined portion, and one of them is an error caused by the optical system of the deflector. There is some deflection distortion. Japanese Patent Application Laid-Open No. 7-22303 discloses a deflection control device of an electron beam drawing apparatus equipped with the deflection distortion correction circuit. An electron beam lithography system changes the physical properties of a sample by deflecting an electron beam to a predetermined position on the sample such as a wafer or mask, and irradiates electrons to draw patterns such as transistors, memories, and wiring The electron beam deflection control method is similar to that of the inspection apparatus, but the scanning method and required specifications are different. The deflection control device described in Japanese Patent Application Laid-Open No. 7-22303 uses a line generator having the same configuration as the analog integration circuit. Also, the deflection distortion correction method described in Japanese Patent Laid-Open No. 7-22303 is called a lookup table method and operates as follows. First, the analog value of the analog ramp wave of the line generator is A / D converted, and the digital value is input to the memory as an address. In the memory, a correction value for the address is input in advance, and the correction amount is output as a digital value. The digital value of the correction amount is D / A converted to obtain an analog correction signal, which is added to the analog ramp wave to correct deflection distortion. In this method, an analog circuit that generates a scanning signal and a digital circuit that generates a correction signal are mixed. Thus, in order to perform various corrections, a method of performing processing digitally is more suitable than an analog method.
[0004]
In the above known example, a ramp wave realized by an analog circuit is used as a basic scanning signal. However, in Japanese Patent Laid-Open No. 2000-100322, a staircase obtained by stepwise designation of a digital value and DA conversion. A digital method using a wave as a basic scanning signal is disclosed. In this method, scanning control and various corrections can be performed using digital operations based on the scanning signal deflection position, various apparatus error information, irradiation position height information, etc. There is a feature that it is possible to improve the accuracy of the beam irradiation position and the degree of freedom of beam scanning by correcting the position error.
[0005]
In such a deflection device of a charged particle scanning apparatus of digital type, when high-speed scanning is performed, the operation speed is limited by a delay component of an electronic circuit. Examples of delay components in electronic circuits include frequency characteristics of elements such as amplifiers, changes in frequency characteristics caused by floating circuits that cannot be ignored at high frequencies, noise (mixed noise, amplifier noise, etc.), glitches (digital feedthrough noise), etc. And a filter circuit used for adjusting characteristics such as ringing of an amplifier. These delay components increase the time (settling time) required for the DA conversion output to fall within a predetermined error range of the target value. When DA conversion is performed at a time interval shorter than the settling time, the output waveform is distorted. Therefore, the delay component limits the DA conversion output interval for performing accurate deflection control. Considering this problem in the case of an inspection apparatus such as a wafer, there is no problem if the time constant of the formed filter and the memory delay time are sufficiently smaller than the control output period or the capture period of pixels that are elements of the image. When the period becomes small, the deflection control signal is greatly distorted due to the frequency characteristics of the elements used and the delay component due to the floating circuit, which causes a decrease in deflection position accuracy and an obstacle to speeding up.
[0006]
An example of an attempt to compensate for a delay component in such a digital method is shown in an electron beam drawing apparatus disclosed in Japanese Patent Laid-Open No. 7-106964. In this prior art, the settling time is shortened by adding a pulse signal which is a pseudo impulse signal to a step signal which is an output of DA conversion.
[0007]
[Problems to be solved by the invention]
In an inspection apparatus for wafers or the like, it is strongly desired to improve the resolution in accordance with the demand for fine defect detection by miniaturization of the design rule of an integrated circuit, and this resolution largely depends on the deflection scanning position accuracy. High precision is desired. However, miniaturization further increases the inspection time, which takes an enormous amount of time in the past. For example, the conventional inspection time is on the order of 10 hours for the entire inspection of an 8-inch wafer. In addition, with the increase in inspection area due to the recent increase in wafer size, the entire inspection of a 12-inch wafer is on the order of several tens of hours. Since the inspection time increases in proportion to the accuracy, further increase in the inspection time due to miniaturization becomes a major obstacle to the inspection performance. Therefore, shortening of the inspection time is eagerly desired. For this purpose, it is essential to increase the deflection speed. As described above, both high precision and high speed of the deflection position control are required. However, since these are inherently in a contradictory (tradeoff) relationship, there has already been a limit to pursue simultaneously.
[0008]
Here, the problem of high accuracy and high speed will be described in detail. In the digital deflection control method, it has a bit number that realizes sufficient resolution, can specify the position with high accuracy, and even if DA conversion is possible, the minimum resolution is limited if noise is included in the deflection signal Therefore, noise reduction is indispensable for improving accuracy. As the required accuracy of the inspection apparatus, for example, when detection is performed with an electron beam at intervals of 0.1 μm and deflection is performed over a deflection range of several hundreds of μm, the tolerance is ideally less than one tenth of the interval. Therefore, a positional error of 0.01 μm or less is required. This means positioning with an error of tens of thousands or less of a deflection range of several hundred μm. Further, when the distance is 0.05 μm, double the accuracy is required. If the deflection range of several hundreds of μm is deflected with a maximum amplitude of 4V at 0.05 μm intervals, the deflection voltage can only have an error of 200 μV or less. On the other hand, the noise voltage due to the amplifier noise for generating the deflection voltage is already 200 μV when the amplifier voltage noise density is 5 nV / √ (Hz), the bandwidth is 400 MHz, and the gain is twice, for example, and becomes the limit value of the allowable error. End up. Here, the voltage noise density is close to the limit of a feasible low noise amplifier, the band is a value considering the passage of a step wave with a step width of 10 ns, and the gain 2 is an ultrahigh speed DA conversion output (2V). This value is converted to 4V. If the required speed is increased, the band is further increased, so that the noise specifications become severe.
[0009]
In order to reduce noise, in the case of the above example, it is desired to use a filter (low-pass type) having a cutoff frequency of several MHz to several tens of MHz. In addition, it is conceivable that external noise having a relatively low frequency is mixed, and in order to remove these noises, it is desired to use a filter with a narrow band as described above. On the other hand, there is a demand to increase the maximum amplitude voltage for the purpose of reducing the influence of external noise. For this purpose, the amplification factor of the amplifier is increased, and the frequency band is narrowed accordingly. Thus, in order to prevent noise for higher accuracy, it is required to narrow the frequency band of the deflection voltage generation circuit.
[0010]
However, narrowing the band will cause a large delay component, restricting the passage of the staircase wave, which is the deflection scanning signal, as described above, causing distortion in the output waveform, and hindering speedup. Become. In order to examine this speed-up problem in detail, as an example, when D / A conversion is performed at an inspection interval of 0.1 μm and 200 MHz and a filter frequency of 1.6 MHz passes through the circuit, nonlinear distortion of the scanning waveform The non-negligible part is about 650 ns from the scanning start point, and the non-linear distortion is reduced thereafter, but an error of 1.95 μm or more from the target position occurs. Therefore, one of the effects of the delay component is a problem that there is a deviation from the position specified by the digital value. This positional deviation varies depending on the scanning conditions and is not constant. Therefore, the error of the scanning position varies from inspection to inspection, and accurate position deflection control cannot be performed unless accurate correction is performed. In particular, in a digital deflection circuit, this correction method has been a major issue because it generates free scanning signals such as rotating the scanning direction or starting scanning from a free position.
[0011]
Further, the influence of the portion where the non-linear distortion cannot be ignored becomes an obstacle to speeding up. For example, when the capture frequency is 400 MHz and the number of pixels captured in one scan is 500 pixels, the scan time of one scan is 1.25 μs. Therefore, the time width of 650 ns in which the nonlinear distortion cannot be ignored is more than half of the scan time. This is a wasted time. That is, only half or less of 500 pixels can be inspected. Even if the deflection speed is increased in this way, the effective inspection speed is limited if there is nonlinear distortion due to a delay component.
[0012]
Further, in an inspection apparatus for wafers or the like, there is a demand for a variable speed function that operates at a high speed when accuracy requirements are low and operates at a low speed when high accuracy measurement is required. When performing residue inspection on the bottom of a via hole (through hole) formed on a wafer, the resolution, that is, the accuracy may be the same as before, but there is a need to increase the number of inspections or to perform online inspection. Therefore, a mode for inspecting at a speed of about 2 to several times as high as the above is required. Moreover, since this inspection can be performed only by an electron beam scanning inspection apparatus, the variable speed function as described above is required. To realize this requirement, in the digital deflection circuit, the scanning signal is the same during normal wafer inspection and via hole inspection, and it is easy to shorten the period of image capture timing only during via hole inspection. It is. If it does so, the inspection speed at the time of a via hole inspection will become large. However, for this purpose, it is necessary to convert the staircase wave into a sufficiently smooth ramp wave with a smoothing filter, and to keep the deviation from the ideal ramp wave within a desired error at any point of time. Therefore, the delay component due to the smoothing filter becomes a problem in terms of realizing the variable speed function.
[0013]
From the above-mentioned points, when the electron beam lithography system is configured using a digital deflection system deflection circuit, a noise removal filter is intentionally inserted to achieve high accuracy by noise reduction, and the resulting delay component A solution that corrects as much as possible the waveform distortion and misalignment caused by the above is considered a reasonable method. Considering the delay component compensation method disclosed in Japanese Patent Laid-Open No. 7-106964 again in this respect, firstly, in this conventional method, a correction pulse must be generated every time the digital value changes, Considering a wafer inspection apparatus having a staircase width of several ns, there is a problem that it is actually difficult to generate a pulse wave having a width of several ns or less as a correction signal. Secondly, in the above-described prior art, the stepped unevenness becomes large, and it is impossible to increase the speed by changing the image capturing timing.
[0014]
A first object of the present invention is to realize both high accuracy (resolution improvement) and high speed (inspection time reduction) by sufficiently removing noise by a filter and compensating for a delay component generated by the filter. To provide a charged particle beam scanning apparatus of a digital deflection system.
[0015]
A second object of the present invention is to provide a digital deflection type charged particle beam scanning apparatus that supports an ultra-high-speed inspection mode necessary for via-hole inspection and the like and can be switched to normal high-precision inspection. That is.
[0016]
[Means for Solving the Problems]
The present invention relates to a charged particle beam scanning apparatus including a deflection unit that deflects a charged particle beam and a deflection control unit that generates a scanning signal for controlling deflection of the charged particle beam by the deflection unit.
The deflection control means includes
Basic scanning signal generating means for generating a stepwise basic scanning signal in which the amplitude value increases by a given step amount for each given control output period;
A filter provided in the basic scanning signal output circuit for band-limiting the basic scanning signal generated by the means;
The control output cycle, the step amount, and the time constant representing the delay characteristic of the output circuit including the filter from the basic scan signal generation means to the deflection means as the basic scan signal are input. Correction signal generating means for generating a correction signal for causing the output value to coincide with the value of the basic scanning signal at a reference time point when the value of the basic scanning signal changes stepwise;
Disclosed is a charged particle beam scanning apparatus characterized by comprising addition means for adding the correction signal generated by this means and the basic scanning signal.
[0017]
Furthermore, in the charged particle beam scanning apparatus according to the present invention, the charged particle beam scanning position error caused by noise included in the output value of the output circuit is less than or equal to an allowable value for the passband width of the filter. A charged particle beam scanning apparatus characterized by the above is disclosed.
[0018]
Furthermore, in the charged particle beam scanning apparatus, the present invention determines the passband width of the filter so that values at all times other than the reference time of the output circuit are equal to or less than a predetermined error. Disclosed is a charged particle beam scanning apparatus.
[0019]
Furthermore, the present invention provides an image acquisition means for acquiring a product generated from a sample by scanning of a charged particle beam at each reference time point and acquiring image data relating to the sample in the charged particle beam scanning apparatus. Disclosed is a charged particle beam scanning apparatus characterized in that image data acquired by means is analyzed to inspect the sample.
[0020]
Further, the present invention provides the above-mentioned charged particle beam scanning apparatus, and an acquisition signal generating means for generating a time series of acquisition points whose period can be variably set irrespective of the control output period which is the interval between the reference time points. Providing an image acquisition means for acquiring a product generated by scanning of the charged particle beam at every acquisition time point of the acquisition signal and acquiring image data relating to the sample, and analyzing the image data acquired by the means to analyze the sample Disclosed is a charged particle beam scanning apparatus characterized by performing an inspection.
[0021]
Furthermore, the present invention provides a reference signal generating means for generating a reference signal and inputting the reference signal to the output circuit in the charged particle beam scanning apparatus, and a response output signal of the output circuit when the reference signal is input. Disclosed is a charged particle beam scanning apparatus comprising: an output circuit response acquisition means for acquiring; and a time constant calculation means for calculating a time constant of the output circuit from a response output signal obtained by the means. .
[0022]
In the charged particle beam scanning apparatus, the present invention further provides a reference signal generating means for generating a reference signal and inputting the reference signal to the output circuit, and deflection control by the output of the output circuit when the reference signal is input. Time constant calculating means for analyzing the image data acquired by the image acquisition signal when the charged particle beam is irradiated onto the sample that generates the known pattern and calculating the time constant of the output circuit. A featured charged particle beam scanning device is disclosed.
[0023]
Further, in the charged particle beam scanning apparatus according to the present invention, when the control output cycle is T1, the step amount is K, and the output circuit is approximated to a first-order lag element of a time constant T2, The correction signal generating means generates a step signal having an amplitude of Kexp (-T1 / T2) / (1-exp (-T1 / T2)) and a rising time point coincident with a start time point of the basic scanning signal, and adding the step signal. A means discloses a charged particle beam scanning apparatus characterized in that the basic scanning signal and the step signal are added and then input to the output circuit.
[0024]
Furthermore, in the charged particle beam scanning apparatus according to the present invention, the control output period is T1, the step amount is K, and the output circuit includes a first primary delay element having a time constant T2 and the first delay element. When approximated to a second-order lag element consisting of a second first-order lag element having the same time constant T2 cascaded to the element, the correction signal generating means has an amplitude of Kexp (-T1 / T2) / (1-exp (-T1 / T2)) and the first step signal whose rise time coincides with the start time of the basic scanning signal, and the amplitude is K (T1 / T2) exp (-T1 / T2) / (1-exp (- T1 / T2)) ² And generating a second step signal whose rising time coincides with the start time of the basic scanning signal, and the adding means adds the first step signal and the basic scanning signal to input the output circuit. In addition, a charged particle beam scanning apparatus is disclosed in which the second step signal is added to the first first-order lag element output to obtain the second first-order lag element input. To do.
[0025]
Furthermore, in the charged particle beam scanning apparatus according to the present invention, the control output cycle is T1, the step amount is K, and the output circuit is cascaded with a primary delay element having a time constant T2 and this element. When approximated to a second-order lag element composed of a second first-order lag element of the connected time constant T3, a third-order lag element of time constant T2 is provided, and the correction signal generating means has an amplitude of Kexp. The first step signal whose rising time coincides with the start time of the basic scanning signal at (−T1 / T3) · T3 / (T3-T2) / (1-exp (−T1 / T3)), and the amplitude is Kexp Generating a second step signal whose rising time point coincides with the start time point of the basic scanning signal at (−T1 / T2) · T2 / (T2−T3) / (1−exp (−T1 / T2)); The adding means includes the first step signal and the previous step signal. A signal obtained by adding the first primary delay element output to the input of the second primary delay element and inputting the second step signal to the third primary delay element; Disclosed is a charged particle beam scanning apparatus configured to add to the second first-order lag element output.
[0026]
Furthermore, the present invention relates to a charged particle beam scanning apparatus including a deflection unit that deflects a charged particle beam and a deflection control unit that generates a scanning signal for controlling the deflection of the charged particle beam by the deflection unit.
The deflection control means includes
Basic scanning signal generating means for generating a stepwise basic scanning signal in which the amplitude value increases by a given step amount for each given control output period;
A filter provided in the basic scanning signal output circuit for band-limiting the basic scanning signal generated by the means;
The control output cycle, the step amount, and the time constant representing the delay characteristic of the output circuit including the filter from the basic scan signal generation means to the deflection means as the basic scan signal are input. In a scanning time region where the amount of nonlinear distortion in the output is less than or equal to a predetermined value, the output value of the output circuit matches the value of the basic scanning signal at a reference time point when the value of the basic scanning signal changes stepwise. Correction signal generating means for generating a correction signal having a constant value for
Adding means for adding the correction signal generated by the means and the basic scanning signal;
And a charged particle beam scanning apparatus that performs charged particle beam scanning only in the scanning time region.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing a configuration example of a charged particle beam scanning apparatus of the present invention, which is an application example to an automatic inspection apparatus such as a wafer. However, FIG. 1 shows only the part related to the present invention. The deflection control means 11 is a digital system that uses a staircase wave obtained by stepwise designation of a digital value and DA conversion as a basic scanning signal, and has a time constant equal to or greater than the digital control output period. Which has a delay component 1 that can be easily realized by a filter. The effect of intentionally inserting the delay component 1 is firstly reduction of noise or instantaneous fluctuation of the deflection control signal, thereby greatly contributing to improvement of accuracy of the inspection apparatus. Secondly, each step of the staircase wave (step width is several ns) of the deflection control signal is smoothed, so that the pixel capture cycle can be freely switched regardless of the deflection control output timing. Therefore, it is possible to realize a higher inspection speed and a variable inspection speed function than the conventional one. However, since the delay component causes the deflection control signal to be distorted as described above and the inspection speed is increased, a means for correcting it is indispensable. In particular, the digital method is very problematic because a free scanning signal is generated such as rotating the scanning direction or starting scanning from a free position. Therefore, it is necessary to have a correction unit that corrects the light according to the scanning conditions such as the scanning speed. In order to satisfy the second effect, the staircase wave must remain smooth even after correction.
[0028]
First, a simple inspection operation of the inspection apparatus of FIG. 1 will be shown, and then specific operations of each part in the present invention will be shown. In FIG. 1, the system control unit 10 determines an inspection sequence, and transfers various scanning parameters and commands including correction parameters from the scanning control unit 19 to the deflection control unit 11. The deflection control means 11 deflects the charged particle beam 13 by controlling the voltage applied to the deflector 12 according to the parameters, and scans the target position on the sample 14 such as a wafer or mask. The product generated at that time is taken in as information on the sample 14, and the image processing means 15 processes this product information as pixel data of the beam deflection position, thereby obtaining image data of the sample 14. As a product from the material 14, FIG. 1 shows the case of secondary electrons. However, as long as it reflects the information of the sample, it is possible to transmit either secondary electrons or reflected electrons. It may be an electron. Further, the image processing means 15 obtains a beam irradiation timing signal 16 for defining the beam scanning position and the timing for capturing the information from the deflection control means 11 for deflecting the beam to a predetermined position. The acquired image data is compared with the image or design data having the same pattern on the sample in the image processing means 15, and the result is used by the system control means 10 for evaluation of a portion having a difference in pattern and process management. Inspection is performed by performing data processing.
[0029]
In the above operation, the delay component correction process is roughly divided into two stages. One is a measurement mode for measuring the delay component, which measures the distortion of the deflection control signal that changes largely and slowly, and calculates a delay correction parameter for correcting the delay component. The second mode is a correction mode in which a delay component is corrected during normal inspection, and correct correction is performed from the correction parameter and the scan parameter for each scan.
[0030]
In the measurement mode, first, for the purpose of measuring the lag component, various scanning parameters are transferred from the scanning control means 19 included in the system control means 10 to the deflection control means 11 in the same manner as the above-described normal inspection. Image data of a known pattern drawn at a position where an image can be detected is obtained by the lag component measuring means 17. The delay correction parameter calculation means 20 obtains the time constant of the delay component from the obtained image data of the known pattern according to the procedure shown in FIG. That is, the deflection position at the time of scanning is actually calculated from the image data obtained from the delay component measuring means 17 of the image processing means 15 and the deflection position information that should be obtained in designing when a known pattern is scanned (step). 201), the amount of displacement, which is the amount of distortion of the deflection scanning signal, is calculated (step 202). Next, an approximate function representing the distortion is derived from the positional deviation amount by a statistical method (step 303). In this process, the distortion of the scanning signal due to the delay component changes greatly and gradually with respect to the change in position, so there is no need to calculate the position for all the pixels accurately to calculate the delay component, and the pixels are thinned out. Statistical processing is possible. Next, a delay component parameter such as a time constant for one or a plurality of delay components is calculated from the approximate function, and a delay component correction parameter necessary for the delay component correction unit 18 implemented by the deflection control unit 11 is calculated. Is calculated (step 204). The above measurement mode is performed in advance of the actual inspection, and the calculated delay component correction parameter is transferred to the delay component correction means 18 as an apparatus constant.
[0031]
As described above, it is possible to easily measure the distortion of the lag component by providing the lag component measuring means 17 in the image processing means 15, and this measurement measures the characteristics of the deflection circuit in the same operation state as the inspection. Therefore, an accurate value can be obtained. In addition, the measurement sensitivity is improved by changing the scanning parameters such as the scanning speed (pixel interval) and performing the measurement several times.
[0032]
In addition, although the example which used image data was shown above as a delay component measuring method, if this can calculate the distortion amount by a delay component, it can also be replaced with another form. For example, even if the known pattern is a linear pattern arranged at equal intervals and the time crossing between patterns is measured based on a signal detected during scanning, the amount of distortion due to the delay component can be approximately calculated. is there. Further, as shown in FIG. 3A, the deflection scanning signal 16a that should be taken out from the deflection control means 11, and the output deflection scanning signal 100 is taken in, and the amount of distortion is obtained by the deflection signal measuring means 17a. It may be. When only the analog part of the deflection control means 11 is measured, the scanning control means 19 uses a reference signal other than the scanning signal as shown in FIG. Characteristics can be measured. For example, the frequency sweep signal 16b is output as the reference signal from the reference signal generating means 21, and this is input to the analog part of the deflection control means 11, and the output is taken into the deflection signal measuring means 17b. The correction parameter calculation means 20 can calculate delay component parameters such as the time constant of the delay component by calculating frequency response characteristics using Fourier transform. However, it is assumed that the analog portion includes a delay component 1 provided for noise removal or the like. Thus, if the characteristic of the delay component is known by some method, the correction mode described later can be operated, and the operation of the correction mode is not limited by the measurement method.
[0033]
In the correction mode for correcting the delay component at the normal inspection, the delay component correction means 18 included in the deflection control means 11 is based on the correction parameters given from the system control means 10 and the scan parameters for each scan. An accurate correction value is calculated and an operation for giving the correction value to the deflection control signal is performed. The evaluation of the delay component correction can be easily performed by measuring the deflection position and calculating the distortion amount in a state where the delay component correction is performed. Hereinafter, the operation of the delay component correction means 18 will be described in detail.
[0034]
FIG. 4 is a diagram for explaining a relationship between an analog output and an example of a typical timing signal showing an example of the deflection control signal. However, here, for the sake of simplicity, a deflection control signal output from an analog deflection circuit is shown. The scanning of the sample on the two-dimensional plane by the electron beam is usually performed by a raster scanning method. In the figure, a deflection control signal waveform for one raster is shown. This waveform generally takes the shape of a ramp wave 30 (solid line). Since this ramp wave 30 is not a perfect straight line, if sample information is captured at a timing given at regular intervals on the time axis, the pixel capture intervals on the sample are not uniform. This causes an error in the inspection process using the pixel data. Therefore, when high-precision inspection is required, only the time region in which the ramp wave 30 can be regarded as a substantially straight line 31 (broken line) is used. . Scanning for inspection is performed with both ends of this time region as the start and end.
[0035]
Signals used for image acquisition with respect to the deflection control signal of FIG. 4 include an image capture start signal 32, an image capture timing signal 33 that is a synchronization signal, an image capture valid signal 34, and the like. The beam irradiation timing signal 16 in FIG. 1 specifically shows these signals, and in particular, the image capture timing signal 33 corresponds as a representative signal. These signals are input to the image processing means 15 in FIG. The image processing means 15 captures wafer information as pixels at the rising edge of the image capture timing signal 33 when the image capture valid signal 34 is active, and obtains a pattern image on the sample. The time width TS of the ramp wave use region in FIG. 4 is determined from the capture interval of one pixel and the number of pixels captured in one scan, and the height of the ramp wave (more precisely, the potential difference in the use region of the ramp wave) H is the wafer. It is determined by the control voltage value for the upper pixel interval and the distance on the wafer and the number of pixels in one scan.
[0036]
The basic method for capturing pixel data using an analog deflection circuit has been described for the sake of simplicity. However, in the case of the digital deflection circuit of FIG. 1, the influence of the delay component 1 must be taken into account. . FIG. 5 shows a deflection control signal generated by a digital method. In the digital system, the deflection control signal is a staircase wave, and each step is accurately synchronized with the image capture timing signal 33. In the digital method, the pixel interval can be set by each step voltage ΔH, and the scan start position can be set by the scan start voltage V0. However, it is easy to set these to a desired value at any time. The scanning start position can be freely set and various position errors can be corrected freely. As described above, the digital method has a feature that the controllability is much better than the analog method, but it is necessary to remove the influence caused by the delay component 1 as described above.
[0037]
Considering the case where the delay component 1 is a first-order lag of the time constant T2, the response output signal e1 to the step signal is
[Expression 1]

It becomes. Here, K is the amplitude of the input step signal, and t represents the time from the step input. In the inspection apparatus of FIG. 1, the amplitude K of the step signal is the step voltage ΔH of FIG. 5, and this step signal is added to the analog circuit one after another at every control output cycle T1 (cycle of the signal 33) (FIG. 5). Waveform 44 digital control signal), an analog signal affected by the delay component 1 is output. Therefore, if the value of the response output signal e1 for one step signal when t = T1 elapses is within, for example, an error of 1% with respect to the desired value K = ΔH, the analog deflection control is performed. The signal 100 has substantially the waveform 45 shown in FIG. 5, and an almost ideal scanning position can be designated at least at the position of the capture timing signal 33. However, in order to realize an amplitude error of 1% at t = T1, a frequency band of 3/4 times the frequency of the signal 33 is required for the analog circuit. For example, when the frequency of the signal 33, that is, the control output frequency is 400 MHz, the analog circuit is required to have a 300 MHz band, which is an unreasonable condition both from the feasibility of the circuit and from the above-described noise countermeasures.
[0038]
Therefore, when the delay component 1 is the first-order lag of the time constant T2, the response output signal e2 of the staircase wave 44 of the control period T1 has elapsed t = n · T1 (n = 1, 2,) from the start of scanning. Since this is obtained by adding the values at time t = T1, 2 · T1,..., N · T1 of e1 in (Equation 1),
[Expression 2]

It becomes. A waveform 46 in FIG. 5 is a response signal waveform of the delay component 1 with respect to the digital control signal 44, and (Equation 2) indicates a value at t = n · T1 (n = 1, 2,...) Of the waveform 46. ing. However, in FIG. 5, the pass band of the delay component 1 is about 1/30 times the control output frequency (1 / T1). For example, when the control output frequency is 100 MHz, the band of the analog circuit that obtains the waveform 45 is 75 MHz, and when the band of the analog circuit is 3.2 MHz, the waveform 46 is obtained.
[0039]
The waveform 46 in FIG. 5 is the application start time t of the digital control signal, as can be seen from (Equation 2). ₀ The waveform 45 gradually moves away from (= 0), and the difference from the waveform 45 becomes substantially constant after the time ts. Further, there is a region Z where the deviation from the straight line, that is, the nonlinear distortion is large until the time ts, and the line becomes almost straight thereafter. Here, the region Z is a region where the non-linear distortion exceeds the allowable error, and the difference ΔV from the subsequent waveform 45 becomes a substantially constant value Kα / (1-α) after ts, and the deflection position is constant from the target position. Cause a shift. For example, when the control output frequency is 100 MHz (T1 = 10 ns), the analog circuit band is 3.2 MHz (waveform 46), and the allowable error is within 5%, the positional deviation due to the error ΔV is 4.49 pixels. Yes, it can be calculated that the area Z is for 24 pixels. As can be seen from the second term of (Equation 2), does the deflection position deviation increase as the scanning speed, that is, each step voltage ΔH (= K) increases, and does the control output frequency (1 / T1) increase? As the pass band of the analog circuit (proportional to 1 / T2) decreases, α in (Expression 2) increases and approaches 1, and the error voltage ΔV and the region Z that cause the positional deviation increase.
[0040]
As described above, when the delay component 1 can be regarded as a first-order lag system, the second term on the right side of (Equation 2) causes an error caused by the delay component. Since this second term is equal to the value obtained by replacing t = n · T1 in (Equation 1) and the amplitude K with the amplitude −Kα / (1-α), the step signal of amplitude −Kα / (1-α) is obtained. Is equal to the value at t = nT1 when applied to the first-order lag circuit of time constant T2, ie, lag component 1. Therefore, in the present invention, a step signal having an amplitude of + Kα (1−α) at the time t0 = 0 is input as a correction signal to the analog circuit at the time of the first digital basic scanning signal input. Then, e2 in (Expression 2) becomes Kn, and the second term which is an error term does not appear. FIG. 6A illustrates the correction signal. FIG. 6B shows a control signal when the digital basic scanning signal and the correction signal are digitally added in advance, and the first step is K / (1-α).
[0041]
Here, the time constant T2 of the delay component is a value obtained by measuring the analog circuit characteristics including the delay component described above, and is calculated by the delay correction parameter calculation means 20 in the system control means 10 of FIG. Each step voltage K = ΔH and the control output cycle T1 are values given by the system control means 10 in FIG. 1 as device constants or scanning parameters, so that the amplitude Kα / (1-α) of the correction signal can be easily obtained. , Distortion and error due to delay components can be corrected. Therefore, in a digital beam scanning inspection apparatus, high accuracy is achieved by reducing noise by intentionally inserting a noise removal filter, and waveform distortion and positional deviation due to a delay component caused thereby are accurately corrected. Simultaneously improve the resolution and accuracy according to the requirements of fine defect detection by miniaturization of integrated circuit design rules, etc., and shorten the inspection time along with the increase of inspection time by miniaturization and enlargement of inspection area realizable. Note that in applications where the region Z in FIG. 5 can be ignored, it is possible to calculate only the error voltage ΔV that changes due to the change of the scanning condition and correct only the positional deviation caused by this.
[0042]
Next, an operation in the case of reading a larger amount of pixel data at high speed as in the via hole inspection will be described. When the correction signal is applied as described above, the waveform of the obtained analog deflection control signal is different from the waveform 45 obtained by the analog circuit having the broadband characteristic at time t = n · T1 (n = 1, 2,...). It matches, but is different at other times. As shown in FIG. 7, the ripple voltage e3 obtained by subtracting the ideal output value V1 at this time from the value V3 at the time n · T1 + c (0 ≦ c ≦ 1) of the output waveform 46 after correction is obtained. The following formula is obtained.
[Equation 3]

The value of e3 when α = 0 in (Equation 3) corresponds to the case of the waveform 45 obtained by an analog circuit having a wideband characteristic, and the ripple voltage is larger than when the waveform 45 is compensated. It is shown that. Further, the ripple voltage e3 in (Equation 3) does not change even if the value of n changes. Therefore, if the maximum voltage of the ripple is within an allowable error, the image capturing period of the image capturing timing signal 33 can be freely set regardless of the control output period T1. In this case, the voltage V1 in FIG. 7 is the control voltage for the pixel interval, and the error is e3.
[0043]
From the above, the time constant of the delay component necessary for smoothing can be calculated. If the image capture cycle T1 during high-speed operation is 1/2 of the control output cycle T1 and the error is within 5% of the pixel interval, the time constant of the delay component required for smoothing is the control output cycle T1. About 5 times. If it is exactly 5 times, the error is 4.99%. In this case, since there is a relationship of (delay component frequency) = 1 / 2π (time constant), for example, if the control output frequency is 100 MHz, a delay component of 3.2 MHz or less is required. Considering that there is an error in the positive direction due to ripple, the accuracy can be improved by outputting the image capture timing signal several percent earlier than the timing of the control output cycle. The percentage can be accurately calculated using (Equation 3). In this way, the filter (delay component) for smoothing the digital deflection scanning signal is intentionally inserted, and the waveform distortion and the position shift due to the delay component are as described above in the smoothed smooth waveform state. If correction is performed using the correction signal, a predetermined pixel capture period can be freely set regardless of the deflection control output timing, and a via-hole inspection requiring an ultra-high-speed inspection can be easily performed.
[0044]
In the configuration and operation of FIG. 1 described above, it is assumed that a filter is inserted mainly for noise removal. Here, this filter will be described again. In general, the output noise voltage e4 of the operational amplifier is obtained by (Equation 4).
[Expression 4]

Here, EN is the input noise voltage density, GN is the gain, and BW is the frequency band. EN is the total input noise voltage density, and is obtained by the mean square of current noise, voltage noise, and thermal noise of resistance. The combined input noise voltage density En is usually several nV / √ (Hz) in a low-noise type high-speed amplifier. Here, for example, if the input voltage noise density is 1 nV / √ (Hz), the band is 400 MHz, and the gain is doubled, the output noise voltage of the operational amplifier is 40 μV. In the inspection apparatus, when the electron beam is detected at an interval of 0.05 μm, a deflection range of 400 μm is scanned with an amplitude of 4 V, and the allowable error is less than 1/10 of the inspection interval, the allowable error is 50 μV. . This is approximately equal to the output noise voltage of 40 μV of the operational amplifier, indicating a limit of allowable error. Furthermore, the output noise voltage e4 of the operational amplifier shows an effective value, and as a peak value, there is a noise of ± 3.3 times as high as a probability of 0.1%. Therefore, the frequency bandwidth of the analog circuit must be limited, and a filter is inserted as the delay component 1. When the input voltage noise density En is set to about 5 nV / √ (Hz), which is a common value, if the filter band that is sufficiently within the above-described allowable error 50 μV is calculated in consideration of the effective coefficient, the band is several MHz. Become. From the above, in the case of the required specification level of the inspection apparatus, a filter having a band of several MHz to several tens of MHz is desired. Further, as described in the prior art, mixing of external noise having a relatively low frequency is also conceivable, and such band limitation is desirable from the viewpoint of noise countermeasures. Then, by performing the above-described correction after performing the band limitation, a high-precision and high-speed inspection apparatus can be realized.
[0045]
Next, the case where the delay component 1 is not a first-order delay but a second-order or higher-order delay element will be described. For example, in the case of a second-order delay in which two delay components of the time constant T2 are combined, the response output signal e5 of the staircase wave of the control period T1 is (Expression 5).
[Equation 5]

Here, the second term on the right side is the timing at which the first step of the staircase wave occurs (t in FIG. 5). ₀ = 0) and the step signal of amplitude −Kα / (1-α) passes through a second-order delay circuit in which two delay components of the time constant T2 are combined at time t = n · T1. Is equal to The third term on the right side of (Equation 5) is the timing t at which the first step of the staircase wave occurs. ₀ = Amplitude added to 0-K (T1 / T2) α / (1-α) ² The step signal is equal to the value at time t = n · T1 when the delay component passes through the first-order delay circuit having the time constant T2. Therefore, as the correction signal, in order to cancel the second term, a step signal of amplitude + Kα / (1−α) is t ₀ = 0 (T1 / T2) α / (1−α) in order to input to the second-order lag circuit at the time of = 0, and to cancel the third term ² Step signal of t ₀ What is necessary is just to input into a 1st delay circuit of a back | latter stage at the time of = 0.
[0046]
In the case of a secondary delay in which two delay components of the time constants T2 and T3 are combined, the response output signal e6 of the staircase wave of the control period T1 is (Expression 6).
[Formula 6]

The second term on the right side is t ₀ = 0 when the step signal of amplitude −Kα / (1-α) · T2 / (T2−T3) added to the timing of 0 passes through the first-order delay circuit whose delay component is the time constant T2. = N · T1 and the third term on the right side of (Equation 6) is t ₀ = 0 when the step signal of amplitude −Kβ / (1-β) · T3 / (T3−T2) added to the timing of 0 passes through the first-order delay circuit whose delay component is the time constant T3. = Equal to the value at n · T1. Therefore, as the correction signal, in order to cancel the second term, a step signal of amplitude + Kα / (1−α) · T2 / (T2−T3) is expressed as t ₀ Is input to the first-order lag circuit of the preceding time constant T2 at the time of = 0, and in order to cancel the third term, a step signal of amplitude + Kβ / (1-β) · T3 / (T3-T2) is t ₀ What is necessary is just to input into the first order delay circuit of the time constant T3 of a back | latter stage at the time of = 0.
[0047]
A similar technique can be used to correct higher order delays. However, components within the error range may be omitted, or an approximate function may be obtained and a correction method according to the function may be selected. The characteristics of the high-order filter include Chebyshev characteristics, Butterworth characteristics, and Bessel characteristics. However, considering that the input signal is a staircase wave, ringing occurs, so a configuration that has Chebyshev characteristics should be avoided. When the Butterworth characteristic is obtained, ringing hardly occurs, and when the Bessel characteristic is obtained, no ringing occurs. As described above, the high-order delay component may have a peak depending on the configuration, and the waveform may be disturbed. Therefore, the delay component having a very complicated configuration is not preferable. More generally, the correction means for high-order delay correction is complicated, and these correction means need to be prepared in advance. Therefore, the delay component to be inserted should be about the first order delay as much as possible. It is. As a circuit design guideline, for the most part, it is desirable to design a wide band of one or more digits of the delay component to be inserted, and to insert a large delay component of about the first order in the final stage.
[0048]
Next, a specific configuration example of the deflection control unit 11 including the delay component correction unit 18 of FIG. 1 will be described. FIG. 8 is a block diagram showing the deflection control means 11 when correction is performed by the method shown in FIG. 6A. The correction amount calculation unit 113 receives a step amount K = ΔH from the scan management unit 111. The parameter PM including the control output period T1 and the time constant T2 of the delay component is received, and the amplitude of the correction signal in FIG.
[Expression 7]

Is calculated. The DA conversion unit 114 converts this into an analog correction amount, and outputs it from the time when the scanning start signal TM from the scanning management unit 111 is input. The step-like correction signal AM generated in this way is added by the analog adder 115 with the deflection control signal before correction output from the DA converter 112, and thus the delay component is corrected by the method shown in FIG. Done.
[0049]
FIG. 9 is a modification of the configuration of FIG. 8 and corresponds to the correction method shown in FIG. The correction amount calculation unit 113 calculates the same correction amount MD as in FIG. 8 (Equation 7), but holds this in a built-in register and outputs it from the input time point of the scanning start signal TM. The digital value and the digital deflection control signal before correction are added by the digital adder 115 </ b> B, then converted into an analog signal by the DA converter 112, and an analog signal including the correction signal is input to the delay component 1.
[0050]
Here, the calculation error of the correction signal itself is considered. First, the influence of the voltage accuracy of the correction signal is related to the magnitude of the amplitude MD of the step signal. For example, when the amplitude MD of the step signal is the same as the amount of the 10-pixel interval, if the allowable error of the positional deviation is 10% (1/10 pixel), the amplitude MD can have an error of 1%. The influence of the time accuracy of the correction signal is that the error voltage e7 is expressed by the following equation, where the error time is a and the number of steps is n.
[Equation 8]

Here, when the control output frequency is 1 / T1 = 100 MHz, the delay component is 1 / (2π) T2 = 1.6 MHz, and the allowable error is 1/10 pixel, about 1/10 of the control output period (10 ns) is allowable. Accordingly, the correction signal is not required to have particularly high accuracy.
[0051]
FIG. 10 is a configuration example of the delay component correction means 18 in the case of a secondary delay in which two delay components 1A and 1B having a time constant T2 exist. In this case, the correction amount calculation unit 113B calculates the amplitudes MD1 and MD2 of the two correction signals.
[Equation 9]

The DA converters 114B and 114C convert these digital values MD1 and MD2 into analog signals to generate analog correction signal amplitudes MA1 and MA2, and output them from the input time point of the scan start signal TM. Of these signals, the signal MA1 is added to the analog control signal before correction by the adder 115C and then input to the first-order first delay component 1A. The output and the signal MA2 are added by the adder 115D to be the first-order delay component of the subsequent stage. 1B, and thus correction of distortion or the like due to the second-order lag component is performed. In addition, in the case of a circuit configuration in which addition between two first-order lag components is difficult, a lag component with a time constant T2 is prepared separately, and a correction signal MA2 is input thereto, and the output is output as the lag component 1B. May be added.
[0052]
FIG. 11 is a configuration example of the delay component correction means 18 in the case of a second-order delay in which two delay components 1C and 1D of the time constants T2 and T3 are combined. In this case, the correction amount calculation unit 113C calculates two amplitudes MD3 and MD4 by the following equation.
[Expression 10]

The signal MA3 analogized by the DA converter 114B is input to the delay component 1D in the subsequent stage, and the signal MA4 analogized by the DA converter 114C is supplied to the first-order lag component (time constant T2) 116 separately provided for correction. input. This delay component 116 output is added to the delay component 1D output. The two DA converters 114B and 114C start outputting after the input of the scanning start signal TA. When addition between the two delay components 1C and 1D is difficult, another delay component with a time constant T3 is prepared, and the signal MA3 is input to this, and the output is the output point of the delay component 1D. You may make it add by.
[0053]
Similarly, even when the order of the delay component is further increased, a signal for correcting an error caused thereby can be derived, and accurate correction is possible. However, if a delay component with a very special configuration is inserted, it is necessary to prepare a corresponding complicated correction means. Since the insertion of the delay component is aimed at noise reduction and smoothing, it is not preferable to make the delay component too complicated because it also complicates the correction means.
As described above, the correction unit can sequentially generate an accurate correction signal according to the scanning condition, and can correct the distortion of the delay component that changes due to the change of the scanning condition.
[0054]
Although the correction method and the specific configuration characteristic of the present invention have been described in detail above, finally, operations related to the operation of the entire apparatus will be described. First, the measurement mode for measuring the delay component and transferring parameters to the correction means, and the correction mode for performing correction during normal inspection are performed in the entire system and are performed for all devices. Therefore, it is necessary to prepare a system command for executing a series of sequences and to prepare a work manual.
[0055]
In the measurement mode, the work that occurs during the measurement or correction described above is the loading of the position of the known pattern and pattern data to be scanned with respect to the system control unit, and the loading of the sample in which the known pattern is drawn into the sample chamber (already This is not necessary when loaded or provided on the stage), scanning condition input, measurement execution input, delay component characteristic calculation calculation execution input, and the like.
[0056]
In the correction mode, there are transfer of correction data from the system control means 10 to the deflection control means 11, input of execution commands for delay correction, and the like, and parameters are passed to the correction means when the measurement itself is not performed systematically. Loading work is required. In this case, if the system commands are prepared, all can be automatically performed in a short time. If commands are registered in the system control unit in advance, they can be automatically executed at the time of each correction alignment or calibration.
[0057]
When the operation panel is used, an execution confirmation is presented when the scanning condition is changed, and execution is selected according to an instruction on the operation panel. Moreover, the overall management is facilitated by visual display of measurement results and recording as history data.
[0058]
Although the details of the inspection apparatus for wafers and the like by electron beam scanning have been described above, the present invention applies to all apparatuses that perform beam scanning by deflecting the beam from the beam light source, such as a drawing apparatus and a microscope (SEM). It is apparent that the present invention can be applied to a charged particle beam scanning apparatus including
[0059]
【The invention's effect】
The present invention has the following effects.
(1) A charged particle beam scanning apparatus capable of high-accuracy and high-speed scanning can be realized by using a digital deflection control system in which scanning conditions can be variably set, and if this is used for an inspection apparatus such as a wafer, an integrated circuit Fine defects can be detected with high accuracy by miniaturizing the design rule, and the inspection time can be shortened with respect to miniaturization and enlargement of the inspection area.
(2) The digital deflection scanning signal can be smoothed without causing an error in the deflection position, and the scanning position can be easily specified in a cycle shorter than the control output cycle. For example, a via hole ( Through hole) It is effective to perform inspection of residues at the bottom at high speed and with sufficient accuracy.
(3) When the non-linear portion of the scanning signal is not used, it is only necessary to correct the misalignment, and high-speed and high-accuracy scanning is possible with a simpler configuration.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a configuration example of a charged particle beam scanning apparatus of the present invention.
FIG. 2 is a flowchart showing a processing procedure in a delay component measurement mode.
FIG. 3 is an explanatory diagram of a delay component measurement system.
FIG. 4 is an explanatory diagram of an analog scanning signal.
FIG. 5 is an explanatory diagram of scanning signals of a digital deflection circuit.
FIG. 6 is an explanatory diagram of a first-order lag component correction method.
FIG. 7 is a detailed explanatory diagram of a scanning signal at the time of delay component correction.
FIG. 8 is an example of a correction circuit for a first-order lag component.
FIG. 9 is a modification of FIG.
FIG. 10 is an example of a correction circuit when there are two first-order lag components having the same time constant.
FIG. 11 is an example of a correction circuit when there are two first-order lag components with different time constants.
[Explanation of symbols]
1 Delay component
10 System control means
11 Deflection control means
12 Deflector
13 Charged particle beam
14 samples
15 Image processing means
16 Beam irradiation timing signal
17 Delay component measuring means
18 Delay component correction means
19 Scanning control means
20 Delay correction parameter calculation means
21 Reference signal generating means
32 Image capture start signal
33 Image capture timing signal
34 Image capture enable signal
111 Scan management unit
112, 114, 114B, 114C DA converter
113, 113B, 113C Correction amount calculation unit
115, 115B, 115C, 115D Adder

Claims (3)

In a charged particle beam scanning apparatus comprising: a deflection unit that deflects a charged particle beam; and a deflection control unit that generates a scanning signal for controlling the deflection of the charged particle beam by the deflection unit.
The deflection control means includes
Basic scanning signal generating means for generating a stepwise basic scanning signal in which the amplitude value increases by a given step amount for each given control output period;
A filter provided in the basic scanning signal output circuit for band-limiting the basic scanning signal generated by the means;
The control output cycle, the step amount, and the time constant representing the delay characteristic of the output circuit including the filter from the basic scan signal generation means to the deflection means as the basic scan signal are input. Correction signal generating means for generating a correction signal for causing the output value to coincide with the value of the basic scanning signal at a reference time point when the value of the basic scanning signal changes stepwise;
The correction signal generated and by adding said basic scanning signal by means, and an adding means for outputting a scanning signal for controlling the deflection of the charged particle beam Rutotomoni,
A reference signal generating means for generating a reference signal and inputting it to the output circuit, and a charged particle beam whose deflection is controlled by the output of the output circuit when the reference signal is input is irradiated to a sample for generating a known pattern A charged particle beam scanning apparatus characterized by comprising time constant calculating means for analyzing image data acquired by the image acquisition signal from time to time and calculating a time constant of the output circuit . In a charged particle beam scanning apparatus comprising: a deflection unit that deflects a charged particle beam; and a deflection control unit that generates a scanning signal for controlling the deflection of the charged particle beam by the deflection unit.
The deflection control means includes
Basic scanning signal generating means for generating a stepwise basic scanning signal in which the amplitude value increases by a given step amount for each given control output period;
A filter provided in the basic scanning signal output circuit for band-limiting the basic scanning signal generated by the means;
The control output cycle, the step amount, and the time constant representing the delay characteristic of the output circuit including the filter from the basic scan signal generation means to the deflection means as the basic scan signal are input. Correction signal generating means for generating a correction signal for causing the output value to coincide with the value of the basic scanning signal at a reference time point when the value of the basic scanning signal changes stepwise;
Addition means for adding the correction signal generated by this means and the basic scanning signal and outputting as a scanning signal for controlling the deflection of the charged particle beam,
The control output cycle is T1, the step amount is K, and the output circuit is connected to a first first-order lag element having a time constant T2 and a second 1 having the same time constant T2 cascaded to this element. When approximated to a second order delay element comprising a second delay element, the correction signal generating means has an amplitude of K exp (−T1 / T2) / (1− exp (−T1 / T2)) and the rising point is the basic scan. A first step signal that coincides with the signal start time, and the amplitude is K (T1 / T2) exp (-T1 / T2) / (1- exp (-T1 / T2)) 2 and the rising time is the basic scanning signal. A second step signal that coincides with the start time of the first step signal, and the adding means adds the first step signal and the basic scanning signal as an input to the output circuit, and the second step signal. To the first first-order lag element output to A charged particle beam scanning apparatus characterized by being configured to receive a second primary delay element input .
. In a charged particle beam scanning apparatus comprising: a deflection unit that deflects a charged particle beam; and a deflection control unit that generates a scanning signal for controlling the deflection of the charged particle beam by the deflection unit.
The deflection control means includes
Basic scanning signal generating means for generating a stepwise basic scanning signal in which the amplitude value increases by a given step amount for each given control output period;
A filter provided in the basic scanning signal output circuit for band-limiting the basic scanning signal generated by the means;
The control output cycle, the step amount, and the time constant representing the delay characteristic of the output circuit including the filter from the basic scan signal generation means to the deflection means as the basic scan signal are input. Correction signal generating means for generating a correction signal for causing the output value to coincide with the value of the basic scanning signal at a reference time point when the value of the basic scanning signal changes stepwise;
Addition means for adding the correction signal generated by this means and the basic scanning signal and outputting as a scanning signal for controlling the deflection of the charged particle beam,
The control output cycle is T1, the step amount is K, and the output circuit includes a first order lag element having a time constant T2 and a second first order lag element having a time constant T3 cascaded to the element. When a second order lag element is approximated, a third order lag element having a time constant T2 is provided, and the correction signal generating means has an amplitude of K exp (−T1 / T3) · T3 / (T3−T2). / (1- exp (-T1 / T3)), the first step signal whose rising time coincides with the start time of the basic scanning signal, and the amplitude is K exp (-T1 / T2) .T2 / (T2-T3) ) / (1- exp (-T1 / T2)) to generate a second step signal whose rising time coincides with the start time of the basic scanning signal, and the adding means includes the first step signal and the second step signal. Adding the first first-order lag element output to the second 1 Characterized in that delay the elements of the input and configured to sum said second said step signal of the third signal obtained by inputting the primary delay element and the second primary delay element output A charged particle beam scanning device.

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