JP4160043B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to an arrangement of external pin terminals in a semiconductor integrated circuit device incorporating a semiconductor memory device. More specifically, the present invention relates to the arrangement of power supply pin terminals, data input / output pin terminals, and peripheral signal pin terminals in a general-purpose DRAM (dynamic random access memory).

  FIG. 26 schematically shows a chip layout of a conventional semiconductor memory device disclosed in, for example, Japanese Patent Laid-Open No. 3-214669 (Patent Document 1). 26, the semiconductor memory device is formed on a semiconductor chip 1100 and includes four memory blocks MB1, MB2, MB3, and MB4. Each of memory blocks MB1-MB4 includes a plurality of memory cells. During normal operation (external access), a 1-bit memory cell is selected in each of memory blocks MB1 to MB4 to write / read data (in the case of × 4 configuration).

  In the central region of semiconductor chip 1100 (region between memory blocks MB1 and MB3 and memory blocks MB2 and MB4), pads for receiving power supply voltage and ground voltage from the outside and pads for inputting and outputting signals are arranged. Such a configuration in which the pads are arranged in the center area of the chip is known as a lead-on-chip (LOC) arrangement, and the tip of the lead frame is arranged above the chip, and the pads are arranged in the center area of the chip. The lead frame is connected by wire bonding. Since the pads are arranged in a line in the chip central region, the pad occupation area can be reduced as compared with the configuration in which the pads are arranged along both sides of the peripheral portion of the semiconductor chip 1100, and the semiconductor chip utilization efficiency is improved. .

  In this pad arrangement, power supply pads VC1 and VC2 are usually arranged at opposite ends of the central region of the semiconductor chip 1100 for the purpose of maintaining pin compatibility with the semiconductor memory device of the previous generation. Data input / output pads DQ1 to DQ4 are intensively arranged adjacent to one power supply pad VC1. The other power supply pad VC2 supplies a power supply voltage to circuits other than the data input / output circuit. Although power supply pads VC1 and VC2 are shown as supplying power supply voltage Vcc, similarly, ground pads for supplying ground voltage Vss are also arranged adjacent to power supply pads VC1 and VC2, respectively, but the drawing is simplified. In order to do this, this ground pad is not shown.

  Data input / output pads DQ1 to DQ4 exchange data with memory blocks MB1 to MB4 via internal data buses 1102a to 1102d, respectively. Although not clearly shown in FIG. 26, a data input / output buffer is provided adjacent to each of data input / output pads DQ1-DQ4. These data input / output buffers operate when supplied with an operation power supply voltage and a ground voltage from a power supply pad VC1. By providing a dedicated power supply for the data input / output buffer separately from other circuits, the power supply voltage and ground voltage used for this data input / output are stabilized, and the data input / output operation (especially the data output operation) is stabilized. (Stable data input / output without being affected by power supply noise) and higher speed (reducing the load on the power supply circuit to perform charge / discharge operation at high speed to input / output data).

Japanese Patent Laid-Open No. 4-267550 (Patent Document 2) discloses a configuration for stably supplying the power supply voltage to the internal memory block in the LOC arrangement. In the configuration shown in Patent Document 2, in the LOC arrangement, a plurality of power pads are arranged in the central area in accordance with the internal circuit, and these power pads are commonly connected to the bus bar connected to the pin terminal. . The power supply voltage of each power supply pad is stabilized by supplying the power supply voltage from the bus bar to each power supply pad.
JP-A-3-214669 JP-A-4-267550

  In the configuration disclosed in Patent Document 1 described above, data input / output buffers are arranged adjacent to data input / output pads DQ1 to DQ4. These data input / output buffers operate in common by receiving power supply voltage Vcc from the power supply pad. Since a plurality of (four in FIG. 26) data input / output buffers are coupled to one power supply pad, the load on the power supply pad (power supply line) increases. The current supply capability of the power supply pad VC1 is determined by external specifications. Therefore, when the number of data input / output buffers (particularly data output buffers) connected to power supply pad VC1 is increased, a sufficiently large current can be stably supplied from power supply pad VC1 to each data input / output buffer. The power supply voltage and the ground voltage fluctuate, and the data input / output buffer cannot charge / discharge each output node at a high speed, resulting in a problem that the high speed operation cannot be performed. Particularly during data output operation, if the power supply voltage fluctuates and the operation speed of the output buffer slows down, the time that valid output data appears on the external pin terminal through the pad is slowed down, making high-speed reading impossible. The problem arises.

  A power supply pad VC2 provided around the central region of the semiconductor chip 1100 is used to supply a power supply voltage to the peripheral circuit. Although the peripheral circuits are not clearly shown in FIG. 26, they are distributed on the semiconductor chip 1100. For this reason, the length of the power supply line from the power supply pad VC2 to each peripheral circuit becomes long, causing problems such as a decrease in power supply voltage due to wiring resistance and instability of the power supply voltage, and the peripheral circuit can be operated stably. The problem of disappearing arises.

  Further, in order to shorten the power supply line from the power supply pad VC1 to the data input / output buffer and reduce the load on the power supply line as much as possible, the data input / output buffer and the data input / output pads DQ1 to DQ4 are centrally arranged near the power supply pad VC1. The Therefore, the length of the internal data line 1102a between the memory block MB1 and the data input / output pad DQ1 and the length of the internal data line 1102b between the memory block MB2 and the data input / output pad DQ2 are the same as those of the memory block MB3 and the data input / output pad DQ3. It becomes longer than the length of the internal data line 1102c between them and the length of the internal data line 1102d between the memory block MB4 and the data input / output pad DQ4.

  In this case, the wiring resistance and parasitic capacitance of internal data lines 1102a and 1102b are larger than that of internal data lines 1102c and 1102d, and the signal propagation delay in internal data lines 1102a and 1102b is larger than that of internal data lines 1102c and 1102d. The problem arises that the size becomes large and high-speed access becomes impossible. That is, at the time of data reading, the timing at which the read data from memory blocks MB1 and MB2 appears on pads DQ1 and DQ2 is determined and the data from memory blocks MB3 and MB4 appears on data input / output pads DQ3 and DQ4. It is later than the timing, and it is necessary to determine the output data confirmation timing in accordance with this later timing, and the access time during data reading becomes longer.

  Similarly, at the time of data writing, internal write is performed on each of memory blocks MB1-MB4 according to a write pulse (generated in response to a write enable signal) from write data appearing on pads DQ1-DQ4. Write data is generated and transmitted via internal data lines 1102a to 1102d. In this case, the write data is written in memory blocks MB3 and MB4 at the timing when write data is written in memory blocks MB1 and MB2. The data writing time becomes longer than the timing at which data is written.

  As shown in FIG. 27, in the conventional data input / output pad arrangement, peripheral pads PD1-PDn receiving address signals and clock signals (external control signals such as row address strobe signal / RAS and write enable signal WE) Master control circuit 1110 that receives an internal signal from pads PD1-PDn and generates a signal for controlling an access operation to memory blocks MB1-MB4 has a data input / output pad DQ1-DQ4 formation region in the central region of semiconductor chip 1100. Provided in the excluded area. Buffers provided corresponding to pads PD1-PDn operate by receiving a power supply voltage from power supply pad VC2. Usually, the peripheral pads PD1-PDn are arranged in a line. An internal signal from peripheral pad PD1 is applied to master control circuit 1110 via signal line 1112, and an internal signal from pad PDn is applied to master control circuit 1110 via signal line 1113.

  Master control circuit 1110 outputs necessary control signals to memory blocks MB1-MB4 and defines data input / output timings of data input / output buffers provided corresponding to data input / output pads DQ1-DQ4. Generate a signal. In general, in a DRAM, an address signal applied to an address input pad is taken in response to the fall of row address strobe signal / RAS to generate an internal row address signal. Normally, as will be described later in detail, for the address signal, the setup time and hold time are determined with respect to the falling edge of this signal / RAS. As shown in FIG. 27, when the signal lines 1112 and 1113 are different in length, the signal propagation delays of the signal lines 1112 and 1113 are different. Therefore, it is necessary to set the setup time and hold time in the worst case. There is a problem that the internal operation start timing cannot be advanced and high-speed operation cannot be realized. Further, the distance from the master control circuit 110 to the memory blocks MB1 to MB4 is different, the operation timing of the memory blocks MB1 to MB4 is not constant, and the access time becomes longer in the worst case.

  Moreover, in the above-mentioned patent document 1, the package provided with the arrangement | positioning of the external pin terminal according to a pad arrangement | positioning is disclosed (FIGS. 26 and 27). However, in this case, the number of pin terminals that supply the power supply voltage and the ground voltage is one from the outside, and even if a bus bar is used, it is difficult to suppress power supply noise, and the power supply voltage and the ground voltage can be stably supplied. The problem arises that the voltage cannot be guaranteed.

  In addition, the data pin terminals are only positioned in the package according to the internal pad arrangement, and the same problems as those described for the data pads occur.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit device having a pin position on which a semiconductor memory device can operate stably at high speed.

  Another object of the present invention is to provide a semiconductor integrated circuit device having an external pin arrangement for realizing high speed and stable operation of a semiconductor memory device.

  A semiconductor integrated circuit device according to a first aspect of the present invention is a semiconductor integrated circuit device in which a semiconductor memory device is mounted in a rectangular package, and is disposed at one end of one side of the package. The first power supply pin terminal to which the power supply voltage to be used is supplied and at least one for transferring data to and from the semiconductor memory device is disposed adjacent to the first power supply pin terminal on one side. A plurality of first data pin terminals and a plurality of first peripheral pin terminals arranged between the first data pin terminals and a central portion on one side of the package and supplied with a signal for accessing the semiconductor memory device A second power supply pin terminal disposed at the center of the package and supplied with a power supply voltage to the semiconductor memory device, and disposed at the other end of one side of the package and connected to the semiconductor memory device. A third power supply pin terminal to which a power supply voltage is supplied and at least one second data pin arranged adjacent to the third power supply pin terminal and for transferring data to and from the semiconductor memory device A second peripheral pin terminal disposed between the terminal and the second data pin terminal and the second power supply pin terminal, to which a signal for accessing the semiconductor memory device is supplied; A first ground pin terminal disposed at one end of the other side of the package opposite to the first power supply pin terminal and supplied with a ground voltage used by the semiconductor memory device, and on the other side At least one third data pin terminal arranged adjacent to the first ground pin terminal and facing the first data pin terminal, for transferring data to and from the semiconductor memory device; and A third data pin terminal and A third plurality of peripheral pin terminals which are arranged opposite to the first plurality of peripheral pin terminals between the other central portion of the package and to which a signal for accessing the semiconductor memory device is supplied; A second ground pin terminal disposed at the center of the other side of the package so as to face the second power supply pin terminal and supplied with a ground voltage used by the semiconductor memory device, and the other end of the other side of the package A third ground pin terminal to which a ground voltage to be used by the semiconductor memory device is supplied and a second data pin terminal adjacent to the third ground pin terminal and facing the second data pin terminal; At least one fourth data pin terminal for exchanging data between and a second plurality of peripheral pin terminals between the fourth data pin terminal and the second ground pin terminal For the semiconductor memory device And a fourth plurality of peripheral pin terminals to which signals for access are supplied.

  A semiconductor integrated circuit device according to a second aspect of the present invention is a semiconductor integrated circuit device in which a semiconductor memory device is mounted in a rectangular package, and is disposed at one end of one side of the package. The first power supply pin terminal to which the power supply voltage to be used is supplied and at least one for transferring data to and from the semiconductor memory device is disposed adjacent to the first power supply pin terminal on one side. A first data pin terminal and a first power pin terminal adjacent to the first data pin terminal on one side of the package and sandwiching the first data pin terminal between the first data pin terminal and the semiconductor memory A second power supply pin terminal to which a power supply voltage to be used by the device is supplied; a third power supply pin terminal to which a power supply voltage to be used by the semiconductor memory device is provided; 2 power supply A plurality of first peripheral pin terminals disposed on one side of the package and supplied with a signal for accessing the semiconductor memory device, and between the first power supply pin terminal and the third power supply pin terminal; A fourth power supply pin terminal disposed at the other end, to which a power supply voltage used by the semiconductor memory device is supplied, and a third power supply terminal and a third power supply pin terminal on one side of the package; A fifth power supply pin terminal to which a power supply voltage used by the storage device is supplied, and a fourth power supply pin terminal sandwiched between the fourth and fifth power supply pin terminals on one side of the package; At least one second data pin terminal for transmitting / receiving data between them, and between the fifth power supply pin terminal and the third power supply pin terminal on one side of the package, and for the semiconductor memory device access A second plurality of peripheral pin terminals to which signals to be performed are supplied and one end portion of the other side opposite to one side of the package are arranged to face the first power supply pin terminal and are used by the semiconductor memory device. A first ground pin terminal to which a ground voltage is supplied, and the other side of the first ground pin terminal are arranged adjacent to the first ground pin terminal and opposite to the first data pin terminal, and data is transmitted to and from the semiconductor memory device. And a second power supply pin terminal so that the third data pin terminal is sandwiched between at least one third data pin terminal for transmitting and receiving and a first ground pin terminal on the other side of the package A second ground pin terminal to be supplied with a ground voltage used by the semiconductor memory device, and a third power supply pin terminal at the center of the other side of the package, Ground voltage used by semiconductor memory devices is supplied And a third ground pin terminal disposed between the second ground pin terminal and the third ground pin terminal on the other side of the package so as to face the second plurality of peripheral pin terminals. A third plurality of peripheral pin terminals to which a signal for accessing the storage device is supplied and a fourth ground which is arranged at the other end of the other side of the package and to which a ground voltage used by the semiconductor storage device is supplied A pin terminal, a fifth ground pin terminal disposed on the other side of the package opposite to the fifth power supply pin terminal, to which a ground voltage used by the semiconductor memory device is supplied, and fourth and fifth At least one fourth data pin terminal arranged to be sandwiched between the ground pin terminals and opposed to the second data pin terminal, for transferring data to and from the semiconductor memory device; The fifth contact on the other side of the package A fourth plurality of peripheral pins which are arranged between the pin terminal and the third ground pin terminal so as to face the second plurality of peripheral pin terminals and are supplied with signals for accessing the semiconductor memory device Terminal.

  In the present invention, power supply pin terminals for supplying a power supply voltage and a ground voltage are distributed along the package side, and in the semiconductor memory device, a power supply is provided for each function of an internal circuit such as a peripheral circuit and a data input / output circuit. Pins can be assigned, and the internal circuit of the semiconductor memory device can be stably operated by suppressing generation of power supply noise.

  Similarly, the data pin terminals are distributed in the package, and high-speed access can be achieved by arranging the data pads according to the positions of the memory blocks in the semiconductor memory device and connecting the corresponding data pin terminals. Realized.

  Further, the pads can be arranged inside the semiconductor memory device in the same arrangement as the pin terminals, and the positions of the pads in the following can be realized accordingly. That is, a data input / output pad is arranged corresponding to each memory block and in the vicinity thereof, and a peripheral pad is arranged in the vicinity of the center portion. By realizing such a pad arrangement, the length of the internal data bus can be made the same for all data input / output buffers, and data input / output can be performed at high speed. In addition, by arranging an external signal input pad in the central part, a master control circuit as a peripheral circuit can be arranged in the central part of the chip so that external signals can be transmitted to the peripheral circuit of each memory block with the shortest signal line length. And high-speed access is possible.

[Arrangement of power supply pad and I / O buffer]
FIG. 1 schematically shows a layout of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, the semiconductor memory device is formed on a semiconductor chip 1 and includes four memory blocks MB1 to MB4. Each of these memory blocks MB1 to MB4 includes a plurality of memory cells, and a 1-bit memory cell is selected during operation (the configuration of the memory block will be described in detail later). Memory blocks MB1 and MB3 are arranged on one side of the central area in the first direction (horizontal direction in FIG. 1) of memory blocks MB1 to MB4, and memory blocks MB2 and MB4 are arranged on the other side. In this central region, data input / output pad portions 3a, 3b, 3c and 3d are arranged corresponding to memory blocks MB1 to MB4 and adjacent to the corresponding memory blocks. In the following description, the “pad portion” is used as a term indicating both a pad connected to the lead frame and a buffer provided in the vicinity thereof.

  Pad portion 3a exchanges data with memory block MB1 via internal data bus 2a. Data input / output pad portion 3b inputs / outputs data to / from memory block MB2 via internal data bus 2b. Data input / output pad unit 3c inputs / outputs data via memory block MB3 and internal data bus 2c. Data input / output pad unit 3d exchanges data with memory block MB4 via internal data bus 2d. For reasons that will be described in detail later, data input / output pad portions 3a-3d are arranged near the center position (in the horizontal direction in the figure) of corresponding memory blocks MB1-MB4.

  Power supply pads 5 and 6 are arranged at both ends of the central area, and power supply pads 7 are arranged at the central area of the central area. Power supply pad 5 transmits power supply voltage V1 (Vcc and Vss) to data input / output pad portions 3c and 3d, and power supply pad 6 transmits power supply voltage V2 (Vcc and Vss) to data input / output pad portions 3a and 3b. Power supply pad 7 transmits power supply voltage V3 (Vcc and Vss) to a control circuit included in peripheral circuit 4 indicated by a broken line block and an external signal input buffer such as an address signal and a block selection signal described later.

  This semiconductor memory device has a lead-on-chip structure as a package structure, each having a plurality of lead frames whose tips extend to the upper center of the semiconductor chip 1, and each lead frame tip and each pad are bonded wires. Connected by In FIG. 1, corresponding external pin terminals are also shown. That is, power supply pad 5 is connected to pin terminal 15a for inputting power supply voltage Vcc and pin terminal 15b for inputting ground voltage Vss. Data input / output terminals 17c and 17d are connected to pad portions 3c and 3d, respectively. Power supply pad 7 is connected to pin terminal 16a for receiving power supply voltage Vcc and pin terminal 16b for receiving ground voltage Vss. The data input / output pad unit 3a is connected to the data input / output pin terminal 17a, and the data input / output pad unit 3b is connected to the data input / output pin terminal 17b. Power supply pad 6 is connected to power supply voltage Vcc input pin terminal 15c and ground voltage Vss input pin terminal 15b. The arrangement positions of the pin terminals and the arrangement positions of the pads substantially correspond to each other. Internal data buses 2a-2d extend over corresponding memory blocks MB1-MB4, and each has the same length.

  FIG. 2 schematically shows configurations of the pad section and the power supply pad shown in FIG. FIG. 2 shows the configuration of the pad portions 3a and 3b and the power supply pad 6. In FIG. 2, pad portion 3a includes an input / output buffer 3aa for exchanging data via internal data bus 2a, and pad 3ab for exchanging data with this input / output buffer 3aa. Data input / output pad portion 3b includes an input / output buffer 3b for exchanging data via internal data bus 2b, and pad 3bb for exchanging data signals with this input / output buffer 3ba. Power supply pad 6 receives power supply voltage Vcc from external pin terminal 15c and transmits it to internal power supply lines 6aa and 6ab, and receives ground voltage Vss through pin terminal 15d and via ground lines 6ba and 6bb. A ground pad 6b for transmission is included. Power supply lines 6aa and 6ab are formed of the same layer wiring, and ground lines 6ba and 6bb are formed of the same wiring layer. Input / output buffer 3aa operates using power supply voltage Vcc of power supply line 6aa and ground voltage Vss on ground line 6ba as operating power supply voltages. Input / output buffer 3ba operates using power supply voltage Vcc on power supply line 6ab and ground voltage Vss on ground line 6bb as operating power supply voltages. In the following description, the power supply voltage includes both voltages Vcc and Vss unless otherwise specified.

  As shown in FIGS. 1 and 2, voltage V2 (Vcc and Vss) applied to power supply pad 6 is used by input / output buffers 3aa and 3ba included in data input / output pad portions 3a and 3b. On the other hand, voltage V1 (Vcc and Vss) on power supply pad 5 is used only for input / output buffers included in data input / output pad portions 3c and 3d. Since each of the power supply pads 5 and 6 reduces the load, the power supply voltage can be stably supplied, and the input / output buffer included in the corresponding data input / output pad unit can be driven at a high speed accordingly. That is, for example, in FIG. 2, when the amount of current flowing through power supply lines 6aa and 6ab and ground lines 6ba and 6bb, that is, consumed, is determined in advance, the voltage on those power supply lines and ground lines is used as the operating power supply voltage. Sufficient current is supplied to input / output buffers 3aa and 3ba, and pads 3ab and 3bb can be charged and discharged stably and at high speed during data reading.

  Even if the current supply capability of the power supply pad 6 is sufficient to supply sufficient current if the two input / output buffers 3aa and 3ba are used, if the number of input / output buffers increases, these input / output buffers A large amount of current is consumed in accordance with the operation, the voltages on the power supply lines 6aa and 6ab and the ground lines 6ba and 6bb vary, the voltage level of the data signal output from the input / output buffer varies, and stable operation is possible. Disappear. However, by reducing the number of input / output buffers connected to one power supply pad in this way, it is possible to stably transmit power supply voltage Vcc and ground voltage Vss at a constant voltage level even during operation. Further, by arranging the power supply pads corresponding to the groups of the memory blocks as shown in FIG. 1, the lengths of the power supply lines and the ground lines between the power supply pads and the input / output pad portions can be shortened. A change in voltage due to wiring resistance in the power supply line and the ground line can be prevented, and constant power supply voltage Vcc and ground voltage Vss can be supplied stably.

  Further, by disposing the power supply pad 7 used only for the peripheral circuit at the center of the chip, the power supply voltage Vcc and the ground voltage Vss (shown as voltage V3) can be stably supplied to the peripheral circuit for the same reason. The peripheral circuit 4 can operate stably and at high speed.

  Further, the following advantages can be obtained by arranging data input / output pad portions DQ1 to DQ3 in the vicinity of the central portion of corresponding memory blocks MB1 to MB4, respectively.

  FIG. 3 schematically shows the configuration of one memory block. In FIG. 3, memory block MB is divided into n (for example, 32) memory array blocks MA1-MAn. A row decoder RD is provided for these memory arrays MA1 to MAn, and a column decoder CD is provided in parallel with the extending direction of internal data bus 2 in the vicinity of memory arrays MA1 to MAn. A local column circuit LCC is provided adjacent to the column decoder CD, and a local row circuit LRC is provided adjacent to the row decoder RD. A control signal and an address signal are applied to local column related circuit LCC and local row related circuit LRC from master control circuit 4a. Row decoder RD may be arranged corresponding to each of memory cell arrays MA1-MAn.

  In operation, row decoder RD selects one word line only in a predetermined number (for example, one) of memory arrays MA1-MAn. All the memory arrays except the memory array including the selected word line maintain the standby state (this operation is realized by the local row system circuit LRC). A column selection signal from the column decoder CD is applied to a selected one of the memory arrays MA1 to MAn. Therefore, only the selected memory array is connected to internal data bus 2.

  Internal data bus 2 extends over memory arrays MA1 to MAn. Therefore, for example, when memory array MA1 is selected, read data from selected memory array MA1 is transmitted to one end of internal data bus 2 via local column circuit LCC. On the other hand, when memory array MAn is selected, the data in memory array MAn is transmitted to the other end of internal data bus 2 via local column circuit LCC. By arranging data input / output pad portion 3 near the center of internal data bus 2, the time required for read data to be transmitted to pad portion 3 when memory array MA1 is selected and memory array MAn are selected. Sometimes, the time when the memory cell data is transmitted to the pad unit 3 can be made equal, and the time difference between the memory cell data transmitted to the pad unit 3 caused by the position of the selected memory array can be reduced. it can. For example, when pad portion 3 is provided at the other end of data bus 2 close to master control circuit 4a, the time that the data read from memory array MA1 is transmitted to pad portion 3 is the longest, and the access time Is determined by this worst case, and high-speed reading cannot be performed.

  Therefore, as shown in FIG. 3, by arranging the data input / output pad portion 3 in the vicinity of the central portion of the data bus 2 (the central portion of the memory block MB), the data reading time difference depending on the position of the selected memory array can be reduced. High-speed reading can be realized. This also applies to the data write operation. Even when the number of bits of data read from one memory block increases to 2 bits and 4 bits, the data input / output pad portion is arranged as centrally as possible in the memory block MB. This minimizes the variation in the data read time difference depending on the position of the selected memory array.

  As described above, by arranging the data input / output pad portions in a distributed manner corresponding to each memory block, it is possible to arrange the power pads corresponding to the groups of the data input / output pad portions arranged in a distributed manner. The number of data input / output buffers connected to one power supply pad can be reduced, the power supply voltage and ground voltage of each data input / output buffer can be stabilized, and the semiconductor operates stably and at high speed. A storage device can be realized.

  In addition, when the data input / output pad is arranged near the center of the corresponding memory block, the memory block has an array division structure, and the position on the internal data line to which the selected memory cell data is transmitted is different. In this case, the shift of the memory cell data propagation time due to the selected array position can be reduced, and data can be input / output at high speed. In addition, by arranging the input / output pad portion in the vicinity of the corresponding memory block corresponding to each memory block, the internal data lines need only be arranged across the corresponding memory block, and the internal data line from one end of the chip to the other end of the chip There is no need to extend the data bus, the length of the internal data line can be reduced, the propagation delay of the data signal on the internal data line can be reduced, and data can be input / output at high speed. it can.

  Further, by arranging a power supply pad dedicated to the peripheral circuit in the center of the chip, the power supply voltage and the ground voltage can be stably supplied to the peripheral circuit, and the peripheral circuit can be operated at high speed and stably. The peripheral circuit 4 steps down the external power supply voltage Vcc to generate an internal operating power supply voltage, a substrate bias generation circuit that generates a negative voltage Vbb as a substrate bias voltage, and a bit line precharge or memory cell capacitor cell When a circuit for generating an intermediate potential to be applied to the plate is included, these voltages can be transmitted to each of the memory cell blocks MB1 to MB4 with a short wiring length. Further, the wiring layout is simplified by simplifying the wiring layout. Thereby, a necessary voltage can be reliably transmitted to each circuit stably.

[External signal pad layout]
FIG. 4 schematically shows a layout of an external signal pad of the semiconductor memory device according to the present invention. In the configuration shown in FIG. 4, parts corresponding to those in the configuration shown in FIG.

  In FIG. 4, a peripheral circuit is arranged at the center between one data input / output pad portions 3a and 3b and the other data input / output pad portions 3c and 3d. This peripheral circuit has a master control circuit 4a for controlling an access operation to the memory blocks MB1 to MB4, and a peripheral pad portion 21a receiving an address signal and a clock signal (access control signals such as a row address strobe signal and a write enable signal). , 21b, 21c, and 21d. Power supply pads 7 for these peripheral circuits are arranged in the vicinity of the master control circuit 4a. Each of peripheral pad portions 21a-21d transmits an input signal to master control circuit 4a via signal lines 22a-22d. By symmetrically arranging the peripheral pads 21a to 21d in the central portion of the central region with the master control circuit 4a as the center, the length of the signal lines 22a to 22d can be shortened, and the propagation delay of the address signal and the clock signal (This is because by shortening the signal line, the resistance and parasitic capacitance of each signal line can be reduced, and the RC delay can be reduced).

  Since the propagation delay of the signal line can be reduced, the setup time and hold time of the external signal (address signal and clock signal) can be shortened, and high-speed access is realized (the internal operation start timing is advanced. Because it can be). The shortening of the setup time and hold time will be described below with reference to FIG.

  FIG. 5 is a diagram exemplarily showing the setup time and hold time of the address signal. FIG. 5A shows the setup time and hold time required for the external control signal during the data read operation. In the DRAM, the row address signal and the column address signal are given in a time division manner. For the address signal, an RAS previous row address setup time tsu (RA-RAS) for setting the row address signal in a definite state before the fall of the row address strobe signal / RAS is defined, and the external row address strobe signal RAS post-row address hold time th (RAS-RA) for maintaining the row address signal after the fall of / RAS is defined. After this RAS row address hold time th (RAS-RA) is completed, the row selection operation is started internally in the DRAM.

  Similarly, for the column address signal, CAS pre-column address setup time tsu (CA-CAS) and CAS post-column address hold time th (CAS-CA) are defined for column address strobe signal / CAS. The valid output data Q is output after the RAS access time ta (RAS) has elapsed since the row address strobe signal / RAS fell. This time is also defined by a time CAS access time ta (CAS) after column address strobe signal / CAS falls and becomes active. In the DRAM, a RAS “H” pulse width tw (RASH) is defined to precharge internal signal lines and internal nodes to an initial state. Once signal / RAS is raised to a high level, signal / RAS cannot be lowered until after RAS “H” pulse width tw (RASH) has elapsed.

  These setup time, hold time and access time are all determined by external specifications. Therefore, as shown in FIG. 5B, when the internal signal has a delay time Td with respect to the external signal, the setup time and the hold time become longer by this delay time Td. Therefore, as shown in FIG. 5A, the internal row selection start operation timing is delayed by this delay time Td, and the RAS access time and CAS access time are lengthened, so that data can be read at high speed. Disappear. Therefore, it is preferable from the viewpoint of high-speed access that the delay time Td be as short as possible and the setup time and hold time be as short as possible.

  As shown in FIG. 4, by arranging the external signal input pad portions 21a to 21d on both sides of the master control circuit 4a as the center, the length of the signal lines 22a to 22d can be shortened, and the internal signal propagation delay time can be reduced. The delay time Td can be shortened accordingly. Thereby, the setup time and hold time can be shortened, and high-speed access is realized.

[Power distribution method]
FIG. 6 is a diagram showing an example of the configuration of power supply voltage distribution in the power supply pad layout according to the present invention. 6 shows a configuration of an area between power supply pad 6 and memory blocks MB1 and MB2 of the semiconductor memory device shown in FIG. In FIG. 6, data input / output pad portions 3a and 3b, peripheral pad portions PA1 to PA3 receiving external signals (address signal and clock signal), power supply pad 7 for peripheral circuits, and power supply voltage from power supply pad 7 The master control circuit 4a which operates in response to the above is shown.

  In FIG. 6, data input / output pad portions 3a and 3b operate by receiving power supply voltage (including Vcc and Vss) from power supply pad 6 through power supply line (including ground line) 30. Peripheral pad portions PA1-PA3 commonly receive a power supply voltage (including Vcc and Vss) from power supply pad 7 through power supply line 31. Master control circuit 4a operates by receiving power supply voltage (including Vcc and Vss) from power supply pad 7 through power supply line 32. Power supply lines 33a and 33b are also provided on power supply pad 7, and transmit power supply voltages (including Vcc and Vss) to local circuits of memory blocks MB1 and MB2, respectively. The power supply lines 31, 32, 33a and 33b are different wirings (wiring layers at the same level). By forming the power supply lines 31, 32, 33a and 33b with separate wirings, it is possible to prevent the voltage fluctuations on these wirings from affecting each other and to stably stabilize the peripheral circuit (peripheral pad portion PA1). -PA3 and the master control circuit 4a) can be operated. At this time, since the data input / output pad portions 3a and 3b are supplied with the power supply voltage from the power supply pad 6 provided in the vicinity via the power supply line 30, the power supply voltage is stable and operates at high speed. be able to.

  As shown in FIG. 6, a power supply line 30 (including both a power supply line for supplying a power supply voltage Vcc and a ground line for supplying a ground voltage Vss) connected to a power supply pad 6 and a pad 7 for a peripheral circuit are connected. The power supply line 31 is arranged separately from each other, and only the power supply line for supplying the power supply voltage to only the data input / output buffers included in the pad portions DQ1 and DQ2 is connected to the power supply pad 6. By connecting only the power supply line for supplying the power supply voltage to the buffer circuit for the control signal or address signal included in the peripheral pad portions PA1 to PA3 to the pad 7 for use, the following advantages can be obtained. Even if the voltages Vcc and / or Vss on the power supply line 30 fluctuate during the operation of the data input / output buffers included in the pad portions 3a and 3b, this influence is applied to the data input / output buffers included in the pads 3a and 3b. The voltage fluctuation on the power supply line 30 has no effect on the buffers for inputting control signals and address signals included in the peripheral pad portions PA1 to PA3. Therefore, peripheral circuits included in peripheral pad portions PA1 to PA3 and master control circuit 4a operate by receiving a stable power supply voltage from peripheral circuit power supply pad 7. That is, the peripheral circuit can stably operate even when data signals are input / output.

  Further, a power supply voltage can be separately applied to the data input / output buffer and the peripheral circuit, and signals such as HSTL (high speed transistor logic; high level is 1.2V, low level is 0.8V), etc. It is possible to easily cope with a high-speed interface in which the power supply voltage level for input / output and the internal operation power supply voltage level are different. That is, for example, an external interface level power supply voltage is applied to the power input / output pad 6 for data input / output to operate the data input / output buffer at the voltage level of the high speed interface, A voltage of a higher voltage level is applied, a step-down circuit is provided in the peripheral circuit portion, and this internal step-down circuit is applied to the peripheral circuit included in the peripheral circuit pad portion. Thereby, the buffer for inputting the control signal and the address signal operates with the power supply voltage corresponding to the external interface, and the internal circuit can operate with a higher voltage level. In this case, conversely, a configuration in which a high-speed interface level power supply voltage is applied to the peripheral circuit pad 7, a booster circuit is provided in the peripheral circuit, and a power supply voltage for the operation of the internal circuit is generated from the booster circuit is used. May be. In any configuration, it is possible to easily cope with an interface in which the internal operation power supply voltage level and the power supply voltage level for signal input / output are different.

  FIG. 7 is a diagram illustrating another configuration example of the power distribution. In the configuration shown in FIG. 7, unlike the configuration shown in FIG. 6, the power supply voltage (Vss and Vcc) is applied from the power supply pad 6 to the peripheral pad portion PA1 through the power supply line 40. Power supply voltages (Vcc and Vss) are transmitted from power supply pad 7 to power supply line 41 to peripheral pad portions PA2 and PA3. Power supply voltage is transmitted from power supply pad 7 to memory blocks MB1 and MB2 via power supply lines 42a and 42b, respectively. Also in this case, data input / output pad portions 3a and 3b and peripheral pad portion PA receive power supply voltages via different power supply lines, and data input / output pad portions 3a and 3b are stabilized via power supply line 30. It operates stably and at high speed when supplied with power supply voltage.

  In the configuration shown in FIGS. 6 and 7, a power supply pad is further provided between the peripheral pad portion PA1 and the data input / output pad portion 3b, and a power supply voltage is supplied from the additional power supply pad to the peripheral pad portion. It may be used. In this case, for example, a configuration in which the power supply voltage is separately applied to the address signal input pad unit and the clock signal input pad unit may be used.

  In either case, power supply pads are provided in the vicinity of the peripheral circuits (peripheral pad section and master control circuit section), and the power supply voltage is transmitted from the power supply pad 7 to these peripheral circuits to shorten the length of the power supply line. The peripheral circuit can be operated stably.

[Pin assignment 1]
FIG. 8 shows a package and pin arrangement for housing the semiconductor memory device of the present invention. In FIG. 8, a semiconductor integrated circuit device (a device including a package for mounting a semiconductor memory device) 50 includes, for example, 40 external pin terminals. Power supply voltage Vcc and ground voltage Vss are applied to the terminals of pin numbers 1 and 40, respectively. Pin numbers 2, 3, 38 and 39 adjacent to the pin terminals of pin numbers 1 and 40 are used as data input / output pin terminals. On the other side, power supply voltage Vcc and ground voltage Vss are applied to pin terminals 20 and 21. Adjacent to these pin terminals of pin numbers 20 and 21, pin terminals of pin numbers 18, 19, 22, and 23 for data input / output are arranged. Voltages Vcc and Vss applied to the pin terminals of pin numbers 20 and 21 are used in a data input / output buffer for inputting / outputting data to / from the pin terminals of pin numbers 18, 19, 22 and 23.

  Power supply voltages Vcc and Vss are applied to the pin terminals of pin numbers 9 and 32 in the center of the chip. The voltages Vcc and Vss applied to the pin terminals of these pin numbers 9 and 32 are used in the peripheral circuit (external address signal and external clock signal input buffer). Pin terminals with pin numbers 4 to 8, pin numbers 10 to 17, pin numbers 24 to 31 and pin terminals 33 to 37 are used as address signal or clock signal input pin terminals, respectively. The semiconductor memory device has a lead-on-chip structure, and a lead frame extends from each pin terminal to the vicinity of the pad shown in FIG. 8 and the like, and the lead frame and the pad are bonded wires in that portion. Connected. Therefore, the arrangement positions of the pin terminals and the arrangement positions of the pad portions described so far have a substantially corresponding relationship (however, since the pad portions are arranged in one row and the pin terminals are arranged in two rows, a complete 1 Not a one-to-one relationship).

  The voltage Vcc and Vss input pin terminals (pads) at both ends are used as pin terminals for supplying a power supply voltage and a ground voltage to the data input / output pad portion, and the data input / output pin terminals are both upper and lower sides of the semiconductor memory device 50 of FIG. As described above, the address signal and clock signal input pin terminals are arranged in the central area between the data input / output pin terminals, and the power supply pin terminals for peripheral circuits are arranged in the central part. Chip pad layout can be realized.

[Pin assignment 2]
FIG. 9 shows another arrangement of external pin terminals of the semiconductor memory device (semiconductor integrated circuit device) according to the present invention. In FIG. 9, external pin terminals provided outside the package are generally shown. 9, power supply pin terminals PT1 and PT13 for applying a power supply voltage Vcc are arranged at both ends on one side in the long side direction of the package 55, and pins for applying a ground voltage Vss at both ends on the other side of the package 55. Terminals PT14 and PT26 are arranged. Data pin terminals PT2 and PT3 for inputting / outputting data signals are arranged adjacent to power supply pin terminal PT1, and external data pin terminals for inputting / outputting data signals are adjacent to the other power supply pin terminal PT13. PT11 and PT12 are arranged. Similarly, pin terminals PT15 and PT16 for inputting / outputting data signals are arranged adjacent to the ground pin terminal PT14, and pin terminals PT24 and PT25 for inputting / outputting data signals are adjacent to the ground pin terminal PT26. Is placed.

  In the configuration shown in FIG. 9, a pin terminal PT4 for supplying power supply voltage Vcc is disposed adjacent to data pin terminal PT3, and ground voltage Vss is applied adjacent to data input / output pin terminal PT16. A pin terminal PT17 is provided for this purpose. Similarly, a power supply pin terminal PT10 for supplying the power supply voltage Vcc is disposed adjacent to the pin terminal PT11, and a ground pin terminal PT23 for supplying the ground voltage Vss is adjacent to the data input / output pin terminal PT24. Be placed. Power supply voltage Vcc applied to pin terminals PT1 and PT4 and ground voltage Vss applied to pin terminals PT14 and PT17 are applied to a data input / output buffer for inputting / outputting data to / from data input / output pin terminals PT2, PT3, PT15 and PT16. Power supply voltage. Similarly, power supply voltage Vcc applied to pin terminals PT10 and PT13 and ground voltage Vss applied to pin terminals PT23 and PT26 are data input / output buffers for inputting / outputting data to / from pin terminals PT11, PT12, PT24 and PT25. Used only for

  A pin terminal PT7 for supplying the power supply voltage Vcc is arranged at the center of the package 55. Similarly, a ground pin terminal PT20 for supplying the ground voltage Vss is arranged corresponding to the pin terminal PT7. Pin terminals PT5 to PT6 for inputting an address signal and a clock signal (external control signal) are arranged between the pin terminals PT4 and PT7. Similarly, an address signal and a clock signal are provided between the pin terminals PT7 and PT10. Pin terminals PT8 to PT9 for inputting are arranged. Pin terminals PT18 to PT19 for inputting address signals and clock signals are arranged between the pin terminal PT20 and the pin terminal 17, and for inputting address signals and clock signals between the pin terminal PT20 and the pin terminal PT23. Pin terminals PT21 to PT22 are arranged. Power supply voltages Vcc and Vss applied to pin terminals PT7 and PT20 arranged at the center of package 55 are used only in a peripheral circuit that receives the address signal and the clock signal and generates an internal control signal.

  As shown in FIG. 9, the power supply pins (Vcc and Vss) can be supplied from the pin terminals on both sides to the data input / output buffer by arranging the power supply pins with the data input / output pins interposed therebetween. Thus, it is possible to prevent a change in power supply voltage (voltage fluctuation due to wiring resistance) depending on the distance from the pad to the data input / output buffer, and supply power supply voltages (Vcc and Vss) from two pin terminals. As a result, the current supply capability to the data input / output buffer is increased, and the power supply voltage can be stably supplied to the data input / output buffer.

  FIG. 10 is a diagram showing a layout of pads and circuits of the semiconductor memory device having the pin terminal arrangement shown in FIG. In FIG. 10, only half of the package shown in FIG. 9 is shown. A layout symmetrical to the configuration shown in FIG. 10 is arranged on a chip housed in the package. In FIG. 10, the data input / output buffer and the peripheral circuit are highlighted, and the memory block is not shown.

  In FIG. 10, pin terminals arranged outside the semiconductor chip 1 are exemplarily shown. This pin terminal includes a power supply pin terminal PTAA for supplying a power supply voltage Vcc arranged at one end of the semiconductor chip 1, and data input / output pin terminals PTDA and PTDB arranged adjacent to the pin terminal PTAA. And pin terminal PTAB for supplying power supply voltage Vcc arranged adjacent to data input / output pin terminal PTDB. A power supply pin terminal PTAE for supplying power supply voltage Vcc for the peripheral circuit is arranged corresponding to the center portion of chip 1.

  Similarly, on the other side of the semiconductor chip 1, ground pin terminals PTAC and PTAD for supplying the ground voltage Vss are arranged opposite to the power supply pin terminals PTAA and PTAB, and between these pin terminals PTAC and PTAD, Data input / output pin terminals PTDC and PTDD are arranged. In addition, a pin terminal PTAF for supplying the ground voltage Vss is disposed opposite to the power supply pin terminal PTAE at the center of the chip 1.

  Power supply pin terminals PTAA and PTAC are connected to power supply pad 60a, and pin terminals PTAB and PTAD are connected to power supply pad 60b. Power supply pad 60a includes a pad 60aa receiving power supply voltage Vcc from pin terminal PTAA, and a pad 60ab receiving ground voltage Vss from ground pin terminal PTAC. Power supply pad 60b includes a pad 60ba receiving power supply voltage Vcc from pin terminal PTAB and a pad 60bb receiving ground voltage Vss from pin terminal PTAD. A data input / output pad portion for exchanging data signals with pin terminals PTDA to PTDD is arranged between power supply pads 60a and 60b. In FIG. 10, pad 80aa for exchanging data signals with input / output buffer 80ab, pad 80ba for exchanging data signals with input / output buffer 80bb, pad 80ca for exchanging data signals with input / output buffer 80bb, A pad 80da for exchanging data signals with the input / output buffer 80db is shown. These pads 80aa-80da are shown arranged in a row. Data input / output pads 80aa, 80ba, 80ca, and 80da are connected to pin terminals PTDA, PTDC, PTDB, and PTDD, respectively, as indicated by broken lines in FIG.

  Power supply voltage supply lines 61a and 61b are arranged to surround input / output buffers 80ab, 80bb, 80cb and 80db from power supply pads 60aa and 60ba, and input / output buffers 80ab, 80bb and 80cb are arranged from ground pads 60ab and 60bb. And ground voltage supply lines 62a and 62b are arranged to surround 80db. Power supply voltage supply line 61a and ground voltage supply line 62a (collectively referred to as power supply lines) supply power supply voltages Vcc and Vss to input / output buffers 80ab and 80cb, and power supply lines 61b and 62b include input / output buffers 80bb and Power supply voltages Vcc and Vss are supplied to 80 db. Since the input / output buffers 80ab to 80db are supplied with the power supply voltages Vcc and Vss from the two power supply pads 60a and 60b, respectively, the power supply lines 61a, 61b, 62a and 62b of the input / output buffers 80ab to 80db are operated. The power supply fluctuation can be sufficiently suppressed, and the input / output buffers 80ab to 80db can be stably operated by being supplied with a stable power supply voltage.

  On the other hand, pads 63 and 64 are arranged facing peripheral circuit pin terminals PTAE and PTAF, respectively. Pads 63 and 64 are connected to corresponding lead terminals PTAE and PTAF from bonding wires indicated by broken lines in the figure, and are supplied with power supply voltage Vcc and ground voltage Vss. Pad 63 supplies power supply voltage Vcc on power supply voltage supply line 65, and pad 64 supplies ground voltage Vss to ground voltage supply line 66. Peripheral circuit 67 arranged adjacent to pads 63 and 64 operates using power supply voltages Vcc and Vss on power supply lines 65 and 66 as operating power supply voltages. The power supply wirings 65 and 66 connected to the pads 63 and 64 supply the power supply voltage only to the peripheral circuit 67. Power supply pads 60a and 60b are connected only to a power supply wiring for supplying a power supply voltage to an input / output buffer for exchanging data signals. Power supply lines for supplying a power supply voltage from power supply pads 60a and 60b to other peripheral circuits are not connected. Therefore, even if the power supply voltage on power supply lines 61a, 61b, 62a and 62b fluctuates during data signal input / output, power supply lines 65 and 66 for peripheral circuit 67 are not affected by the fluctuation of the power supply voltage. , Can maintain a stable power level. As a result, the peripheral circuit 67 can operate stably without receiving fluctuations in the power supply voltage during data signal input / output.

[Pin assignment 3]
FIG. 11 shows a third pin arrangement of a package for housing the semiconductor memory device according to the present invention. In the pin arrangement shown in FIG. 11, power supply pins are arranged between data input / output pin terminals. That is, at one end of one side of package 55a, power supply pin terminal PT2a receiving one power supply voltage Vcc is arranged between data input / output pin terminals PT1a and PT3a, and at one end of one side of package 55a, A power supply pin terminal PT12a receiving power supply voltage Vcc is arranged between data input / output pin terminals PT11a and PT13a.

  On the other side of package 55a, a ground pin terminal PT15a receiving the other power supply voltage (ground potential) Vss is arranged between data input / output pin terminals PT14a and PT16a at one end of the package 55a, and a ground pin terminal at the other end. PT25a is arranged between data input / output pin terminals PT24a and PT26a. The power supply pin terminal PT2a is arranged so as to face the ground pin terminal PT15a, and the power supply pin terminal PT12a and the ground pin terminal PT25a are arranged so as to face each other.

  On the other hand, the power supply pin terminal PT7a receiving the power supply voltage Vcc is arranged at the central portion on one side of the package 55a in order to supply the power supply voltage to the peripheral circuit. A ground pin terminal PT20a is arranged opposite to the pin terminal PT7a.

  Pin terminals PT4a-PT6a, PT8a-PT10a, PT17a-PT19a and PT21a-PT23a are pin terminals for peripheral circuits that receive an address signal or a clock (control) signal.

  FIG. 12 shows an internal arrangement of the semiconductor memory device housed in package 55a shown in FIG. In FIG. 12, memory blocks are not shown in order to simplify the drawing. In addition, only the configuration of one side of the semiconductor memory device is shown. A configuration similar to the configuration shown in FIG. 12 is also arranged for the other memory block portion (not shown).

  In FIG. 12, a power supply pad (pad for supplying voltages Vcc and Vss) 70 is arranged between data input / output pads 74a and 75a. The power supply pad 70 includes a power supply pad 70a connected to the pin terminal PT12a through a lead frame and a ground pad 70b connected to the ground pin terminal PT25a.

  The pad 74a is connected to the pin terminal PT26a and connected to a data input / output buffer (I / O buffer) 74b arranged adjacent thereto. An I / O buffer 73b is disposed adjacent to the I / O buffer 74b. The I / O buffer 73b is connected to a data input / output pad 73a disposed adjacent thereto. The data input / output pad 73a is connected to the pin terminal PT13a.

  On the other hand, a data input / output pad (DQ pad) 75a is disposed adjacent to the ground pad 70b. The DQ pad 75a is connected to an I / O buffer 75b disposed adjacent to the DQ pad 75a, and is connected to the pin terminal PT11a. An I / O buffer 76b is disposed adjacent to the I / O buffer 75b. The I / O buffer 76b is connected to the frame lead (ie, pin terminal) PT24a through the DQ pad 76a.

  A set of the DQ pad and the I / O buffer constitutes a DQ pad portion. The DQ pad portions 73 (73a, 73b), 74 (74a, 74b), 75 (75a, 75b), and 76 (76a, 76b) and the power supply pad 70 are arranged in alignment along the first direction. .

  I / O buffers 73b, 74b, 75b, and 76b receive power supply voltage Vcc from pad 70a through power supply line 71, and receive ground potential Vss from pad 70b through ground line 72.

  In addition, the wiring resistance of power supply line 71 (ground line 72) with respect to I / O buffers 73b and 74b can be made equal to that with respect to I / O buffers 76 and 75b (because the wiring length is substantially the same). The power supply voltage Vcc (or ground voltage Vss) having substantially the same voltage level can be supplied to these I / O buffers 73b to 76b, and the signal voltage levels output from the I / O buffers 73b to 76b are substantially equal to each other. Therefore, it is possible to prevent malfunction due to signal voltage levels different from each other, and to ensure accurate operation.

  As for the peripheral circuit, the peripheral pad portion 77c is representatively shown. Peripheral pad portion 77c receives power supply voltage Vcc through power supply line 78 from power supply pad 77a disposed at the center of the chip, and receives ground potential Vss through ground line 79 from ground pad 77b. Power supply pad 77a and ground pad 77b are connected to power supply pin terminal PT7a and ground pin terminal PT20a arranged to face each other.

  Peripheral pad portion 77c includes a pad for receiving an address signal or a clock signal from a pin terminal (not shown), and a buffer for buffering and outputting a signal applied from the pad (not shown). The configuration of the peripheral pad portion is the same as that in the embodiment described above. In FIG. 12, a bonding wire for connecting the pad and the pin terminal is shown by a broken line.

[Other internal arrangements]
FIG. 13 is a diagram showing another internal arrangement of the semiconductor memory device housed in package 55a shown in FIG. In FIG. 13, only the portion related to data input / output is shown.

  In FIG. 13, power supply pad 90a is connected to frame lead PT12a via a bonding wire indicated by a broken line and receives power supply voltage Vcc. The ground pad 90b is disposed adjacent to the power supply pad 90a, is connected to the frame lead PT25a via a bonding wire indicated by a broken line, and receives the ground potential Vss therefrom. I / O buffers 91b and 92b and I / O buffers 93b and 94b are arranged symmetrically with respect to pads 90a and 90b. DQ pads 91a and 92a are arranged adjacent to I / O buffers 91b and 92b, respectively. The pad 91a is connected to the I / O buffer 91b and connected to the frame lead (pin terminal) PT13a via a bonding wire indicated by a broken line. The pad 92a is connected to the I / O buffer 92b and connected to the frame lead (pin terminal) PT26a via a bonding wire indicated by a broken line.

  DQ pads 93a and 94a are arranged adjacent to I / O buffers 93b and 94b, respectively. The pad 93a is connected to the opposing frame lead PT11a via a bonding wire indicated by a broken line and connected to the adjacent I / O buffer 93b. The pad 94a is connected to the opposing frame lead PT24a via a bonding wire (shown by a broken line) and is connected to a corresponding I / O buffer 94b.

  Pads 90a, 90b, 91a, 92a, 93a and 94a are arranged in alignment with each other along the first direction in the region between I / O buffers 91b and 93b and I / O buffers 92b and 94b.

  Power supply line 95a and ground line 96a are connected to power supply pads 90a and 90b arranged outside I / O buffers 91b and 93b, respectively, and supply power supply voltage Vcc and ground potential Vss to I / O buffers 91b and 93b. .

  A power supply line 95b and a ground line 96b connected to power supply pads 90a and 90b are arranged along the outside of I / O buffers 92b and 94b, respectively. I / O buffers 92b and 94b are connected to power supply voltage Vcc and ground potential Vss. Are supplied from the power line 95b and the ground line 96b.

  Wiring extending from pad 90a to power supply lines 95a and 95b is shown to intersect with ground lines 96a and 96b. In order to realize the configuration having this intersection, wiring formed in a wiring layer different from the wiring layer in which the ground line is formed in this intersection region is used. By adopting a two-layer structure, an intersection can be easily realized.

  In the configuration shown in FIG. 13, one power supply line 95 (95a or 95b) and one ground line 96 (96a or 96b) simply drive two I / O buffers. The I / O buffer is stably supplied with the power supply voltage and the ground voltage from these power supply line and ground line, and operates stably.

[Pin assignment 4]
FIG. 14 shows a fourth pin arrangement of the package for housing the semiconductor memory device according to the present invention.

  In FIG. 14, this package 55b has 16 DQ pin terminals, that is, DQ pin terminals PT1b, PT3b, PT4b, PT6b, PT8b, PT10b, PT11b and PT13b on one side of the package 55b, and DQ pin on the other side of the package 55b. Pin terminals PT14b, PT16b, PT17b, PT19b, PT21b, PT23b, PT24b and PT26b are included.

  In the pin arrangement shown in FIG. 14, the power supply pin terminal and the ground pin terminal are arranged on each side of the package 55b. That is, on one side of package 55b, power supply pin terminal PT2b is arranged between DQ pin terminals PT1b and PT3b, and ground pin terminal PT5b is arranged between DQ pin terminals PT4b and PT6b. On the other side of package 55b, ground pin terminal PT9b is arranged between DQ pin terminals PT8b and PT10b, and power supply pin terminal PT12b is arranged between DQ pin terminals PT11b and PT13b.

  A ground pin terminal PT15b disposed corresponding to the pin terminal PT2b is disposed between the DQ pin terminals PT14b and PT16b. The power pin terminal PT18b is disposed between the DQ pin terminals PT17b and PT19b so as to face the ground pin terminal PT5b. Be placed. The power pin terminal PT22b is disposed between the DQ pin terminals PT21b and PT23b so as to face the ground pin terminal PT9b, and the ground pin terminal PT25b is disposed between the DQ pin terminals PT24b and PT26b so as to face the power pin terminal PT12b. Is done.

  Power supply pin terminal PT7b and ground pin terminal PT20b are arranged at the center of package 55b, and are used to supply power supply voltage Vcc and ground potential Vss to the peripheral circuits of the semiconductor memory device housed in package 55b.

  In the LOC structure, the power supply pad is disposed in the central region of the memory chip. Therefore, in the internal wiring layout, which of power supply pin terminal and ground pin terminal is arranged on which side of this package 55b is not affected at all. In addition, according to the pin arrangement shown in FIG. 14, the following effects can be obtained.

  FIG. 15 is a diagram showing an internal layout of a semiconductor memory device housed in a package having the same pin arrangement as that shown in FIG. The semiconductor memory device shown in FIG. 15 has a x32-bit configuration for inputting / outputting 32-bit data. In FIG. 15, only the portion related to the portion for inputting / outputting 16-bit data is representatively shown. Show.

  Referring to FIG. 15, this semiconductor memory device includes two memory blocks MB # 1 and MB # 2 in which 8-bit memory cells are simultaneously selected. Memory block MB # 1 between memory blocks MB # 1 and MB # 2 and I / O (DQ) pad portions 100a-100h for inputting / outputting data are arranged in a line, and memory block MB I / O pad portions 100i-100p for inputting / outputting data with # 2 are arranged in a line.

  The power supply pad 101 is disposed between the pad portions 100a and 100b and connected to the opposing power supply pin terminal PP1. A ground pad 102 is disposed between pad portions 100c and 100d and connected to a corresponding ground pin terminal GP1. The power supply pad 103 is disposed between the pad portions 100e and 100f and connected to the opposing power supply lead (pin terminal) PP2. A ground pad 104 is disposed between the pad portions 100g and 100h and connected to a corresponding ground lead (pin terminal) GP2. Power supply pads 101 and 103 are connected to supply power supply voltage Vcc on power supply line 109a extending along one side of pad portions 100a-100h. Ground pads 102 and 104 are connected to supply ground voltage Vss on ground line 110a extending along the other side of pad portions 100a-100h. DQ pad portions 100a-100h operate using voltages Vcc and Vss on wirings 109a and 110a as operating power supply voltages.

  With respect to the DQ pad portions 100i-100j, the ground pad 105 is disposed between the pad portions 100i and 100j and connected to the opposing ground lead (pin terminal) GP3. A power supply pad 106 is disposed between the pad portions 100k and 100l and connected to the opposing power supply lead (pin terminal) PP3. The ground pad 107 is disposed between the pad portions 100m and 100n and connected to the opposing ground lead (pin terminal) GP4, and the power pad 108 is disposed between the pad portions 100o and 100p and is opposed to the power supply. The lead (pin terminal) PP4 is connected.

  Ground pads 105 and 107 are connected to supply ground voltage Vss on ground line 110b extending along one side of DQ pad portions 100i-100p in parallel with ground line 110a. Power supply pads 106 and 108 are connected to supply power supply voltage Vcc to power supply line 109b extending along the other side of DQ pad portions 100i-100p.

  DQ pad portions 100i-100p operate using voltages Vcc and Vss on wirings 109b and 110b as operating power supply voltages. The DQ pad portions 100a to 100h are connected to the corresponding frame leads DQT1 to DQT16.

  As shown in FIG. 15, by arranging the DQ pad portions 100a to 100p in two rows in a zigzag shape, a large number of DQ pads are provided in a limited region with a sufficient area margin along the first direction. The pad portion can be arranged, and the pitch condition at the time of high integration for the DQ pad portion can be relaxed.

  By placing both power and ground pins on each side of the package, the power and ground pads can be placed in line with the DQ pad portion. A set of power and ground lines can be separately arranged for a group of DQ pad portions aligned on one column and a group of DQ pad portions arranged aligned on the other column. Thus, the layout of the power supply line and the ground line for the DQ pad portion arranged in a zigzag shape becomes easy.

  One power supply line receives power supply voltage Vcc from a plurality of power supply pads, and one ground line receives ground voltage Vss from a plurality of ground pads. Therefore, the voltages on these power supply line and ground line can be stabilized, and the internal circuit (I / O buffer in the DQ pad portion) can be operated stably. These power supply lines and ground lines are only required to supply power supply voltages and ground voltages only to the corresponding DQ pad portions, and the load on these power supply lines and ground lines can be reduced. The DQ pad portion can be operated at high speed and stably.

[Modification 1]
FIG. 16 is a diagram showing a modified example of the internal layout of the DQ pad portion, power supply pad, and ground pad shown in FIG. The arrangement shown in FIG. 16 is the same as the arrangement shown in FIG. 15 except for the arrangement of the power supply line and the ground line, and parts corresponding to those shown in FIG. 15 are given the same reference numerals. Detailed description thereof will be omitted.

  In FIG. 16, the power pad 101 is connected to the power line 115a, and the ground pad 105 is connected to the ground line 116a. The power supply line 115a and the ground line 116a are arranged parallel to each other between the DQ pad portions 100a and 100b and the DQ pad portions 100i and 100j, and voltages Vcc and Vss are applied only to these DQ pad portions 100a, 100b, 100i and 100j. Supply.

  Ground pad 102 is connected to ground line 116b, and power supply pad 106 is connected to power supply line 115b. Wirings 115b and 116b are arranged in parallel between DQ pad portions 100c and 100d and DQ pad portions 100k and 100l, and supply voltages Vcc and Vss only to these DQ pad portions 100c, 100d, 100k and 100l. To do.

  Power supply pad 103 and ground pad 107 are connected to power supply line 115c and ground line 116c arranged in parallel between DQ pad portions 100e and 100f and DQ pad portions 100m and 100n, respectively. Power supply line 115c and ground line 116c supply voltages Vcc and Vss only to these DQ pad portions 100e, 100f, 100m and 100n.

  The ground pad 104 and the power pad 108 are connected to the ground line 116d and the power line 115d arranged in parallel between the DQ pad parts 100g and 100h and the DQ pad parts 100o and 100p, and these DQ pad parts 100g, 100h and 100o. Voltages Vss and Vcc are supplied as operating power supply voltages only to 100 and 100p.

  The power supply lines and the ground lines are grouped and alternately arranged in the arrangement direction. Each set of one power supply line and one ground line is merely required to supply power supply voltage Vcc and ground voltage Vss only to the corresponding group of DQ pad portions. Therefore, the power supply line and the ground line have reduced wiring capacitance and wiring resistance, and the load is reduced. Accordingly, each DQ pad part can stably receive an operating power supply voltage, and the DQ pad part is stable and fast. Can work. In addition, the power supply lines and the ground lines are only arranged in two rows, the wiring occupation area can be reduced, and high density and high integration of the semiconductor memory device can be easily realized.

[Modification 2]
FIG. 17 shows still another modification of the internal layout of the semiconductor memory device according to the present invention. In FIG. 17, the arrangement of pin terminals (lead frames) is the same as that shown in FIGS. 15 and 16, and the corresponding parts are denoted by the same reference numerals.

  The DQ pad portions 100a-100p are arranged in two rows and shifted from each other along the first direction. This is the same as the arrangement shown in FIGS. In FIG. 17, each of DQ pad portions 100a-100p is shown to include I / O buffers 120a-120p and DQ pad portions 122a-122p. DQ pad portions 122a-122p are connected to leads (pin terminals) DQT1-DQT16 via bonding wires not shown for the sake of simplicity of the drawing.

  The power pads 130a-130d are arranged in one row in alignment with the DQ pads 122a-122h, and the ground pads 132a-132d are also arranged in alignment so as to form another row in alignment with the DQ pads 122i-122p. The Power supply pads 130a-130d are connected to power supply frame leads (pin terminals) PP1, PP3, PP2 and PP4 through bonding wires indicated by broken lines. The ground pads 132a to 132d are respectively connected to ground frame leads (pin terminals) GP3, GP1, GP4 and GP2 through bonding wires indicated by broken lines.

  The power supply line 125 is connected to the power supply pads 130a to 130d, and supplies the power supply voltage Vcc to the DQ pad portions 100a to 100p (I / O buffers 120a to 120p) in common. The ground line 127 is connected to the ground pads 132a to 132d, and supplies the ground voltage Vss in common to the DQ pad portions 100a to 100p.

  The power supply line 125 may be formed of wirings that are formed in the same wiring layer for each portion between the power supply pads and separated from each other. That is, for example, the power supply wiring between the power pads 130a and 130b may be configured by a wiring different from or different from the power supply wiring between the power pads 130b and 130c. Such an arrangement is also applied to the ground line 127. By using such a divided power supply wiring structure and a divided ground line structure, it is possible to prevent power supply noise generated in one DQ pad portion from propagating to another DQ pad portion.

  In the arrangement shown in FIG. 17, the operation power supply voltage transmission lines are arranged in two rows, and the wiring occupation area can be reduced accordingly. In addition, this arrangement does not require the power supply lines and the ground lines to be alternately arranged along the first direction, and the layout of the power supply lines and the ground lines is facilitated.

[Modification 3]
FIG. 18 is a diagram showing still another external layout of the semiconductor memory device housed in package 55b shown in FIG. The semiconductor memory device 140 shown in FIG. 18 does not have a LOC structure. The semiconductor memory device 140 has a configuration of a pad peripheral arrangement in which pads are arranged around the chip. That is, the DQ pad portions 150a to 150d, the power supply pad 152a, and the ground pad 154a are arranged in alignment around the outside of the memory block MBA. In the outer peripheral portion of the other memory block MBB, DQ pad portions 150e-150h, ground pad 154b, and power supply pad 152b are arranged in alignment with each other.

  Power supply pad 152a is disposed between DQ pad portions 150a and 150b and connected to power supply line 156a extending along one side of DQ pad portions 150a-150d. Ground pad 154a is disposed between DQ pad portions 150c and 150d and is connected to a ground line 158a extending along the other side of DQ pad portions 150a-150d.

  On the other side of semiconductor device (chip) 140, ground pad 154b is disposed between DQ pad portions 150e and 150f, and power supply pad 152b is disposed between DQ pad portions 150g and 150h. Ground line 158b and power supply line 156b are disposed along one side and the other side of DQ pad portions 150e-150h.

  DQ pad portions 150a-150d and 150e-150h receive operation power supply voltages from corresponding power supply lines 156a or 156b and corresponding ground lines 158a and 158b, and execute data input / output operations for memory blocks MBA and MBB.

  By alternately arranging the power supply pads and the ground pads on each side of the chip peripheral portion of the pad peripheral arrangement type semiconductor memory device, the power supply lines and the ground lines are arranged in each group of the DQ pad portions with the minimum wiring length. Therefore, the wiring layout is facilitated, and the operation power supply voltage can be stably supplied to the corresponding DQ pad portion.

  Peripheral circuit 160 arranged in the central portion of semiconductor memory device 140 receives power supply voltage Vcc from power supply pad 161 arranged on one side via power supply line 163 and ground voltage from ground pad 162 arranged on the other side. The semiconductor device operates by receiving Vss via the ground line 164, and controls an access operation to the semiconductor memory device.

[Pin assignment 5]
FIG. 19 shows still another pin arrangement of the package of the semiconductor memory device according to the present invention.

  In the configuration shown in FIG. 19, a power supply pin terminal that receives power supply voltage Vcc and a ground pin terminal that receives ground voltage Vss are arranged on each side of memory package 55c with a pair of data input / output pin terminals interposed therebetween. The That is, on one side of memory package 55c, data input / output (DQ) pin terminals PT2c and PT3c at one end are arranged between power supply pin terminal PT1c and ground pin terminal PT4c, and at the other end, DQ pin terminal PT11c and PT 12c is arranged between power supply pin terminal 10c and ground pin terminal 13c.

  On the other side of memory package 55c, DQ pin terminals PT15c and 16c are arranged between ground pin terminal 14c and power supply pin terminal PT17c at one end, and DQ pin terminals PT24c and PT25c are connected to ground pin terminal PT23c and power supply at the other end. Arranged between pin terminals PT26c.

  Power supply pin terminal PT7c and ground pin terminal PT20c arranged at the center of each side of package 55c receive signals from address / clock pin terminals PT5c-PT6c, PT8c-PT9c, PT18c-PT19c and PT21c-PT22c. The circuit is used to supply operating power supply voltages of power supply voltage Vcc and ground voltage Vss to the circuit. Pin terminals PT1c-PT26c are arranged corresponding to internal bonding pads of the semiconductor memory device housed in package 55c.

  FIG. 20 shows an internal layout of the semiconductor memory device housed in package 55c shown in FIG. In FIG. 20, like the configuration shown in FIG. 10, only the portion related to the portion for inputting / outputting 4-bit data is representatively shown.

  The arrangement of FIG. 20 is the same as that shown in FIG. 10 except for the connection between the pad portion 60a and the leads PTAG and PTAH, and the corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. .

  Referring to FIG. 20, pad portion (power supply pad) 60a includes power supply pad 180aa connected to power supply lead (pin terminal) PTAH1 (for example, pin terminal PT26c) via a bonding wire indicated by a broken line, and bonding indicated by a broken line. A ground pad 180ab connected to ground lead PTAG (for example, pin terminal PT13c) through a wire is included.

  The configuration shown in FIG. 20 is the same as the arrangement shown in FIG. 10 because the arrangement of the internal pads is the same as the arrangement shown in FIG. Give effect.

  The pin arrangement shown in FIG. 19 can also be applied to a pad peripheral arrangement as shown in FIG.

[Pin assignment 6]
FIG. 21 is a diagram showing still another pin arrangement of the package according to the present invention. In the pin arrangement shown in FIG. 21, address / clock pin terminals (peripheral pin terminals) are arranged between power supply pin terminals or between ground pin terminals. That is, on one side of package 55d, address / clock pin terminals PT5d-PT7d are arranged between power supply pin terminals PT4d and PT8d, and address / clock pin terminals PT10d-PT12d are arranged between power supply pin terminals PT9d and PT13d. Is done. On the other side of package 55d, address / clock pin terminals PT21d-PT23d are arranged between ground pin terminals PT20d and PT24d, and address / clock pin terminals PT26d-PT28d are arranged between ground pin terminals PT25d and PT29d. In the central portion of package 55d, power supply pin terminals PT8d and PT9d are arranged adjacent to each other and opposed to ground pin terminals PT24d and PT25d arranged on the other side.

  Regarding the DQ pin terminal, on one side of the package 55d, the power supply pin terminal PT2d is arranged between the DQ pin terminals PT1d and PT3d, and the power supply pin terminal PT15d is arranged between the DQ pin terminals PT14d and PT16d. On the other side of package 55d, ground pin terminal PT18d is disposed between DQ pin terminals PT17a and PT19d at one end, and ground pin terminal PT31d is disposed between DQ pin terminals PT30d and PT32d at the other end. .

  According to the pin arrangement shown in FIG. 21, a powerful operating power supply voltage supply source can be realized for the peripheral circuit as shown in FIG.

  FIG. 22 is a diagram showing an internal layout of the semiconductor memory device housed in the package shown in FIG. In FIG. 22, only one arrangement of one and the other ends of the semiconductor memory device is representatively shown. In addition, memory blocks are not shown for the sake of simplicity.

  In FIG. 22, power pad portion 200 includes a power pad and a ground pad arranged between DQ pad portions (DQ1, DQ2) 202a, 202b and DQ pad portions (DQ3, DQ4) 202c, 202d. Each DQ pad portion 202a-202d includes an I / O buffer and a DQ pad portion. DQ pad portions (DQ1, DQ3) 202a, 202c receive operating power supply voltages Vcc and Vss through power supply wiring 210 including a power supply line and a ground line. The power supply wiring 210 is connected to the pad portion 200. DQ pad portions (DQ2, DQ4) 202b and 202d receive operating power supply voltages Vcc and Vss from pad portion 200 through power supply wiring 212.

  Each of the peripheral pad portions (PA1-PA3) includes a peripheral pad and a buffer, and is disposed between power supply pad portions 204a and 204b. DQ pad portions 202a-202d, power pad portions 200, 204a, 204b and peripheral pad portions 206a-206c are arranged in alignment with each other. Peripheral pad portions 206a-206c receive power supply voltage Vcc from power supply pad portions 204a and 204b through power supply line 214 and receive ground potential Vss through ground line 216. Each of power supply line 214 and ground line 216 only needs to have a power supply structure according to the internal structure of peripheral pad portions 206a-206c.

  Power supply pad portion 204a also supplies operating power supply voltages Vcc and Vss to memory block MB1 (not shown) via power supply wiring 217a, and to the other memory block MB2 (not shown) via power supply wiring 218a. It is shown to supply similar operating power supply voltages Vcc and Vss. Power supply pad portion 204b supplies operation power supply voltages Vcc and Vss to memory block MB1 through power supply wiring 217b, and supplies operation power supply voltages Vcc and Vss to memory block MB2 through power supply wiring 218b. Indicated.

  The power pad portion 204 c is arranged symmetrically with respect to the power pad portion 204 b with respect to the master control circuit 208. Master control circuit 208 receives operating power supply voltages Vcc and Vss through power supply wiring 220 from power supply pad portions 204b and 204c.

  According to the arrangement shown in FIG. 22, peripheral pad portions 206a-206c and master control circuit 208 receive operating power supply voltages Vcc and Vss from two pad portions, and these circuit portions are enhanced power supply voltage sources. It operates stably and accurately in response to the operating power supply voltage.

  In the pin arrangement shown in FIG. 21, a power supply pin terminal that receives power supply voltage Vcc and a ground pin terminal that receives ground voltage Vss may be arranged on the respective sides of package 55d.

[Pin assignment 6]
FIG. 23 is a diagram showing still another pin arrangement of the package for housing the semiconductor memory device according to the present invention. In the pin arrangement shown in FIG. 23, as the DQ power supply source, the power supply pin terminals are arranged so as to face each other on both sides of the package 55e, and the ground pin terminals are arranged so as to face each other on both sides of the package 55e. . A power pin terminal and a ground pin terminal are arranged on each side of the package 55e. That is, the power supply pin terminal PT1e and the ground pin terminal PT4e are arranged at one end of one side of the package 55e so as to sandwich the DQ pin terminals PT2e and PT3e therebetween, and the DQ pin terminal PT15e and A power supply pin terminal PT14e and a ground pin terminal PT17e are arranged so as to sandwich PT16e therebetween. Power supply pin terminal PT1e and ground pin terminal PT4e are arranged to face power supply pin terminal 14e and ground pin terminal PT17e, respectively. At the other end of the package 55e, the power supply pin terminal PT10e and the ground pin terminal PT13e are arranged so as to sandwich the DQ pin terminals PT11e and PT12e therebetween, and at the other end of the package 55e, the power supply pin terminal PT23e and the ground pin terminal PT26e. Are arranged so as to sandwich power supply DQ pin terminals PT24e and PT25e therebetween. Power supply pin terminal PT10e and ground pin terminal PT13e are arranged to face power supply pin terminal PT23e and ground pin terminal PT26e, respectively.

  At the center of the package 55e, the power supply pin terminal PT7e is disposed on one side of the package 55e, and the ground pin terminal PT20e is disposed on the other side so as to face the power supply pin terminal PT7e.

  Voltages Vcc and Vss applied to pin terminals PT7e and PT20e are operation power supplies of peripheral circuits which operate in response to signals applied via address / clock pin terminals PT5e-PT6e, PT8e-PT9e, PT18e-PT19e and PT21e-PT22e. Used as voltage.

  FIG. 24 shows an internal layout of the semiconductor memory device housed in the package shown in FIG. The arrangement shown in FIG. 24 is the same as the arrangement shown in FIG. 20 except for the power supply pad portion. The corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In FIG. 24, power supply pad 260a is connected to frame leads (pin terminals) PTAB and PTAI disposed on both sides of the semiconductor memory device (chip) via bonding wires indicated by broken lines, and ground pad 260b is provided on both sides of the chip. It is connected to the arranged frame leads (pin terminals) PTAG and PTAC via bonding wires indicated by broken lines.

  Power supply line 261 is arranged to be connected to power supply pad 260a and surround the DQ pad portion (I / O buffer and DQ pad). A ground line 262 is connected to the ground pad 260b and disposed so as to surround the DQ pad portion. Since power supply pad 260a receives power supply voltage Vcc from two frame leads (pin terminals) PTAB and PTAI and ground pad 260b receives ground voltage Vss from two frame leads (pin terminals) PTAG and PTAC, these wirings 261 and The voltage on 262 is stabilized, and the I / O buffer included in the DQ pad portion can be stably operated.

[Example of change]
FIG. 25 shows an arrangement of internal pads of the semiconductor memory device according to the present invention. In the arrangement shown in FIG. 25, four memory blocks MB1-MB4 (300a-300d) are shown as an example. DQ pad portions DQ1-DQ4 (305a-305d) are arranged corresponding to memory blocks 300a-300d, respectively. The arrangement of the DQ pad portion is the same as that shown in FIG. DQ pad portions 305a-305d input / output data to / from corresponding memory blocks MB1-MB4 (300a-300d), respectively.

  In the arrangement shown in FIG. 25, power supply bus bar 320a is further arranged on one side of chip 1 so as to be coupled to power supply pin terminals 15a and 15c and to extend over the chip to supply power voltage Vcc. To communicate. Power supply bus bar 320a has a portion extending over memory blocks 300a and 300c and extending in parallel with the central region.

  A ground bus bar 320b for supplying a ground potential is coupled to the ground pin terminals 15b and 15d on the other side of the chip 1 and extends over the chip 1 to transmit the ground voltage Vss. Ground bus bar 320b extends over memory blocks 300b and 300d, and has a portion parallel to the central region and parallel to (opposed to) power supply bus bar 320a.

  Each of power bus bar 320a and ground bus bar 320b is composed of a low-resistance conductor having a width sufficiently wider than the internal power supply wiring, and stably supplies power supply voltage Vcc and ground voltage Vss.

  Power pad portions 310a-310d are aligned with and corresponding to DQ pad portions 305a-305d.

  Each of power pad portions 310a-310d includes a power pad and a ground pad, which are connected to ground bus bar 320b and power bus bar 320a, respectively.

  Each of power supply pad portions 310a-310d supplies power supply voltage Vcc and ground voltage Vss only to the corresponding DQ pad portion. For example, power supply pad portion 310a supplies operating power supply voltages Vcc and Vss only to DQ pad portion 305a.

  There is no power supply wiring arranged to extend over a plurality of DQ pad portions. In other words, the power supply line and the ground line are only arranged with the minimum length, so that the area occupied by the power supply wiring can be reduced, and the peripheral circuit is arranged in the central portion of the chip where this power supply wiring is not provided This can be used as a region for improving the chip area utilization efficiency.

  In addition, power bus bar 320a and ground bus bar 320b have sufficiently large line widths (wider than bonding wires), and DQ pad portions 305a-305d are stably supplied with an operating power supply voltage and operate stably. Can do.

  Further, each of the DQ pad portions 305a to 305d receives the operation power supply voltage from the corresponding power supply pad portion 310a to 310d, and the power supply noise (ground noise or power supply voltage noise) generated in a certain DQ pad portion is reliably detected. Absorbed by power bus bar 320a and ground bus bar 320b, this power noise can be prevented from affecting other DQ pad portions, and the influence of noise can be reliably suppressed.

  Further, the power supply wiring does not extend beyond the corresponding DQ pad portion, and the DQ pad portions 305a to 305d are arranged in close proximity to the corresponding memory blocks 300a to 300d, and therefore the memory blocks 300a and 300b. And the area between the memory blocks 300c and 300d can be used for arranging peripheral circuits. In FIG. 25, the peripheral circuit region 4 is arranged at the central portion. In this region 4, since the power supply wiring for the DQ pad portion is not provided, this peripheral circuit region 4 can be used exclusively for the arrangement of the peripheral circuit, and the power supply wiring of this DQ pad portion is used. A complicated wiring layout to avoid is not required, the wiring layout for the peripheral circuit is facilitated, and the internal pad layout shown in FIG. 1 and the like can be easily realized. The peripheral circuit region 4 includes a power supply pad portion 7 as in the configuration shown in FIG. The power pad portion 7 may be coupled to the power bus bar 320a and the ground bus bar 320b, or may be connected to another power pin terminal (shown in FIG. 25) via a bonding wire and a frame lead.

  In the power supply pad portion, the power supply pad and the ground pad may be arranged so as to sandwich the corresponding DQ pad portion in the first direction. In addition, the arrangement of the power bus bar and the ground bus bar may be used in combination with that of the above-described embodiment. By arranging the power supply bus bar and the ground bus bar, the voltages Vcc and Vss can be stably supplied to each pad portion, and the wiring layout is facilitated.

  In the above embodiment, the peripheral circuit is described as having a function related to the operation of receiving the address signal and the clock signal and controlling the internal access operation. However, the peripheral circuit arranged at the center of the chip is a high voltage generating circuit for boosting a word line, which is normally used in a semiconductor circuit, and a negative voltage Vbb for generating a negative voltage Vbb applied to the substrate region of the memory array. A circuit that generates a constant voltage, such as a voltage generation circuit and an intermediate voltage generation circuit that generates an intermediate voltage for bit line precharging, may be included. In this case, by arranging a circuit that generates such a constant voltage in the center, all the wiring values for transmitting the constant voltage to each memory cell array can be made equal and affected by wiring resistance and the like. Therefore, a desired constant voltage of the same voltage level can be supplied to the memory array block, and stable operating characteristics can be ensured.

  In the above-described embodiment, a configuration in which data input / output is performed in units of 4 bits and all memory blocks operate simultaneously to input / output 1-bit memory cell data is shown as an example. However, data input / output may be performed in units of x8 bits or x16 bits. Furthermore, the block may use a configuration in which only two memory blocks are activated by changing the internal circuit.

  Further, in the above embodiment, the pad layout of the semiconductor memory device having the lead-on-chip configuration has been described. However, even in the case where the semiconductor memory device is not such a lead-on-chip configuration, the data input / output pad is also provided. Are distributed in correspondence with each memory block, each data input / output pad is grouped and a power supply pad is provided for each, and external signals (address signal and clock signal) are provided between the data input / output pad sections. A configuration in which an input pad is provided and a pad for supplying a power supply voltage to these peripheral circuits (which may be only an input buffer) is provided in the center, and an external pin terminal is arranged in the same manner as the pad If this is the case, it is possible to achieve the same effect and to incorporate a semiconductor memory device that operates stably and at high speed. It is possible to achieve an integrated circuit device.

  The present invention is generally applicable to a memory integrated device integrated on a semiconductor chip and mounted in a rectangular package.

  In particular, by applying the present invention to a semiconductor memory device having a LOC arrangement, a semiconductor memory device (semiconductor integrated circuit device) that operates stably and at high speed can be realized.

1 schematically shows a chip layout and an arrangement of internal pin terminals of a semiconductor memory device according to an embodiment of the present invention; FIG. FIG. 2 is a diagram schematically showing a configuration of a power supply pad and a data input / output pad unit shown in FIG. 1. FIG. 2 schematically shows a configuration of a memory block of the semiconductor memory device shown in FIG. 1. It is a figure which shows the layout of the peripheral circuit part in the semiconductor memory device of this invention. FIG. 5 is a signal waveform diagram used for explaining the effect of the semiconductor memory device shown in FIG. 4 while showing the setup time and holdup time defined for the semiconductor memory device. It is a figure which shows an example of the form of distribution of the power supply voltage from the power supply pad in the semiconductor memory device of this invention. It is a figure which shows the other form of distribution of the power supply voltage from the power supply pad in the semiconductor memory device of this invention. It is a figure which shows arrangement | positioning of the external pin terminal in the semiconductor memory device (semiconductor integrated circuit device) of this invention. It is a figure which shows other arrangement | positioning of the external pin terminal in the semiconductor memory device (semiconductor integrated circuit device) of this invention. FIG. 10 schematically shows an internal layout of the semiconductor memory device having the external pin terminal arrangement shown in FIG. 9. It is a figure which shows other external pin arrangement of the semiconductor memory device according to this invention. FIG. 12 is a diagram showing an internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 11. FIG. 12 is a diagram showing another internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 11. It is a figure which shows other external pin arrangement of the semiconductor memory device according to this invention. FIG. 15 is a diagram showing an internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 14. FIG. 15 is a diagram showing another internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 14. FIG. 15 is a diagram showing still another internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 14. FIG. 15 is a diagram showing still another internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 14. It is a figure which shows other external pin arrangement of the semiconductor memory device according to this invention. FIG. 20 is a diagram showing an internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 19. It is a figure which shows other external pin arrangement of the semiconductor memory device according to this invention. FIG. 22 is a diagram showing an internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 21. It is a figure which shows other external pin arrangement of the semiconductor memory device according to this invention. FIG. 24 is a diagram showing an internal pad arrangement of the semiconductor memory device housed in the package shown in FIG. 23. It is a figure which shows other internal pad arrangement | positioning of the semiconductor memory device according to this invention. 1 is a diagram schematically showing an entire configuration of a conventional semiconductor memory device. It is a figure for illustrating arrangement of a peripheral circuit in a conventional semiconductor memory device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor memory device (semiconductor chip), 2a, 2b, 2c, 2d Internal data bus, 3a, 3b, 3c, 3d Data input / output pad part, 4 Peripheral circuit, 4a Star control circuit, 5, 6, 7 Power supply pad, MB1, MB2, MB, MB4 memory block, 3aa, 3ba input / output buffer, 3ab, 3bb data input / output pad, 6a power supply voltage pad, 6b ground voltage pad, MA1 to MAn memory array, LCC local column circuit, LRC local row System circuit, 21a, 21b, 21c, 21d external signal input pad section, 22a, 22b, 22c, 22d internal signal line, PA1, PA2, PA3 peripheral pad section, 30, 31, 32, 33a, 33b, 40, 42a, 42b power supply line, 60a, 60b power supply pad, 60aa, 60bb, 63 Power supply voltage pads, 60ab, 60ba, 64 Ground voltage pads, 61a, 61b, 65 Power supply voltage transmission lines, 62a, 62b, 66 Ground voltage transmission lines, 80aa, 80ba, 80ca, 80da Data input / output pads, 80ab, 80bb, 80cb, 80db input / output buffer, 67 peripheral circuit, 70 power supply pad portion, 70a power supply pad, 70b ground pad, 73a, 74a, 75a, 76a DQ pad, 73b, 74b, 75b, 76b I / O buffer, 77a power supply Pad, 77b ground pad, 77c peripheral circuit, 91a, 92a, 93a, 94a DQ pad, 91b, 92b, 93b, 94b DQ buffer, 90a power pad, 90b ground pad, 95a power wiring, 96a ground line, 100a-100b DQ Pad part , 101, 103, 106, 108 Power pad, 102, 104, 105, 107 Ground pad, 109a, 109b Power line, 110a, 110b Ground line, 115a, 115b, 115c, 115d Power line, 116a, 116b, 116c, 116d Ground line, 125 power line, 127 ground line, 130a-130d power pad, 132a-132d ground pad, MBA, MBB memory block, 150a-150h DQ pad part, 152a, 152b power pad, 154a, 154b ground pad, 160 periphery Circuit, 161 power pad, 162 ground pad, 163 power line, 164 ground line, 80aa, 80ba, 80ca, 80da DQ pad, 180aa ground pad, 180ab power pad, 200 power pad part 202a to 202d DQ pad part, 210, 212, 214, 216 Power supply wiring, 206a to 206c Peripheral pad part, 204a, 204b, 204c Peripheral circuit power pad part, 208 Peripheral circuit, 260b Ground pad, 260a Power supply pad, 300a to 300d memory block, 310a-310d power pad portion, 305a-305d DQ pad portion, 320a power bus bar, 320b ground bus bar.

Claims (2)

A semiconductor integrated circuit device in which a semiconductor memory device is mounted in a rectangular package,
A first power supply pin terminal which is disposed at one end of one side of the package and is supplied with a power supply voltage used by the semiconductor memory device;
At least one first data pin terminal which is arranged adjacent to the first power supply pin terminal on the one side and which exchanges data with the semiconductor memory device;
A plurality of first peripheral pin terminals arranged between the first data pin terminal and a central portion on one side of the package and supplied with a signal for accessing the semiconductor memory device;
A second power supply pin terminal disposed at a central portion of the package and supplied with a power supply voltage to the semiconductor memory device;
A third power supply pin terminal which is disposed at the other end of one side of the package and is supplied with a power supply voltage to the semiconductor memory device;
At least one second data pin terminal disposed adjacent to the third power supply pin terminal for transferring data to and from the semiconductor memory device;
A plurality of second peripheral pin terminals which are arranged between the second data pin terminal and the second power supply pin terminal and to which a signal for accessing the semiconductor memory device is supplied;
A first ground pin terminal disposed at one end of the other side of the package facing the one side and facing the first power supply pin terminal, to which a ground voltage used by the semiconductor memory device is supplied;
On the other side, adjacent to the first ground pin terminal and opposed to the first data pin terminal, at least one third for exchanging data with the semiconductor memory device Data pin terminal,
A signal is provided between the third data pin terminal and the central portion on the other side of the package so as to face the first plurality of peripheral pin terminals, and accesses the semiconductor memory device. A third plurality of peripheral pin terminals;
A second ground pin terminal disposed at the center of the other side of the package so as to face the second power supply pin terminal and supplied with a ground voltage used by the semiconductor memory device;
A third ground pin terminal disposed at the other end of the other side of the package and supplied with a ground voltage used by the semiconductor memory device;
At least one fourth data pin terminal disposed adjacent to the third ground pin terminal and facing the second data pin terminal, for transferring data to and from the semiconductor memory device; And a signal for accessing the semiconductor memory device is provided between the fourth data pin terminal and the second ground pin terminal so as to face the second plurality of peripheral pin terminals. A semiconductor integrated circuit device comprising a fourth plurality of peripheral pin terminals. A semiconductor integrated circuit device in which a semiconductor memory device is mounted in a rectangular package,
A first power supply pin terminal which is disposed at one end of one side of the package and is supplied with a power supply voltage used by the semiconductor memory device;
At least one first data pin terminal which is arranged adjacent to the first power supply pin terminal on the one side and which exchanges data with the semiconductor memory device;
A power supply that is disposed on one side of the package so as to be adjacent to the first data pin terminal and sandwiching the first data pin terminal between the first power pin terminal and used by the semiconductor memory device A second power supply pin terminal to which a voltage is supplied;
A third power supply pin terminal which is disposed at a central portion on one side of the package and is supplied with a power supply voltage used by the semiconductor memory device;
A plurality of first peripheral pin terminals provided on one side of the package and supplied with a signal for accessing the semiconductor memory device between the second power supply pin terminal and the third power supply pin terminal;
A fourth power supply pin terminal which is disposed at the other end of one side of the package and is supplied with a power supply voltage used by the semiconductor memory device;
A fifth power supply pin terminal disposed on one side of the package between the third and fourth power supply pin terminals and supplied with a power supply voltage used by the semiconductor memory device;
At least one second data pin terminal arranged to be sandwiched between the fourth and fifth power supply pin terminals on one side of the package, and for transferring data to and from the semiconductor memory device ,
A plurality of second peripheral pin terminals which are arranged between the fifth power supply pin terminal and the third power supply pin terminal and to which a signal for accessing the semiconductor memory device is supplied;
A first ground pin terminal disposed at one end of the other side of the package facing the one side and facing the first power supply pin terminal, to which a ground voltage used by the semiconductor memory device is supplied;
On the other side, adjacent to the first ground pin terminal and opposed to the first data pin terminal, at least one third for exchanging data with the semiconductor memory device Data pin terminal,
The semiconductor memory device is used on the other side of the package so as to sandwich the third data pin terminal between the first ground pin terminal and the second power supply pin terminal. A second ground pin terminal to which a ground voltage is supplied;
A third ground pin terminal that is disposed opposite to the third power supply pin terminal at the center of the other side of the package and is supplied with a ground voltage used by the semiconductor memory device;
The other side of the package is disposed between the second ground pin terminal and the third ground pin terminal so as to face the second plurality of peripheral pin terminals, and accesses the semiconductor memory device. A third plurality of peripheral pin terminals to which signals are supplied;
A fourth ground pin terminal disposed at the other end of the other side of the package and supplied with a ground voltage used by the semiconductor memory device;
A fifth ground pin terminal disposed on the other side of the package so as to face the fifth power supply pin terminal and supplied with a ground voltage used by the semiconductor memory device;
At least one for transmitting / receiving data to / from the semiconductor memory device, disposed between the fourth and fifth ground pin terminals and opposed to the second data pin terminal. A fourth data pin terminal; and disposed on the other side of the package between the fifth ground pin terminal and the third ground pin terminal so as to face the second plurality of peripheral pin terminals, A semiconductor integrated circuit device comprising a fourth plurality of peripheral pin terminals to which a signal for accessing the semiconductor memory device is supplied.

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