JP4160150B2 - Random number device for gaming machines - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an improvement in a random number generator used in gaming machines, particularly pachinko gaming machines.
[0002]
[Prior art]
In the current game machine control program, an internal counter value is updated by a reset signal input from the outside at a constant period, and the counter value is used as a random number at the timing of winning a start winning opening. However, in this method, a program analysis is performed by a third party, and an illegal act of generating a winning signal at a jackpot timing from outside is induced. Therefore, unlike the so-called “plus 1 method” in which an independent random number generation circuit is provided inside or outside the chip, and the counter value as described above is updated one by one and the counter value at the winning timing is taken out as a random number, It may be possible to deal with such fraud by generating irregular random numbers. As a random number generation method used for the random number generation circuit, a linear congruential method, an M series, or the like is known. In particular, the M length (Maximum length sequence) as a random number generation method is widely used in communication fields such as spread spectrum communication, noise substitution used in control system simulations, and measurement control fields such as RAM fault diagnosis. It has been. It has been found that the M series has no statistical variation within one period, and in the environment of a large-scale computer or workstation, an M series having about 500 to 1000 stages of shift registers is used. Is 2500-1 to 21000-1, and is treated as having a virtually infinite period.
[0003]
[Problems to be solved by the invention]
However, this method is effective temporarily, that is, until the random number generation circuit is analyzed. However, in the long term, such a circuit may be analyzed if time is taken. Once analyzed, the analysis results reach all the gaming machines, so it is not necessarily an effective means. Therefore, even if the control chip of one gaming machine is analyzed, a means is required to prevent the effect from affecting the chips of other gaming machines. The present invention has been made to meet such a demand, and an object of the present invention is to provide a random number generation device in which it is extremely difficult to predict a random number generated for each gaming machine.
[0004]
[Means for Solving the Problems]
That is, the present invention provides a unique data storage means in which n-bit data is stored as an initial value ai and a number i (1 to k) or a number i (1 to k) unique to each gaming machine, and the unique data stored in the storage unit the initial value a i and uniform number i (1 to k) uniform number i (1 to k) or uniform number i (1 to k) is an M-sequence pseudo outputting a random n-bit input Random number generation circuit and n-bit random number output from the M-sequence pseudo-random number generation circuit are assigned bits by using scramble setting value as the scramble number i (1-k) stored in the unique data storage means, This object is achieved by a random number device for a gaming machine comprising: a bit scramble circuit 3 for providing a random number; and a read register for storing a random number bit-assigned by the bit scramble circuit with a predetermined bit width . According to a second aspect of the present invention, the initial value data from the unique data storage means is temporarily stored in a temporary storage memory, and the output data (n-bit random number data) of the M-sequence pseudo-random number generation circuit is further provided. Are output to the bit scramble circuit and stored in the initial value storage memory.
[0005]
[Action]
In the device according to the present invention, when each gaming machine is operated, the unique data storage means has an initial value unique to each gaming machine and a back number i as a gaming machine identification number as a scramble setting value to the scramble circuit of the device. The stored initial value is input to the random number generation circuit while using a common M-sequence pseudo random number generation circuit, bit scramble circuit, and register in each gaming machine when a lottery is performed by winning or the like. The random number data calculated there is different in principle because it is different for each gaming machine (for example, the initial value a i or the number i). Furthermore, as a result of random number data output from the M-sequence pseudo-random number generation circuit being scrambled by inputting different scramble setting values (back number i) in the bit scramble circuit, random number values drawn for each gaming machine are In the case of 16-bit data that is completely different, it is possible to set at least 216 (65,536) types of spine numbers, making it difficult to analyze the generation status of random numbers for each gaming machine.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
In the following, the invention will be described in detail according to the illustrated embodiment. FIG. 1 is a block diagram showing the concept of an embodiment according to the present invention. A unique number i (identification number) and an initial value ai (which may be used) or a number i ( 1 to k) stored in the unique data storage means 1, and an M-sequence pseudo-output that outputs n-bit data with the back number i (n bits) or the initial value a i stored in the unique data storage means 1 as an initial value. A random number generation circuit 2, a bit scramble circuit 3 to which output data (random number) of the M-sequence pseudo-random number generation circuit 2 is stored as a scramble set value stored in the unique data storage means 1, and the bit scramble Bit number scrambled by the circuit 3, for example, a random number unique to a gaming machine is read out by reading registers 0, 1... Z (4a to 4c) for reading an arbitrary number of bit data every 8 bits. Location is configured.
[0007]
The unique data storage means 1 includes initial value data ai or a spine number i as a base point of the first random number sequence for generating random numbers, a combination of arbitrary bits, and a basis for bit allocation to the read registers 4a to 4c. This is sent to the M-sequence pseudo-random number generation circuit 2 and the bit scramble circuit 3. The back number i (unique data) means a unique identification code assigned to each of the chips 1 to k (k: integer). The M-sequence pseudo-random number generation circuit 2 includes an n-bit width M-sequence generation circuit that generates a random number based on the initial value data from the unique data storage unit 1, and the generated random number is sent to the bit scramble circuit 3. . For example, as shown in FIG. 3, the bit scramble circuit 3 is composed of an arbitrary matrix-like switch group, and each bit of the M-sequence pseudo-random number generation circuit 2 is individually connected to each matrix-like switch group. The selection of arbitrary bits and the assignment of bits to the read registers 4a to 4c are determined by the unique data from the unique data storage means 1.
[0008]
For example, when the unique data (back number i) is “1” of 16 bits, for example, the seventh, thirteenth, fifth, eighth, first, sixth, ninth and sixteenth bits of the M-sequence pseudorandom number generation circuit 2 are read registers. 4a is assigned in order from the least significant bit (LSB). Similarly, for example, the third, tenth, fourteenth, fourth, eleventh, twelfth, and twelfth bits of the M-sequence pseudorandom number generation circuit 2 are read from the read register 4b. Allocated sequentially from the least significant bit. The above example shows the case where the unique data is 16 bits. In general, in the case of n bits (= 8 × Z), the number of read registers 4a to 4c is Z, and the bit allocation pattern can be arbitrarily set. By changing it, it becomes possible to provide a random number that is difficult to analyze easily. The read registers 4 a to 4 c are 8-bit width registers that store random number data from the bit scramble circuit 3. As the unique data storage means, for example, EPROM, EEPROM, flash ROM or the like is used.
[0009]
FIG. 2 shows the concept of a state in which the random number generation circuit according to the present invention is incorporated in a plurality of gaming machine chips. The unique data storage means 1 has a back number 1 to a back number k (k is an integer) for each chip. And k <2n) types of identification numbers. The number of the spine number is limited by the number of bits of the bit scramble circuit 3. For example, in the case of 16 bits, it is 216, so it is possible to select 65,536 types of spine numbers. In the case of assigning the back number i, the above number is repeatedly used. However, if there are 65,536 types, the probability that a model with the same number will be placed in one pachinko hall will be extremely low, which is almost impossible. As a result, the random number generation circuit of the gaming machine installed in the pachinko hall is scrambled (encrypted) by the M-sequence pseudo random number generation circuit 2 and the bit scramble circuit 3 based on the unique initial value and the uniform number i, respectively. Therefore, the same random number does not appear as one.
[0010]
Next, what is shown in FIG. 4 is a configuration in which the random number generation device is further made unreadable, and initial value data from the unique data storage means 1 is temporarily stored in the temporary storage memory 5. Further, the output data (n-bit random number data) of the M-sequence pseudo-random number generation circuit 2 is output to the bit scramble circuit 3 and is also stored in the initial value storage memory 5. As a result, when the gaming machine is restarted, the M-sequence pseudorandom number generation circuit 2 generates random number data with the initial value data stored in the memory 5 instead of the initial value data ai stored in the unique data storage means 1. In other words, it is possible to reduce the bias of the random value as much as possible.
[0011]
【The invention's effect】
As described above, the random number generation circuit according to the present invention uses the same M sequence pseudo generation circuit and bit scramble generation circuit itself, while using the initial value written in the specific data storage means set in each gaming machine. As a result of the scramble setting value being different depending on the gaming machine, even if it takes time to predict and analyze the random number generation status for one gaming machine, the analysis result can be applied to the random number generating circuit of another gaming machine. Since it is not possible, fraud can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining the operation of a first embodiment of a random number generator according to the present invention.
FIG. 2 is a conceptual block diagram showing a state in which the random number generation device according to the first embodiment of the present invention is installed in k gaming machines.
FIG. 3 is a conceptual diagram showing a setting example of a bit scramble circuit according to the present invention.
FIG. 4 is a block diagram for explaining the operation of the second embodiment of the random number generator according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Unique data memory | storage means 2 M series pseudorandom number generation circuit 3 Bit scramble circuits 4a-4c Arbitrary quantity read registers 0, 1, ... Z
5 memory

Claims (2)

Unique data storage means 1 in which n-bit data is stored as an initial value ai and a number i (1 to k) or a number i (1 to k) unique to each gaming machine;
M-sequence pseudo-random number generation circuit 2 for outputting a n-bit random number which said intrinsic data storage means 1 is stored in the initial value a i and uniform number i (1 to k) or uniform number i (1 to k) is input When,
The n-bit random number output from the M-sequence pseudo-random number generation circuit 2 is assigned a bit by using the back number i (1-k) stored in the unique data storage means 1 as a scramble set value , and a random number is provided. A bit scramble circuit 3;
A random number device for a gaming machine comprising read registers 4a to 4c for storing random numbers bit-assigned by the bit scramble circuit 3 with a predetermined bit width . A unique data storage means 1 in which n-bit data is stored as an initial value a i and a back number i (1 to k) or a back number i (1 to k) unique to the gaming machine;
A memory 5 in which the initial value a i and the back number i (1 to k) or the back number i (1 to k) stored in the unique data storage means 1 are temporarily stored;
The M-sequence pseudo-random number generation circuit 2 for outputting a random n-bit initial stored in the memory value a i and uniform number i (1 to k) or uniform number i (1 to k) is input,
The n-bit random number output from the M-sequence pseudo-random number generation circuit 2 is assigned a bit by using the back number i (1-k) stored in the unique data storage means 1 as a scramble set value , and a random number is provided. A bit scramble circuit 3;
The read scrambler 4a to 4c for storing the random numbers bit-assigned by the bit scramble circuit 3 with a predetermined bit width ;
A random number device for a gaming machine, wherein the random number output from the M-sequence pseudo-random number generation circuit 2 is stored in the memory 5.

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