JP4164075B2 - Gaming machine wiring inspection equipment - Google Patents

Description

  The present invention relates to a wiring inspection device for a gaming machine that inspects a connection state of signal lines from a received signal received via a signal line that electrically connects a main control device and an image control device in the gaming machine.

  In a gaming machine such as a ball game machine, a plurality of devices, for example, a main control device and a sub-control device are electrically connected to each other by signal lines. Various information is exchanged via this signal line. Since the number of game balls to be paid out is determined based on such information, the plurality of devices need to be appropriately connected to each other by signal lines. In addition, when a device that is not originally connected to a gaming machine is replaced and connected in order to perform an illegal act that makes the game result advantageous, it is also necessary to accurately detect that. .

  For this reason, an apparatus for inspecting whether or not an apparatus in a gaming machine is properly connected or whether an appropriate apparatus is connected has been devised, for example, disclosed in Japanese Patent No. 3078505. Such gaming machines are known.

  In this conventional gaming machine, when the number of signal lines connecting the devices is four, the first signal line has a binary value indicating "1"-"0"-"0"-"0" A binarized signal indicating “0”-“1”-“0”-“0” is supplied to the second signal line, and “0” is supplied to the third signal line. -A binary signal indicating "0"-"1"-"0" is supplied, and a binary signal indicating "0"-"0"-"0"-"1" is supplied to the fourth signal line. Supply the signal.

  In this way, by supplying different signals to each of the signal lines and determining whether or not the content of the signal received via the signal line is appropriate, the connection state of the signal line is inspected. For example, when inspecting the second signal line, if the content of the signal received via the second signal line is “0”-“1”-“0”-“0”, the second signal The line is determined to be in an appropriate connection state, and when the content of the received signal is other than this, it is determined that the second signal line is not in an appropriate connection state. Therefore, it is possible to determine whether or not the connection state of the signal line is appropriate by determining whether or not the received signal is the same signal as the supplied signal.

  As described above, in the conventional gaming machine, when four signal lines are connected, it is necessary to supply a signal corresponding to “0” or “1” to the signal line at least four times. That is, if a signal corresponding to “0” or “1” is not transmitted / received a number of times proportional to the number of signal lines, the connection state of the signal lines is inspected, and whether the connected device is appropriate. It was not possible to inspect whether or not.

  As described above, in order to determine the connection state of signal lines and whether or not the connected apparatus is appropriate in the conventional apparatus, “0” or “1” is equal to or more than the number of signal lines. It was necessary to supply a signal corresponding to.

  In addition, the purpose of providing gaming machines is to increase the interest of the players and attract them to the games, so that as much as amusement that can be enjoyed casually, the games by the gaming machines are permeated to as many people as possible. It is to follow. In order to achieve such an object, it is necessary to always provide a player with a novel and interesting game machine.

  For this reason, it is necessary to add a new game to the existing games or to devise an effect accompanying the progress of the game. In order to realize such a thing, the gaming machine has to be controlled in a more complicated manner, or it must be promptly processed. When performing complex control or speeding up processing, the number of signal lines that connect the control devices of the gaming machine may have to be increased. This trend is fully expected to continue. In particular, in the case where an effect is produced by an image, it is necessary to process a huge amount of data at a high speed in order to enhance the effect, and the number and type of signal lines must be increased. As the types and number of signal lines increase, the inspection of whether or not the signal lines are properly connected becomes complicated and the possibility of miswiring can increase. For this reason, it is necessary to facilitate the inspection of the signal lines.

  Furthermore, when it is discovered that a device that allows fraud is incorporated in the gaming machine, the player's enthusiasm for the game is immediately reduced due to suspicion and distrust of the gaming machine, and the above-mentioned purpose cannot be achieved. It is clear.

  The present invention has been made in view of the problems as described above, and can easily and quickly inspect that the signal lines connecting the control devices of the gaming machines are accurately connected, An object of the present invention is to provide a gaming machine wiring inspection device capable of detecting that a connected control device is appropriate.

In order to achieve the above object, the present invention, 2 ⁿ be a different 2 ⁿ pieces of identification signals to each other that can identify each of the signal lines low-level signal and a high-level signal and The identification signal comprising: a signal composed of either a low level signal or a high level signal is output up to n times, and the output signal is inspected.

Accordingly, this is a device for inspecting 2 ⁿ signal lines, and a signal consisting of either a low level signal or a high level signal is output up to n times, and the output signal is 2 ⁿ signals. A wiring inspection device for a gaming machine that is different for each of the lines is included in the concept of the present invention.

Further, 2 ⁿ + m has a different 2 ⁿ + m pieces of identification signals to each other that can identify each of the signal lines identification signal comprising a low-level signal and a high level signal, low level signals or high A signal composed of any of the level signals is generated up to n + 1 times and output to the signal line, and the output signal is inspected.

Accordingly, this is a device for inspecting 2 ⁿ + m signal lines, and a signal composed of either a low level signal or a high level signal is output up to n + 1 times, and the output signal is 2 ⁿ + m lines. A gaming machine wiring inspection apparatus that is different for each of the signal lines is included in the concept of the present invention.

  More specifically, the present invention provides a gaming machine wiring inspection apparatus as follows.

(1) 2 ⁿ different identifications capable of identifying each of 2 ⁿ signal lines (n is a positive integer value) electrically connecting the main control device and the image control device in the gaming machine An identification signal for supplying an identification signal comprising a low-level signal and a high-level signal from one of the main control device and the image control device to the other device via the signal line A wiring inspection device for a gaming machine including a supply means and inspecting a connection state of the signal line from a reception signal received via the signal line in the other device, wherein the other device receives the reception signal A signal line receiving unit that determines a connection state of the signal line by comparing a high level signal and / or a low level signal included in the signal with previously stored check data, and the identification signal supply unit includes: Trust Identification signal generation means for sequentially generating either the low-level signal or the high-level signal for each of the lines, and performing the process up to n times to generate the identification signal as the identification signal to the signal line And the identification signal generating means assigns a low level signal to 2 ⁿ / 2 signal lines and assigns a high level signal to the remaining signal lines at the time of signal generation each time. to generate a signal in the signal line allocation pattern, made different every signal line allocation pattern each time have a signal line allocation means for generating the identification signal, the signal line assigning unit assigns the current signal line For signal lines that are half of the signal lines to which the low-level signal was assigned in the previous signal line assignment, a low-level signal is assigned, and the remaining signal lines are assigned a high level. For signal lines that are half of the signal lines to which the high-level signal was assigned during the previous signal line assignment, the high-level signal is assigned, and for the remaining half of the signal lines A wiring inspection device for a gaming machine, characterized by assigning a low level signal .

(2) 2 ⁿ + m signal lines (n is a positive integer value and m is 1 or more (2 ^{n + 1} −2 ⁿ ) electrically connecting the main control device and the image control device in the gaming machine to each other. ) A positive integer value less than 2), which are 2 ⁿ + m identification signals different from each other, each of which includes an identification signal composed of a low level signal and a high level signal. An identification signal supply means for supplying the signal from any one of the image control devices to the other device via the signal line, and the signal line from the received signal received via the signal line in the other device; A wiring inspection device for a gaming machine that inspects the connection state of the game machine, wherein the other device compares a high level signal and / or a low level signal included in the received signal with check data stored in advance. To determine the connection status of signal lines The identification signal supply means sequentially generates either the low level signal or the high level signal for each of the signal lines, and performs this up to n + 1 times. It has an identification signal generation means for emitting the generated signal to the signal line as the identification signal, and the identification signal generation means assumes that there are 2 ^{n + 1} signal lines. the ^{n + 1/2} signal lines assigned a low level signal, to generate a signal in the signal line allocation pattern which allocates a high level signal to the rest of the signal line, the signal line allocation pattern each time the 2 ⁿ + m pieces of identification signals of said 2 ^{n + 1} pieces of identification signals in when to generate 2 ^{n + 1} pieces of identification signals made different all, each of the 2 ⁿ + m signal lines Supply the signal line allocation hand The stage assigns a low-level signal to the signal line that is a half of the signal line to which the low-level signal was assigned at the time of the previous signal line assignment, and assigns the low-level signal to the remaining signal lines. Assigns a high-level signal and assigns a high-level signal to the other half of the signal lines to which the high-level signal was assigned at the time of the previous signal line assignment, and the other half of the signal line. A wiring inspection device for a gaming machine , wherein a low-level signal is assigned to the line.

According to the above-described invention of (1), as an identification signal for 2 ⁿ signal lines, a signal generated by n times of either a low level signal or a high level signal is used, (2) According to the invention, as an identification signal for 2 ⁿ + m signal lines, because of the use of signals to one of the signal of the low level signal or a high level signal is generated by n + 1 times, 2 ⁿ times or Compared with the conventional device that had to be generated 2 ⁿ + m times, the state of the signal line, for example, whether or not the wiring is connected in the desired arrangement, or the signal line is disconnected or short-circuited in a very short time Thus, it is possible to generate an identification signal that can determine whether or not a failure such as the above has occurred. In addition, since the state of the signal line can be inspected in a short time, it can be inspected frequently, and can be inspected even while the game is in progress, and the state of the signal line can be accurately judged without interfering with the game. Can do.

  By doing so, it is possible to check whether or not the external device is properly connected to the gaming machine, and it is also possible to check whether or not the external device connected to the gaming machine is appropriate. It is.

  In addition, “generate a signal with a signal line allocation pattern” means that a signal line allocation pattern is stored in advance in a storage unit of a control device of a gaming machine, for example, a ROM, and a signal is output from the storage unit. Not only when a signal line assignment pattern is read out and a signal is generated as an identification signal in accordance with the read signal line assignment pattern, but also when the signal is generated, the signal line assignment pattern is determined by calculation processing each time, and calculation processing is performed. This includes the case where a signal is generated as an identification signal in accordance with the signal line allocation pattern obtained by the above.

  In this way, signals can always be generated with the same signal line assignment pattern, and the signal line assignment pattern order can be changed as appropriate by obtaining the signal line assignment pattern by an arithmetic process based on a certain rule. It is also possible to generate a signal. When the signal line assignment pattern order is appropriately changed to generate a signal, it is possible to detect the illegal act more accurately and to trigger the illegal act in advance. .

(3) The identification signal supply means outputs a high-level signal for a signal line that has issued a low-level signal for each of the n times up to n times, and a high level for all of the times up to the n-time. The gaming machine wiring inspection apparatus according to (1) above, wherein a low-level signal is generated n + 1 times for the signal line that issued the signal.

(4) The identification signal supply means outputs a high-level signal for a signal line that has issued a low-level signal for each of up to n + 1 times, and a high-level signal for all of the up to n + 1 times. The gaming machine wiring inspection apparatus according to (2) above, wherein a low-level signal is generated n + 2 times for the signal line that issued the signal.

According to the invention of (3) or (4) described above, 2 ⁿ signal lines or 2 ⁿ + m signal lines are connected in a signal line connection state, for example, in a desired arrangement. It is possible to generate an identification signal that can check whether or not a failure such as a disconnection or a short circuit has occurred in the signal line.

(5) wherein the other of the device and a high-level signal and / or a low-level signal included in the received signal, characterized in that it comprises a signal line determining means for determining a connection state of the signal line above ( A wiring inspection apparatus for gaming machines according to 1) to 4) .

(6) The image control device of a high-level signal and / or a low-level signal included in the received signal, characterized in that it comprises a signal line determining means for determining a connection state of the signal line above ( 1) - (4) the gaming machine wire inspection apparatus according.

According to the inventions of (5) and (6) described above, it is possible to determine that the signal line connecting the control devices of the gaming machine is properly connected, and the connected control device is appropriate. Can be determined.

  According to the present invention, it is possible to easily and quickly inspect that the signal lines connecting the control devices of the gaming machines are accurately connected, and the connected control devices are appropriate. It can be detected.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an overview of a bullet ball gaming machine that is an example of the gaming machine according to the present invention.

  The ball game machine 10 is provided with an outer frame 12 that forms an outer frame of the gaming machine, and a front frame 14 that is pivotally supported by the outer frame 12 so as to be openable and closable. Various members such as a glass door 16, an upper plate 18 and a lower plate 20 for receiving game balls, a hitting ball handle 22, and a storage unit for storing the game board 24 are provided.

  The game board 24 is provided with a game area 28 partitioned by rails 26, and an image display device 30 for displaying various images such as a graphic image is provided at a substantially central portion of the game area 28. Yes. Furthermore, in the game area 28, a specific prize opening 32 that defines a condition for starting the change of the symbols, a big prize opening 34 that opens and closes when the game is a big hit, a plurality of other general prize openings 36 and 38, a game Windmills 40 and 42 that affect the fall of the ball, a number of game nails (not shown), and an out port 44 are also provided.

  When the player rotates the hitting ball handle 22 described above, the game balls are supplied one by one from the upper plate 18 to the hitting ball launching unit (not shown). With a high strength, it is shot as a hit ball in the game area 28 by a hit ball launching device (160 shown in FIG. 2 described later).

  The hit ball launched into the game area 28 falls while changing the moving direction by repeatedly contacting the windmill and the game nail described above, and flows into the various winning holes 32 to 38 and the outlet 44 described above. When the hit ball wins any one of the winning holes 32 to 38, a predetermined number of game balls are paid out to the upper plate 18 or the lower plate 20 as a winning ball.

  Further, when a hit ball is won in the specific winning slot 32 of the winning holes, the symbols displayed on the image display device 30 start to change, and after a predetermined moving image and a pattern variation mode are displayed for a predetermined time. , Stop changing the design. When the symbol variation displayed on the image display device 30 is specific when the variation of the symbol is stopped, for example, when the numerical value indicated by the symbol is 1 to 9 The game is a big hit. When the game is a big hit, after a predetermined demo image is displayed on the image display device 30, the above-described big winning opening 34 is opened, and the hit ball can flow into the big winning opening 34.

  The open state of the big prize opening 34 is continued until a predetermined number of hit balls are won in the big prize opening 34, for example, ten pieces are won, or until a predetermined time elapses after the open state, for example, 30 seconds elapses. To do. Thereafter, the special winning opening 34 is closed. When the hit ball passes through a specific area (not shown) provided in the big prize opening 34 while the big prize opening 34 is open, the big prize opening 34 is temporarily closed. It will be opened again later. The operations of the open state and the closed state of the special prize opening 34 are repeated a plurality of times, for example, 15 times, and then the special prize opening 34 is closed.

An example of the structure of the back surface of the ball game machine shown in FIG. 1 is shown in FIG.
A back set board 100 is provided on the back side of the front frame 14 of the ball game machine 10, and the back set board 100 has a spare tank 110 for prize balls, a prize ball payout device 120, and prize ball control. The device 230, the prize ball passage 140 for supplying the stored balls from the prize ball reserve tank 110 to the prize ball payout device 120, the main controller 200 for overall control of the ball game machine 10, and the ball hitting device 160 A launch control device 150 is provided for controlling the above.

  The above-described prize ball control device 230 performs control relating to the prize ball based on the control signal issued from the main control device 200, and the prize ball payout device 120 performs predetermined control based on the control signal issued from the prize ball control device 230. The number of prize balls is paid out to the upper plate 18 or the lower plate 20.

  In addition, an image control device 260 for controlling the above-described image display device 30 is also provided in the approximate center of the back surface of the game board 24.

  A path (not shown) for guiding a hit ball is connected to the winning holes 32 to 38 described above, and a prize port sensor (170 shown in FIG. 3 to be described later) for detecting that the hit ball has passed. Is provided. The hit ball whose passage has been detected by the winning hole sensor 170 flows down to the already played ball flow path of the back set board 100 and is discharged to the outside of the bullet ball game machine 10.

  On the other hand, the hit ball that has flowed into the out port 44 immediately flows down to the already played ball flow path of the back set board 100 without being detected by the winning port sensor 170 and is discharged to the outside of the ball game machine 10. .

  The above-described winning port sensor 170 is electrically connected to the main control device 200. When the winning port sensor 170 detects the passing of a hit ball, it issues a detection signal to the main control device 200. The main control device 200 is electrically connected to the prize ball control device 230 via a plurality of signal lines (not shown), and the main control device 200 detects the detection signal generated from the winning hole sensor 170. Based on this, a prize ball command is issued to the prize ball control device 230. The prize ball control device 230 is electrically connected to the prize ball payout device 120, and the prize ball control device 230 emits from the main control device 200 in order to pay out a predetermined number of prize balls from the prize ball payout device 120. The prize ball payout device 120 is driven in accordance with the received prize ball command, and the prize ball payout device 120 pays out a predetermined number of prize balls to the upper plate 18 or the lower plate 20.

  As shown in FIG. 3, the ball and ball game machine 10 is configured with a main controller 200 as a center, and includes a prize opening sensor 170, an image control apparatus 260, a prize ball control apparatus 230, a big prize opening driving source 180, and various lamps 190. Each is electrically connected. The prize winning port driving source 180 is a solenoid for opening or closing the aforementioned prize winning opening 34, and various lamps 190 are provided on or around the game board 24, and the progress of the game. It is a lamp that lights up or flashes in response to.

  Main controller 200 is electrically connected to image controller 260 for processing the image data displayed on image display device 30 described above by signal lines (not shown) made up of a plurality of conductive lines. Further, the image control device 260 is electrically connected to the image display device 30 described above.

  When a game ball wins a winning opening of the specific winning opening 24, a design change start command signal is issued to the image control device 260 via the signal line described above. Receiving the symbol variation start command signal, the image control device 260 reads predetermined image data, for example, symbol image data, from a storage device such as a read-only memory of the image control device 260 and supplies it to the image display device 30.

  FIG. 4 is a block diagram showing a circuit configuration of the main control device 200, the prize ball control device 230, and the image control device 260 in the above-described bullet ball game machine.

  Main controller 200 includes central processing circuit (hereinafter referred to as CPU) 202, read only memory (hereinafter referred to as ROM) 204, random access memory (hereinafter referred to as RAM) 206, clock generation circuit 208, and input / output interface. The circuit 210 is connected to an input / output bus 212. The input / output bus 212 is configured to input / output data signals or address signals.

  The ROM 204 stores a program for controlling the progress of the game and a subroutine program for outputting an identification signal as shown in FIG. 6, FIG. 14, FIG. These programs are appropriately read from the ROM 204 and executed by the CPU 202. The RAM 206 stores variable values and flag values used when these programs are executed.

  The ROM 204 also stores a signal line assignment pattern as shown in FIG. 7, FIG. 16, FIG. 17, or FIG. The value of this signal line assignment pattern is read when the subroutine shown in FIG. 6 is executed.

  The clock generation circuit 208 generates a clock signal for determining the progress timing of the game at a predetermined time interval.

  The main control device 200 is connected to a sensor (not shown) such as the above-described winning detection sensor, and a process corresponding to the progress of the game is executed based on a signal emitted from the sensor. .

  The configuration of the prize ball control device 230 and the image control device 260 is the same as that of the main control device 200. The prize ball control device 230 includes a CPU 232, a ROM 234, a RAM 236, a clock generation circuit 238, and an input / output interface circuit 240. The image control device 260 includes a CPU 262, a ROM 264, a RAM 266, a clock generation circuit 268, and an input / output interface circuit 270.

  The ROM 234 of the prize ball control device 230 stores various data such as a program for controlling the prize ball payout device 120 and data corresponding to a prize ball command issued from the main control device 200. Further, the ROM 234 of the prize ball control device 230 is used to determine a program for receiving an identification signal shown in FIG. 9, FIG. 12, or FIG. 13 to be described later, and a signal line state shown in FIG. 10 or FIG. The program is stored.

  The ROM 264 of the image control device 260 stores a program for controlling the image display device 30, various image data such as design image data, and message data to be displayed. Further, the ROM 264 of the image control device 260 has a program for receiving an identification signal shown in FIG. 9, FIG. 12, or FIG. 13 described later, and a program for judging the state of the signal line shown in FIG. 10 or FIG. Is remembered.

  The input / output interface circuit 210 of the main controller 200 described above is electrically connected to the input / output interface circuit 240 of the prize ball controller 230 via a signal line 250. The input / output interface circuit 210 of the main controller 200 is also electrically connected to the input / output interface circuit 270 of the image controller 260 via the signal line 280.

The signal lines 250 and 280 are composed of a plurality of 2 ⁿ (n is a positive integer value) conductive lines such as 4 or 8, or 2 ⁿ + m lines such as 7 or 13 (n is a positive integer). The numerical value m is composed of a plurality of conductive lines of 1 or more and a positive integer value less than (2 ^{n + 1} −2 ⁿ ). From the signal lines 250 and 280, “2 ⁿ signal lines that electrically connect the main control device and the image control device in the gaming machine to each other” and “the main control device and the image control device in the game machine are electrically connected to each other. 2 ⁿ + m signal lines to be connected to each other ”.

  FIG. 5 shows a functional block diagram of the main controller 200, the prize ball controller 230, and the image controller 260 described above. In the functional block diagram shown in FIG. 5, as will be described later, an identification signal issued from the main control device 200 is received by the prize ball control device 230 or the image control device 260, and the signal lines 250 and 280 are connected. Only those related to the function of judging the state are shown. As described above, the main controller 200, the prize ball controller 230, and the image controller 260 are electrically connected to each other by the signal lines 250 and 280.

  The main controller 200 includes an identification signal supply unit 214, and the identification signal supply unit 214 includes an identification signal generation unit 216 and a signal line allocation unit 218. The signal line assigning means 218 determines which identification signal is assigned to each signal line constituting the signal line 250 or 280. The identification signal generation unit 216 generates the identification signal allocated by the signal line allocation unit 218. With this configuration, the identification signal supply means 214 can supply an identification signal that can identify each signal line constituting the signal lines 250 and 280 to the prize ball controller 230 and the image controller 260. It can be done.

  The prize ball control device 230 and the image control device 260 include an identification signal receiving unit 290, and the identification signal receiving unit 290 includes a signal line determination unit 292. The identification signal receiving unit 290 receives a signal supplied to the signal lines 250 and 280. The signal line determination unit 292 determines the connection state of the signal lines 250 and 280 based on the value indicated by the signal received by the identification signal reception unit 290. As will be described later, the value indicated by the received signal is a data value obtained by binarizing the received signal, for example, “0” or “1”. Judging from.

  In the following, some embodiments will be described and explained as the essence of the present invention. In the following description, it is assumed that the ball game machine is activated, and the CPU, ROM, RAM, input / output interface circuit, input / output bus and the like as described above are in steady operation.

[First embodiment]
FIG. 6 shows a subroutine of identification signal transmission processing executed in main controller 200 described above.

  First, initial processing for initializing variables and flags is executed (step S11), and a signal line allocation pattern is read from the ROM 204 of the main controller 200 (step S12).

This signal line assignment pattern is stored in the ROM 204 as a table as shown in FIG. Example shown in FIG. 7 (a), the signal lines 250 and 280 are those when it is configured of eight, namely 2 ^three signal lines. For convenience, the eight signal lines are distinguished from each other as first to eighth signal lines. The value indicated by the signal is indicated by using a data value “0” or “1” obtained by binarization.

  When step S12 is executed for the first time, the first row of the table shown in FIG. 7A is read. That is, a signal is assigned to each of the signal lines in a pattern of “1” for the first signal line to the fourth signal line and “0” for the fifth signal line to the eighth signal line. Become. A pattern shown in one horizontal row of the table shown in FIG. 7A indicates one “signal line allocation pattern”.

  After executing the process of step S12, it is determined whether it is time to output a signal (step S13). When it is determined that it is not the timing to output a signal, it waits until the signal is output. On the other hand, when it is determined that it is time to output a signal, a signal corresponding to the signal line allocation pattern read in step S12 is generated (step S14), and the generated signal is output to the signal lines 250 and 280 (step S14). S15).

  For example, the signal generated here is generated as a voltage signal of 0 volt for the data value “0”, and is generated as a voltage signal of 5 volt for the data value “1”. The voltage value of the signal is not limited to the voltage value shown here. For example, the data value “0” is generated as a voltage signal of 2.5 volts, and the data value “1” is 4.6 volts. It may be generated as a voltage signal. By generating such a signal, a “low level signal” or a “high level signal” is formed.

  In the above-described embodiment, the case where the level is distinguished by the voltage value is shown. However, if the signal can be identified by any measuring means capable of detecting the signal flowing through the signal lines 250 and 280, It is included in “low level signal” and “high level signal”.

Next, it is determined whether or not signals have been output to the signal lines 250 and 280 for all signal line allocation patterns (step S16). This determination is made as to whether or not the number of signal lines has reached n times when the number of signal lines is 2 ^{n as} will be described later. For example, when the number of signal lines is 8, it is determined whether it has reached 3 times.

  If it is determined that all the allocation patterns are not output to the signal lines 250 and 280, the process returns to step S12 described above. When performing the second process, in step S12, the signal line allocation pattern of the second line shown in FIG. 7A is read. That is, “1” is set for the first signal line, the second signal line, the fifth signal line, and the sixth signal line, and the third signal line, the fourth signal line, the seventh signal line, and the eighth signal line are set. On the other hand, a signal is assigned to each signal line with a signal line assignment pattern of “0”.

  When the process of step S12 for the third time is executed, the signal line allocation pattern for the third line shown in FIG. 7A is read. That is, “1” is set for the first signal line, the third signal line, the fifth signal line, and the seventh signal line, and the second signal line, the fourth signal line, the sixth signal line, and the eighth signal line are set. On the other hand, a signal is assigned to each signal line with a signal line assignment pattern of “0”.

  When the number of signal lines is 8, as described above, the processes in steps S12 to S16 are repeated three times. At the first time, the first row of the table shown in FIG. 7A is read to generate a signal, and at the second time, the second row of the table shown in FIG. 7A. In the third time, a signal is generated by reading the third row of the table shown in FIG. 7A. When the processing of steps S12 to S16 is repeated three times, in step S16 described above, it is determined that signals have been output to the signal lines 250 and 280 for all signal line allocation patterns, and this subroutine is terminated.

By performing such processing, when the number of signal lines is 2 ⁿ , the processing in steps S12 to S16 is repeated up to n times.

By repeating the processing of steps S12~S16 described above, the identification signal capable of identifying each of the 2 ⁿ signal lines, i.e., it is possible to generate different signals for every 2 ⁿ signal lines It can be done. For example, the signals generated for the first signal line are “1”-“1”-“1”, which is the identification signal of the first signal line. The signals generated for the sixth signal line are “0”-“1”-“0”, which is the identification signal for the sixth signal line.

When the number of signal lines is 2 ⁿ , the processes in steps S12 to S16 may be repeated up to n + 1 times. For example, when the number of signal lines is 8, the processes in steps S12 to S16 are repeated up to four times.

  In the embodiment described above, when the fourth signal is generated, the signal line allocation pattern in the fourth row shown in FIG. 7A is read to generate a signal. That is, a signal is assigned with a signal line assignment pattern having a data value “0” for the first signal line and a data value “1” for the eighth signal line. The symbol “−” shown in the fourth row of FIG. 7A indicates that a signal having an arbitrary data value may be assigned. That is, in the signal line assignment pattern in the fourth row, the data value “0” or the data value “1” may be assigned to the second signal line to the seventh signal line.

  When the signal line is assigned up to four times, the identification signal of the first signal line is “1”-“1”-“1”-“0”, and the identification signal of the eighth signal line is “ 0 "-" 0 "-" 0 "-" 1 ".

Thus, when the identification signal is generated by assigning the signal line up to four times, the connection state of all of the 2 ⁿ signal lines can be accurately determined as will be described later.

  By performing such processing, “a signal line that has issued a low-level signal for each of the n times up to a high level signal and a high-level signal for all of the n times up to n times. For the signal line that emitted the signal, a low level signal is generated n + 1 times ".

  FIG. 8 shows a time chart of the identification signal generated when the processing of the flowchart shown in FIG. 6 is executed with the signal line allocation pattern shown in FIG. The example shown in FIG. 8 is when the number of signal lines is 8, and signal lines are assigned up to four times to generate signals. In the fourth signal line assignment, the data value “0” is assigned to the second signal line to the seventh signal line.

  The signals generated by the first signal allocation for the first signal line to the eighth signal line are SG11 to SG81. SG11 to SG81 correspond to the signal line assignment pattern of the first row in FIG. Further, the signals SG12 to SG82 generated by the second signal allocation for the first signal line to the eighth signal line correspond to the signal line allocation pattern of the second row in FIG. Furthermore, the signals SG13 to SG83 generated by the third signal allocation for the first signal line to the eighth signal line correspond to the signal line allocation pattern of the third row in FIG. The signals SG14 to SG84 generated by the fourth signal allocation correspond to the signal line allocation pattern of the fourth row in FIG.

  The signals generated in this way are different signals for all of the first signal line to the eighth signal line, and form an identification signal that can identify the first signal line to the eighth signal line. For example, for the second signal line, an identification signal “1”-“1”-“0”-“0” is made from SG21, SG22, SG23, and SG24, and for the seventh signal line, SG71 and SG72. SG73 and SG74 form an identification signal “0”-“0”-“1”-“0”.

  In the above-described embodiment, the processing when the processing of the flowchart shown in FIG. 6 is executed using the signal line allocation pattern shown in FIG. 7A is shown. However, FIGS. The processing of the flowchart shown in FIG. 6 may be executed using the signal line allocation pattern shown in FIG.

  In the example shown in FIG. 7B, in the first allocation, “1” is set for the first signal line, the third signal line, the fifth signal line, and the seventh signal line, and the second signal. “0” is assigned to the line, the fourth signal line, the sixth signal line, and the eighth signal line. In the second round, “1” is set for the first signal line, the second signal line, the fifth signal line, and the sixth signal line, and the third signal line, the fourth signal line, the seventh signal line, and the “0” is assigned to 8 signal lines. Further, in the third time, “1” is set for the first signal line, the second signal line, the third signal line, and the fourth signal line, and the fifth signal line, the sixth signal line, and the seventh signal line. Also, “0” is assigned to the eighth signal line. Even when the signal is generated in this way, different signals can be generated for all of the first signal line to the eighth signal line, and this signal can be identified from the first signal line to the eighth signal line. It can be an identification signal.

  Also in the examples shown in FIG. 7C and FIG. 7D, different signals can be generated for all of the first signal line to the eighth signal line, and these signals are used as the first signal line to the eighth signal. It can be an identification signal that can identify a line.

As shown in FIGS. 7A to 7D, the allocation patterns are all different, but “1” is always assigned to half of the signal lines, and the remaining half of the signal lines. “0” is assigned to. By performing such a process, “a signal line assignment in which a low level signal is assigned to 2 ⁿ / 2 signal lines and a high level signal is assigned to the remaining signal lines at the time of each signal generation. “Generate a signal with a pattern”.

  Further, the assignment patterns shown in FIGS. 7A to 7D are not limited to the assignment patterns, and it is sufficient that all the assignment patterns assigned to each signal line are different. It is also possible to generate the identification signal by making all the patterns different.

  Further, by executing the processing with the above-described configuration, “for each of the signal lines, either the low level signal or the high level signal is sequentially generated, and this is performed up to n times. The generated signal can be issued to the signal line as the identification signal.

  Further, by generating an identification signal using a signal line assignment pattern as shown in FIG. 7, “a signal assigned with a low level signal at the time of the previous signal line assignment is assigned to this signal line assignment. For signal lines that are half of the line, a low-level signal is assigned, for the remaining signal lines, a high-level signal is assigned, and a signal that was assigned a high-level signal during the previous signal line assignment A signal having a high level may be assigned to a signal line that is half the line, and a signal having a low level may be assigned to the other half of the signal line.

  FIG. 9 shows a subroutine of identification signal reception processing executed in the prize ball control device 230 and the image control device 260.

  First, initial processing for initializing the values of variables and flags is executed (step S21). Next, it is determined whether or not the value indicated by the signal on one of the signal lines constituting the signal line 250 or 280 has changed (step S22). For example, when a signal as shown in FIG. 8 is supplied to the signal lines 250 and 280, SG11 to SG41 of SG11 to SG81 that are the first identification signals are changed from “0” to “1”. The value of the signal changes. By detecting when the value of this signal has changed, it is determined whether or not the value of the signal on one of the signal lines has changed.

  Next, the received signal value is converted into data by binarizing (step S23), and the obtained data value is stored in the RAM 236 or 266 (step S24). Hereinafter, the data obtained by this processing is referred to as received data.

Next, it is determined whether or not a signal has been received a predetermined number of times (step S25). This predetermined number of times is n times or n + 1 times when the number of signal lines is 2 ⁿ as in step S16 described above.

  After all signals supplied to the signal lines 250 and 280 are received, a subroutine for determination processing as described later is called and executed (step S26), and then this subroutine is terminated.

  FIG. 10 shows a subroutine of determination processing that is called and executed in step S26 of FIG.

  First, the value of the variable i is initialized, for example, set to 1 (step S31). The value of the variable i indicates the number of the signal line, and corresponds to 1 to 8 of the first signal line to the eighth signal line in the above-described example.

  Next, the data of the i-th signal line is read from the RAM 236 or 266 described above. For example, if the identification signal for the first signal line in the example when there are eight signal lines is normally received, the received data read from the RAM 236 or 266 is “1” − “1” −. It should be “1”-“0” (step S32).

  Next, check data for the i-th signal line stored in advance in the ROM 234 or 264 described above is read (step S33). This check data is data obtained by binarizing an identification signal to be received if the signal lines 250 and 280 are appropriately connected.

  Thereafter, the received data for the i-th signal line actually received is compared with the check data read from the ROM 234 or 264 (step S34). If it is determined that the received data is not different from the check data, the received signal matches the scheduled identification signal, and the process proceeds to step S40 described later.

  On the other hand, when it is determined that the received data is different from the check data, it is determined whether or not all the values of the read received data are “1” (step S35). When it is determined that the values of the received data are all “1”, it is determined that the i-th signal line is in a short circuit state (step S36). When it is determined that the values of all received data are not “1”, it is determined whether or not all the values of received data are “0” (step S37). When it is determined that the values of the received data are all “0”, it is determined that the i-th signal line is in a disconnected state (step S38). When it is determined that the values of the received data are not all “0”, it is determined that a wiring error has been made for the i-th signal line (step S39).

After executing the processing of step S34, step S36, step S38 or step S39 described above, the value of the variable i is increased by 1 (step S40), and it is determined whether or not all signal lines have been determined (step). S81). That is, it is determined whether all 2 ⁿ signal lines have been determined. If it is determined that all the signal lines have not been determined, the process returns to step S32 described above.

  If it is determined in step S81 that all signal lines have been determined, this subroutine is immediately terminated.

  As described above, when the number of signal lines is eight, the number of signal line assignments is three or four. When the number of signal line assignments is 3, the connection state of the signal lines can be determined for the second signal line to the seventh signal line by the determination process described above. However, when the number of signal line assignments is 3, the first signal lines are “1”-“1”-“1” and all are “1”. The connection status of the line cannot be determined. When the number of signal line assignments is 3, the eighth signal line is “0”-“0”-“0” and all are “0”. The connection status of the line cannot be determined.

  For this reason, the number of signal line assignments is four, and in the fourth assignment, “0” is assigned to the first signal line and “1” is assigned to the eighth signal line. By doing so, it is possible to determine the connection state of all the signal lines by the determination process described above.

Thus, when the number of signal lines is 2 ⁿ , the connection state of all the signal lines can be determined by allocating the signal lines up to n + 1 times.

[Second Embodiment]
In the first embodiment described above, the identification signal is unilaterally transmitted from the main controller 200 to the prize ball controller 230 and the image controller 260. On the other hand, only when the transmission permission signal is transmitted from the prize ball control device 230 or the image control device 260 to the main control device 200 and the transmission permission signal is received, the main control device is sent to the prize ball control device 230 or the image control device 260. It is good also as a structure which employ | adopts the structure which 200 transmits an identification signal, what is called an answer back system. An example is shown below.

  FIG. 11 shows a subroutine of identification signal transmission processing executed in main controller 200 in this case. Note that this subroutine corresponds to the subroutine of FIG. 6 described above, and steps for performing the same processing are denoted by the same reference numerals and description of part of the processing is omitted.

  In step S17, it is determined whether or not a transmission permission signal is transmitted from the prize ball control device 230 or the image control device 260. When it is determined that the transmission permission signal is transmitted, a signal corresponding to the allocation pattern is generated (step S14), and the generated signal is transmitted as an identification signal to the prize ball control device 230 and the image control device 260 (step S15). ).

  On the other hand, the prize ball control device 230 and the image control device 260 execute a subroutine as shown in FIG. Note that this subroutine corresponds to the subroutine of FIG. 9 described above, and steps for performing the same processing are denoted by the same reference numerals and description of part of the processing is omitted.

  After executing the initial process in step S21, it is determined whether or not to transmit a transmission permission signal to main controller 200 (step S27). This determination is made by, for example, whether or not the prize ball control device 230 or the image control device 260 has a margin for receiving a signal from the main control device 200 and executing the process, or receiving a signal from the main control device 200. This is performed by determining whether or not the timing should be.

  When it is determined that the transmission permission signal is not transmitted to the main control device 200, the process waits as it is. On the other hand, when it is determined that the transmission permission signal is transmitted to the main control device 200, the transmission permission signal is transmitted to the main control device 200 (step S28), and the processing after step S22 as described above is executed.

  As described above, the identification signal is transmitted from the main controller 200 to the prize ball controller 230 and the image controller 260 only when the transmission permission signal is received from the prize ball controller 230 and the image controller 260. Thus, the signal can be received with a margin, and the received signal can be accurately determined.

[Third embodiment]
Further, it is possible to determine the signal received by the winning ball control device 230 or the image control device 260 and determine whether or not to issue the above-described transmission permission signal based on the result.

  FIG. 13 shows a subroutine of identification signal reception processing executed in the prize ball control device 230 and the image control device 260 in such a configuration. This subroutine corresponds to the subroutine of FIG. 9 and FIG. 11 described above. Steps for performing the same processing are denoted by the same reference numerals, and description of some processing is omitted. And

  In step S23, after the value of the received signal is converted into data by binarizing, it is determined whether or not the received signal matches the planned signal based on the value of the received data (step S29). ). The process in step S29 is the same as the process in steps S32 to S34 of FIG. 10 shown in the first embodiment described above, and the received data obtained by binarizing the actually received signal and the ROM 234 or The check data read from H.264 is compared.

  For example, when it is determined that the main control device 200 outputs a signal in the signal line assignment pattern shown in FIG. 7A, the first signal output as the identification signal from the main control device 200 is the first signal. The signal line to the eighth signal line are “1”-“1”-“1”-“1”-“0”-“0”-“0”-“0”, and the winning ball control device 230 The image control apparatus 260 should receive this signal. Therefore, the prize ball control device 230 and the image control device 260 determine whether or not the received signal matches the signal output from the main control device 200 in step S29.

  In step S29, when it is determined that the received signal matches the planned signal, a transmission permission signal is transmitted to main controller 200, and the process of step S25 described above is executed. On the other hand, if it is determined in step S29 that the received signal does not match the planned signal, this subroutine is immediately terminated.

  By performing such processing, the connection state of the signal line can be quickly determined, and the identification signal can be transmitted and received accurately.

[Fourth embodiment]
In the first to third embodiments described above, the main controller 200 has shown a case where a signal is generated according to a signal line allocation pattern stored in advance in the ROM 204. However, the present invention is not limited to this. The signal line allocation pattern may be determined by calculation processing each time it is generated.

  FIG. 14 shows a subroutine for performing such processing. Note that this subroutine corresponds to the subroutine of FIG. 6 described above, and steps for performing the same processing are denoted by the same reference numerals and description of part of the processing is omitted.

  First, initial processing is performed (step S11). The processing in this subroutine is a process of assigning “0” to all signal lines, a process of assigning “1” to all signal lines, and the processes of steps S41 to S15 shown in FIG. Includes a process of determining the value of the maximum number n of times that are repeatedly executed.

  Next, “0” is assigned to the signal lines that are half of the signal lines to which “1” has been assigned (step S41), and the remaining half of the signal lines to which “1” has been assigned, “1” is assigned (step S42). Next, “0” is assigned to the signal lines that are half of the signal lines to which “0” has been assigned (step S43), and the remaining half of the signal lines to which “0” has been assigned, “ 1 "is assigned (step S44). Thereafter, after executing the processes of steps S13 to S15 described above, it is determined whether or not the number of times of executing the processes of steps S41 to S15 has reached the maximum number n determined in step S11 described above (step S45). ). When it is determined that the number of processes has not reached the maximum number n, the process returns to step S41. On the other hand, when it is determined that the number of processes has reached the maximum number n, this subroutine is immediately terminated.

  By executing the above-described processing, for example, when the number of signal lines is eight, when the processing from step S41 to step S44 described above is first executed, the first signal in FIG. The same line assignment pattern is obtained. Further, when the processing of step S41 to step S44 is executed for the second time, the same signal line allocation pattern as the second time of FIG. 7A is obtained. Furthermore, when the processing of step S41 to step S44 is executed for the third time, the same signal line allocation pattern as the third time of FIG. 7A is obtained.

  It should be noted that after executing the processing of step S45 described above, in the allocation up to n times, “1” is assigned to the signal line to which all “0” is assigned, and the signal line to which “1” is all assigned. When “0” is assigned to the signal and the signal is output, it becomes possible to determine a problem such as a wrong wiring or an illegal replacement of the wiring.

  By adding such processing, “the identification signal supply means outputs a high level signal and a maximum of n times for a signal line that has issued a low level signal for each of the n times. For a signal line that emits a high-level signal for each of the above, a low-level signal can be generated at the (n + 1) th time.

By performing the processing as described above, “for each of the signal lines, either the low-level signal or the high-level signal is sequentially generated, and this is performed up to n times to generate the generated signal. “To be issued to the signal line as the identification signal” and “When a signal is generated each time, a low level signal is assigned to 2 ⁿ / 2 signal lines, and a high level signal is assigned to the remaining signal lines. In addition to generating a signal with the signal line allocation pattern, the identification signal is generated by making all of the signal line allocation patterns different for each time different. "

[Fifth embodiment]
The determination processing shown in FIG. 10 described above is performed for each of the signal lines, and the determination is made for each of the signals received at each time. However, all the received signals may be determined at a time. . An example of such processing is shown in FIG.

  First, 0 is assigned to inspection data that is a variable (step S51), and 2 is stored in a variable i (step S52).

  Next, the XOR operation of the first received data and the i-th received data is performed, the result is stored in the variable Z (step S53), the OR operation of Z and the inspection data is performed, and the result is inspected. The data is stored (step S54).

Next, the value of the variable i is increased by 1 (step S55), and it is determined whether or not the value of the variable i is equal to or less than the total number of times required for reception (step S56). The total number of times required for this reception is, for example, four when the number of signal lines is eight. That is, when the number of signal lines is 2 ⁿ , n + 1 times. If it is determined that the value of the variable i is less than the total number of times required for reception, the process returns to step S53.

  If the actually received signal is a scheduled signal, when the received data becomes “0” and “1” while repeatedly executing the processes of steps S53 and S54 described above, Both cases always occur. For this reason, while the process is repeated, the value of Z obtained by the XOR operation in step S53 is always 1, and the value of the inspection data is 1 by the OR operation in step S54. When the value of the inspection data once becomes “1”, the value of the inspection data is always “1” regardless of whether the value of Z becomes “0” or “1”. It becomes. By executing such processing, when the actually received signal is a planned signal, the value of the inspection data is “1”.

  In step S56 described above, when it is determined that the value of the variable i is larger than the total number of times required for reception, 1 is substituted for the variable k (step S57), and the value of the inspection data of the kth signal line is 1. Whether or not (step S58). When it is determined that the value of the inspection data of the kth signal line is 1, the process proceeds to step S62 described later. When it is determined that the value of the inspection data of the kth signal line is not 1, it is determined that the kth signal line is in a short circuit state (step S60). When it is determined that the values of the received data are not all “1”, it is determined that the kth signal line is in a disconnected state (step S61).

  After executing the above-described step S58, S60 or S61, the value of the variable k is increased by 1 (step S62), and it is determined whether or not the value of the variable k is equal to or less than the total number of signal lines (step S62). S62). When it is determined that the value of the variable k is less than or equal to the total number of signal lines, the process returns to step S58, and when it is determined that the value of the variable k is greater than the total number of signal lines, this subroutine is terminated.

  By performing such a process, the determination process can be simplified.

[Sixth embodiment]
In the above-described embodiment, the number of signal lines is 2n (n is a positive integer), for example, 8 or 16, but the number of signal lines is 2 ⁿ + m (n is a positive number). An example in which m is a positive integer value greater than or equal to 1 and less than (2 ^{n + 1} −2 ⁿ ) is shown below.

When the number of signal lines is 2 ⁿ + m, the identification signal can be generated assuming 2 ^{n + 1} virtual signal lines.

For example, when the number of signal lines is 5, n = 2 and m = 1, so that an identification signal is generated assuming a virtual signal line with 2 ^{2 + 1} = 8. . Examples thereof are shown in FIGS. In FIGS. 16A to 16D, the signal line assignment pattern shown in FIG. 7A is used as a virtual eight signal line assignment pattern. That is, the signal line allocation pattern for 8 lines shown in FIG. 7A is used as a signal line allocation pattern for 8 virtual signal lines, and 5 signal lines are derived from the signal line allocation pattern for 8 lines. An allocation pattern is selected, and the selected signal line allocation pattern is allocated as a signal line allocation pattern of five actual signal lines.

  In the example shown in FIG. 16A, the actual five signals are the same as those of the first signal line to the fifth signal line in the eight signal line assignment patterns shown in FIG. This is a signal line assignment pattern of the first signal line to the fifth signal line.

  Further, FIG. 16B shows the second signal line to the sixth signal line of the eight signal line assignment patterns shown in FIG. 7A, and the actual five signal lines. This is a signal line allocation pattern of the first signal line to the fifth signal line. Similarly, FIG. 16 (c) shows the three signal lines to the seventh signal line of the eight signal line assignment patterns shown in FIG. 7 (a). FIG. 16D shows a signal line assignment pattern of the first signal line to the fifth signal line. FIG. 16D shows the fourth signal line of the eight signal line assignment patterns shown in FIG. The signal line allocation pattern of the first signal line to the fifth signal line of the actual five signal lines is used for the eighth signal line.

  In the example shown in FIGS. 16A to 16D, the continuous five signal lines are selected from the signal line assignment pattern of the eight signal lines shown in FIG. Although the case of allocating to signal lines has been shown, the present invention is not limited to this, and any five signal lines may be selected from the eight signal lines and allocated to the actual five signal lines. For example, the first signal line, the third signal line, the fourth signal line, the sixth signal line, and the eighth signal line are selected from the eight signal lines shown in FIG. The five signal lines may be allocated.

  The order of the signal lines may be different. For example, the sixth signal line of the virtual signal line is allocated to the first signal line of the actual signal line, the third signal line of the virtual signal line is allocated to the second signal line of the actual signal line, The eighth signal line of the virtual signal line is allocated to the third signal line of the signal line, the third signal line of the virtual signal line is allocated to the fourth signal line of the actual signal line, and the third signal line of the actual signal line is allocated. The eighth signal line of virtual signal lines may be allocated to the five signal lines.

  In the example shown in FIGS. 17A to 17C, six signal line assignment patterns are selected from the eight signal line assignment patterns shown in FIG. The signal line allocation pattern of the first signal line to the sixth signal line of the six signal lines.

  In the example shown in FIGS. 18A and 18B, seven signal line assignment patterns are selected from the eight signal line assignment patterns shown in FIG. The signal line allocation pattern of the first signal line to the seventh signal line of the seven signal lines.

  The signal line assignment patterns as shown in FIGS. 16 to 18 described above are stored in the ROM 204 in advance, and an identification signal can be generated by reading out the pattern.

In other words, 2 ⁿ + m signal line assignment patterns are selected from virtual 2 ^{n + 1} signal line assignment patterns, and the selected signal line assignment pattern is used as a signal of actual 2 ⁿ + m signal lines. By allocating as a line allocation pattern, it is possible to obtain a signal line allocation pattern when the number of signal lines is 2 ⁿ + m. The signal line allocation pattern obtained in this way is stored in the ROM 204 in advance, and the subroutine shown in FIG. 6 is executed, so that the signal line can be obtained even when the number of signal lines is 2 ⁿ + m. It is possible to inspect the connection state.

With the configuration as described above, “for each of the signal lines, either the low level signal or the high level signal is sequentially generated, and this is performed up to n + 1 times to generate the generated signal. “Send to the signal line as an identification signal” and “Assuming that there are 2 ^{n + 1} signal lines, a low level signal is assigned to 2 ^{n + 1/2} signal lines at each signal generation. When a signal is generated with a signal line allocation pattern in which a high-level signal is allocated to the remaining signal lines, and 2 ^{n + 1} identification signals are generated by making all the signal line allocation patterns different from each other. The 2 ⁿ + m identification signals of the 2 ^{n + 1} identification signals in FIG. 3 can be supplied to each of the 2 ⁿ + m signal lines.

[Seventh embodiment]
In the sixth embodiment described above, the main controller 200 has shown a case where a signal is generated in accordance with an allocation pattern stored in advance in the ROM 204. However, the present invention is not limited to this. Alternatively, the signal line assignment pattern may be determined by arithmetic processing.

  FIG. 19 shows a subroutine for performing such processing. Note that this subroutine corresponds to the subroutine of FIG. 14 described above, and steps for performing the same processing are denoted by the same reference numerals and description of part of the processing will be omitted.

First, a storage area for storing signal line allocation patterns of 2 ^{n + 1} virtual signal lines is secured in the RAM 206 of the main controller 200 (step S71). Next, by storing the same data in the storage area secured in step S71, the same data is substituted for all of the 2 ^{n + 1} signal line allocation patterns (step S72). For example, “0” is substituted for all 2 ^{n + 1} signal line allocation patterns, or “1” is substituted. Next, in order to allocate the actual 2 ⁿ signal line allocation patterns, 2 ^{n + 1} to 2 ⁿ are selected, and the selected ones are associated with the actual 2 ⁿ signal lines (step S73).

Next, the processes of steps S41 to S44 in FIG. 14 are executed. The processes in steps S41 to S44 are performed on the signal line allocation pattern of 2 ^{n + 1} virtual signal lines, and the data in the storage area secured in step S71 is updated. Is done.

After the signal line allocation pattern of 2 ^{n + 1} virtual signal lines is obtained by the processing of steps S41 to S44, signals are generated and output for the actual 2 ⁿ signal lines ( Steps S14 to S16).

  By performing processing in this way, a signal line assignment pattern can be obtained by performing arithmetic processing every time a signal is generated.

By performing such processing, “for each of the signal lines, either the low level signal or the high level signal is sequentially generated, and this is performed up to n + 1 times. “To the signal line as the identification signal” and “ ^{assuming that} there are 2 ^{n + 1} signal lines, a low level signal is applied to the 2 ^{n + 1/2} signal lines at each signal generation. Signals are generated with a signal line assignment pattern in which high-level signals are assigned to the remaining signal lines, and 2 ^{n + 1} identification signals are generated by making all the signal line assignment patterns different from each other. The 2 ⁿ + m identification signals of the 2 ^{n + 1} identification signals at the time may be supplied to each of the 2 ⁿ + m signal lines.

  Also in the sixth and seventh embodiments described above, the number of signal line assignments may be increased by one as in the first embodiment. For example, when the number of signal lines is five, the number of signal line assignments may be performed up to four times instead of three. In this way, the connection state of all the signal lines can be determined.

  By processing in this way, “for a signal line that has issued a low level signal for each of the times up to n + 1 times, a high level signal is output for each time up to n + 1 times. For a signal line that emits, a low level signal can be generated n + 2 times ”.

When the number of signal lines is 2 ⁿ -2, the number of signal line assignments is set to n, so that not only the determination of miswiring or illegal wiring replacement but also disconnection or short-circuiting can be performed. It can also be determined.

  In the above-described embodiment, the case where the connection state of the signal line is inspected from the value indicated by the received signal is shown, but when the main control device 200 determines that the signal is output with a predetermined signal line assignment pattern, A constant identification signal is always transmitted to the prize ball control device 230 and the image control device 260. Therefore, the prize ball control device 230 and the image control device 260 can determine that the predetermined main control device 200 is normally connected when a scheduled identification signal is transmitted.

  That is, when the scheduled identification signal is not transmitted to the prize ball control device 230 or the image control device 260, a device different from the main control device 200 to be originally connected is the prize ball control device 230 or the image control device 260. It can also be determined that it is connected to.

  By performing the configuration and processing as described above, it is possible to detect when a device that allows some fraud is incorporated in a gaming machine.

It is a front view which shows the general view of a bullet ball game machine. It is a figure which shows the general | schematic structure of the back side of a bullet ball game machine. It is a block diagram which shows the structure of a bullet ball game machine. 3 is a block diagram showing circuit configurations of a main control device 200, a prize ball control device 230, and an image control device 260. FIG. 3 is a block diagram illustrating functions of a main control device 200, a prize ball control device 230, and an image control device 260. FIG. 3 is a flowchart showing a subroutine of identification signal transmission processing executed in main controller 200. It is a figure which shows the example of a signal line allocation pattern when the number of signal lines is eight. It is a time chart of the identification signal produced | generated when the process of the flowchart shown in FIG. 6 is performed. 10 is a flowchart showing a subroutine of identification signal reception processing executed in the prize ball control device 230 and the image control device 260. It is a flowchart of the subroutine of the determination process called and performed in step S26 of FIG. 3 is a flowchart showing a subroutine of identification signal transmission processing executed in main controller 200. 10 is a flowchart showing a subroutine of identification signal reception processing executed in the prize ball control device 230 and the image control device 260. 10 is a flowchart showing a subroutine of identification signal reception processing executed in the prize ball control device 230 and the image control device 260. It is a flowchart which shows the subroutine which determines a signal line allocation pattern by arithmetic processing every time it produces | generates a signal. 7 is a flowchart showing a subroutine for determining the number of received signals all at once in the prize ball control device 230 and the image control device 260. It is a figure which shows the example of a signal line allocation pattern when the number of signal lines is five. It is a figure which shows the example of a signal line allocation pattern when the number of signal lines is six. It is a figure which shows the example of a signal line allocation pattern when the number of signal lines is seven. When the number of signal lines is 2 ⁿ + m, it is a flowchart showing a subroutine for determining a signal line allocation pattern by calculation processing each time a signal is generated.

Explanation of symbols

200 Main Control Unit 214 Identification Signal Supply Unit 216 Identification Signal Generation Unit 218 Signal Line Assignment Unit 230 Prize Ball Control Unit 250 Signal Line 260 Image Control Unit 280 Signal Line

Claims (6)

2 ⁿ identification signals different from each other that can identify each of 2 ⁿ signal lines (n is a positive integer value) electrically connecting the main control device and the image control device in the gaming machine. Identification signal supply means for supplying an identification signal comprising a low level signal and a high level signal from one of the main control device or the image control device to the other device via the signal line And a wiring inspection device for a gaming machine that inspects a connection state of the signal line from a reception signal received via the signal line in the other device,
The other device includes a signal line receiving means for comparing a high level signal and / or a low level signal included in the received signal with check data stored in advance to determine a connection state of the signal line. ,
The identification signal supply means sequentially generates either the low-level signal or the high-level signal for each of the signal lines and performs this up to n times as the identification signal. Having an identification signal generating means for emitting to the signal line, and
The identification signal generating means assigns a signal with a signal line assignment pattern in which a low level signal is assigned to 2 ⁿ / 2 signal lines and a high level signal is assigned to the remaining signal lines at the time of signal generation each time. to generate a, we have a signal line allocation means for generating the identification signal made different every signal line allocation pattern each time,
The signal line allocating means, for the current signal line allocation,
For signal lines that are half of the signal lines that were assigned a low level signal at the time of the previous signal line assignment, assign a low level signal, assign a high level signal for the remaining signal lines, and
Assign a high-level signal to half of the signal lines to which a high-level signal was assigned during the previous signal line assignment, and assign a low-level signal to the other half of the signal lines. A gaming machine wiring inspection device characterized by the above. 2 ⁿ + m signal lines (n is a positive integer value, and m is 1 or more and less than (2 ^{n + 1} −2 ⁿ ) to electrically connect the main control device and the image control device in the gaming machine 2 ⁿ + m identification signals different from each other, each of which can be identified as a positive integer value), and an identification signal composed of a low level signal and a high level signal is used as the main control device or the image control device. Including an identification signal supply means for supplying from one device to the other device via the signal line, and a connection state of the signal line from a received signal received via the signal line in the other device A game machine wiring inspection device for inspecting
The other device includes a signal line receiving means for comparing a high level signal and / or a low level signal included in the received signal with check data stored in advance to determine a connection state of the signal line. ,
The identification signal supply means sequentially generates either the low level signal or the high level signal for each of the signal lines, and performs the process up to n + 1 times as the identification signal. Having an identification signal generating means for emitting to the signal line, and
The identification signal generation means assigns a low level signal to 2 ^{n + 1/2} signal lines and generates the remaining signal lines on the assumption that there are 2 ^{n + 1} signal lines. is to generate a signal in the signal line allocation pattern which allocates a high-level signal, the at when made different every signal line allocation pattern each time and generates the 2 ^{n + 1} pieces of identification signals 2 ^{n + 1} 2 ⁿ + m of the identification signals are supplied to each of the 2 ⁿ + m signal lines ,
The signal line allocating means, for the current signal line allocation,
For signal lines that are half of the signal lines to which the low level signal was assigned at the time of the previous signal line assignment, a low level signal is assigned, for the remaining signal lines, a high level signal is assigned, and
Assign a high-level signal to half of the signal lines to which a high-level signal was assigned during the previous signal line assignment, and assign a low-level signal to the other half of the signal lines. A gaming machine wiring inspection device characterized by the above. The identification signal supply means generates a high level signal for a signal line that has emitted a low level signal for each of the n times up to n times, and a high level signal for all of the times up to the n times. 2. The gaming machine wiring inspection apparatus according to claim 1 , wherein a low level signal is generated n + 1 times for the signal line. The identification signal supply means generates a high level signal for a signal line that has emitted a low level signal for each of the n + 1 times, and a high level signal for all of the n + 1 times. 3. The gaming machine wiring inspection apparatus according to claim 2 , wherein a low level signal is generated n + 2 times for the signal line. Said other device, according to claim 1 to 4, the high level signal and / or a low-level signal included in the received signal, characterized in that it comprises a signal line determining means for determining a connection state of the signal line The game machine wiring inspection device described. 5. The image control apparatus according to claim 1 , further comprising: a signal line determination unit that determines a connection state of the signal line from a high level signal and / or a low level signal included in the reception signal. The game machine wiring inspection device described.

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