JP4167628B2 - Logic conversion circuit - Google Patents

Description

The present invention relates to the logical conversion circuits.

  The progress of semiconductor integrated circuit technology in recent years is remarkable, and various high-function logic integrated circuits have been developed in addition to simple memory elements. However, it can be said that the evolution of logic has not progressed since the advent of LSI, in that these logic circuits perform operations using binary signals. In current semiconductor integrated circuits, such binary operations can be performed at a very high speed for simple numerical calculations, but are rather easy for humans such as pattern recognition and image processing. There is a disadvantage that it takes a lot of time.

  On the other hand, research has been conducted to develop a computer that operates like a biological brain, that is, a neural circuit computer (neurocomputer), as an element that can perform high-speed arithmetic processing that is not possible with the conventional LSI. This neurocomputer has a structure in which a large number of neuron elements are connected like a neural circuit.

  Most conventional neuron elements are manufactured by CMIS devices, and in that case, they did not have a learning function of changing the operation of the circuit by learning. For example, Patent Document 1 describes a MIS type neuron element in which a large number of input units capacitively coupled to the gate electrode of a MISFET are arranged. This is a function that uses the capacitive coupling to perform the operation of adding the product of the signal strength and the coupling strength of the plurality of input terminals by the number of input units, but the function of storing the calculation result as a learning effect is I don't have it.

  On the other hand, in recent years, proposals relating to the first conventional example for realizing a learning function using the remanent polarization of a ferroelectric have been issued. For example, Patent Document 2 describes that, in a MIS type neuron element in which a plurality of input portions capacitively coupled to the gate electrode of a MISFET are arranged, all the capacitive insulating films of the input portions are made of a ferroelectric material. . Patent Document 3 describes an element in which a gate insulating film of a MISFET on the output side is made of a ferroelectric material in a MIS type neuron element in which a plurality of input portions capacitively coupled to a gate electrode of a MISFET are arranged. Yes.

  Further, LSIs are developing at a very high speed, and miniaturization and high integration of transistors are progressing. However, improvement in yield is difficult due to miniaturization of transistors and enlargement of chip area. In addition, the circuit scale becomes very large, and system LSIs that produce a wide variety of products in small quantities occupy the mainstream, which requires a lot of manpower and time for designing. For this reason, it is not easy to shorten the development period. A reconfigurable circuit has attracted attention as a solution to such a problem. A reconfigurable circuit is a circuit that enables rewriting with changes in circuit specifications after the manufacture of an LSI. Examples thereof include an FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device). These make it possible to realize a changeable logic circuit by combining basic logic blocks in multiple stages. That is, in this FPGA / CPLD, a switch element or a multiplexer is used as a program element, and the function is determined by a combination of basic logic circuits using these elements. However, in these methods, the area occupied by the redundant circuit of the basic logic block is large and the wiring becomes long. On the other hand, an element has been proposed that uses a ferroelectric to enable the program element itself to convert logic (for example, see Non-Patent Document 1).

  FIG. 15 is an equivalent circuit diagram of a neuron element according to the second conventional example described in the above publication. In this example, a residual charge is generated in a ferroelectric capacitor by a pulse signal, and the potential of the floating gate is controlled by using this residual charge, thereby realizing a logical conversion circuit between a NOR circuit and a NAND circuit. Are trying.

As shown in FIG. 15, this logic conversion circuit includes an n-channel MIS transistor (NMISFET 510). Here, the gate electrode of the NMISFET 510 is a floating gate 506 in a floating state that is not connected to other terminals. The source is grounded and the drain is connected to the output terminal 509. The output terminal 509 is connected via a load resistance element 508 to a power supply voltage supply terminal 507 for supplying a power supply voltage VDD.

  Also, two input terminals 500 and 501 that are capacitively coupled to the floating gate 506, paraelectric capacitors 503 and 504 interposed between the input terminals 500 and 501 and the floating gate 506, and a control terminal 502 that receives a control signal. And a ferroelectric capacitor 505 interposed between the control terminal 502 and the floating gate 506.

  Here, the logic of the input signal from the input terminal 500 is X1, the input signal from the input terminal 501 is X2, the charge amount of the control terminal 502 is CR, the charge amount φF of the floating gate 506, the output signal of the output terminal 509 Let Y be the logic. Further, the threshold voltage of the NMISFET 510 is set to 0V. Furthermore, when X1 and X2 are set to “1”, a charge amount Q0 is induced in each upper electrode (electrode on the input terminal side) of the paraelectric capacitors 503 and 504.

  FIG. 16 is a table showing the charge amount of each part with respect to the input signals X1 and X2 when a negative pulse signal is applied to the control terminal 502 as a table with the logical value of the output signal Y.

First, a negative voltage pulse signal is applied to the control terminal 502 to generate a residual charge of −Q0 / 2 on the upper electrode of the ferroelectric capacitor 505. At this time, the charge amount φF of the floating gate 506 is as shown in FIG. At this time, if the charge of the floating gate 506 is positive, a channel is formed at the SiO ₂ / Si interface and the MOS transistor is turned on, so that the output value Y becomes the value shown in FIG. As can be seen from FIG. 16, the circuit operation at this time is a NOR circuit operation.

  FIG. 17 is a table showing the charge amounts of the respective parts with respect to the input signals X1 and X2 when a negative pulse signal having a larger amplitude is applied to the control terminal 502, with the logical value of the output signal Y as a table.

  First, a negative voltage pulse signal with a larger amplitude is applied to the control terminal 502 to generate a residual charge of −3Q0 / 2 on the upper electrode of the ferroelectric capacitor 505. At this time, the charge amount φF of the floating gate 506 is as shown in FIG.

If the charge of the floating gate 506 is positive, a channel is formed at the SiO ₂ / Si interface and the NMISFET 510 is turned on, so the output value Y is as shown in FIG. As can be seen from FIG. 17, the circuit operation at this time is a NAND circuit operation. Thus, by controlling the residual charge of the ferroelectric capacitor, it is possible to realize a program element that is a logic conversion circuit of a NOR circuit and a NAND circuit.
Japanese Patent No. 312756 Japanese Patent No. 2929909 Japanese Patent No. 2942088 Naoichi Kawaguchi, Seimin Tsuji, Eisuke Tokumitsu, "61th JSAP Scientific Lecture Proceedings", 6a-g-1

However, Oite the logical conversion circuits according to the second conventional example, there is a disadvantage that residual charges generated in the ferroelectric film of the ferroelectric capacitor 505 is influenced by the potential φF of the floating gate 506.

Here, assuming that the voltage applied to the ferroelectric film (the control terminal side is positive) is Vferr, Vferr is expressed by the following formula (101).
Vferr = CR−φF = −φF (101)
It is represented by

  Here, attention is paid to the region where no pulse signal is applied to the control terminal 502, and the discussion proceeds. At this time, it can be seen from the equation (101) that the voltage applied to the ferroelectric film depends on the potential φF of the floating gate 506. Since φF varies depending on the input, the voltage applied to the ferroelectric film always varies according to the equation (101). As a result, there is a problem that the residual charge induced in the ferroelectric film fluctuates. This problem will be described with reference to the drawings.

18A and 18B are respectively a timing chart showing the time change of the potential of the floating gate of the logic conversion circuit according to the second conventional example, and the time change of the voltage applied to the ferroelectric film. It is a timing chart which shows. Here, the voltage value of the logical value “0” is 0V, and the voltage value of the logical value “1” is 5V. After inputting (0, 0), (1, 1), (0, 1), (1, 0) to the input terminals 500 and 501, respectively, a pulse signal of −10V is applied to the control terminal 502, and the ferroelectric Residual charges are induced in the body capacitor 505. Thereafter, inputs (0, 0), (1, 1), (0, 1), and (1, 0) are repeatedly input to the input terminals 500 and 501, respectively.

  At this time, as can be seen from FIG. 18A, it can be seen that the voltage applied to the ferroelectric film fluctuates even in a region where no pulse signal is applied. That is, as shown in the region Rx of FIG. 18A, the potential φF of the floating gate 506 with respect to the input (0, 1) before the pulse signal is applied and the potential φF with respect to the input (1, 0) are mutually different. Is different. This is because, as described above, when an input signal is applied to the input terminal, the voltage applied to the ferroelectric film of the ferroelectric capacitor varies. Further, as shown in a region Ry in FIG. 18A, after the pulse signal is applied to the control terminal 502, the floating gate potential φF for the same input for the first time and the second time is different from each other. This is also because when the voltage is applied to the input terminal, the voltage applied to the ferroelectric film of the ferroelectric capacitor is not constant, and the residual charge of the ferroelectric capacitor varies.

Thus, Oite the logical conversion circuits of the NOR circuit and the NAND circuit of the second conventional example, the results vary by the voltage residual charge of the ferroelectric capacitor is applied to the other input terminal, the ferroelectric capacitor There is a problem that the residual charge induced by the method cannot be stably maintained and the logic conversion function becomes unstable.

An object of the present invention is to provide a stable logic converting circuits.

The present invention for solving the above problems is a logic conversion circuit that can be switched between NAND circuit operation and NOR circuit operation,
The logic conversion circuit includes a plurality of signal input units (65), an output terminal (70), a control terminal (67), a power supply voltage supply terminal (71), an n-channel MIS transistor (61), and a potential generator (Egn). ),
With
The n-channel MIS transistor (61) includes a source terminal (62), a drain terminal (63), a gate insulating film (66), and a floating gate (64).
The output terminal (70) is connected to the drain terminal (63),
The power supply voltage supply terminal (71) is connected to the drain terminal (63) via a load resistance element (69),
The source terminal (62) is grounded;
Each of the plurality of signal input sections (65) includes an input terminal (65a) and a paraelectric film (65c), and one surface of each paraelectric film (65c) is formed on each input terminal (65a). And the other surface of each paraelectric film (65c) is connected to the floating gate (64),
The potential generator (Egn) is interposed between the control terminal (67) and the floating gate (64),
The potential generator (Egn)
A first semiconductor layer;
A first gate insulating film formed on the first semiconductor layer; a first gate electrode (211) formed on the first gate insulating film; and in the first semiconductor layer A first MISFET (56) having first and second P-type diffusion regions formed in regions located on both sides of the first gate electrode in FIG.
A second semiconductor layer;
A second gate insulating film formed on the second semiconductor layer; a second gate electrode (212) formed on the second gate insulating film; and in the second semiconductor layer A second MISFET (54) having first and second N-type diffusion regions formed in regions located on both sides of the second gate electrode in FIG.
A first electrode (52) commonly connected to the first and second gate electrodes, a second electrode (50) facing the first electrode (52), and the first electrode ( 52) a ferroelectric capacitor (51) having a ferroelectric film interposed between the second electrodes (50);
A first voltage supply unit (53) for supplying a first voltage to the first N-type diffusion region of the second MISFET (54);
A second voltage supply unit (57) for supplying a ground voltage lower than the first voltage to the first P-type diffusion region of the first MISFET (56);
An output voltage corresponding to the voltage input to the second electrode (52) of the ferroelectric capacitor (51) is connected in common to the second P-type diffusion region and the N-type diffusion region of each MISFET. A voltage output unit (55) for outputting,
The substrate potential of the first MISFET (56) is the first voltage,
The substrate potential of the second MISFET (54) is the second voltage,
The second electrode (50) is connected to the control terminal (67);
The voltage output unit (55) is connected to the floating gate (64);
Before applying a pulse signal to the control terminal (67), the threshold voltage of the n-channel MIS transistor (61) is applied with a logical value “1” to any one of the plurality of signal input sections (65). The logic conversion circuit operates as a NOR circuit by making it smaller than the potential of the floating gate (64) when
By applying a pulse signal to the control terminal (67), the NOR circuit is switched to the NAND circuit,
After a pulse signal is applied to the control terminal (67), the threshold voltage of the n-channel MIS transistor (61) is applied with a logical value “0” to any one of the plurality of signal input sections (65). The logic conversion circuit operates as a NAND circuit by making it larger than the potential of the floating gate (64) when
The NAND circuit is switched to the NOR circuit by resetting the polarization of the ferroelectric film.

The present invention, to provide a stable logic converting circuits may FIG Rukoto.

( Potential generator used in logic conversion circuit according to this embodiment )
FIGS. 1A and 1B are a plan view and a cross-sectional view taken along the line XIb-XIb, respectively, of a potential generator used in the logic conversion circuit according to this embodiment .

  In FIGS. 1A and 1B, 200 is an input electrode, 201 is an upper electrode of a ferroelectric capacitor, 202 is a ferroelectric film of the ferroelectric capacitor, 203 is a lower electrode of the ferroelectric capacitor, and 204 is Contacts 205 are substrate electrodes of P-type MIS transistors (hereinafter referred to as PMIS), that is, PMIS substrate electrodes, 206 are NMIS substrate electrodes of N-type MIS transistors (hereinafter referred to as NMIS), 207 are PMIS drain electrodes, 208 are output electrodes, 209 is an NMIS drain electrode, 210a is a first interlayer insulating film, 210b is a second interlayer insulating film, 211 is a PMIS gate electrode made of polycrystalline polysilicon, 212 is an NMIS gate electrode, 213 is a PMIS drain region, and 214 is PMIS source region, 215 is an NMIS source region, 216a is an NMIS region In region, 217 is an N-type well region, 218 is a P-type well region, 219 is a LOCOS oxide film, 220 is an N-type triple well region, 221 is a P-type Si substrate, 222 is an N-type high-concentration contact region, and 223 is P-type This is a type high concentration contact region. Although not shown in FIGS. 1A and 1B, silicon is not present between the PMIS gate electrode 211 and the N-type well region 216 and between the NMIS gate electrode 212 and the P-type well region 217. Gate insulating films such as an oxide film and a silicon oxynitride film are interposed.

  As shown in FIGS. 1A and 1B, an N-type well region 216 and a P-type well region 217 are provided in a P-type Si substrate 221, and the bottom surface of the P-type well region 217 and The side surface is surrounded by the N-type triple well region 220. Further, a LOCOS oxide film 219 is formed on the surface portion of the P-type Si substrate 221 so as to surround an active region where a transistor or the like is provided. On the P-type Si substrate 221, a first interlayer insulating film 210a and a second interlayer insulating film 210b made of a thick silicon oxide film are sequentially formed.

The potential generator includes a P-type MIS transistor (PMIS) formed on the N-type well region 217 and an N-type MIS transistor (NMIS) formed on the P-type well region 218. The PMIS source region 214 and the NMIS source region 215 are electrically connected to the common output electrode 208 via the contact 204. The NMIS drain region 216 is electrically connected to the NMIS drain electrode 209 receiving the power supply voltage via the contact 204, and the PMIS drain region 213 is electrically connected to the PMIS drain electrode 207 receiving the ground voltage via the contact 204. It is connected to the. The output electrode 208, the PMIS drain electrode 207, and the NMIS drain electrode 209 are all formed on the second interlayer insulating film 210b. A PMIS substrate electrode 205 and a P-type well region 217 are provided on the second interlayer insulating film 210b. An N-type high concentration contact region 222 is formed in the N-type well region 216, and the PMIS substrate electrode 205 is electrically connected to the N-type high concentration contact region 222 through the contact 204. A P-type high concentration contact region 223 is formed in the P-type well region 217, and the NMIS substrate electrode 206 is electrically connected to the P-type high concentration contact region 223 through the contact 204.

  The ferroelectric capacitor is formed on the lower electrode 203 formed on the first interlayer insulating film 210a, the ferroelectric film 202 formed on the lower electrode 203, and the ferroelectric film 202. And the upper electrode 201. The lower electrode 203 of the ferroelectric capacitor is electrically connected to the PMIS gate electrode 211 and the NMIS gate electrode 212, and the upper electrode 201 of the ferroelectric capacitor is an input provided on the second interlayer insulating film 210b. It is connected to the electrode 200.

When an input voltage is applied to the input electrode 200, when the capacitance value of the gate insulating film is very small compared to the ferroelectric film 202, the voltage applied to the ferroelectric film 202 becomes small. The residual polarization of the film 202 is reduced, and the voltage of the lower electrode 203, that is, the gate bias applied to the PMIS gate electrode 211 and the NMIS gate electrode 212 is reduced. In addition, when the capacitance value of the gate insulating film is much larger than that of the ferroelectric film 202, the distribution voltage to the ferroelectric film 202 increases, but the polarization eventually becomes saturated, so that V = Q / As can be seen from C, the voltage of the lower electrode 203, that is, the gate bias applied to the PMIS gate electrode 211 and the NMIS gate electrode 212 is also reduced. Thus, in order to maximize the gate bias, the capacitance ratio between the ferroelectric film 202 and the gate insulating film must be set to an optimum value. Therefore, if the material and film thickness of the ferroelectric film 202 and the gate insulating film are not changed, the area ratio between the ferroelectric film 202 and the gate insulating film becomes important. Here, since the ferroelectric film 202 is formed on the first interlayer insulating film 210a, the ratio between the ferroelectric film 202 and the gate insulating film can be easily adjusted.

Next, a method for manufacturing this potential generator will be described.

First, a LOCOS oxide film 219 is formed on the P-type Si substrate 221 as element isolation. Next , in order to independently control the substrate potential of each MIS transistor, an N-type triple well region 220 is formed in the region where the NMIS transistor is formed by high-energy As ion implantation. Although not shown, the N-type triple well region 220 is connected to the potential control electrode through a contact, and the N-type triple well region 217 and the N-type triple well region 220 are prevented from being forward biased. The potential of the well region 220 is controlled.

Here , in order to control the potential of each substrate region independently of each other, an N-type triple well is used here , but an SOI technology may be used.

  Next, an N-type well region 216 is formed by As ion implantation, and a P-type well region 217 is formed by B ion implantation.

  Thereafter, a gate insulating film having a thickness of 10 nm and a polycrystalline silicon film having a thickness of 400 nm are formed on the substrate, and then the polycrystalline silicon film is patterned to form a PMIS gate electrode 211 having a gate length of 5 μm and a gate width of 50 μm. Then, an NMIS gate electrode 212 having a gate length of 5 μm and a gate width of 25 μm is formed.

  Then, the PMIS drain region 213 and the PMIS source region 214 are formed in the N-type well region 216 by B ion implantation using the PMIS gate electrode 211 as a part of the mask. Similarly, an NMIS drain region 216a and an NMIS source region 215 are formed in the P-type well region 217 by As ion implantation using the NMIS gate electrode 212 as a part of the mask.

  Next, in order to reduce the contact resistance, the surface portions of the gate electrodes 211 and 212, the source regions 214 and 215, the drain regions 213 and 216a, and the high-concentration contact regions 222 and 223 are silicided. To do. Thereafter, a TEOS film by plasma CVD is deposited on the substrate to deposit a first interlayer insulating film 210a.

Next, holes that penetrate through the first interlayer insulating film 210a and reach the gate electrodes 211 and 212 are formed, and then contacts 204 such as tungsten filling the holes are formed. Thereafter, TiN is deposited as an adhesion layer on the first interlayer insulating film 210a and the contact 204 by CVD, and then a Pt film (platinum film) is deposited by sputtering. Then, the lower electrode 203 is formed by patterning the Pt film and the TiN film. In this case , lead lanthanum titanate ((Pb _0.85 (La _0.1 Ti _0.9 ) _0.15 O) having a substrate temperature of about 600 ° C. and an area of 50 μm ² and a film thickness of 400 μm is formed on the lower electrode 203 and the first interlayer insulating film 210a. ₃ ) After depositing a PLT film, which is a film, by sputtering, the PLT film is patterned to form a ferroelectric film 202 on the lower electrode 203. Thereafter, the ferroelectric film 202, the lower electrode 203, and the first electrode A Pt film is deposited on the first interlayer insulating film 210 a by sputtering, and then the Pt film is patterned to form an upper electrode 201 on the ferroelectric film 202.

  Next, a second interlayer insulating film 210b made of TEOS is deposited on the substrate, penetrating through the second interlayer insulating film 210b, the source regions 214 and 215, the drain regions 213 and 216, After forming holes reaching the high-concentration contact regions 222 and 223, the holes 204 are filled with tungsten or the like to form the contacts 204. Then, an Al wiring including the PMIS drain electrode 207, the output electrode 208, the NMIS drain electrode 209, the PMIS substrate electrode 205, the NMIS substrate electrode 206, the input electrode 200 and the like is formed on the second interlayer insulating film 210b.

  In this Al wiring, an input electrode 200 that is electrically connected to the upper electrode 201 of the ferroelectric capacitor is an electrode that receives an input signal, and an output that is electrically connected to the PMIS source region 214 and the NMIS source region 215. The electrode 208 is an electrode that outputs an output signal. The NMIS drain electrode 209 and the PMIS substrate electrode 205 are connected to a power supply voltage supply unit (not shown) that supplies the power supply voltage VDD. The PMIS drain electrode 207 and the NMIS substrate electrode 206 are connected to a ground (not shown) that supplies a ground voltage VSS.

Although a P-type Si substrate is used here , an N-type Si substrate may be used.

Figure 2 is an equivalent circuit diagram of the potential generator. As shown in FIG. 2, the gate portion 52, which is a common gate electrode of the N-type MIS transistor (NMISFET) 54, which is the second MISFET, and the P-type MIS transistor (PMISFET) 56, which is the first MISFET, This is equivalent to a circuit to which a ferroelectric capacitor 51 that is one capacitor is connected.

  The source which is one diffusion region of the N-type MIS transistor 54 and the source of the P-type MIS transistor 56 are connected to each other and to the output terminal 55. The drain which is the other diffusion region of the N-type MIS transistor 54 is connected to the power supply voltage supply unit 53 which supplies the power supply voltage VDD, and the drain of the P-type MIS transistor 56 is connected to the ground 57 which supplies the ground voltage VSS. . The substrate potential of the N-type MIS transistor 54 is the ground voltage VSS, and the substrate potential of the P-type MIS transistor 56 is the power supply voltage VDD. Thus, a circuit that extracts an output from a source is called a source follower circuit.

Here, the operation of the source follower circuit is a potential generator of this. It is assumed that the potential (gate bias) of the gate unit 52 is Vg and the potential of the output terminal 55 is Vs. It is assumed that the N-type MIS transistor 54 operates in the saturation region and the P-type MIS transistor 56 is in an off state. When the threshold voltage of the N-type MIS transistor 54 is Vtn and the threshold voltage of the P-type MIS transistor 56 is Vtp, the current Is flowing through the N-type MIS transistor 54 is expressed by the following equation (2).
Is = μn · Cox · Wn (Vg−Vs−Vtn) ² / 2Ln (2)
It is represented by Here, μn is the mobility of electrons, Cox is the capacitance of the gate insulating film, Wn is the gate width, and Ln is the gate length.

Since the P-type MIS transistor 56 is in the off state, it can be regarded as a very large resistance. For this reason, Is is almost zero. Therefore, from the equation (2), the potential Vs of the output terminal 55 is expressed by the following equation (3).
Vs = Vg−Vtn (3)
It is represented by

  That is, the potential Vs of the output terminal 55 is a value that is smaller than the potential Vg of the gate portion by the threshold voltage Vtn of the N-type MIS transistor 54. The range of the potential Vs of the output terminal 55 is between VSS and VDD. In this way, the input is transmitted almost directly to the next stage circuit by the source follower circuit. Furthermore, since the mutual influence between the source follower circuit and the preceding stage or the next stage circuit is small, the source follower circuit is used as a buffer amplifier (buffer) inserted between the circuits.

This potential generator, the ferroelectric capacitor between two MIS transistors 54 and 56 constituting a source follower circuit, the common gate 52 and the input terminal 50 is the gate electrode of the MIS transistor 54 and 56 51 is provided. When charges are induced in the gate portion 52 by the polarization of the ferroelectric capacitor 51, a voltage signal to be output from the output terminal 55 of the source follower circuit can be generated in a nonvolatile manner by the potential generated thereby.

Then, operation characteristics of this potential generator, FIG 3 will be described with reference to FIG. In the following description of the operation, the power supply voltage VDD is set to 0V, and the ground voltage VSS is set to -5V. Further, the threshold voltage of the N-type MIS transistor 54 is set to 1.0V, and the threshold voltage of the P-type MIS transistor 56 is set to −1.0V.

  3A and 3B are a time chart showing the time change of the voltage at the input terminal 50 and a time chart showing the time change of the voltage at the gate section 52 and the output terminal 55, respectively.

  As shown in FIG. 3A, when a pulse signal of −10 V is input to the input terminal 50, remanent polarization occurs in the ferroelectric capacitor 51. As shown in FIG. 3B, even after the pulse signal passes, the potential of the gate portion 52 is held at −0.85 V due to the residual polarization of the ferroelectric capacitor 51. Next, since the potential of the gate portion 52 is transmitted to the output terminal 55 through the above-described source follower circuit, as shown in FIG. 3B, the potential of the output terminal 55 is also passed after the pulse signal has passed. Is held at -2.2V. As described above, by inputting the pulse signal to the input terminal 50, the negative potential is held at the output terminal 55 due to the polarization of the ferroelectric capacitor 51 even after the potential of the input terminal 50 returns to 0V. . With this nonvolatile bias, the potential of the output terminal 55 can be held at a desired potential without constantly applying a voltage to the input terminal 50, and power consumption can be suppressed.

Next, the stability of the potential of the gate portion 52 in the circuit operation of this potential generator will be described with reference to FIG.

  4A, 4 </ b> B, and 4 </ b> C are sequentially a circuit diagram showing a configuration of a test circuit for examining the potential stability of the gate unit 52, and a time showing a time change of the potential of the input terminal 50. It is a time chart which shows a time change of a chart and potential of gate part 52.

  As shown in FIG. 4A, in addition to the potential generator shown in FIG. 2, the test circuit includes a second input terminal 59, the second input terminal 59, and an output terminal 55 of the potential generator. And a paraelectric capacitor 58 having a capacitance value of 0.1 pF. When a -10V pulse signal is input to the input terminal 50, a potential of -1.08V is generated in the gate portion 52. Thereafter, by inputting a 5V pulse signal to the second input terminal 59, a transient current flows through each of the MIS transistors 54 and 56 and the paraelectric capacitor 58 when the pulse signal rises and falls, respectively. Although the potential of the portion 52 varies slightly, it can be seen that in the region where the potential of the gate portion 52 is stable, the potential of the gate portion 52 becomes almost stable to −1.00 V and returns to the original set voltage.

Therefore, the potential generator of this, even when the output potential of the ferroelectric capacitor as in the conventional example is changed, the charge induced in the ferroelectric capacitor does not vary, the residual polarization is held stably The Further, the transient current can be suppressed by increasing the threshold voltage of the MIS transistor. However, increasing the threshold voltage affects the output as seen from the equation (3), and further transmits the potential. Since the MIS transistor sometimes does not operate in the saturation region, the threshold voltage cannot be increased too much.

In contrast, the potential generator of this, as described above, the threshold voltage of the N-type MIS transistor is 1.0 V, the threshold voltage of the P-type MIS transistor is -1.0 V, the threshold voltage of each MIS transistor Even if it is not so large, the optimum operation can be obtained. As described above, the potential generator is configured by connecting the source follower circuit to the ferroelectric capacitor 51, so that even if the pulse signal is applied to the second input terminal 59 to change the potential of the output terminal 55, the gate is changed. The potential of the portion 52 hardly changed.

As described above, according to the potential generator of this, by using the ferroelectric capacitor 51, without the addition of constantly voltage to the input terminal 50, the residual polarization of the output terminal 55 potential, of that is the output signal It is possible to keep the voltage almost constant. Thereby, reduction of the power consumption of the circuit using this electric potential generator is realizable.

  In particular, by connecting a source follower circuit to the output side electrode of the ferroelectric capacitor 51, the residual polarization generated in the ferroelectric capacitor 51 even when a voltage fluctuation is applied to the output section (output terminal 55) of the source follower circuit. Has little effect. That is, the potential induced by the remanent polarization is stably transmitted to the next stage circuit through the source follower circuit.

Here, PLT is used as the material constituting the ferroelectric film of the ferroelectric capacitor. However, the ferroelectric film of the present invention may be any material as long as it exhibits a polarization characteristic with hysteresis. For example, bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ) (BIT), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ) (Y1), lead zirconate titanate (Pb (Zr _0.45 Ti _0.55 ) O ₃ ) ( By using a ferroelectric material such as PZT) or a polymer compound that stores data by utilizing charge bias as a ferroelectric film in the ferroelectric capacitor of the potential generator of the present invention, The same effect as the embodiment can be obtained.

( Potential generator as reference example 1 )
FIG. 5 is an equivalent circuit of the potential generator as Reference Example 1 .

As shown in the figure, the potential generator includes almost the same elements as potential generator shown in FIG. 2, in the present embodiment, the gate of the N-type MIS transistor 54 is connected to the ground 57 2 is different from FIG. 2 in that it is maintained at the ground potential VSS.

Operating characteristics of this potential generator is similar to FIG. 2, where, the N-type MIS transistor 54 functions as a high resistance, to increase the threshold voltage Vpt of the P-type MIS transistor 56 And there is an advantage that the transient current can be extremely reduced.

Instead of the N- type MIS transistor 54, a resistance element having a high resistance value may be arranged.

( Potential generator as reference example 2 )
FIG. 6 is an equivalent circuit diagram of the potential generator as Reference Example 2 .

As shown in the figure, the potential generator of this includes almost the same elements as potential generator shown in FIG. 2, in the present embodiment, P-type MIS transistor source voltage supply unit 53 gates the 56 2 is different from that shown in FIG. 2 in that the power supply voltage VDD is maintained.

Operating characteristics of this potential generator is similar to FIG. 2, where, since the P-type MIS transistor 56 functions as a high resistance, without increasing the threshold voltage Vpn of the N-type MIS transistor 54 There is an advantage that the transient current can be extremely reduced.

Instead of the P- type MIS transistor 56, a resistance element having a high resistance value may be arranged.

(First Embodiment)
FIG. 7 is an equivalent circuit diagram of the logic conversion circuit according to the first embodiment .

Logic conversion circuit of this embodiment, the source over the scan terminals 62, and the drain terminal 63, a gate insulating film 66, and a n-channel type MIS transistor (NMISFET61) and a gate electrode. Here, the gate electrode of the NMISFET 61 is a floating gate 64 in a floating state that is not connected to other terminals. The source terminal 62 is grounded together with the substrate region of the NMISFET 61, and the drain terminal 63 is connected to the output terminal 70. The output terminal 70 is connected to a power supply voltage supply terminal 71 for supplying a power supply voltage VDD via a load resistance element 69.

  In addition, two signal input portions 65 that are capacitively coupled to the floating gate 64 are provided. The signal input unit 65 includes an input terminal 65a, an input gate electrode 65b connected to the input terminal 65a, and a paraelectric film 65c interposed between the input gate electrode 65b and the floating gate 64. That is, the input gate electrode 65b and the floating gate 64 are capacitively coupled by the paraelectric film 65c. However, three or more signal input units 65 may be provided.

Then, in the present embodiment, a control terminal 67 for receiving a control signal, potential generation equipment shown in FIG. 2 is interposed between the floating gate 64. That is, the control terminal 67 and the input terminal 50 of the potential generator are connected, and the output terminal 55 of the potential generator and the floating gate 64 are connected.

  In the present embodiment, the capacitance value of each paraelectric film 65c of the input unit 65 is 0.5 pF, and the electrical resistance of the load resistance element 69 is 100 kΩ. The gate length of the N-type MIS transistor 61 is 10 μm, the gate width is 50 μm, and the threshold voltage is −0.8V. The voltage VDD of the power supply voltage supply terminal 71 is set to 5V.

  Next, the operation characteristics of the circuit of this embodiment will be described with reference to FIGS. 8 (a), (b) and FIG.

  FIGS. 8A and 8B are time charts showing temporal changes in the potential of the floating gate 64 when the logical values of the input signals input to the input terminals 65a of the two input sections 65 are changed in sequence. 6 is a time chart showing a time change of a voltage applied to the chart and the ferroelectric capacitor 51; Here, after the logic value signals (0, 0), (1, 1), (0, 1), (1, 0) are input to the input terminals 65a of the two input sections 65, the control terminal 67 A pulse signal of −10 V is applied to the ferroelectric film 51 to generate a residual charge in the ferroelectric film of the ferroelectric capacitor 51. Thereafter, the logical value signals (0, 0), (1, 1), (0, 1), (1, 0) are repeatedly input to the input terminals 65a of the two input sections 65.

At this time, as can be seen from FIGS. 8A and 8B, the voltage applied to the ferroelectric capacitor 51 is substantially constant in a region where no pulse signal is applied. This is because the floating gate 64 of the logic conversion circuit of this embodiment corresponds to an electrode connected to the output terminal 55 of the paraelectric capacitor 58 shown in FIG. 4A, and as shown in FIG. It can also be seen from the fact that the voltage of the gate portion 52 connected to the ferroelectric capacitor is not subject to fluctuations due to fluctuations in the voltage applied to the output terminal 55. That is, in the logic conversion circuit of the present embodiment, the potential generator Egn shown in FIG. 2 is interposed between the floating gate 64 and the control terminal 67, so that the potential VF of the floating gate 64 is ferroelectric. The voltage applied to the ferroelectric film of the capacitor 51 is hardly affected, and the voltage of the ferroelectric film can be kept almost constant.

  Specifically, as shown in the region Rx of FIG. 8A, before the pulse signal is applied to the control terminal 67, the floating gate 64 when the logical value (0, 1) is input is received. The potential and the potential of the floating gate 64 when receiving the input of the logical value (1, 0) are substantially the same. 8A, after the pulse signal is applied to the control terminal 67, the potential of the floating gate 64 when the same logic value is input for the first time and the second time is received. It is almost the same. This is because the voltage applied to the ferroelectric material hardly fluctuates, and the residual charge induced in the ferroelectric material does not fluctuate.

FIG. 9 is a time chart showing the time change of the potential Vout of the output terminal 70 with respect to the same logical value input as in FIG. In this example, the threshold voltage of the N-type MIS transistor 61 is set to the potential of the floating gate 64 when the logical value “1” is applied to one of the two input sections 65 before the pulse signal is applied to the control terminal 67. After the pulse signal is applied to the control terminal 67, the potential is made higher than the potential of the floating gate 64 when the logical value “0” is applied to one of the two input portions 65. As shown in FIG. 9, the logic conversion circuit of this embodiment operates as a NOR circuit before a pulse signal is applied to the control terminal 67, and NANDs after the pulse signal is applied to the control terminal 67. Operates as a circuit.

In the present embodiment, as described above, the threshold voltage of the N-type MIS transistor is set to −0.8V. Further, it can be seen that the logic can be converted by the residual charge induced in the ferroelectric capacitor. Thus, the present implementation mode, since the residual charge induced in the ferroelectric film does not change, the circuit operation of the logic conversion circuit is realized to be a very stable as compared with the conventional example. Needless to say, when the circuit operation of this embodiment is operating as a NAND circuit, it is possible to switch from NAND circuit operation to NOR circuit operation by resetting the polarization of the ferroelectric.

In the present embodiment, an N-type MIS transistor and a load resistor circuit are used as the inverter circuit, but a P-type MIS transistor and a load resistor may be used.

(First reference form)
FIG. 10 is an equivalent circuit diagram of the logic conversion circuit according to the first reference embodiment . The logic conversion circuit according to this embodiment includes a p-channel MIS transistor (PMISFET 73) connected in series to the NMISFET 61 in place of the load resistance element 69 in the structure shown in FIG. That is, an inverter circuit composed of a CMIS device is provided. The source of the PMISFET 73 is connected to the power supply voltage supply unit that supplies the power supply voltage VDD, and the drain of the PMISFET 73 is connected to the drain of the NMISFET 61. The output terminal 70 is connected to the drain of the NMISFET 61 and the drain of the PMISFET 73. The floating gate 64 is provided across the NMISFET 61 and the PMISFET 73, and a paraelectric film 74 is interposed between the floating gate 64 and the substrate region of the PMISFET 73.

The circuit configuration of this preferred embodiment is substantially the same as the first embodiment in that the inverter circuit is constituted by a CMIS circuit is different. The operational characteristics of the circuit in this reference embodiment are the same as those in the first embodiment. In particular, in this preferred embodiment, compared with the first embodiment uses the CMIS circuit to the inverter circuit, it is possible to further suppress the power consumption.

Further, with the configuration shown in FIG. 10, the voltage applied to the ferroelectric film of the ferroelectric capacitor 51 (see FIG. 2) is hardly influenced by the fluctuation of the potential of the floating gate 64 shown in FIG. It is not necessary to apply the signal at the timing as shown in FIGS. That is, there is an advantage that the function of the logic conversion circuit can be switched between the NOR circuit operation and the NAND circuit operation by applying a pulse signal regardless of the value of the input signal.

( Reference form 2 )
FIG. 11 is a block circuit diagram showing a configuration of the semiconductor integrated circuit device according to the second embodiment . As shown in the figure, the semiconductor integrated circuit device according to the second embodiment includes logic conversion circuits 80 arranged in an array, and each logic conversion circuit 80 is connected to each other by a wiring 82 via a switch element 81. It has a structure. As each logical conversion circuit 80 in the present embodiment, the logic conversion circuit of the first embodiment (see FIG. 7) is used. A first control signal line 83 extending along the array column and a second control signal line 84 extending along the array row are provided, and the first control signal line 83 and the second control signal line 84 are provided. Each logic conversion circuit 80 is switched between a NOR operation and a NAND operation according to the control signal by the supplied control signal.

According to the second embodiment , by applying a pulse voltage signal of −5V to the selected first control signal line 83 and applying a pulse voltage signal of −5V to the selected second control signal line 84 at the same time. Switching of the circuit operation of only the logic conversion circuit 80 located at the intersection of the selected first control signal line 83 and the selected second control signal line 84 (switching of NOR operation or NAND operation) can be performed. . As described above, the circuit operation of the logic conversion circuit 80 can be controlled by the first and second control signal lines 83 and 84.

In the second embodiment , a fuse transistor is used as the switch element 81. After the basic structure of the semiconductor integrated circuit device is formed, the fuse transistor is connected and disconnected according to the type and application of the product. The design flexibility of finally reconfiguring the specifications and logic of the semiconductor integrated circuit can be realized.

  As the switch element 81, a MIS transistor, flash EEPROM, MFMIS, or the like can be used. In that case, the switch element 81 can be used to reconfigure the specifications and logic of the semiconductor integrated circuit during use.

( Reference form 3 )
12A and 12B are a plan view and a longitudinal sectional view showing the configuration of the MISFET according to Reference Embodiment 3. FIG. MISFET90 of this embodiment, For example, a NMISFET54 or PMISFET56 in potential generator shown in FIG.

The MISFET 90 of the third embodiment includes a gate electrode 91, a gate insulating film 92 provided below the gate electrode 91, a source region 93 and a drain region 94 formed in the Si substrate, and a gate electrode 91. A side wall 95 provided on the side surface is provided. That is, after the sidewall 95 is formed on the side surface of the gate electrode 91, As ions or B ions are implanted using the gate electrode 91 and the sidewall 95 as part of the mask, thereby forming the source region 93 and the drain region. 94 is formed. In the MISFET formed by such a manufacturing method, assuming that the gate length is Lg, the gate width is Wg, and the gate-source overlap amount is Lgs, the gate-channel region capacitance Cox and the gate-source overlap capacitance Cgs is the following formula (4), (5)
Cox = (ε · ε0 · Lg · Wg) / tox (4)
Cds = (ε · ε 0 · Lgs · Wg) / tox (5)
Represented by

  Therefore, if Lg >> Lgs, then Cox >> Cgs, and the fluctuation of polarization of the ferroelectric film can be more effectively suppressed by the following action.

FIGS. 13A, 13B, and 13C are respectively an equivalent circuit diagram of the potential generating device in which the MISFET of the third embodiment is arranged, and an equivalent capacitor C1 of the source follower circuit when input from the input terminal, respectively. And a circuit diagram showing an equivalent capacitor of a source follower circuit when the potential of the output terminal varies. FIGS. 13B and 13C show only one of the NMISFET 54 and the PMISFET 56 as the equivalent capacitors C1 and C2. In the case of the structure shown in FIG. MISFETs 54 and 56 have equivalent capacitors C1 and C2, respectively.

  When a write voltage is applied from the input terminal 50 of the potential generator shown in FIG. 13A, as shown in FIG. 13B, the equivalent capacitor C1 includes a gate-channel capacitance Cox and a gate. -The source overlap capacitor Cgs is connected in parallel. A sufficiently large voltage is applied to the ferroelectric film by optimizing the distribution ratio between the voltage Vf applied to the ferroelectric capacitor 51 and the voltage Vc applied to the MISFET to be substantially the same. A large remanent polarization is obtained.

  As shown in FIG. 13C, when the potential of the output terminal 55 of the potential generator changes, the equivalent capacitor C2 of the source follower circuit is only the gate-source overlap capacitance Cgs. Therefore, by setting the capacitance Cgs to be sufficiently small, for example, Cgs≈Cox / 100, the voltage Vf distributed to the ferroelectric capacitor 51 is sufficiently smaller than the voltage applied to the equivalent capacitor C2. can do. Therefore, the polarization state of the ferroelectric film is hardly affected even by the voltage fluctuation of the output terminal 55.

For example, by configuring the NMISFET or PMISFET in the potential generating device Egn of the logic conversion circuit shown in FIG. 7 with the MISFET 90 of the present embodiment, the floating gate (FIG. 7) is maintained while maintaining a high writing function to the ferroelectric film. The fluctuation of the polarization of the ferroelectric film due to the fluctuation of the voltage of the floating gate 64) shown in FIG.

Potential generator of the present reference embodiment 3 can be applied to the logic conversion circuit and a logic conversion circuit of the second embodiment shown in FIG. 10, in the reference embodiment 2 shown in FIG. 11.

( Reference form 4 )
In this reference embodiment 4, in the structure of the potential generator shown in FIG. 2, so as to change the potential of the power supply voltage VDD and the ground voltage VSS in response to the potential of the output terminal 55. That is, as shown in FIG. 7, when the potential generator Egn is incorporated in the logic conversion circuit , the power supply voltage VDD and the ground voltage VSS are changed according to the potential of the floating gate 64 (see FIG. 7). Become.

  In the potential generator shown in FIG. 2, the potential of the output terminal 55 (floating gate) is in the range from VSS to VDD.

  When the power supply voltage VDD is 5V and the ground voltage VSS is -5V, when the potential of the output terminal 55 (floating gate) is 1V, the voltage between the source and the drain of the PMISFET 56 is as large as 6V.

  On the other hand, when the power supply voltage VDD is 5V and the ground voltage VSS is 0V, when the potential of the output terminal 55 (floating gate) is 1V, the voltage between the source and the drain of the PMISFET 56 is as very low as 1V.

  Therefore, when the potential of the output terminal 55 (floating gate) is positive, VDD = 5 (V) and VSS = 0 (V). When the potential of the output terminal 55 (floating gate) is negative, VDD = 0 (V ), VSS = -5 (V), the source-drain voltage can be maintained in an appropriate range. As a result, the voltage between the gate and the source can be reduced, so that the voltage applied to the ferroelectric film can be kept small, and fluctuations in polarization of the ferroelectric film can be suppressed. it can.

The potential generator of this embodiment can also be applied to the logic conversion circuit of Reference Embodiment 1 shown in FIG. 10 and the logic conversion circuit of Reference Embodiment 2 shown in FIG.

( Reference form 5 )
FIG. 14 is an equivalent circuit diagram of the potential generator according to Reference Embodiment 5 . As shown in the figure, the potential generator of the present reference embodiment 5 has a structure of connecting the pass transistor 96 to the input terminal 50 of the shown to electrostatic position generator in FIG. A control signal terminal 98 is connected to the gate of the pass transistor 96, a back gate terminal 99 is connected to the substrate region, an input terminal 50 is connected to the source, and a previous input terminal 97 is connected to the drain. .

  A gate bias is applied to the control signal terminal 98 so that the pass transistor 96 is turned on only when the pulse signal shown in FIG. Further, a voltage of 0V is applied to the back gate terminal 99 when the pass transistor 96 is ON, and a voltage of −1V is applied when the pass transistor 96 is OFF. In other words, when the pass transistor 96 is OFF, the substrate region voltage is set lower by −1V than when the pass transistor 96 is ON.

According to the fifth embodiment , when the pass transistor 96 is turned off by the ON / OFF control of the pass transistor 96 and the voltage control of the back gate terminal 99, the drain / source capacitance Cds is small. A voltage is largely distributed to the drain-source capacitance Cds, while almost no voltage is distributed to the body capacitor 51. As a result, fluctuations in the polarization of the ferroelectric capacitor 51 can be suppressed.

According to the present invention, a stable logical conversion circuits are provided.

(A), (b) are respectively a cross-sectional views in plan view and XIb-XIb line of the electrostatic level generator. It is an equivalent circuit diagram of a photoelectric position generator of FIG. (A), (b) are respectively a is a time chart showing a time variation of the voltage of a time chart, and the gate and an output terminal that indicates the time variation of the voltage of the input terminal. (A), (b), (c) are respectively a circuit diagram showing a configuration of a test circuit for checking the potential stability of the Gate unit, a time chart showing the time variation of the potential of the input terminal, 5 is a time chart showing a temporal change in potential of the gate part. It is an equivalent circuit of the electric potential generator as the reference example 1 of this invention. It is the equivalent circuit schematic of the electric potential generator as the reference example 2 of this invention. 1 is an equivalent circuit diagram of a logic conversion circuit according to a first embodiment of the present invention. (A), (b) shows the time change of the potential of a floating gate when the logical value of the input signal inputted into each input terminal of two input parts in a 1st embodiment is changed in order, respectively. It is a time chart which shows the time change of the voltage applied to a time chart and a ferroelectric capacitor with time. Is a time chart showing the time variation of the potential of the output terminal for FIG 8 (a) the same logic value input in the first embodiment. FIG. 3 is an equivalent circuit diagram of a logic conversion circuit according to Reference Embodiment 1 of the present invention. It is a block circuit diagram which shows the structure of the logic conversion circuit which concerns on the reference form 2 of this invention. (A), (b) is the top view and longitudinal cross-sectional view which show the structure of MISFET which concerns on the reference form 3 of this invention. (A), (b), (c) is an equivalent circuit diagram of the potential generating device in which the MISFET of Reference Embodiment 3 is arranged, respectively, and a circuit diagram showing an equivalent capacitor of the source follower circuit when inputting from the input terminal, respectively. , And a circuit diagram showing an equivalent capacitor of a source follower circuit when the potential of the output terminal varies. 10 is an equivalent circuit diagram of a potential generator according to Reference Embodiment 5. FIG. It is an equivalent circuit diagram of a neuron element (logic conversion circuit) according to a second conventional example described in a conventional publication. It is a figure which shows the electric charge amount of each part with respect to an input signal when a negative pulse signal is added to the control terminal in a prior art example as a table with the logical value of an output signal. It is a figure which shows the electric charge amount of each part with respect to the input signal when the negative pulse signal with a still larger amplitude is added to the control terminal in the prior art as a table with the logical value of the output signal Y. (A), (b) is a timing chart which shows the time change of the potential of the floating gate of the neuron element which concerns on a prior art example, respectively, and the timing chart which shows the time change of the voltage applied to a ferroelectric film, respectively. .

Explanation of symbols

50 second electrode
51 Ferroelectric capacitor
52 first electrode
53 1st voltage supply part
54 Second MISFET
55 Voltage output section
57 Second voltage supply unit
56 First MISFET
58 Paraelectric capacitor
61 n-channel MIS transistor
62 Source terminal
63 Drain terminal
64 floating gate
65 Multiple signal inputs
65a input terminal
65c Paraelectric film
66 Gate insulation film
67 Control terminal
69 Load resistance element
70 Output terminal
71 Power supply voltage supply terminal
211 first gate electrode
212 Second gate electrode
Eng potential generator

Claims (1)

A logic conversion circuit that can be switched between NAND circuit operation and NOR circuit operation,
The logic conversion circuit includes a plurality of signal input units (65), an output terminal (70), a control terminal (67), a power supply voltage supply terminal (71), an n-channel MIS transistor (61), and a potential generator (Egn). ),
With
The n-channel MIS transistor (61) includes a source terminal (62), a drain terminal (63), a gate insulating film (66), and a floating gate (64).
The output terminal (70) is connected to the drain terminal (63),
The power supply voltage supply terminal (71) is connected to the drain terminal (63) via a load resistance element (69),
The source terminal (62) is grounded;
Each of the plurality of signal input sections (65) includes an input terminal (65a) and a paraelectric film (65c), and one surface of each paraelectric film (65c) is formed on each input terminal (65a). And the other surface of each paraelectric film (65c) is connected to the floating gate (64),
The potential generator (Egn) is interposed between the control terminal (67) and the floating gate (64),
The potential generator (Egn)
A first semiconductor layer;
A first gate insulating film formed on the first semiconductor layer; a first gate electrode (211) formed on the first gate insulating film; and in the first semiconductor layer A first MISFET (56) having first and second P-type diffusion regions formed in regions located on both sides of the first gate electrode in FIG.
A second semiconductor layer;
A second gate insulating film formed on the second semiconductor layer; a second gate electrode (212) formed on the second gate insulating film; and in the second semiconductor layer A second MISFET (54) having first and second N-type diffusion regions formed in regions located on both sides of the second gate electrode in FIG.
A first electrode (52) commonly connected to the first and second gate electrodes, a second electrode (50) facing the first electrode (52), and the first electrode ( 52) a ferroelectric capacitor (51) having a ferroelectric film interposed between the second electrodes (50);
A first voltage supply unit (53) for supplying a first voltage to the first N-type diffusion region of the second MISFET (54);
A second voltage supply unit (57) for supplying a ground voltage lower than the first voltage to the first P-type diffusion region of the first MISFET (56);
An output voltage corresponding to the voltage input to the second electrode (52) of the ferroelectric capacitor (51) is connected in common to the second P-type diffusion region and the N-type diffusion region of each MISFET. A voltage output unit (55) for outputting,
The substrate potential of the first MISFET (56) is the first voltage,
The substrate potential of the second MISFET (54) is the second voltage,
The second electrode (50) is connected to the control terminal (67);
The voltage output unit (55) is connected to the floating gate (64);
Before applying a pulse signal to the control terminal (67), the threshold voltage of the n-channel MIS transistor (61) is applied with a logical value “1” to any one of the plurality of signal input sections (65). The logic conversion circuit operates as a NOR circuit by making it smaller than the potential of the floating gate (64) when
By applying a pulse signal to the control terminal (67), the NOR circuit is switched to the NAND circuit,
After a pulse signal is applied to the control terminal (67), the threshold voltage of the n-channel MIS transistor (61) is applied with a logical value “0” to any one of the plurality of signal input sections (65). The logic conversion circuit operates as a NAND circuit by making it larger than the potential of the floating gate (64) when
By resetting the polarization of the ferroelectric film, the NAND circuit can be switched to the NOR circuit.
Logic conversion circuit.

Images