JP4174501B2 - Analog signal processing circuit - Google Patents

Description

The present invention relates to an analog signal processing circuits, directed to the analog signal processing circuits, in particular to obtain an output current corresponding to the peak value of the input current.

  Conventionally, in an analog signal processing circuit, when an output corresponding to the peak value of an input is to be obtained, it is mainly handled by a voltage. FIG. 21 shows a voltage mode peak hold circuit. In the figure, 201 and 202 are operational amplifiers, 203 and 204 are diodes, 205 is a resistor, 206 is a reset switching element, 207 is a charge holding capacitor, 208 is a voltage input terminal, and 209 is a voltage output terminal. Thus, the voltage mode peak hold circuit is composed of a plurality of operational amplifiers, diodes, capacitors, and the like, and the circuit scale tends to be large. Further, when handling current input, the method is mainly to convert the input current into a voltage value in the current-voltage conversion circuit and then input it to the peak hold circuit of FIG. 21, which further increases the circuit scale.

  As described above, the circuit scale becomes large when an output corresponding to the peak value of the input is conventionally obtained. This increases the area occupied by the circuit and the power consumption.

  An object of the present invention is to provide a current mode peak hold circuit for obtaining an output current corresponding to a peak value of an input current with a smaller circuit scale.

In order to achieve the above object, an analog signal processing circuit of the present invention includes first and second field effect transistors having gates connected in common and sources connected to a first reference potential , and the first and second field effect transistors. A first main electrode connected to the gate of the first field effect transistor, a second main electrode connected to the drain of the first field effect transistor, and a control electrode connected to the second reference potential. And the second main electrode at a connection portion between the drain of the first field effect transistor and the second main electrode of the first transistor. And a second transistor having a control electrode connected to a third reference potential and a first main electrode connected to a fourth reference potential, the second reference potential and the third reference potential Difference of the reference potential of the first Wherein the transistor second transistor is obtained by setting the value it is not turned ON simultaneously.

  As described above, according to the analog signal processing circuit of the present invention, a current mode peak-hold circuit can be obtained with a small circuit configuration, and the occupied area and power consumption can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, a representative MOS transistor will be described as a field effect transistor.
(First embodiment)
FIG. 1 is a circuit diagram showing a first embodiment of an analog signal processing circuit according to the present invention. In the figure, reference numerals 1 and 2 _denote first and second P-type MOS transistors having gate terminals connected in common and source terminals connected to a power supply potential (V _DD ) which is a predetermined reference potential. 3, a collector is connected to the commonly connected gate terminals of the first and second P-type MOS transistors 1 and 2, an emitter is connected to the drain terminal of the MOS transistor 1, and a base is a reference potential lower than V _DD This is an NPN transistor connected to (V _BIAS1 ). Further, 4 is a terminal connecting the drain of the MOS transistor 1 and the emitter of the NPN transistor 3, 5 is a terminal connecting the gates of the MOS transistor 1 and the MOS transistor 2 in common, and 6 is a drain terminal of the MOS transistor 2.

The current is input from the terminal 4 and output from the terminal 6. In the figure, i _D1 (t) is the drain current of the MOS transistor 1 at time t, i _in (t) is the input current at time t, and i _out (t) is the output current at time t. The direction is positive. Note that i _out (t) matches the drain current of the MOS transistor 2.

2A and 2B are schematic waveform diagrams of the input current i _in (t) and the output current i _out (t) for explaining the operation of the analog signal processing circuit. First, it is assumed that the MOS transistor 1 operates in the saturation region, i _D1 (t) and i _in (t) coincide with each other, and the NPN transistor 3 is cut off (cut-off state). Here, when i _in (t) begins to increase as _in the period from time t ₀ to t ₁ , since i _D1 (t) <i _in (t), the voltage at the terminal 4 decreases and V _BIAS1 When the voltage drops by about 0.5 to 0.7 V from the NPN transistor 3, the NPN transistor 3 enters the forward active region and turns on, and the current i _in (t) −i _D1 (t) flows out from the terminal 5 through the NPN transistor 3 i _in (t) and i _D1 (t) match, that is, the gate-source voltage V _GS (t) of the MOS transistor 1 is

となるように端子５の電圧を下降させる。ここで、Ｖ_ｔｈｐはＰ型のＭＯＳトランジスタの閾値電圧、μ_ｐ は正孔の移動度、Ｃ_ＯＸは単位面積当たりのＭＯＳトランジスタのゲート酸化膜容量、Ｌ_１ はＭＯＳトランジスタ１のゲート長、Ｗ_１ はＭＯＳトランジスタ１のゲート幅である。なお端子５の電圧は、この端子に接続されているＭＯＳトランジスタ１および２のゲート−ソース間寄生容量から、ＮＰＮトランジスタ３を通じて電荷が引き抜かれることにより下降する。この時、図１の回路はカレントミラー回路として動作し、入力電流に比例した出力電流が得られる。すなわち、出力電流ｉ_ｏｕｔ（ｔ）は、ＭＯＳトランジスタ２のゲート−ソース間電圧が、ＭＯＳトランジスタ１のゲート−ソース間電圧Ｖ_ＧＳ（ｔ）に一致することから、

The voltage at the terminal 5 is lowered so that Here, V _thp is the threshold voltage of the P-type MOS transistor, μ _p is the mobility of holes, C _OX is the gate oxide film capacitance of the MOS transistor per unit area, L ₁ is the gate length of the MOS transistor 1, W ₁ is the gate width of the MOS transistor 1. Note that the voltage at the terminal 5 drops when charges are extracted through the NPN transistor 3 from the gate-source parasitic capacitances of the MOS transistors 1 and 2 connected to the terminals. At this time, the circuit of FIG. 1 operates as a current mirror circuit, and an output current proportional to the input current is obtained. That is, since the output current i _out (t) is equal to the gate-source voltage V _GS (t) of the MOS transistor 1, the gate-source voltage of the MOS transistor 2 is equal to

で与えられ、（２）式に（１）式を代入して整理すると、

When substituting (1) into (2) and rearranging,

となる。ここで、Ｌ_２ 、Ｗ_２ はそれぞれＭＯＳトランジスタ２のゲート長、ゲート幅である。

It becomes. Here, L ₂ and W ₂ are the gate length and gate width of the MOS transistor 2, respectively.

Next, when the increase _in i _in (t) stops during the period from time t ₁ to time t ₂ , i _D1 (t) = i _in (t), so that the voltage at the terminal 4 is set so that the NPN transistor 3 is cut off. Rises and settles to about V _BIAS1 . Here, since the terminal 5 has high impedance, the charge at time t ₁ does not change, and the gate-source voltages of the MOS transistors 1 and 2 are kept at V _GS (t ₁ ). At this time, the output current i _out (t) is _calculated from the equations (1) and (2):

となり、時刻ｔ_１における入力電流ｉ_ｉｎ（ｔ_１）に比例した電流が保存される。

Thus, a current proportional to the input current i _in (t ₁ ) at time t ₁ is stored.

Since _i in (t) as in the period _{t 3} from the time _{t 2} is _i in _{(t 1) V} be below the GS _{(t 1)} is stored, the output current _{i out} (t) is ( 4) Value represented by the equation. At this time, the voltage at the terminal 4 rises to the vicinity of V _DD at the maximum in order to keep i _D1 (t) = i _in (t), and the MOS transistor 1 operates in the non-saturated region.

Next, if a current exceeding i _in (t ₁ ) is input during the period from time t ₃ to time t ₄ and continues to increase, the voltage at the terminal 4 drops to about 0.5 to 0.7 V from V _BIAS1. When the voltage drops approximately, the NPN transistor 3 enters the forward active region again and turns on, and the current i _in (t) −i _D1 (t) flows out from the terminal 5 through the NPN transistor 3 and becomes i _in (t). The voltage at the terminal 5 is lowered so that i _D1 (t) matches, that is, the gate-source voltage V _GS (t) of the MOS transistor 1 becomes the value represented by the equation (1). Then, an output current i _out (t) corresponding to the input current represented by the expression (3) is obtained.

From the above description, it can be seen that an output current corresponding to the peak value of the input current can be obtained by repeating the above operation according to the increase or decrease of the input current.
(Second embodiment)
FIG. 3 shows a second embodiment of the analog signal processing circuit of the present invention. In the figure, reference numeral 8 denotes a charge holding capacitor for storing the charge of the terminal 5. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The operation of this embodiment is the same as that of the first embodiment. However, when the voltage at the terminal 5 decreases, the gate-source parasitic of the MOS transistors 1 and 2 connected to this terminal is reduced. The difference is that charges are extracted through the NPN transistor 3 from the capacitance of the charge holding capacitor 8 in addition to the capacitance. That is, since the capacitance value for storing charges at the terminal 5 increases, the amount of stored charges can be increased. For this reason, when there is a leak current at the terminal 5, the voltage fluctuation error of the terminal 5 after a lapse of a certain time can be made smaller than in the case of the first embodiment, and more stably according to the peak value of the input current. Output current can be obtained.
(Third embodiment)
FIG. 4 shows a third embodiment of the analog signal processing circuit of the present invention. Reference numeral 9 denotes a switching element for short-circuiting the power supply potential (V _DD ), which is a predetermined reference potential, with the terminal 5, and 9A is a pulse signal input terminal for controlling opening and closing of the switching element. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The operation of this embodiment is the same as that of the first embodiment when the switching element 9 is turned off. However, the terminal 5 and V _DD are short-circuited when the switching element 9 is turned on. Therefore, it differs in that the potential of the terminal 5 can be reset to a predetermined reference potential. That is, if the switching element 9 is turned on after the peak hold operation, the voltage at the terminal 5 is raised to a predetermined reference potential and then the switching element 9 is turned off, the same operation as in the first embodiment is performed. The peak hold operation can be performed.

Needless to say, also in this embodiment, it is possible to add a charge holding capacitor 8 to the terminal 5, and the same effect as in the second embodiment can be obtained.
(Fourth embodiment)
FIG. 5 shows a fourth embodiment of the analog signal processing circuit of the present invention. 10 is a switching element for short-circuiting the terminal 4 and the terminal 5, and 10A is a pulse signal input terminal for controlling opening and closing of the switching element. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The operation of this embodiment is the same as that of the first embodiment when the switching element 10 is turned off, but the terminals 4 and 5 are short-circuited when the switching element 10 is turned on. Therefore, this embodiment is different in that it operates as a normal current mirror circuit. Therefore, the peak hold function shown in the first embodiment can be arbitrarily set. In addition, after the peak hold operation, when the switching element 10 is turned on when a reference current smaller than the peak current is input, the potential of the terminal 5 is raised to the reference potential. A reference output current corresponding to the input can be obtained, and a reset function can be provided. Thereafter, if the switching element 10 is turned off, the same operation as in the first embodiment is performed, and a new peak hold operation can be performed.

  Needless to say, also in this embodiment, it is possible to add a charge holding capacitor 8 to the terminal 5, and the same effect as in the second embodiment can be obtained.

Furthermore, also in this embodiment, it is possible to add the switching element 9 for short-circuiting the terminal 5 and the power supply potential (V _DD ) which is a predetermined reference potential, and the same effect as in the third embodiment can be obtained. can get.
(Fifth embodiment)
FIG. 6 shows a fifth embodiment of the analog signal processing circuit of the present invention. In the figure, reference numeral 101 denotes a constant current source for supplying a bias current to the MOS transistor 1 in advance, which is connected to the terminal 4 and the ground potential, and supplies a constant current I _B1 . 102, a constant current source for supplying a pre-bias current to the MOS transistor 2 and the terminal 6 is connected to the ground potential, and supplies the I _B2 becomes a constant current. Here, the relationship between I _B1 and I _B2 is in accordance with the size ratio of the MOS transistor 1 and the MOS transistor 2,

なる関係であることが望ましい。なお、図１と同一構成部材については同一符号を付し、詳細な説明を省略する。また、本実施例の動作は第１の実施例の動作と同様であるが、ＭＯＳトランジスタ１に入力される電流ｉ_ｉｎ（ｔ）が、バイアス電流Ｉ_Ｂ１と入力信号電流ｉ_ｓｉｎ（ｔ）の和によって表される点、およびＭＯＳトランジスタ２から出力される電流ｉ_ｏｕｔ（ｔ）が、バイアス電流Ｉ_Ｂ２と出力信号電流ｉ_ｓｏｕｔ（ｔ）の和によって表される点において異なる。本実施例によれば信号成分のみを独立して取り扱うことが可能となる。なお、本実施例においては、第１の実施例に定電流源１０１および定電流源１０２を付加した形で説明を行っているが、もちろん第２、第３および第４の実施例においても本実施例と同様の構成を取ることが可能であり同様の効果が得られる。
（第６の実施例）
図７に本発明のアナログ信号処理回路による第６の実施例を示す。本実施例は、第１の実施例の逆導電型による構成を示すものである。同図において、１１および１２は、ゲート端子を共通接続とし、ソース端子を所定の同一基準電位である接地電位に接続した第１、および第２のＮ型ＭＯＳトランジスタである。１３は、ＭＯＳトランジスタ１１，１２の共通接続されたゲート端子にコレクタを接続し、ＭＯＳトランジスタ１１のドレイン端子にエミッタを接続し、ベースをＶ_ＤＤよりも高い基準電位（Ｖ_{ＢＩＡＳ１}）に接続したＰＮＰトランジスタである。また、１４はＭＯＳトランジスタ１１のドレインとＰＮＰトランジスタ１３のエミッタを接続した端子、１５はＭＯＳトランジスタ１１とＭＯＳトランジスタ１２のゲートを共通接続した端子、１６はＭＯＳトランジスタ１２のドレイン端子である。なお、電流は端子１４から入力され、端子１６より出力される。同図中のｉ_Ｄ１１（ｔ）は、時刻ｔにおけるＭＯＳトランジスタ１１のドレイン電流、ｉ_ｉｎ（ｔ）は時刻ｔにおける入力電流、ｉ_ｏｕｔ（ｔ）は時刻ｔにおける出力電流であり、それぞれ矢印の向きを正とする。なお、ｉ_ｏｕｔ（ｔ）はＭＯＳトランジスタ１２のドレイン電流に一致する。

It is desirable that In addition, the same code | symbol is attached | subjected about the same structural member as FIG. 1, and detailed description is abbreviate | omitted. The operation of this embodiment is the same as that of the first embodiment. However, the current i _in (t) input to the MOS transistor 1 is the same as the bias current I _B1 and the input signal current i _sin (t). The difference is that the current i _out (t) output from the MOS transistor 2 is expressed by the sum of the bias current I _B2 and the output signal current i _sout (t). According to the present embodiment, only the signal component can be handled independently. In the present embodiment, the constant current source 101 and the constant current source 102 are added to the first embodiment, but of course the second, third and fourth embodiments are also described. A configuration similar to that of the embodiment can be taken, and a similar effect can be obtained.
(Sixth embodiment)
FIG. 7 shows a sixth embodiment of the analog signal processing circuit of the present invention. This embodiment shows the configuration of the reverse conductivity type of the first embodiment. In the figure, reference numerals 11 and 12 denote first and second N-type MOS transistors having gate terminals connected in common and source terminals connected to a ground potential which is a predetermined same reference potential. PNP 13 has a collector connected to the commonly connected gate terminals of MOS transistors 11 and 12, an emitter connected to the drain terminal of MOS transistor 11, and a base connected to a reference potential (V _BIAS1 ) higher than V _DD. It is a transistor. Further, 14 is a terminal connecting the drain of the MOS transistor 11 and the emitter of the PNP transistor 13, 15 is a terminal connecting the gates of the MOS transistor 11 and the MOS transistor 12, and 16 is a drain terminal of the MOS transistor 12. The current is input from the terminal 14 and output from the terminal 16. In the figure, i _D11 (t) is the drain current of the MOS transistor 11 at time t, i _in (t) is the input current at time t, and i _out (t) is the output current at time t. The direction is positive. Note that i _out (t) matches the drain current of the MOS transistor 12.

The operation of the analog signal processing circuit will be described with reference to FIGS. _First , it is assumed that the MOS transistor 11 operates in the saturation region, i _D11 (t) and i _in (t) match, and the PNP transistor 13 is cut off. Here, when i _in (t) begins to increase as _in the period from time t ₀ to t ₁ , i _D11 (t) <i _in (t), so the voltage at the terminal 14 rises and V _BIAS1 From about 0.5 to 0.7 V, the PNP transistor 13 enters the forward active region and is turned on, and the current i _in (t) -i _D11 (t) flows into the terminal 15 through the PNP transistor 13 i _in (t) and i _D11 (t) match, that is, the gate-source voltage V _GS (t) of the MOS transistor 11 is

となるように端子１５の電圧を上昇させる。ここで、Ｖ_ｔｈｎはＮ型のＭＯＳトランジスタの閾値電圧、μ_ｎ は電子の移動度、Ｃ_ＯＸは単位面積当たりのＭＯＳトランジスタのゲート酸化膜容量、Ｌ_１１はＭＯＳトランジスタ１１のゲート長、Ｗ_１１はＭＯＳトランジスタ１１のゲート幅である。なお端子１５の電圧は、この端子に接続されているＭＯＳトランジスタ１１および１２のゲート−ソース間寄生容量に、ＰＮＰトランジスタ１３を通じて電荷が供給されることにより上昇する。この時、図７の回路はカレントミラー回路として動作し、入力電流に比例した出力電流が得られる。すなわち、出力電流ｉ_ｏｕｔ（ｔ）は、ＭＯＳトランジスタ１２のゲート−ソース間電圧が、ＭＯＳトランジスタ１１のゲート−ソース間電圧Ｖ_ＧＳ（ｔ）に一致することから、

The voltage at the terminal 15 is increased so that Here, V _thn is the threshold voltage of the N-type MOS transistor, μ _n is the electron mobility, C _OX is the gate oxide film capacitance of the MOS transistor per unit area, L ₁₁ is the gate length of the MOS transistor 11, and W ₁₁ Is the gate width of the MOS transistor 11. Note that the voltage at the terminal 15 rises when electric charges are supplied through the PNP transistor 13 to the gate-source parasitic capacitances of the MOS transistors 11 and 12 connected to this terminal. At this time, the circuit of FIG. 7 operates as a current mirror circuit, and an output current proportional to the input current is obtained. That is, since the output current i _out (t) is equal to the gate-source voltage V _GS (t) of the MOS transistor 11, the gate-source voltage of the MOS transistor 12 is

で与えられ、（７）式に（６）式を代入して整理すると、

When substituting (6) into (7) and rearranging,

となる。ここで、Ｌ_１２、Ｗ_１２はそれぞれＭＯＳトランジスタ１２のゲート長、ゲート幅である。

It becomes. Here, L ₁₂ and W ₁₂ are the gate length and gate width of the MOS transistor 12, respectively.

Next, when i _in (t) stops increasing as _in the period from time t ₁ to time t ₂ , i _D11 (t) = i _in (t), so that the voltage at the terminal 14 is set so that the PNP transistor 13 is cut off. _Falls and settles to about V _BIAS1 . Here, since the terminal 15 has high impedance, the charge at time t ₁ does not change, and the gate-source voltages of the MOS transistors 11 and 12 are kept at V _GS (t ₁ ). At this time, the output current i _out (t) is _calculated from the equations (6) and (7):

となり、時刻ｔ_１における入力電流ｉ_ｉｎ（ｔ_１）に比例した電流が保存される。

Thus, a current proportional to the input current i _in (t ₁ ) at time t ₁ is stored.

Since _i in (t) as in the period _{t 3} from the time _{t 2} is _i in _{(t 1) V} be below the GS _{(t 1)} is stored, the output current _{i out} (t) is ( 9) The value is expressed by the equation. At this time, the voltage of the terminal 14 decreases to the minimum near the ground potential in order to keep i _D11 (t) = i _in (t), and the MOS transistor 11 operates in the non-saturated region.

Next, when a current exceeding i _in (t ₁ ) is input during the period from time t ₃ to time t ₄ and continues to increase, the voltage at the terminal 14 rises and approximately 0.5 to 0.7 V from V _BIAS1. The PNP transistor 13 again enters the forward active region when it rises to the ON state, and is turned on. The current i _in (t) -i _D11 (t) flows out of the terminal 15 through the PNP transistor 13 and i _in (t) The voltage at the terminal 15 is lowered so that i _D11 (t) matches, that is, the gate-source voltage V _GS (t) of the MOS transistor 11 becomes the value represented by the equation (6). Then, an output current i _out (t) corresponding to the input current represented by the equation (8) is obtained.

From the above description, it can be seen that an output current corresponding to the peak value of the input current can be obtained by repeating the above operation according to the increase or decrease of the input current.
(Seventh embodiment)
FIG. 8 shows a seventh embodiment of the analog signal processing circuit of the present invention. In the figure, reference numeral 18 denotes a charge holding capacitor for storing the charge of the terminal 15. The same components as those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted. The operation of this embodiment is the same as that of the sixth embodiment. However, when the voltage at the terminal 15 rises, the parasitic capacitance between the gate and source of the MOS transistors 11 and 12 connected to this terminal is increased. In addition, the charge holding capacitor 18 is different in that the charge is supplied through the PNP transistor 13. That is, since the capacitance value for storing charges at the terminal 15 increases, the amount of stored charges can be increased. For this reason, when there is a leakage current at the terminal 15, the voltage fluctuation error of the terminal 15 after a lapse of a certain time can be made smaller than in the case of the sixth embodiment, and more stably according to the peak value of the input current. Output current can be obtained.
(Eighth embodiment)
FIG. 9 shows an eighth embodiment of the analog signal processing circuit of the present invention. Reference numeral 19 denotes a switching element for short-circuiting the terminal 15 and a ground potential which is a predetermined reference potential, and 19A is a pulse signal input terminal for controlling opening and closing of the switching element. The same components as those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted. The operation of this embodiment is the same as that of the sixth embodiment when the switching element 19 is turned off, but the terminal 15 and the ground potential are short-circuited when the switching element 19 is turned on. Therefore, it differs in that the potential of the terminal 15 can be reset to a predetermined reference potential. That is, if the switching element 19 is turned on after the peak hold operation is performed, and the switching element 19 is turned off after the voltage at the terminal 15 is lowered to the predetermined reference potential, the same operation as in the sixth embodiment is performed. The peak hold operation can be performed.

Needless to say, also in this embodiment, it is possible to add a capacitor 18 for charge holding to the terminal 15, and the same effect as in the seventh embodiment can be obtained.
(Ninth embodiment)
FIG. 10 shows a ninth embodiment of the analog signal processing circuit according to the present invention. Reference numeral 20 denotes a switching element for short-circuiting the terminals 14 and 15. Reference numeral 20A denotes a pulse signal input terminal for controlling opening and closing of the switching element. The same components as those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted. The operation of this embodiment is the same as that of the sixth embodiment when the switching element 20 is turned off, but the terminals 14 and 15 are short-circuited when the switching element 20 is turned on. Therefore, this embodiment is different in that it operates as a normal current mirror circuit. Therefore, it can be seen that the peak hold function shown in the sixth embodiment can be arbitrarily set. In addition, after the peak hold operation, when the switching element 20 is turned on when a reference current smaller than the peak current is input, the potential of the terminal 15 is lowered to the reference potential. A reference output current corresponding to the input can be obtained, and a reset function can be provided. Thereafter, if the switching element 20 is turned off, the same operation as in the sixth embodiment is performed, and a new peak hold operation can be performed.

  Needless to say, also in this embodiment, it is possible to add a capacitor 18 for charge holding to the terminal 15, and the same effect as in the seventh embodiment can be obtained.

Further, also in this embodiment, it is possible to add the switching element 19 for short-circuiting with the terminal 15 and the ground potential which is a predetermined reference potential, and the same effect as in the eighth embodiment can be obtained.
(Tenth embodiment)
FIG. 11 shows a tenth embodiment of the analog signal processing circuit of the present invention. In the figure, reference numeral 111 denotes a constant current source for supplying a bias current to the MOS transistor 11 in advance, which is connected to the terminal 14 and the power supply potential (V _DD ), and supplies a constant current of I _B11 . Reference numeral 112 denotes a constant current source for supplying a bias current to the MOS transistor 12 in advance, which is connected to the terminal 16 and the power supply potential (V _DD ), and supplies a constant current I _B12 . Here, the relationship between I _B11 and I _B12 is in accordance with the size ratio of the MOS transistor 11 and the MOS transistor 12,

なる関係であることが望ましい。なお、図７と同一構成部材については同一符号を付し、詳細な説明を省略する。また、本実施例の動作は第６の実施例の動作と同様であるが、ＭＯＳトランジスタ１１に入力される電流ｉ_ｉｎ（ｔ）が、バイアス電流Ｉ_Ｂ１１と入力信号電流ｉ_ｓｉｎ（ｔ）の和によって表される点、およびＭＯＳトランジスタ１２から出力される電流ｉ_ｏｕｔ（ｔ）が、バイアス電流Ｉ_Ｂ１２と出力信号電流ｉ_ｓｏｕｔ（ｔ）の和によって表される点において異なる。本実施例によれば信号成分のみを独立して取り扱うことが可能となる。なお、本実施例においては、第６の実施例に定電流源１１１および１１２を付加した形で説明を行っているが、もちろん第７、第８および第９の実施例においても本実施例と同様の構成を取ることが可能であり同様の効果が得られる。
（第１１の実施例）
図１２に本発明のアナログ信号処理回路による第１１の実施例を示す。本実施例は、第１の実施例の改良型で、高速動作を可能にするものである。同図において、７は、エミッタをＭＯＳトランジスタ１のドレインとＮＰＮトランジスタ３のエミッタとを共通接続した端子に接続し、ベースをＶ_ＤＤよりも低い基準電位（Ｖ_{ＢＩＡＳ２}）に接続し、コレクタをＶ_ＤＤよりも低い基準電位である接地電位に接続したＰＮＰトランジスタである。図１と同一構成部材については同一符号を付し、詳細な説明を省略する。なお、Ｖ_{ＢＩＡＳ１}とＶ_{ＢＩＡＳ２}の関係は、ＮＰＮトランジスタ３とＰＮＰトランジスタ７を同時にオンすることがないような値に設定されていれば良く、特に大小関係は問わないが、Ｖ_{ＢＩＡＳ１}−Ｖ_{ＢＩＡＳ２}が、上記の条件を満たしつつ、できる限り大きくすることが望ましい。

It is desirable that In addition, the same code | symbol is attached | subjected about the same structural member as FIG. 7, and detailed description is abbreviate | omitted. The operation of the present embodiment is the same as that of the sixth embodiment, but the current i _in (t) input to the MOS transistor 11 is equal to the bias current I _B11 and the input signal current i _sin (t). The difference is that the current i _out (t) output from the MOS transistor 12 is expressed by the sum, and the current i _out (t) output from the MOS transistor 12 is expressed by the sum of the bias current I _B12 and the output signal current i _sout (t). According to the present embodiment, only the signal component can be handled independently. In the present embodiment, the constant current sources 111 and 112 are added to the sixth embodiment, but of course, the seventh, eighth and ninth embodiments also differ from the present embodiment. The same configuration can be taken and the same effect can be obtained.
(Eleventh embodiment)
FIG. 12 shows an eleventh embodiment of the analog signal processing circuit of the present invention. This embodiment is an improved version of the first embodiment and enables high-speed operation. In the figure, reference numeral 7 denotes an emitter connected to a terminal where the drain of the MOS transistor 1 and the emitter of the NPN transistor 3 are connected in common, a base connected to a reference potential (V _BIAS2 ) lower than V _DD , and a collector connected to V _This is a PNP transistor connected to a ground potential which is a reference potential lower than _DD . The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. _The relationship between _{V BIAS1} and _{V BIAS2} has only to be set to such a value as not to turn on the NPN transistor 3 and the PNP transistor 7 simultaneously, but not limited particularly magnitude _relation, V _{BIAS1 -V BIAS2} is It is desirable to make it as large as possible while satisfying the above conditions.

Next, the operation of the analog signal processing circuit will be described with reference to FIGS. 2A and 2B. Here, as an example, it is assumed that V _BIAS1 −V _BIAS2 is set to 0.6V. First, assuming that the MOS transistor 1 is operating in the saturation region and i _D1 (t) and i _in (t) coincide with each other, the potential of the terminal 4 is approximately between V _BIAS1 and V _BIAS2 . The base-emitter voltages of the NPN transistor 3 and the PNP transistor 7 are both about 0.3 V, and both transistors are cut off. Here, when i _in (t) begins to increase as _in the period from time t ₀ to t ₁ , i _D1 (t) <i _in (t), so the voltage at the terminal 4 drops. At this time, PNP transistor 7 while keeping the cut-off, NPN transistor 3 when the voltage of the terminal 4 is lowered by about 0.5~0.7V from _{V BIAS1} is turned on enter the forward active _{region, i in} The current of (t) -i _D1 (t) flows out from the terminal 5 through the NPN transistor 3 so that i _in (t) and i _D1 (t) match, that is, the gate-source voltage V _GS (t ) Decreases the voltage of the terminal 5 so that the value represented by the expression (1) is obtained. Note that the voltage at the terminal 5 drops when charges are extracted through the NPN transistor 3 from the gate-source parasitic capacitances of the MOS transistors 1 and 2 connected to the terminals. At this time, the circuit of FIG. 12 operates as a current mirror circuit, and an output current proportional to the input current is obtained as expressed by the equation (3).

Next, since i _D1 (t) = i _in (t) when the increase of i _in (t) stops as in the period from time t ₁ to t ₂ , both the NPN transistor 3 and the PNP transistor 7 are cut off. As a result, the voltage at the terminal 4 rises and generally settles at an intermediate potential between V _BIAS1 and V _BIAS2 . Here, since the terminal 5 has high impedance, the charge at time t ₁ does not change, and the gate-source voltages of the MOS transistors 1 and 2 are kept at V _GS (t ₁ ). At this time, as the output current i _out (t) is expressed by the equation (4), a current proportional to the input current i _in (t ₁ ) at the time t ₁ is stored. When i _in (t) falls below i _in (t ₁ ) as _in the period from time t ₂ to time t ₃ , the voltage at terminal 4 further increases, but NPN transistor 7 remains cut off. Therefore, since V _GS (t ₁ ) is stored, the output current i _out (t) has a value represented by the equation (4). By the way, when the voltage at the terminal 4 rises by about 0.5 to 0.7 V from V _BIAS2 , the PNP transistor 7 enters the forward active region and is turned on, i _D1 (t) −i _in (t), i. _Since a current of _in (t ₁ ) −i _in (t) is passed, an increase in the voltage at the terminal 4 is suppressed. For this reason, since the voltage amplitude of the terminal 4 can be made smaller than that in the first embodiment, a higher speed operation is possible.

Next, if a current exceeding i _in (t ₁ ) is input during the period from time t ₃ to time t ₄ and continues to increase, the voltage at the terminal 4 drops to about 0.5 to 0.7 V from V _BIAS1. When the voltage drops approximately, the NPN transistor 3 enters the forward active region again and turns on, and the current i _in (t) −i _D1 (t) flows out from the terminal 5 through the NPN transistor 3 and becomes i _in (t). The voltage at the terminal 5 is lowered so that i _D1 (t) matches, that is, the gate-source voltage V _GS (t) of the MOS transistor 1 becomes the value represented by the equation (1). Then, an output current i _out (t) corresponding to the input current represented by the expression (3) is obtained.

  From the above description, by repeating the above operation according to the increase / decrease of the input current, it is possible to obtain an output current according to the peak value of the input current and to enable a higher speed operation than the first embodiment. Recognize.

In this embodiment, the charge holding capacitor 8 is added to the terminal 5, the reset switching element 9 is added between the terminal 5 and a predetermined reference potential, and the terminals 4 and 6. It is possible to add constant current sources 101 and 102 to the same, and the same effects as those of the second, third and fifth embodiments can be obtained.
(Twelfth embodiment)
FIG. 13 shows a twelfth embodiment of the analog signal processing circuit of the present invention. This embodiment shows the configuration of the eleventh embodiment by the reverse conductivity type, which is an improved type of the sixth embodiment and enables high-speed operation. In the figure, reference numeral 17 denotes an emitter connected to a terminal where the drain of the MOS transistor 11 and the emitter of the PNP transistor 13 are commonly connected, a base connected to a reference potential (V _BIAS2 ) higher than the ground potential, and a collector grounded. It is an NPN transistor connected to V _DD which is a reference potential higher than the potential. The same components as those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted. Note that the relationship between V _BIAS1 and V _{BIAS2 only} needs to be set to such a value that the PNP transistor 13 and the NPN transistor 17 are not turned on at the same time. The relationship between V _{BIAS2 and} V _BIAS1 is not particularly limited. It is desirable to make it as large as possible while satisfying the above conditions.

Next, the operation of the analog signal processing circuit will be described with reference to FIGS. 2A and 2B. In this example, it is assumed that V _BIAS2 −V _BIAS1 is set to 0.6V. First, assuming that the MOS transistor 11 operates in the saturation region and i _D11 (t) and i _in (t) coincide with each other, the potential of the terminal 14 is approximately between V _BIAS1 and V _BIAS2 . The base-emitter voltages of the PNP transistor 13 and the NPN transistor 17 are both about 0.3 V, and both transistors are cut off. Here, when i _in (t) begins to increase as _in the period from time t ₀ to t ₁ , i _D11 (t) <i _in (t), so the voltage at the terminal 14 increases. At this time, while the NPN transistor 17 maintains the cut-off, when the voltage at the terminal 14 rises by about 0.5 to 0.7 V from V _BIAS1 , the PNP transistor 13 enters the forward active region and is turned on, i _in The current of (t) -i _D11 (t) flows into the terminal 15 through the PNP transistor 13 so that i _in (t) and i _D11 (t) match, that is, the gate-source voltage V _GS (t ) Increases the voltage at the terminal 15 so that the value is expressed by the equation (6). Note that the voltage at the terminal 15 rises when electric charges are supplied through the PNP transistor 13 to the gate-source parasitic capacitances of the MOS transistors 11 and 12 connected to this terminal. At this time, the circuit of FIG. 13 operates as a current mirror circuit, and an output current proportional to the input current is obtained as expressed by the equation (8).

Next, since i _D11 (t) = i _in (t) when the increase _in i _in (t) stops as in the period from time t ₁ to t ₂ , both the PNP transistor 13 and the NPN transistor 17 are cut off. As a result, the voltage at the terminal 14 falls and generally settles at an intermediate potential between V _BIAS1 and V _BIAS2 . Here, since the terminal 15 has high impedance, the charge at time t ₁ does not change, and the gate-source voltages of the MOS transistors 11 and 12 are kept at V _GS (t ₁ ). At this time, the output current i _out (t) is stored as a current proportional to the input current i _in (t ₁ ) at time t ₁ , as expressed by equation (9).

When i _in (t) falls below i _in (t ₁ ) as _in the period from time t ₂ to t ₃ , the voltage at the terminal 14 further decreases, but the PNP transistor 17 remains cut off. Since V _GS (t ₁ ) is stored, the output current i _out (t) is a value represented by the equation (9). By the way, when the voltage at the terminal 14 decreases by about 0.5 to 0.7 V from V _BIAS2 , the NPN transistor 17 enters the forward active region and is turned on, i _D1 (t) −i _in (t), i. _Since a current of _in (t ₁ ) −i _in (t) flows, the voltage drop at the terminal 14 is suppressed. For this reason, since the voltage amplitude of the terminal 14 can be made smaller than in the case of the sixth embodiment, a higher speed operation is possible.

Next, when a current exceeding i _in (t ₁ ) is input during the period from time t ₃ to time t ₄ and continues to increase, the voltage at the terminal 14 rises and approximately 0.5 to 0.7 V from V _BIAS1. The PNP transistor 13 again enters the forward active region when it rises to the ON state, and is turned on. The current i _in (t) -i _D11 (t) flows out of the terminal 15 through the PNP transistor 13 and i _in (t) The voltage at the terminal 15 is increased so that i _D11 (t) matches, that is, the gate-source voltage V _GS (t) of the MOS transistor 11 becomes the value represented by the equation (6). Then, an output current i _out (t) corresponding to the input current represented by the equation (8) is obtained.

  From the above description, by repeating the above operation according to the increase / decrease of the input current, it is possible to obtain the output current according to the peak value of the input current and to enable the operation at higher speed than the sixth embodiment. Recognize.

Also in this embodiment, the charge holding capacitor 18 is added to the terminal 15, the reset switching element 19 is added between the terminal 15 and a predetermined reference potential, and the terminals 14 and 16. It is possible to add constant current sources 111 and 112 to the same, and the same effects as in the seventh, eighth and tenth embodiments can be obtained.
(Thirteenth embodiment)
FIG. 14 shows a thirteenth embodiment of the analog signal processing circuit according to the present invention. In this embodiment, an N-type MOS transistor is used instead of the NPN transistor of the first embodiment. In the figure, reference numeral 23 denotes an N-type MOS transistor having a drain connected to the terminal 5, a source connected to the terminal 4, and a gate connected to a reference potential (V _BIAS1 ) lower than V _DD . The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The operation of this embodiment is the same as that of the first embodiment. However, when the voltage at the terminal 4 drops from V _{BIAS1 by} the threshold voltage of the MOS transistor 23 or more, the MOS transistor 23 is turned on and the voltage at the terminal 5 is lowered. Let Also in this embodiment, an output current corresponding to the peak value of the input current can be obtained as in the first embodiment.

In this embodiment, the charge holding capacitor 8 is added to the terminal 5, the reset switching element 9 is added between the terminal 5 and a predetermined reference potential, and the terminals 4 and 5 are connected to each other. It is possible to add the switching element 10 between them, and it is possible to add the constant current sources 101 and 102 to the terminals 4 and 6, and the same effects as those of the second, third, fourth and fifth embodiments. Is obtained.
(Fourteenth embodiment)
FIG. 15 shows a fourteenth embodiment of the analog signal processing circuit according to the present invention. This embodiment is of the reverse conductivity type of the thirteenth embodiment, and uses a P-type MOS transistor instead of the PNP transistor of the sixth embodiment. In the figure, reference numeral 33 denotes a P-type MOS transistor having a drain connected to the terminal 15, a source connected to the terminal 14, and a gate connected to a reference potential (V _BIAS1 ) higher than the ground potential. The same components as those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted. The operation of this embodiment is the same as that of the sixth embodiment. However, when the voltage at the terminal 14 increases from V _{BIAS1 by} the threshold voltage of the MOS transistor 33 or more, the MOS transistor 33 is turned on and the voltage at the terminal 15 is increased. Let Also in the present embodiment, an output current corresponding to the peak value of the input current can be obtained as in the sixth embodiment.

In this embodiment, the charge holding capacitor 18 is added to the terminal 15, the reset switching element 19 is added between the terminal 15 and a predetermined reference potential, and the terminals 14 and 15 are connected to each other. It is possible to add the switching element 20 between them, and it is possible to add the constant current sources 111 and 112 to the terminals 14 and 16, and the same effects as those of the seventh, eighth, ninth and tenth embodiments Is obtained.
(15th Example)
FIG. 16 shows a fifteenth embodiment according to the analog signal processing circuit of the present invention. This embodiment is an improved version of the thirteenth embodiment and enables high-speed operation. The NPN transistor of the eleventh embodiment is replaced with an N-type MOS transistor, and the PNP transistor is replaced with a P-type MOS transistor. It is a thing. In the figure, reference numeral 27 denotes a source connected to a terminal commonly connected to the drain of the MOS transistor 1 and the source of the MOS transistor 23, a gate connected to a reference potential (V _BIAS2 ) lower than V _DD , and a drain connected to the V _This is a P-type MOS transistor connected to a ground potential which is a reference potential lower than _DD . Constituent members that are the same as those shown in FIG. _The relationship between _{V BIAS1} and _{V BIAS2} has only to be set to a value so as not to turn on simultaneously the MOS transistor 23 and MOS transistor 27, although not limited particularly magnitude _relation, V _{BIAS1 -V BIAS2} is It is desirable to make it as large as possible while satisfying the above conditions. The operation of this embodiment is the same as that of the eleventh and thirteenth embodiments. However, when the voltage at the terminal 4 drops from V _{BIAS1 by} the threshold voltage of the MOS transistor 23 or more, the MOS transistor 23 is turned on and the terminal 5 is turned on. When the voltage at the terminal 4 rises from V _{BIAS2 by} the threshold voltage of the MOS transistor 27 or more, the MOS transistor 27 is turned on, thereby i _D1 (t) −i _in (t), i _iin (t ₁ ). A current of −i _in (t) is supplied to suppress an increase in voltage at the terminal 4. For this reason, in this embodiment, the voltage amplitude of the terminal 4 can be made smaller than in the case of the thirteenth embodiment, so that a higher speed operation is possible, and the eleventh and thirteenth embodiments can be used. Similarly, an output current corresponding to the peak value of the input current is obtained.

In this embodiment, the charge holding capacitor 8 is added to the terminal 5, the reset switching element 9 is added between the terminal 5 and a predetermined reference potential, and the terminals 4 and 6 are connected. It is possible to add the constant current sources 101 and 102, and the same effects as those of the second, third and fifth embodiments can be obtained.
(Sixteenth embodiment)
FIG. 17 shows a sixteenth embodiment of the analog signal processing circuit of the present invention. This embodiment is an improved version of the fourteenth embodiment and enables high-speed operation. The PNP transistor in the twelfth embodiment is replaced with a P-type MOS transistor, and the NPN transistor is replaced with an N-type MOS transistor. It is a thing. In the figure, reference numeral 37 denotes a source connected to a terminal in which the drain of the MOS transistor 11 and the source of the MOS transistor 33 are commonly connected, a gate connected to a reference potential (V _BIAS2 ) higher than the ground potential, and a drain grounded. This is an N-type MOS transistor connected to V _DD which is a reference potential higher than the potential. Constituent members that are the same as in FIG. 15 are given the same reference numerals, and detailed descriptions thereof are omitted. Note that the relationship between V _BIAS1 and V _BIAS2 may be set to a value that does not turn on the MOS transistor 33 and the MOS transistor 37 at the same time. The relationship between V _{BIAS2 and} V _BIAS1 is not particularly limited. It is desirable to make it as large as possible while satisfying the above conditions. The operation of this embodiment is the same as that of the twelfth and fourteenth embodiments. However, when the voltage at the terminal 14 rises from V _{BIAS1 by} the threshold voltage of the MOS transistor 33 or more, the MOS transistor 33 is turned on and the terminal 15 voltage is raised of the voltage of the terminal 4 is lowered than the threshold voltage of the MOS transistor 37 from the _{V BIAS2} by MOS transistor 37 is turned _{on, i D11 (t) -i in} (t) i.e. _i in _(t 1) A current of −i _in (t) is supplied to suppress the voltage drop at the terminal 4. For this reason, in this embodiment, the voltage amplitude of the terminal 14 can be made smaller than in the case of the fourteenth embodiment, so that a higher speed operation is possible, and the twelfth and fourteenth embodiments can be achieved. Similarly, an output current corresponding to the peak value of the input current is obtained.

  In this embodiment, the charge holding capacitor 18 is added to the terminal 15, the reset switching element 19 is added between the terminal 15 and a predetermined reference potential, and the terminals 14 and 16 are connected. The constant current sources 111 and 112 can be added, and the same effects as those of the seventh, eighth and tenth embodiments can be obtained.

In the present invention, when the transistors (or the first and second transistors) that are not the first and second field effect transistors are bipolar transistors, the first and second main electrodes are the collector, emitter, and control electrode. Can be considered to correspond to the drain and source for the first and second main electrodes and the gate for the control electrode when the transistor is a field effect transistor.
(Seventeenth embodiment)
Next, an example of an apparatus using a peak detection circuit will be described.

  In general, an apparatus for forming an image on a photosensitive drum surface using a laser beam such as a laser beam printer, as shown in FIG. 18, a laser diode 1906, a polygon mirror 1907 for scanning the laser, a lens system 1908, and a reflection mirror 1909. , And a photosensitive drum 1910, and the photodetecting device 1911 detects that the laser beam has passed a predetermined position, and generates a horizontal synchronizing signal as a binary electric signal.

  As shown in FIG. 19, the photodetector includes a photodiode 1921, a resistor R 1 that converts the photocurrent of the photodiode 1921 into voltage, and the photoelectric conversion output Vp as one input, and a binary value. The voltage comparator 1922 includes a reference voltage Vref for determining the threshold level for the conversion to the other input.

  However, in the circuit shown in FIG. 19, the photoelectric conversion output Vp and the reference voltage Vref that are input to the voltage comparator 1922 are independent of each other, so that the amount of light input to the photodetector is changed. Since the amplitude of the photoelectric conversion output Vp varies while the value of the reference voltage Vref is constant, the threshold level changes relatively. For this reason, the generation timing of the horizontal synchronizing signal Vout may fluctuate greatly, or the slope when the rising or falling waveform of the photoelectric conversion output Vp crosses the threshold level may be different. It was. For this reason, fluctuations in laser power due to changes over time, temperature changes, etc., or fluctuations in light quantity due to the effects of light transmittance and reflectance deterioration due to contamination of the polygon mirror 1907, the lens system 1908, and the reflection mirror 1909 are stabilized. It was an obstacle to get output. Furthermore, there is no versatility between models using different laser powers, and the resistor R1 is adjusted according to the laser power for each model, or the reference voltage Vref is configured with a variable voltage source. Must be adjusted.

  In this embodiment, even when the amount of incident light changes, a highly accurate horizontal synchronization signal can be generated stably.

  FIG. 20 is a diagram showing a light detection device according to an embodiment of the present invention, and can be suitably used as the light detection device 1911 of the image forming apparatus shown in FIG. In the figure, reference numeral 2101 denotes a photodiode which is a photoelectric conversion means, 2102 denotes a current mode peak hold circuit which is means for holding a current value proportional to a peak current value output from the photodiode 2101, and 2103 denotes a photodiode. A current input comparator 2104 is proportional to the output current of the photodiode 2101, which is a means for comparing the current value proportional to the current value output by the 2101 and the current value held in the peak hold circuit 2102 in the current mode. A current mirror circuit 2105 for transmitting a current to the current mode peak hold circuit 2102 and a current input comparator 2103; a constant current source 2105 for supplying a bias current Ibias for making the current mirror circuit 2104 active beforehand; 2106 is This is a constant current source for supplying current (XY) · Ibias for canceling the bias current component. The current mode peak hold circuit 2102 includes an NPN transistor 2107 having a base connected to a constant voltage Vbias, PMOS transistors 2108 and 2109 having a 1: Y size ratio, and a hold capacitor 2110. A current input comparator 2103 , Constant current sources 2111 and 2112, NPN transistors 2113 and 2114, and an inverter 2115.

  The photodiode 2101 outputs a current Ip corresponding to the amount of incident light, and is guided to the current mode peak hold circuit 2102 through the current mirror circuit 2104. At this time, if the maximum value of the current Ip is Ipmax, the drain current of the PMOS transistor 2109 is held at a current value of Y · (Ipmax + Ibias). The current (X−Y) · Ibias for canceling the bias current component supplied from the constant current source 2106 is added to the held current Y · (Ipmax + Ibias), whereby one of the current input comparators 2103 is A current of Y · Ipmax + X · Ibias is injected into the input terminal. Further, a current of X · (Ip + Ibias) is drawn from the other input terminal of the current input comparator 2103 through the current mirror circuit 2104. The two current inputs meet at node A and the bias current component is cancelled. Then, as indicated by the direction of the arrows in the figure, a current of Y · Ipmax−X · Ip, that is, X · ((Y / X) · Ipmax−Ip) flows from the node A to the node B. Here, when a current flows from the node A to the node B, the potential of the node C drops toward the ground potential GND, so that the output Vout of the inverter 15 becomes a high level, and conversely, the current flows from the node B to the node A. When the current flows, the potential of the node C rises toward the power supply potential VDD, so that the output Vout of the inverter 15 becomes a roll level. Therefore, when X · ((Y / X) · Ipmax−Ip)> 0, that is, Ip is smaller than Yp / X of Ipmax, the photodetector of this embodiment outputs a high level, and X · ((Y / X ) · Ipmax−Ip) <0, that is, when Ip is larger than Yp / X of Ipmax, the photodetector of this embodiment outputs a low level. As can be seen from the above description, in the photodetector of this embodiment, if X and Y are set to desired values, the threshold level is automatically determined according to the peak value of the input light, and the incident light amount Regardless of fluctuations, a highly accurate horizontal synchronization signal can be obtained stably and constantly.

  Further, according to the present embodiment, in the photodetection device for an image forming apparatus that forms an image on the photosensitive drum surface using laser light, the photoelectric conversion means and the means for holding the peak value of the photoelectric conversion means; Means for generating a reference level according to the held peak value, and means for comparing the output of the photoelectric conversion means for electrically generating a horizontal synchronization signal with the generated reference level. As a result, it is possible to provide an image forming apparatus capable of obtaining a stable image output. Further, even in a model using a different laser power, the maximum value of the incident light amount irradiated to the light detection device is stored in memory. Since the threshold level is automatically determined, it is possible to provide an extremely versatile photodetector and image forming apparatus that do not require adjustment by model. That.

  Of course, the circuit format of the current mode peak hold means 2102 and the circuit format of the current input comparator 2103 used in this embodiment can be replaced with other circuit formats, and the output current of the photodiode 2101 can be changed. Although the current mirror 2104 is used as a means for transmitting to the current mode peak hold means 2102 and the current input comparator 2103, other current transfer means may of course be used. Needless to say, a configuration using the reverse conductivity type element of this embodiment is also possible, and the same effect can be obtained.

It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a current waveform diagram for demonstrating an example of operation | movement of the peak hold circuit based on this invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. It is a schematic circuit diagram for explaining an example of an analog signal processing circuit according to the present invention. 2 is a schematic perspective view for explaining an example of a main part of the configuration of the image forming apparatus. FIG. It is a schematic circuit diagram for demonstrating an example of the circuit for obtaining a synchronizing signal. It is a schematic circuit diagram for demonstrating an example of the circuit for obtaining the synchronizing signal which has the analog signal processing circuit which concerns on this invention. It is a schematic circuit diagram which shows an example of the peak hold circuit of a voltage mode.

Explanation of symbols

1, 2, 27, 33 PMOS transistor 3, 17 NPN transistor 4, 14 Current input terminal 5, 15 Charge hold terminal 6, 16 Current output terminal 8, 18, 207 Charge hold capacitor 9, 10, 19, 20, 206 Switching element 9A, 10A, 19A, 20A Pulse signal input terminal 101, 102, 111, 112 Constant current source 11, 12, 23, 37 NMOS transistor 7, 13 PNP transistor 203, 204 Diode 201, 202 Operational amplifier 205 Resistance 208 Voltage Input terminal 209 Voltage output terminal

Claims (1)

First and second field effect transistors having a gate connected in common and a source connected to a first reference potential;
A first main electrode is connected to the gates of the first and second field effect transistors, a second main electrode is connected to the drain of the first field effect transistor, and controlled to a second reference potential. A first transistor with electrodes connected;
The second main electrode is connected to a connection portion between the drain of the first field effect transistor and the second main electrode of the first transistor, the conductivity type being different from that of the first transistor. A second transistor having a control electrode connected to a third reference potential and a first main electrode connected to a fourth reference potential;
An analog signal processing circuit in which a difference between the second reference potential and the third reference potential is set to a value that does not turn on the first transistor and the second transistor at the same time.

Images