JP4177851B2 - Logic circuit design method - Google Patents

Description

  The present invention relates to logic circuit design, and particularly relates to a technology related to top-down design from a C language description.

  Conventionally, logic circuit hardware has been designed using HDL languages such as Verilog-HDL and VHDL. However, in recent years, system level description languages called SpecC and SystemC have appeared, and hardware design using the C language has attracted attention.

  As a conventional technique, there is one that provides a language that enables simulation at an intermediate level between an algorithm description and an RT level description (disclosed in Japanese Patent Laid-Open No. 2001-109788). FIG. 16 shows a conventional logic simulation system for reducing the algorithm description 103 to a clock level description, decomposing a plurality of functions of the algorithm description 103 into partial functions operable in one clock, and operating the functions. Assemble the partial functions. The multiple functions are expressed in a language using registers as variables as the clock level simulator 108 which is a clock level description.

  As illustrated in FIG. 16, a clock level verification unit 106 is newly provided between the algorithm level verification unit 102 and the RT level verification unit 115. The clock level verification unit 106 includes a clock level system 107. The clock level system 107 includes a clock level simulation model 108 and a clock level CPU model 109, which are clock level descriptions. The clock level system 107 is automatically generated by the built-in C compiler 111 and subjected to description conversion. In the description conversion, a register which is a tool of the conventional function synthesis tool 112 is used as a term (a word or a primary variable). . The algorithm description 103 is converted into a clock level simulation model 108 by a model conversion tool 113 having a tool described by the function synthesis tool 112. The clock level CPU model 109 is automatically generated from the C-program 104 by the embedded C compiler 111. The clock base simulator 114 is formed of a clock level simulation model 108 and a clock level CPU model 109.

  In recent years, among behavioral synthesis tools and the like, those that can be directly converted into an HDL RT level description have begun to be provided. However, a circuit designed with such a tool not only greatly increases the circuit scale but also lowers the quality of the circuit as compared to a circuit designed directly with RT level description. In addition, since the circuit configuration cannot be freely controlled, it is very difficult to obtain a circuit intended by the designer, and it is very difficult to read the designed circuit.

  In addition, in the conventional technology described above, a model that takes into account all of the three major components of hardware, the data path, control, and clock, is generated. Therefore, logic verification using a clock level simulator is performed at the RT level. It is only faster than verification and does not change the complexity of verification. In addition, since it is broken down into functions that can be processed in units of clocks, it becomes a description with a lower level of abstraction, and eventually a description equivalent to the RT level. This does not eliminate the difficulty of responding to specification changes and the complexity of hardware architecture studies in conventional RT-level design, and requires detailed design and verification equivalent to RT-level design. .

  More specifically, since the operation is performed in units of clocks, the description is conscious of hardware. For example, clock level verification is performed not only at the clock but also at a level including reset. The reset is necessary to determine the initial state of the hardware, but is not necessary at the stage of examining the hardware architecture or verifying the function. Rather, it is important to clarify basic hardware processing units, functional blocks, and control units.

  Further, the hardware architecture examination and the hardware function design / verification considering the clock operation are nothing but the simultaneous examination of the arithmetic function, the control function, and the timing function, and the concept becomes complicated. In other words, clocks and resets are not required when considering hardware architecture and designing functions, but rather cause complicated considerations. This makes it impossible to take advantage of the design at a high level of abstraction called C language.

  The above-described conventional clock level simulation model 108 needs to write a detailed control description by disassembling the processing in units of clocks using CDFG (Control Data Flow Graph) or the like. For this reason, it is extremely difficult to design unless hardware for cycle operation can be imagined.

  In this description of the clock level simulation model 108, one case statement corresponds to one clock, and the function is broken for each case so that the clock is simulated. It is necessary to call the function many times in cycle units. This is a major factor that reduces the simulation speed. Furthermore, one state transition needs to be one function.

  In view of the above problems, an object of the present invention is to enable efficient design of hardware with good quality in a short time from algorithm description written in pure C language in logic circuit design.

  In order to solve the above-mentioned problems, the solving means taken by the inventions of claims 1 to 12 is a logic circuit design method using a logic circuit design system having a state dividing means, a clock inserting means, and a conversion tool. The state dividing means re-describes the algorithm C description in which the logic circuit operation or control algorithm is described in the C language in the state for each processing unit based on the function, and sets the execution order of the processing as the state transition. The function C conversion step for converting the hardware control into the function C description describing the hardware control, and the clock insertion means adds a clock that is a concept of time to the function C description generated by the function C conversion step. An RT level C conversion step of inserting a description and converting it into a register transfer (RT) level C description, and the conversion tool comprises: The serial RT level C RT level C description generated by the conversion step, in which a HDL conversion step of converting the RT level description by HDL.

  According to this, the hardware of the logic circuit can be easily designed based on the algorithm C description written in the existing pure C language represented by ANSI-C and C ++. In addition, since the function C description is generated by dividing the algorithm C description into a plurality of states in a processing unit that is not bound by a clock cycle, it can be expressed so that one state is executed in a plurality of cycles. It is. Therefore, it is suitable as a description style for studying hardware architecture at a higher level of abstraction. Therefore, the hardware architecture can be examined at a level with a higher level of abstraction than before.

  In the invention of claim 1, the function C conversion step in the logic circuit design method divides the algorithm C description into a plurality of states including at least one idle state or initialization state.

  According to the first aspect, even when the clock description is inserted in the RTLC conversion step, it always becomes an idle state when it does not operate. This eliminates the need for cycle adjustments when adding a time concept to the state machine, just inserting a clock description.

  According to a second aspect of the present invention, in the function C conversion step in the logic circuit design method, the algorithm C description includes at least a data input state corresponding to data input processing, an arithmetic state corresponding to arithmetic processing, and a data output. The result output state corresponding to the process is divided.

  According to the second aspect, it is possible to unify the conversion style to the function C description. In addition, since the data input state and result output state can be expressed as a state in which data is input / output to / from the state machine or the outside of the module, when inserting the clock description in the RTLC conversion step, Cycle timing adjustment is easy.

  According to a third aspect of the present invention, the logic circuit design method includes a function verification step of verifying only a data path and control of a hardware function using the function C description, excluding a clock. When it is confirmed that the hardware function is correct in the function verification step, the process proceeds to the RT level C conversion step.

  According to the third aspect, the data path and the control, which are hardware components, can be determined at an early stage of design. Further, since there is no clock concept in the function C description, high-speed function verification is possible and verification is easy. It is also easy to modify the design when changing. For this reason, the effect that a design period can be shortened significantly is acquired. Furthermore, by inserting a clock measurement function for each state, it is possible to estimate the execution cycle of each state in detail, so that the processing performance can be estimated with high accuracy. That is, since a functional model (simulation model) in C language that is normally created in parallel with hardware can be substituted with this functional C description, double development can be prevented.

  According to a fourth aspect of the present invention, in the logic circuit design method, the clock insertion unit includes an operation verification step of verifying a hardware clock cycle timing operation using the RT level C description, and the operation verification When it is confirmed that the clock cycle timing operation is correct in the step, the process proceeds to the HDL conversion step.

  According to the fourth aspect, at the stage where the RTLC description is generated, the operation can be verified by paying attention to the problem concerning the clock cycle timing. This facilitates verification, improves verification efficiency, and improves debugging efficiency. As a result, the design period can be shortened.

  In the invention of claim 5, the function C conversion step in the logic circuit design method is described in which the state transition expression is described by a switch statement, each divided processing unit is described by a multi-branch expression, and the execution order is case. It is expressed by specifying the transition destination in and a state machine is described so as to be closed using a loop expression.

  According to claim 5, the state machine can be described without changing the algorithm operation in the existing C language. That is, without using a special dedicated language, it is possible to insert the state transition expression and correctly execute the arithmetic processing operation in the state machine. Furthermore, since there is no exit from state transitions every cycle, there is no need to assign one state transition to one function, and there is no need to call a function every cycle, so simulation can be executed at high speed. it can. In other words, in C language, it is possible to explicitly embed “control”, which is a hardware component, in the arithmetic processing. In the function C description, the hardware arithmetic unit and the control are controlled. A part can be described. As a result, not only can the hardware architecture be examined early, but also functional verification can be performed at high speed.

  In the invention of claim 6, in the function C conversion step in the logic circuit design method of claim 5, when a plurality of processes are executed in parallel in one state, the plurality of state machines are expressed as loops. It shall be described to be closed using each.

  According to the sixth aspect, in the C language algorithm C description, it is possible to easily describe the parallel operation while maintaining the characteristics of the C language high-speed simulation and without changing the operation. This is because it can be described in consideration of parallel operation when considering the hardware architecture, and the degree of freedom of hardware consideration at an early stage is increased, and an advanced control method can be described. This makes it possible to easily change to a parallel operation description when converting to an RTLC description.

  According to a seventh aspect of the present invention, in the logic circuit design method, as the pre-processing of the function C conversion step, the state dividing unit re-describes the algorithm C description for each module focusing on hardware functions. Assume that a module dividing step for generating an algorithm C description for each module is provided.

  According to the seventh aspect, the hardware architecture can be examined at a high level of abstraction, and the hardware-specific functions can be intentionally separated. As a result, the arithmetic processing function and the storage function can be easily separated, and the function C conversion step in the next stage can be easily designed, and the RT level C description can also be easily designed. Further, even when a partial change is made, it is easy to deal with each functional unit.

  In the invention of claim 8, the module dividing step in the logic circuit design method of claim 7 divides the algorithm C description into at least a memory part and an arithmetic processing part.

  According to the eighth aspect, when the HDL RTL code is generated, the replacement with the memory library can be easily performed, and the design considering the hardware architecture can be performed from an early stage. For this reason, it is possible to prevent the circuit scale from becoming large and to design in consideration of the memory as in the case of designing by HDL, and to easily change the memory to be used. In addition, design and simulation can be performed by changing only the arithmetic processing unit to the function C description or the RT level C description, thereby improving the ease of design and the simulation speed.

  In the ninth aspect of the invention, the module dividing step in the logic circuit design method of the seventh aspect divides the algorithm C description into a hardware soft macro or an arithmetic unit corresponding to the hard macro as a separate module. And

  According to the ninth aspect, when the HDL RTL code is generated, it can be easily replaced with a macro library such as a multiplier macro, and the design considering the hardware architecture can be performed from an early stage. Further, it is possible to explicitly and explicitly prevent an increase in circuit scale when using automatic synthesis or the like. In addition, design and simulation can be performed by changing only the arithmetic processing unit excluding the multiplier macro and the memory unit to the function C description or the RT level C description, thereby improving the design easiness and the simulation speed.

  In the invention of claim 10, the module dividing step in the logic circuit design method of claim 7 divides the parameter setting register unit for arithmetic processing as another module for the algorithm C description.

  According to the tenth aspect, the code can be partially changed without changing the code of the arithmetic processing unit or the like in the case of changing the number of registers. Further, since it is not necessary to search for a desired variable name from a large code at the time of failure analysis at the time of function verification, debugging is facilitated. Furthermore, it is possible to easily replace the register portion with a memory when hardware is used.

  In the invention according to claim 11, the RT level C conversion step in the logic circuit design method extracts and extracts from the function C description a state transition description representing control and an operation processing description representing a data path. It is assumed that a clock description, which is a concept of time, is inserted into each of the state transition description and the arithmetic processing description.

  According to the eleventh aspect, as in the case of describing the HDL RT level, the readability of the code is improved, and the debugging performance at the time of failure analysis at the time of verification is improved.

  In the invention of claim 12, the RT level C conversion step in the logic circuit design method generates an RT level C description by applying a grammar of SystemC or SpecC.

  According to the twelfth aspect, the design language can be determined after verifying the hardware function without depending on the design language. As a result, the design can be started even if the design language, the simulation tool, the behavioral synthesis tool, and the like are not determined at the beginning of development. Therefore, the development efficiency can be greatly improved and the development period can be shortened.

  The solution provided by the inventions of claims 13 to 24 rewrites an algorithm C description in which an algorithm for arithmetic or control of a logic circuit is described in C language in a state for each processing unit based on a function. By describing the execution order of the processes as state transitions, the function C conversion step for converting the hardware control into the function C description describing the control of the hardware, and the function C description generated by the function C conversion step, This is a program that inserts a clock description, which is a concept, and executes an RT level C conversion step for converting into a register transfer (RT) level C description.

  In the invention according to claim 13, the function C conversion step in the program divides the algorithm C description into a plurality of state descriptions including at least one idle state or initialization state.

  According to a fourteenth aspect of the present invention, in the function C conversion step in the program, the algorithm C description includes at least a description of a data input state corresponding to a data input process, a description of an operation state corresponding to an arithmetic process, and data The result output state corresponding to the output process is divided into descriptions.

  According to a fifteenth aspect of the present invention, in the program, the function C description is used to execute a function verification step for verifying only a data path and control of a hardware function, excluding a clock. In the function verification step, when it is confirmed that the hardware function is correct, the process proceeds to the RT level C conversion step.

  According to a sixteenth aspect of the present invention, in the program, the RT level C description is used to execute an operation verification step of verifying a hardware clock cycle timing operation. In the operation verification step, the clock cycle timing is verified. When the operation is confirmed to be correct, the RT level C description generated by the RT level C conversion step is shifted to an HDL conversion step for converting the RT level description into an HDL RT level description.

  The function C conversion step in the program is such that the state transition expression is described by a switch statement in the program, each processing unit is described by a multi-branch expression, and the execution order is set in the case. , And a state machine is described to be closed using a loop expression.

  In the invention of claim 18, in the function C conversion step in the program of claim 17, when a plurality of processes are executed in parallel in one state, the plurality of state machines are expressed using a loop expression. It shall be written to close each.

  Further, in the program according to the nineteenth aspect, in the program, as the preprocessing of the function C conversion step, the algorithm C description is rewritten for each module by paying attention to hardware functions, and the algorithm C description for each module is changed. Assume that the module division step to be generated is executed.

  In a twentieth aspect of the invention, the module dividing step in the program of the nineteenth aspect divides the algorithm C description into at least a memory part and an arithmetic processing part.

  According to a twenty-first aspect of the present invention, the module dividing step in the program of the nineteenth aspect divides the algorithm C description into a hardware soft macro or an arithmetic unit corresponding to a hard macro as a separate module.

  According to a twenty-second aspect of the present invention, in the module dividing step in the program of the nineteenth aspect, the parameter setting register section for arithmetic processing is divided as a separate module for the algorithm C description.

  In the invention of claim 23, the RT level C conversion step in the program extracts the state transition description representing control and the arithmetic processing description representing the data path from the function C description, and extracts the state transition. Assume that a clock description, which is a concept of time, is inserted into each of the description and the operation processing description.

  According to a twenty-fourth aspect of the present invention, the RT level C conversion step in the program generates RT level C description by applying SystemC or SpecC grammar.

  The invention of claim 25 is a computer-readable recording medium on which the program of any one of claims 13 to 24 is recorded.

  As described above, according to the present invention, the hardware of the logic circuit can be easily designed based on the algorithm C description written in the existing pure C language. Further, since the function C description can be expressed so that one state is executed in a plurality of cycles, it is suitable as a description style for studying the hardware architecture at a higher level of abstraction. Therefore, the hardware architecture can be examined at a level with a higher level of abstraction than before.

  Further, the present invention can be easily realized as a DA (Design Automation) tool. Thereby, the further shortening of a design period is realizable.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a hardware top-down design system based on a C language description, which is a logic circuit design system according to a first embodiment of the present invention. In FIG. 1, 1 is an algorithm C description in which an algorithm for operation or control of a logic circuit to be designed is described in C language, 2 is a function C description that describes hardware control, and 3 is a register transfer (RT ) RT level C description which is a level C language description. The algorithm C description 1 is described in an existing C language represented by ANSI-C and C ++.

  Reference numeral 10 denotes an algorithm verification system, which generates an algorithm C simulator 12 by compiling an algorithm C description 1 with a C compiler 11. Reference numeral 20 denotes a function C conversion system that converts the algorithm C description 1 into the function C description 2 and includes a state dividing unit 21. A function verification system 30 compiles the function C description 2 with the C compiler 31 to generate a function C simulator 32. Reference numeral 40 denotes an RT level C conversion system for converting the function C description 2 into the RT level C description 3, and includes a clock insertion means 41. A timing verification system 50 compiles the RT level C description 3 together with the library 4 that allows clock description by the C compiler 51 to generate a cycle-based C simulator 52.

  Reference numeral 60 denotes an existing conversion tool for converting a C language grammar into an HDL description. The RT level C description 3 is converted into Verilog-HDL5 as an RT level description in HDL.

  FIG. 2 is a processing flow showing the logic circuit design method according to this embodiment. 2, S1 is an algorithm verification step for verifying an algorithm using the algorithm C simulator 12 in the algorithm verification system 10, and S2 is an algorithm C description in the function C conversion system 20 after the algorithm is determined in the algorithm verification step S1. This is a function C conversion step in which the description in one module is state-divided into function processing units and converted to function C description 2. S3 is a function verification step of verifying the function of the hardware using the function C simulator 32 for the function C description 3 converted in the function C conversion step S2, and S4 is a function C step after the function is confirmed in the function verification step S3. This is an RT level C conversion step of inserting a clock description into description 3 and converting it to RT level C description 3. S5 is an operation verification step for verifying the operation of the RT level C description 3 using the cycle-based C simulator 52 by paying attention to the timing of the clock cycle, and S6 is the operation verification step S5 after the operation at the clock timing is confirmed. This is an HDL conversion step of converting the RT level C description 3 into Verilog-HDL5 using the conversion tool 60.

  Hereinafter, a logic circuit design method according to the present embodiment will be described with reference to FIGS.

  First, in the algorithm verification step S1, in the algorithm verification system 10, the algorithm C description 1 is compiled by a C compiler 11 such as cc or gcc, and becomes an algorithm C simulator 12 for verifying the algorithm. Then, using this algorithm C simulator 12, only the arithmetic processing (data path) is verified. At the same time, it is determined whether or not the algorithm has been determined. Then, correction of the algorithm C description 1 and its verification are repeated until the algorithm is determined.

  After the algorithm is determined in the algorithm verification step S1, next, in the function C conversion step S2, the algorithm C description 1 is converted into the function C description 2 by rewriting it in a state for each processing unit. For example, the description in each module of algorithm C description 1 is divided into processing units such as an initialization state corresponding to data input processing, an operation execution state corresponding to arithmetic processing, and a result output state corresponding to data output processing. To do. In addition, the transition destination, transition condition, and transition order of the divided state are described. As a result, the description corresponding to the “control” of the hardware is embedded in the function C description 2.

  The conversion process here can be realized, for example, by embedding a keyword in a comment sentence or the like in a line to be divided and performing program conversion according to the keyword.

  Here, a method of performing state division using a GUI will be described with reference to FIG. As shown in FIG. 3, an algorithm C description 71 before conversion is displayed on the GUI screen 70. The user selects a part 72 to be recognized as a batch of processes on the screen display, specifies a state name in “State Name” 73 for the selected part 72, and specifies an execution order of the processes in “Order” 74 To do. Further, in “End Condition” 75, a condition for exiting the state is input. When specified in this way, the converted function C description 76 is created by program conversion by the state dividing means 21.

  FIG. 4 is a diagram showing an example of state division, in which (a) shows an example of algorithm C description before state division, and (b) shows state division performed on algorithm C description of (a). This is a later function C description. In the algorithm C description shown in FIG. 4A, it can be determined that the text A is in the initialization and idle state, the text B is in the operation execution state, and the text C is in the result output state. The execution order is as follows. That is, after initialization with the text A, the process proceeds to the text B, and the arithmetic processing is executed. When the calculation end condition is satisfied in the text B, the process proceeds to the text C and the calculation result is output. When the calculation result is output, the text A is returned to the idle state.

  As a result of conversion according to such state division and execution order, a function C description as shown in FIG. 4B is obtained. The divided processing units A, B, and C are respectively described by switch statement cases as multi-branch expressions. The execution order is expressed by assigning the transition destination to state in case. Here, the switch-case statement is used as the multi-branch expression, but this is not limited as long as the multi-branch expression can be described.

  Further, since the function C description is described in C language like the algorithm C description, the switch statement is closed using “do” and “while” statements as loop expressions. Then, A which is in an idle state is designated as a condition for exiting the “while” statement. By describing in this way, at the time of execution of the process, the process exits from the switch statement when all the processing units A, B, and C have been processed and returned to the processing unit A again. Therefore, the next time this process is executed, it starts from the state of the processing unit A. Here, the state machine is closed by using “do” and “while” statements as loop expressions, but the same can be realized by using other loop statements such as while statements and for statements. When writing using “while (1)”, a “break” statement may be inserted in state C before returning to the idle state.

  That is, a function C description in which an operation equivalent to an algorithm of exiting from this state transition when processing is completed can be expressed and a description clearly indicating hardware “control” is embedded is completed.

  Here, the effect by having an idle state is demonstrated.

  When the clock is inserted, the circuit always operates. However, if the state machine always returns to the idle state, the idle state is maintained unless the condition for the state transition is satisfied. If there is no idle state, insertion of a clock requires processing such as newly adding control when the respective functions do not operate, complicating the timing design in the RT level C conversion step S4.

  Therefore, by specifying the idle state when creating a function C description that does not have a clock, it is possible to prevent a situation in which the function does not operate correctly even if a clock is inserted. Even if an idle state is provided, the operation at the stage of function C description is not affected. In other words, by having this idle state or initialization state, it is possible to easily convert to an RT level C description simply by inserting a clock.

  When the function C description 2 is generated in the function C conversion step S2, the process proceeds to the function verification step S3, and the function C verification system 30 uses the function C simulator 32 compiled by the C compiler 31 to The function of the wear is verified. Here, it is verified whether or not the arithmetic function can be realized in accordance with control optimal for hardware. If there is a problem or specification change, the state division in the function C conversion step S2 is corrected.

  At this time, the clock which is the concept of time is not reflected in the function C description 2. Therefore, functional verification is performed considering only the data path and control, except for the clock, among the three major components of the hardware. Here, the “data path” of hardware corresponds to arithmetic processing, and “control” corresponds to a state machine described by a switch statement. By not considering the clock which is the concept of time, it is possible to prevent the verification from becoming complicated.

  When it is determined in the function verification step S3 that the hardware function is confirmed, the process proceeds to the RT level C conversion step S4, and the function C description 2 is added to the function C description 2 by the clock insertion means 41 of the RT level C conversion system 40. A clock description, which is a concept of time, is inserted, and an RT level C description 3 is generated. This clock description insertion is executed by, for example, a conversion program.

  FIG. 5 shows an example of the RT level C description 3, which is a description example when applied to CoWare C for the hardware / software co-design tool N2C. In FIG. 5, a “thread rise (clk)” statement is inserted so that the entire state machine operates with a clock. Further, referring to the execution time estimated in the function C description 2, processing such as finely dividing the state is performed. For example, in FIG. 4B, a comment “// 2Cycle” meaning “2 cycles required” is inserted in the EXEC state. In response to this comment, the EXEC status is divided into, for example, EXEC and EXEC1. At this time, instead of using a switch statement, an “if” statement may be used. Further, the port converts into a plurality of signals such as data and enable according to the port protocol. These conversions can be automated by a program.

  When the RT level C description 3 is created in the RT level C conversion step S4, the operation timing of the hardware is verified with clock cycle accuracy in the operation verification step S5. Since the data path and control have already been verified in the function verification step S3 described above, only the timing operation is verified here.

  When the timing operation is confirmed in the operation verification step S5, the RT level C description 3 is converted into Verilog-HDL5 by using the conversion tool 60 in the HDL conversion step S6.

  As described above, according to the present embodiment, the function C description 2 can be created by changing the description at the same level as that of the algorithm C description 1, so that the existing pure C language represented by ANSI-C and C ++ can be used. Based on the written description, the logic circuit hardware can be easily designed.

  In addition, since the function C description 2 is divided into states with a focus on processing units that are not constrained by clock cycles, it can be expressed such that one state is executed in a plurality of cycles. For this reason, the hardware architecture and the hardware control method can be studied at a higher level of abstraction than before.

  Furthermore, since the function C description 2 is divided into states based on the initialization state, the operation state, and the result output state, it is possible to unify the conversion style. This also allows the initialization unit and the result output unit to be expressed as a state of inputting / outputting data to / from the outside of the state machine or the outside of the module. Therefore, even when the clock description is inserted in the RT level C conversion step S4, It is easy to adjust the timing of the clock cycle when transferring data.

  In addition, in the function verification step S3, only the data path and control of the hardware are verified, and the functions excluding the clock timing are determined at an early stage, so that it is a hardware component at an early stage of design. Data path and control can be determined. Furthermore, since there is no clock concept, high-speed functional verification is possible, and verification and correction at the time of design change are easy. Thereby, the effect that a design period can be shortened significantly is acquired.

  Furthermore, by inserting a clock measurement function for each state, it is possible to estimate the execution cycle of each state in detail, so that the processing performance can be estimated with high accuracy. That is, since the function model (simulation model) in C language that is normally created in parallel with the hardware can be substituted by the function C description 2, double development can be prevented.

  In addition, since the clock cycle timing verification is performed last, it is possible to perform the verification by paying attention to the problem related to the cycle timing at this stage, and the verification becomes easy. This improves verification efficiency and debugging efficiency. As a result, the design period can be shortened.

  Furthermore, since one state transition is completed by one “do” and “while” statement, the state machine can be described without changing the algorithm operation in a language such as ANSI-C or C ++. As a result, even if the state transition expression is inserted without using a special dedicated language, the arithmetic processing operation in the state machine can be correctly executed.

  Furthermore, since the state transition does not break (break) every cycle, there is no need to assign one state transition to one function, and there is no need to call a function every cycle, so the simulation is executed at high speed. be able to. This means that, in C language, it is possible to explicitly embed “control”, which is a hardware component, in the arithmetic processing. In the function C description 2, the hardware can be used without using a special language. This means that the calculation unit and control unit can be described. As a result, the hardware architecture can be studied at an early stage, and the function can be verified at high speed.

  In addition, the case where parallel operation is expressed in the function C conversion step S2 will be described.

  FIG. 6 is a description example in the case of expressing a parallel operation. For example, assume that it is desired to execute a plurality of processes in parallel in one state. In this case, as shown in the function C description 2 shown in FIG. 6A-1, a method of clearly indicating parallel processing by a comment (for example, “// parallel”) corresponding to each processing is conceivable (a portion surrounded by a broken line). . FIG. 6A-2 is a description example when the function C description 2 of FIG. 6A-1 is converted to RT level C. FIG. As shown in FIG. 6A-2, conversion may be performed so that two processes operate in the same state “S0 == 2” as in function C description 2.

  However, there may be a case where each processing unit needs to have a state transition. In this case, as shown in FIG. 6B-1, each state machine is described so as to be closed by using “do” and “while” statements (a portion surrounded by a broken line). FIG. 6B-2 is a description example when the function C description 2 in FIG. 6B-1 is converted to the RT level C. As shown in FIG. 6B-2, the two state machines may be converted by inserting conditional statements so that they operate in the same state “S0 == 2” as in function C description 2.

  As described above, since the parallelism of the processing can be clearly shown in the function C conversion step S2, the parallel operation can be described in the function C description 2 without requiring a special simulator, and the simulation can be performed at high speed. Further, since both the hardware control part and the parallelism can be clearly shown, conversion to the parallel description is facilitated when converting to the RT level C description.

(Second Embodiment)
FIG. 7 is a diagram showing a configuration of a hardware top-down design system based on a C language description, which is a logic circuit design system according to the second embodiment of the present invention. In FIG. 7, the same reference numerals as those in FIG. In FIG. 7, reference numeral 22 denotes a module dividing unit included in the function C conversion system 20 </ b> A. The algorithm C description 1 is rewritten for each module by paying attention to the hardware function, and module division is performed. Reference numeral 42 denotes control / data path separation means included in the RT level C conversion system 40A, which separates from the function C description 2 a state transition description representing “control” and an operation description representing “data path”.

  FIG. 8 is a processing flow showing the logic circuit design method according to this embodiment. In FIG. 8, the same processing steps as those in FIG. 2 are denoted by the same reference numerals as those in FIG. In FIG. 8, S7 is a module division determination step for determining whether or not the algorithm C description 1 can be divided into modules by paying attention to the hardware function, and S8 is a memory that is a hardware-specific function for the algorithm C description 1. This is a module dividing step for dividing a hard macro or the like as a separate module. S9 is a control / data path separation step, which separates the “switch” statement description of the state machine representing the control and the operation processing description in the “case” statement of the “switch” statement from the function C description 2. .

  Hereinafter, the logic circuit design method according to the present embodiment will be described with reference to FIGS.

  First, in the algorithm verification step S1, as in the first embodiment, in the algorithm verification system 10, the algorithm C description 1 is compiled by the C compiler 11 to become an algorithm C simulator 12 for verifying the algorithm. Then, using this algorithm C simulator 12, only the arithmetic processing (data path) is verified. At the same time, it is determined whether or not the algorithm has been determined. Then, correction of the algorithm C description 1 and its verification are repeated until the algorithm is determined.

  After the algorithm is determined in the algorithm verification step S1, next, in the module division determination step S7, whether or not the module C description 1 can be divided into modules by paying attention to the hardware function of the algorithm C description 1 to decide. For example, when algorithm C description 1 has a description corresponding to a memory such as an array, or when a hardware macro of a multiplier is assumed, there is a description of a multiplication part, these descriptions are Divide as a separate module. This processing can be realized by recognizing the array and the hard macro using a conversion program or the like. Alternatively, for example, the code can be displayed by GUI or the like, and the description can be divided by cutting and pasting in units of arithmetic processing.

  Here, a method of dividing a module by using a GUI will be described with reference to FIG. As shown in FIG. 9, the file is opened on the GUI screen 80, and the algorithm C description 81 before conversion is displayed. On the screen display, the user selects an assignment statement to the array corresponding to the memory, a multiplication part, or a plurality of parameter setting register parts as the module division part 82, and assigns a module name to “Module Name” 83 for each. Is specified. When designated in this way, the divided C description after conversion is created by program conversion by the module dividing means 22, and the divided individual modules are respectively displayed in the divided C description display field 84.

  FIG. 10 is a diagram illustrating an example of module division. In the figure, (a) is the original algorithm C description, and (b) is the algorithm C description after module division. In FIG. 10A, a portion A where data is input to the array is a hardware memory portion, and portions B1 and B2 assigned to parameters are register portions. Further, the part C that calls the function is the operation execution unit. Part A, parts B1, B2, and part C are each divided into modules as shown in FIG. When there is no description specific to the hardware function in the divided module, the process proceeds to the function C conversion step S2.

  In the function C conversion step S2, a module having a hardware-specific function is basically not converted into a function C description. In the case of including signal line control, only the portion corresponding to the logic circuit is embodied when converting to the RT level C description. For other parts, as in the first embodiment, the state division in the module and the state transition are clearly specified, and converted into the function C description 2. Here, the module corresponding to the operation execution unit is state-divided into a function C description 2.

  FIG. 11 is a diagram illustrating an example of conversion into the function C description 2. In the figure, (a) is an algorithm C description, and (b) is a function C description. A is an initialization state, B is an operation execution state, and C is a result output state. The operation execution state B may be further divided into two states, and FIG. 11B shows a description example further divided. That is, in FIG. 11B, the state B is further divided into a data input state from a memory or the like and a calculation state. In this case, the state transition is A initialization state (idle state) → B1 data input state → B2 operation execution state → C result output state → initialization state (idle state).

  Next, in the function verification step S3, the hardware control and the data path are verified as in the first embodiment, and the hardware function is determined.

  Next, in the control / data path separation step S9, the control / data path separation means 42 in the RT level C conversion system 40A uses the “switch” statement of the state transition description corresponding to “control” from the function C description 2. The operation processing description corresponding to the “data path” written in the “case” statement of the “switch” statement is separated. At this time, the “For” statement and the like are expanded into a counter description. Thereafter, in RT level C conversion step S4, a clock description is inserted to generate RT level C description 3.

  FIG. 12 is a diagram showing an example of conversion of RT level C description along CoWareC for the hardware / software co-design tool N2C. In the figure, (a) is the original algorithm C description, and (b) is the RT level C description. A control part is extracted from the algorithm C description shown in FIG. 12A, a state machine is formed, and a clock description is inserted. In addition, the arithmetic processing in each state of FIG. 12A is individually extracted by paying attention to the same parameter, and a control signal is added so that each of the extracted arithmetic processing operates only in the existing state, Insert a clock description into The “For” statement is separately expanded as a counter description. The RT level C description created in this way is as shown in FIG. The description of FIG. 12B has almost the same configuration as the HDL RTL description, and is highly readable for the hardware designer.

  Next, in the operation verification step S5, the timing verification system 50 performs timing verification using the RT level C description 3 generated in the RT level C conversion step S4. If there is no problem in the timing operation, the RT level C description 3 is converted into Verilog-HDL5 in the HDL conversion step S6.

  As described above, according to the present embodiment, as preprocessing of the function C conversion step S2, the algorithm C description 1 is divided into a plurality of modules by focusing on the hardware function. Therefore, it is possible to intentionally separate hardware-specific functions. As a result, it is possible to easily separate the arithmetic processing function and the storage function, and the division C design step 1 in the next function C conversion step S2 becomes easy, and the algorithm C description 1 is replaced with a hard macro later. Since it is possible to separate descriptions that can be verified as they are, RT-level design is also facilitated.

  In addition, since the state is divided based on the data input state, the operation state, and the result output state, the conversion style to the function C description 2 can be unified. In addition, since the data input state and the result output state can be expressed as a state in which data is input / output to / from the state machine or the outside of the module, the inter-function data is transferred when the clock description is inserted in the RT level C conversion step S4 It is easy to adjust the timing of the clock cycle at the time.

  Also, in the latter half of the design, the state transition description representing “control” is extracted from the function C description 2, and the operation processing description representing “data path” described in each state is extracted individually for each variable. Since the RT level C is generated separately, the readability of the code is improved as in the case of the RT level description by HDL, and the debugging performance of the failure analysis at the time of verification is improved.

  Furthermore, since the memory unit and the arithmetic processing unit are divided, when generating the HDL RTL code, it can be easily replaced with the memory library, considering the hardware architecture from an early stage. Design can be done. For this reason, it is possible to prevent the circuit scale from becoming large, and not only can the design be performed in consideration of the memory, but also the change of the memory to be used can be facilitated as in the case of designing by HDL. In addition, design and simulation can be performed by changing only the arithmetic processing unit to the function C description or the RT level C description, so that design ease and simulation speed are improved.

  In addition, since the parameter setting register unit for arithmetic processing is divided as a separate module, in the case of changing the number of registers, etc., it is necessary to change partly without changing the code of the arithmetic processing unit etc. Can do. In addition, since it is not necessary to search for a desired variable name from a large code at the time of failure analysis during function verification, debugging is facilitated. Furthermore, it is possible to easily replace the register portion with a memory when hardware is used.

  Here, the division of the memory unit is taken as an example. However, for example, when an arithmetic unit such as a multiplier is defined as a soft macro or a hardware macro in hardware, similarly, the arithmetic processing unit is Divide it as a separate module.

(Third embodiment)
FIG. 13 is a diagram showing a configuration of a hardware top-down design system based on a C language description, which is a logic circuit design system according to the third embodiment of the present invention. In FIG. 13, the same reference numerals as those in FIG. In FIG. 13, instead of the RT level C conversion system 40A, the timing verification system 50, and the conversion tool 60 in FIG. 7, a SystemC conversion system 40B, a SystemC verification system 50A, and a SystemC synthesis tool 70 are provided. The System C conversion system 40B includes a control / data path separation unit 42 and a sensitive description insertion unit 43 for sensitive designation, and converts the function C description 2 into the System C description 6. The SystemC verification system 50A compiles the SystemC description 6 by the C compiler 53 using the SystemC library 7 and generates a SystemC simulator 54. The SystemC synthesis tool 70 includes, for example, a SystemC compiler from Synopsy, and converts the SystemC description 6 into Verilog-HDL5.

  FIG. 14 is a processing flow showing the logic circuit design method according to this embodiment. In FIG. 14, the same processing steps as those in FIG. 8 are denoted by the same reference numerals as those in FIG. In FIG. 14, S10 is a SystemC conversion step in which the system C conversion system 40B inserts a sensitive description into the function C description 2 and converts it into the SystemC description 6. S11 performs a system cycle simulation using the SystemC simulator 54. This is a verification step. S12 is an HDL conversion step for synthesizing the SystemC description 6 into Verilog-HDL5 using an existing synthesis tool. The System C conversion step S10 corresponds to the RT level C conversion step of the present invention.

  Hereinafter, the logic circuit design method according to the present embodiment will be described with reference to FIGS.

  Similar to the second embodiment, the function C description 2 is generated in the function C conversion step S2, and the hardware function is determined in the function verification step S3. Then, in the control / data path separation step S9, the control / data path separation means 42 in the SystemC conversion system 40B uses the control description describing the state transition corresponding to the “control” of the hardware and the “data path”. The data path description describing the arithmetic processing in each state is separated. The data path description is described individually for each parameter.

  Next, in SystemC conversion step S10, a sensitive description is added to the control description and data path description separated in step S9. At the same time, conversion to SystemC grammar is performed. This conversion is performed using, for example, a conversion program.

  FIG. 15 is a diagram showing an example of conversion to the SystemC description 6, in which (a) is the original function C description and (b) is the description converted to SystemC. The sensitive description 91 added at the end designates a portion that operates in clock synchronization or a description that should be a combinational circuit in the sensitive list.

  When converted into the SystemC description 6 in step S10, in the SystemC verification step S11, verification based on the clock cycle is performed using the SystemC simulator 54 included in the SystemC verification system 50A. When correct operation is confirmed in the clock cycle-based verification, in the HDL conversion step S12, the SystemC description 6 is converted into the HDL RT level description 5 by using an existing SystemC synthesis tool 70 such as a SystemC compiler.

  As described above, according to the present embodiment, conversion from a function C description to, for example, SystemC can be performed smoothly into a desired design language. Thus, the design language can be determined after verifying the hardware function without depending on the design language. As a result, the design can be started even if the design language, simulation tool, behavioral synthesis tool, etc. are not decided at the beginning of development, so the development efficiency can be greatly improved and the development period can be shortened. . Also, an optimal tool can be selected at the stage of completion of the function C description.

  Although a description example of SystemC is shown here, it goes without saying that if the SpecC grammar is applied according to the same procedure, the function C description can be converted to SpecC, and the same effect can be obtained.

  In each embodiment, conversion to CoWareC, SystemC, SpecC, or the like is performed in the RTLC stage. However, for example, the module is connected to the module designed in these descriptions from the algorithm stage, and the connection follows these grammars. Even though the description in the module or block is written in pure C language, this stepwise design method can be implemented in exactly the same way. As in the embodiments, it is clear that the effect of improving the design efficiency can be sufficiently obtained because the data path, control, and clock, which are the three major components of hardware, are independent of the language.

  The logic circuit design method according to each embodiment of the present invention can be realized by a computer that executes a program for realizing the method. Further, it can be realized by recording a program for realizing the method on a computer-readable recording medium and causing the computer to execute the program recorded on the recording medium. In particular, it goes without saying that the functions of the function C conversion systems 20, 20A, the RT level C conversion systems 40, 40A, and the System C conversion system 40B can be realized by a program.

It is a figure which shows the structure of the top-down design system from the C language description based on the 1st Embodiment of this invention. It is a processing flow figure showing a logic circuit design method concerning a 1st embodiment of the present invention. FIG. 10 is a diagram illustrating an example of dividing an algorithm C description using a GUI in the first embodiment of the present invention. It is a figure which shows an example of the state division | segmentation in the 1st Embodiment of this invention. It is a figure which shows the example of RT level description in which the clock description was inserted. It is a figure which shows an example of the description which expressed parallel operation | movement, and an example of the state division | segmentation. It is a top-down design system block diagram from the C language description based on the 2nd Embodiment of this invention. It is a processing flowchart which shows the logic circuit design method which concerns on the 2nd Embodiment of this invention. In the 2nd Embodiment of this invention, it is a figure which shows the example which divides | segments the algorithm C description using GUI. It is a figure which shows an example of the state division | segmentation in the 2nd Embodiment of this invention. It is a figure which shows the example of a state division | segmentation description conversion in the 2nd Embodiment of this invention. It is a figure which shows the example of conversion into RT level C description in the 2nd Embodiment of this invention. It is a top-down design system block diagram from the C language description based on the 3rd Embodiment of this invention. It is a processing flowchart which shows the logic circuit design method which concerns on the 3rd Embodiment of this invention. It is a figure which shows the converted description example in the 3rd Embodiment of this invention. It is a figure which shows the structure of the conventional logic simulation system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Algorithm C description 2 Function C description 3 RT level C description 5 Verilog-HDL (RT level description by HDL)
20, 20A Function C conversion system 21 State division means 30 Function verification system 40, 40A RT level C conversion system 41 Clock insertion means 50 Timing verification system 60 HDL conversion tool S2 Function C conversion step S3 Function verification step S4 RT level C conversion step S5 operation verification step S6 HDL conversion step S8 module division step S10 SystemC conversion step (RT level C conversion step)

Claims (25)

A logic circuit design method using a logic circuit design system having a state dividing unit, a clock inserting unit, and a conversion tool,
The state dividing means re-describes an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describes a process execution order as a state transition. A function C conversion step of converting the hardware control into a function C description describing the hardware control;
An RT level C conversion step in which the clock insertion means inserts a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converts the clock description into a register transfer (RT) level C description; ,
The conversion tool comprises an HDL conversion step of converting the RT level C description generated by the RT level C conversion step into an HDL RT level description;
The function C conversion step includes:
A logic circuit design method, wherein the algorithm C description is divided into a plurality of state descriptions including at least one idle state or initialization state. A logic circuit design method using a logic circuit design system having a state dividing unit, a clock inserting unit, and a conversion tool,
The state dividing means re-describes an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describes a process execution order as a state transition. A function C conversion step of converting the hardware control into a function C description describing the hardware control;
An RT level C conversion step in which the clock insertion means inserts a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converts the clock description into a register transfer (RT) level C description; ,
The conversion tool comprises an HDL conversion step of converting the RT level C description generated by the RT level C conversion step into an HDL RT level description;
The function C conversion step includes:
The algorithm C description is divided into at least a data input state description corresponding to the data input process, an operation state description corresponding to the operation process, and a result output state description corresponding to the data output process. A logic circuit design method characterized by the above. A logic circuit design method using a logic circuit design system having a state dividing unit, a clock inserting unit, and a conversion tool,
The state dividing means re-describes an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describes a process execution order as a state transition. A function C conversion step of converting the hardware control into a function C description describing the hardware control;
An RT level C conversion step in which the clock insertion means inserts a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converts the clock description into a register transfer (RT) level C description; ,
The conversion tool comprises an HDL conversion step of converting the RT level C description generated by the RT level C conversion step into an HDL RT level description, and
Using the function C description, the hardware function includes a function verification step for verifying only the data path and control, excluding the clock,
In the function verification step, when it is confirmed that the hardware function is correct, the logic circuit design method shifts to the RT level C conversion step. A logic circuit design method using a logic circuit design system having a state dividing unit, a clock inserting unit, and a conversion tool,
The state dividing means re-describes an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describes a process execution order as a state transition. A function C conversion step of converting the hardware control into a function C description describing the hardware control;
An RT level C conversion step in which the clock insertion means inserts a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converts the clock description into a register transfer (RT) level C description; ,
The conversion tool comprises an HDL conversion step of converting the RT level C description generated by the RT level C conversion step into an HDL RT level description, and
The clock insertion means comprises an operation verification step of verifying a hardware clock cycle timing operation using the RT level C description;
In the operation verification step, when it is confirmed that the clock cycle timing operation is correct, the logic circuit design method moves to the HDL conversion step. A logic circuit design method using a logic circuit design system having a state dividing unit, a clock inserting unit, and a conversion tool,
The state dividing means re-describes an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describes a process execution order as a state transition. A function C conversion step of converting the hardware control into a function C description describing the hardware control;
An RT level C conversion step in which the clock insertion means inserts a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converts the clock description into a register transfer (RT) level C description; ,
The conversion tool comprises an HDL conversion step of converting the RT level C description generated by the RT level C conversion step into an HDL RT level description;
The function C conversion step includes:
State transition expression is described by a switch statement.
Describe each processing unit in multi-branch expression,
A logic circuit design method characterized in that an execution order is expressed by specifying a transition destination in a case, and a state machine is described so as to be closed using a loop expression. The logic circuit design method according to claim 5,
The function C conversion step includes:
A logic circuit design method characterized in that when a plurality of processes are executed in parallel in one state, the plurality of state machines are described so as to be closed using a loop expression. A logic circuit design method using a logic circuit design system having a state dividing unit, a clock inserting unit, and a conversion tool,
The state dividing means re-describes an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describes a process execution order as a state transition. A function C conversion step of converting the hardware control into a function C description describing the hardware control;
An RT level C conversion step in which the clock insertion means inserts a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converts the clock description into a register transfer (RT) level C description; ,
The conversion tool comprises an HDL conversion step of converting the RT level C description generated by the RT level C conversion step into an HDL RT level description;
As a pre-processing of the function C conversion step, the state dividing unit includes a module dividing step for rewriting the algorithm C description for each module by paying attention to a hardware function and generating an algorithm C description for each module. A logic circuit design method characterized by that. The logic circuit design method according to claim 7,
The module dividing step includes:
A logic circuit design method, wherein the algorithm C description is divided into at least a memory unit and an arithmetic processing unit. The logic circuit design method according to claim 7,
The module dividing step includes:
A logic circuit design method for dividing the algorithm C description into a hardware soft macro or an arithmetic unit corresponding to the hard macro as a separate module. The logic circuit design method according to claim 7,
The module dividing step includes:
A logic circuit design method for dividing the parameter setting register unit for arithmetic processing into a separate module for the algorithm C description. A logic circuit design method using a logic circuit design system having a state dividing unit, a clock inserting unit, and a conversion tool,
The state dividing means re-describes an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describes a process execution order as a state transition. A function C conversion step of converting the hardware control into a function C description describing the hardware control;
An RT level C conversion step in which the clock insertion means inserts a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converts the clock description into a register transfer (RT) level C description; ,
The conversion tool comprises an HDL conversion step of converting the RT level C description generated by the RT level C conversion step into an HDL RT level description;
The RT level C conversion step includes:
From the function C description, a state transition description representing control and an arithmetic processing description representing a data path are extracted,
A logic circuit design method, wherein a clock description which is a concept of time is inserted into each of the extracted state transition description and operation processing description. A logic circuit design method using a logic circuit design system having a state dividing unit, a clock inserting unit, and a conversion tool,
The state dividing means re-describes an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describes a process execution order as a state transition. A function C conversion step of converting the hardware control into a function C description describing the hardware control;
An RT level C conversion step in which the clock insertion means inserts a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converts the clock description into a register transfer (RT) level C description; ,
The conversion tool comprises an HDL conversion step of converting the RT level C description generated by the RT level C conversion step into an HDL RT level description;
The RT level C conversion step includes:
A logic circuit design method for generating an RT level C description by applying a grammar of SystemC or SpecC. On the computer,
By rewriting an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describing the execution order of processing as a state transition, the hardware A function C conversion step for converting into a function C description describing the control of
An RT level C conversion step of inserting a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converting it into a register transfer (RT) level C description is executed. ,
The function C conversion step includes:
A program characterized in that the algorithm C description is divided into a plurality of state descriptions including at least one idle state or initialization state. On the computer,
By rewriting an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describing the execution order of processing as a state transition, the hardware A function C conversion step for converting into a function C description describing the control of
An RT level C conversion step of inserting a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converting it into a register transfer (RT) level C description is executed. ,
The function C conversion step includes:
The algorithm C description is divided into at least a data input state description corresponding to the data input process, an operation state description corresponding to the operation process, and a result output state description corresponding to the data output process. A program characterized by On the computer,
By rewriting an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describing the execution order of processing as a state transition, the hardware A function C conversion step for converting into a function C description describing the control of
An RT level C conversion step of inserting a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converting it into a register transfer (RT) level C description is executed. ,And,
Using the function C description, a function verification step for verifying only the data path and control of the hardware function, excluding the clock, is performed.
In the function verification step, when it is confirmed that the hardware function is correct, the program shifts to the RT level C conversion step. On the computer,
By rewriting an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describing the execution order of processing as a state transition, the hardware A function C conversion step for converting into a function C description describing the control of
An RT level C conversion step of inserting a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converting it into a register transfer (RT) level C description is executed. ,And,
Using the RT level C description to execute an operation verification step of verifying a clock cycle timing operation of hardware;
In the operation verification step, when the clock cycle timing operation is confirmed to be correct, the RT level C description generated by the RT level C conversion step is shifted to an HDL conversion step for converting the RT level description into an RT level description by HDL. A featured program. On the computer,
By rewriting an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describing the execution order of processing as a state transition, the hardware A function C conversion step for converting into a function C description describing the control of
An RT level C conversion step of inserting a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converting it into a register transfer (RT) level C description is executed. ,
The function C conversion step includes:
State transition expression is described by a switch statement.
Describe each processing unit in multi-branch expression,
A program characterized in that the execution order is expressed by specifying a transition destination in a case, and one state machine is described so as to be closed using a loop expression. The program according to claim 17,
The function C conversion step includes:
A program characterized in that when a plurality of processes are executed in parallel in one state, the plurality of state machines are described so as to be closed using a loop expression. On the computer,
By rewriting an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describing the execution order of processing as a state transition, the hardware A function C conversion step for converting into a function C description describing the control of
An RT level C conversion step of inserting a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converting it into a register transfer (RT) level C description is executed. ,And,
As pre-processing of the function C conversion step, the algorithm C description is rewritten for each module by paying attention to hardware functions, and a module division step for generating an algorithm C description for each module is executed. program. The program according to claim 19, wherein
The module dividing step includes:
A program characterized by dividing the algorithm C description into at least a memory unit and an arithmetic processing unit. The program according to claim 19, wherein
The module dividing step includes:
A program for dividing the algorithm C description into a hardware soft macro or an arithmetic unit corresponding to the hard macro as a separate module. The program according to claim 19, wherein
The module dividing step includes:
A program characterized by dividing a parameter setting register for arithmetic processing as a separate module for the algorithm C description. On the computer,
By rewriting an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describing the execution order of processing as a state transition, the hardware A function C conversion step for converting into a function C description describing the control of
An RT level C conversion step of inserting a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converting it into a register transfer (RT) level C description is executed. ,
The RT level C conversion step includes:
From the function C description, a state transition description representing control and an arithmetic processing description representing a data path are extracted,
A program for inserting a clock description, which is a concept of time, into each of the extracted state transition description and operation processing description. On the computer,
By rewriting an algorithm C description in which a logic circuit operation or control algorithm is described in C language into a state for each processing unit based on a function, and describing the execution order of processing as a state transition, the hardware A function C conversion step for converting into a function C description describing the control of
An RT level C conversion step of inserting a clock description, which is a concept of time, into the function C description generated by the function C conversion step and converting it into a register transfer (RT) level C description is executed. ,
The RT level C conversion step includes:
A program characterized in that an RT level C description is generated by applying a grammar of SystemC or SpecC. A computer-readable recording medium on which the program according to any one of claims 13 to 24 is recorded.

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