JP4178699B2 - Microcomputer output device and microcomputer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer output device and a microcomputer including the output device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, microcomputer output devices for outputting digital signals to peripheral circuits in accordance with CPU control are known. These output devices are composed of a register mapped to a predetermined address of the CPU. When the CPU outputs data to the address, the output data is latched, and the latched data is transferred to the peripheral circuit. Output. The data latched by the register can be read into a general-purpose register in the CPU under the control of the CPU.
[0003]
In such an output device, a register having a plurality of bits is generally provided at one address. In particular, in a general-purpose one-chip microcomputer, the register is fixed to a predetermined bit width (for example, 8 bit width), and the output signal line of the register having the bit width can be connected to a peripheral circuit inside or outside the chip. It is common to prepare it as a port.
[0004]
For example, when a peripheral circuit is connected to an 8-bit width output port, a parallel output device or the like can be connected as a peripheral circuit using the entire 8 bits. In addition, a peripheral circuit for driving various peripheral devices can be connected by using a part of the output port having an 8-bit width. For example, a 7-segment LED is controlled using 4 bits out of 8 bits. Further, it is possible to control, for example, lighting of a lamp by using only one bit from an output port having an 8-bit width.
[0005]
In this way, the control target can be controlled by the CPU writing the value (data) to each bit of the register connected to the control target circuit via the signal line of the output port. In other words, the CPU can output a digital signal corresponding to the written value to the peripheral circuit corresponding to the predetermined bit by writing the value in the predetermined bit of the predetermined address.
[0006]
An example of these output devices will be described with reference to FIG.
FIG. 4 is a configuration example of a conventional memory mapped I / O microcomputer output device. This output device is integrated on one microcomputer chip together with a CPU (not shown). This output device is provided with 8-bit wide registers at a plurality of addresses in the memory space of the CPU. The output of each bit of each register is connected to a different pin (output terminal) of the microcomputer chip, and various peripheral circuits outside the chip can be connected to these pins.
[0007]
The register A of FIG. 4 is an 8-bit wide register from bit 0 to bit 7, and is mapped to address 0xFFFFFA00 in the CPU memory space. “0x” indicates that the numerical value after 0x is a hexadecimal number, and “0b” indicates that the numerical value after 0b is a binary number. The register B has the same configuration as the register A, and is mapped to address 0xFFFFFA01. In addition, a plurality of registers (not shown) mapped to different addresses from the registers C, D,.
[0008]
The output of each bit of each register is connected to a pin of the microcomputer chip. That is, bit 0 of register A is 1 pin, bit 1 is 2 pin, bit 2 is 3 pin, bit 3 is 4 pin, bit 4 is 5 pin, bit 5 is 6 pin, bit 6 is 7 pin, bit 7 is It is connected to pin 8. Bit 0 of register B is 9 pins, bit 1 is 10 pins, bit 2 is 11 pins, bit 3 is 12 pins, bit 4 is 13 pins, bit 5 is 14 pins, bit 6 is 15 pins, bit 7 is It is connected to 16 pins. The output of each bit of the other registers is also connected to different pins in order, and constitutes a plurality of output ports corresponding to each register. FIG. 4 illustrates two output ports, an output port A having 1 to 8 pins and an output port B having 9 to 16 pins.
[0009]
According to such a configuration, for example, if the CPU writes 0b11111111 to address 0xFFFFFA00, all pins 1 to 8 (each pin of output port A) of the microcomputer chip become Hi level, and if 0b00000000 is output to address 0xFFFFFA00. The pins of the output port A are all at the low level.
[0010]
In this way, the CPU can control the peripheral circuits connected through the pins. The data latched in each register can be read by the CPU. For example, if the CPU writes 0b10101010 at address 0xFFFFFA00 and then reads the data at address 0xFFFFFA00 into the general-purpose register of the CPU, the value of the general-purpose register becomes 0b10101010 which is the value of register A.
[0011]
When writing to the register, bit 0 to bit 7 may be rewritten at the same time. However, if the CPU is of a type that can directly control a specific bit on the address, only one specific bit on the register is used. It can also be changed. For example, if an LED is connected to the 8th pin, the CPU only needs to rewrite bit 7 at address 0xFFFFFA00 from 0 to 1 to light this LED. Then, the voltage level of the 8-pin changes from, for example, the Low level to the Hi level, and the LED can be changed from the unlit state to the lit state.
[0012]
[Problems to be solved by the invention]
However, there is a CPU that cannot directly control a specific bit of a register arranged on the address of the CPU, such as a CPU adopting a general RISC. In such a CPU, in order to write a value to a specific bit of the register, (1) the value of the register at the address is read (read) onto the general-purpose register of the CPU, and (2) on the general-purpose register of the CPU. It is necessary to perform a read-modify-write operation in which the bit is changed (modify) and (3) the value of the general-purpose register of the CPU is written (write) to the register at the address.
[0013]
At this time, if a plurality of processing routines write data to the same register, timing multiple access occurs, and an abnormality may occur in the output.
An example of this will be described with reference to FIG.
FIG. 5 is an example of output abnormality due to multiple access of registers.
[0014]
The register A in FIG. 5 corresponds to the register A in FIG. In FIG. 4, 1 pin is a lamp, 2 pin is a solenoid 1, 4 pin is a heater 1, 5 pin is a heater 2, 6 pin is a solenoid 2, 7 pin is a solenoid 3, 8 pin is a solenoid 4 Is connected as a peripheral circuit. Note that pin 2 is unused. Therefore, as shown in FIG. 5, in register A, bit 0 is ramp, bit 1 is solenoid 1, bit 3 is heater 1, bit 4 is heater 2, bit 5 is solenoid 2, bit 6 is solenoid 3, and bit 7 is solenoid. 4 bits. Note that pin 3 is unused.
[0015]
Among these devices to be controlled, the solenoids 1 to 4 must be driven every 4 ms, but the lamp, the heater 1 and the heater 2 have no particular time requirement. Therefore, the control of the register A by the CPU is performed by executing two routines, a base routine having a relatively low priority and a timer interrupt routine having a relatively high priority. The base routine accesses the lamp, heater 1 and heater 2 bits, and the timer interrupt routine accesses the solenoid 1, solenoid 2, solenoid 3 and solenoid 4 bits. The timer interruption time is 4 ms.
[0016]
The CPU that accesses the register A is a CPU that employs a general RISC, and is of a type that cannot directly manipulate specific bits of the register. Therefore, when writing to the register A in each routine, it is necessary to perform the above-described read-modify-write operation.
[0017]
In the example of FIG. 5, a timer interrupt occurs during the process of turning on the lamp by the read, modify, and write operations in the base routines S1, S2, and S3, and the process proceeds to the timer interrupt routine. The processing of the case is shown. In the timer interrupt routine, processing for turning on the solenoid 1 is performed in steps S11, S12, and S13.
[0018]
The operation of the CPU, the value of the general-purpose register of the CPU, and the value of the register A will be described below. Note that the initial value of the register A is 0b00000000, and all the devices are in the OFF state. Hereinafter, “general-purpose register” indicates a general-purpose register of the CPU. In FIG. 5, the right vertical column of registers represents the values of the general-purpose registers of the CPU, and the left vertical column of registers represents the values of the register A.
[0019]
In S1, the value of register A is read into the general-purpose register. Therefore, the value of the general-purpose register is 0b00000000.
In S2, the ramp bit of the general-purpose register is set to 1. That is, the value of bit 0 is modified to 1. Therefore, the value of the general-purpose register is 0b00000001.
[0020]
Here, when a timer interrupt occurs, the processing in the CPU shifts from the base routine to the interrupt routine. In this interrupt routine, the value of the general-purpose register is saved and the processing of S11 to S13 is performed.
In S11, the value of the register A is read to the general purpose register. At this time, since the value of the register A remains 0b00000000, the value of the read general-purpose register is also 0b00000000.
[0021]
In S12, the bit of solenoid 1 of the general-purpose register is set to 1. That is, bit 1 is modified to 1. Therefore, the value of the general-purpose register is 0b00000010.
In S13, the value of the general-purpose register is written to the register A. By this writing, the value of the register A becomes 0b00000010, the 2 pin becomes Hi level, and the solenoid 1 is turned ON.
[0022]
Subsequently, in order to return from the interrupt routine to the base routine, the saved general register value is restored. The value of the restored general-purpose register is the value in S2 and becomes 0b00000001. Then, the process returns to the base routine.
In S3, the value of the general-purpose register is written to the register A. Since the value of the general-purpose register is 0b00000001, the value of the register A is 0b00000001. Therefore, Pin 1 becomes Hi level and the lamp is turned on. At the same time, Pin 2 becomes Low level and Solenoid 1 is turned OFF.
[0023]
For this reason, the solenoid interrupt 1 should have been turned on in the timer interruption routine, but the problem that it is turned off in S3 occurs. This is because the value of the register is 0b00000011 and both the solenoid 1 and the lamp should be turned on. Such a problem also occurs when a timer interrupt occurs immediately after S1.
[0024]
In order to avoid this problem, the registers accessed by the base routine and the timer interrupt routine may be different registers. For example, register A is for the base routine and register B is for the timer interrupt routine. In this way, the above problem does not occur. However, there is a problem that the utilization efficiency of pins of the microcomputer chip is deteriorated. Further, such arrangement is often not possible due to the limitation of the number of pins of the microcomputer chip. For example, when register A is used for the base routine and register B is used for the timer interrupt routine, the bits used for the base routine are only 3 bits corresponding to the lamp, heater 1 and heater 2 of register A, and the timer interrupt The only bits used in the routine are the 4 bits of solenoids 1-4. Therefore, the number of pins used in the 16 pins from 1 to 16 which are output terminals from the register A and the register B is only 7, and the efficiency of use of the pins is deteriorated. In the first place, this is not possible with an output device having only one register.
[0025]
Therefore, normally, there are many cases where one output port cannot be occupied for each execution level, and even when multiple accesses occur, a device controlled from a plurality of execution levels must be assigned to one port.
Therefore, in order to avoid the multiple access problem as described above, there is a method in which interrupts are prohibited and exclusive access control is performed during a read-modify-write period. This avoidance method will be described with reference to FIG.
[0026]
FIG. 6 shows an example in which a countermeasure by software interrupt inhibition / interrupt is applied to the process of FIG. 5 in order to solve the problem in FIG.
The difference from the processing of FIG. 5 is that the interrupt during the processing period (S1, S2, S3) of the base routine of FIG. 5 is prohibited and the interrupt during the processing period of the timer interrupt routine (S11, S12, S13). Is to ban.
[0027]
Hereinafter, it will be confirmed that the multiple access problem described with reference to FIG. 5 does not occur with reference to FIG.
The configuration of the register A in FIG. 6, the initial value of the register A, the control target in each routine, how to indicate the value of each register, and the like are the same as in FIG.
[0028]
In S20, interrupt inhibition is applied (DI).
In S21, the value of the register A is read to the general purpose register. Therefore, the value of the general-purpose register is 0b00000000.
In S22, the ramp bit of the general-purpose register is set to 1. That is, the value of bit 0 of the general-purpose register is modified to 1. Therefore, the value of the general-purpose register is 0b00000001.
[0029]
Here, a timer interrupt occurs. However, since the interrupt is disabled, the execution of the timer interrupt routine is suspended until the interrupt is canceled. Therefore, the processing of the base routine is continued without being interrupted.
In S23, the value of the general-purpose register is written to the register A. Since the value of the general-purpose register is 0b00000001, the value of the register A is 0b00000001, and the lamp is turned on.
[0030]
In S24, the interrupt inhibition is canceled (EI).
Here, when the prohibition of interrupt is canceled, the processing in the CPU shifts to the timer interrupt routine.
In this interrupt routine, the value of the general-purpose register is saved and the processing of S30 to S34 is performed.
[0031]
In S30, interrupt inhibition is applied (DI).
In S31, the value of the register A is read to the general purpose register. At this time, since the value of the register A is 0b00000001, the value of the read general-purpose register is also 0b00000001.
[0032]
In S32, the bit of solenoid 1 of the general-purpose register is set to 1. That is, bit 1 of the general-purpose register is modified to 1. Therefore, the value of the general-purpose register is 0b00000011.
In S33, the value of the general-purpose register is written to the register A. This light turns on the solenoid 1. Since the value written to the register A is 0b00000011, it can be seen that the lamp remains on and correct operation is performed.
[0033]
In S34, the interrupt prohibition is canceled. Therefore, the value of the register A when the interrupt prohibition is released remains the value in S33. Therefore, it can be seen that both the lamp and the solenoid are finally in the ON state and correct operation is being performed.
Thus, by prohibiting interrupts during the read-modify-write period and exclusively controlling access to the registers, the above-mentioned problem of multiple access can be prevented.
[0034]
Note that the interrupt disable / cancel instructions in S30 and S34 of the timer interrupt routine may be omitted as long as they are within the range of this example. However, it is generally inserted for the purpose of facilitating future expansion / change and checking whether an interrupt disable / cancel instruction is correctly inserted. For example, in the future, when a new control target is connected to pin 3 in FIG. 4 and bit 2 which is an unused bit of register A is assigned to be controlled from the highest interrupt routine, the interrupts of S30 and S34 are performed. This is because a prohibit / cancel command is required. In addition, by disabling interrupts uniformly at the write location, there is no need to check whether an interrupt disable / release instruction has been forgotten or whether an interrupt disable / release instruction is not required, making it easier to check. Because it becomes.
[0035]
When the above measures are taken, it is necessary to insert an interrupt disable / cancel instruction for each register write process.
For this reason, the size of the object code increases as the interrupt disable / release instruction is added. When the size of the object code increases, the memory size such as ROM and RAM for storing the object code increases, and the cost increases.
[0036]
In addition, since a predetermined time is required to execute the interrupt disable / interrupt cancel instruction, the processing time also increases. FIG. 7 shows a difference in execution time between the case where the interrupt disable / release instruction of FIG. 6 is inserted and the case where the interrupt disable / release instruction of FIG. 5 is not inserted. FIG. 7A is a diagram showing the execution time when the interrupt disable / cancel instruction of FIG. 5 is not inserted (before countermeasures). On the other hand, FIG. 7B is a diagram showing the execution time when the above-described interrupt disable / cancel instruction of FIG. 6 is inserted (after countermeasures). As shown in this figure, the execution time after the countermeasure of (b) is executed in excess of the execution time of the interrupt disable / release instructions of S20, S24, S30, and S34, compared with the execution time before the countermeasure of (a). Need time.
[0037]
Such an increase in object code size and an increase in processing time may not be negligible, for example, in a control microcomputer. This is because, in the processing in these microcomputers or the like, accesses to registers arranged in the address space frequently occur in order to control devices. Therefore, it is necessary to insert an instruction to disable / release interrupts everywhere, and the added instruction is frequently executed.
[0038]
Furthermore, when software measures are taken in this way, if there is a leak at one location, the exclusive control of access to the registers will not be performed. It is necessary to check whether it is inserted. Then, there is a problem that the number of work steps increases in proportion to the number of write locations in these registers.
[0039]
Accordingly, an object of the present invention is to provide an output device for a microcomputer that does not require exclusive control by software.
[0040]
[Means for Solving the Problems and Effects of the Invention]
  The microcomputer output device according to claim 1, which has been made to solve the above-mentioned problems,A register which is arranged at a predetermined address and can be accessed by the CPU by designating this address, and a value written in the register by the CPU via a plurality of signal lines respectively corresponding to each bit of the register Output asOutput portWhenIt has. Each signal line of the output port is connected to an output part of a different OR circuit.
[0041]
  On the other hand, this one OR circuit has a plurality of input units, and these input units are connected to output units having the same bit number of registers having predetermined bit widths arranged at different addresses. . And all the input parts of each logical sum circuit are constituted in this way.Furthermore, when the CPU executes a plurality of routines that share one output port, each register is accessed by each routine at a different address.
[0042]
Note that the register arranged at an address means a register that can be accessed by a control device such as a CPU by designating the address. The logical sum circuit may be any circuit as long as it takes a logical sum of a plurality of input signals and outputs a signal obtained by taking the logical sum. For example, a wired OR circuit may be used.
[0043]
According to such a configuration, for example, the CPU sets the value of the bit on any one register of different addresses to 1, thereby setting the value of the signal line of the output port output via the OR circuit to 1 Can be.
Therefore, when multiple access occurs as described above, multiple access does not occur if each routine in which multiple access occurs accesses a register located at a different address. Moreover, a value obtained by logically summing the values of the registers is always output to the output port by the above-described OR circuit. Therefore, an expected value is output to the output port without taking measures to disable / release interrupts by software.
[0044]
Therefore, it is not necessary to add an interrupt disable / release instruction, and the object code size can be reduced. Therefore, when selecting a microcomputer, a microcomputer having a relatively small memory capacity can be selected, and the cost can be reduced.
[0045]
In addition, since it is not necessary to execute an interrupt disable / release instruction, the processing time is shortened. In addition, it is not necessary to check whether or not an interrupt disable / cancel instruction is properly inserted every time the software is changed, and the number of steps for software creation / maintenance can be greatly reduced.
[0046]
Furthermore, existing software assigned so that the bit numbers of the registers accessed by each routine do not overlap, such as the base routine and interrupt routine described with reference to FIG. For this purpose, it is only necessary to change the address of the register to be accessed for each routine. That is, since it is not necessary to change the bit allocation in software, existing software resources can be used effectively.
[0047]
By the way, in the invention described in claim 1, each register has a predetermined bit width. The predetermined bit width is, for example, a multiple bit width such as an 8 bit width or a 16 bit width. The bit width of each register may be different. For example, a 32-bit wide register of bit 31 to bit 0 is provided at address 1 and a 32-bit wide register of bit 31 to bit 0 is provided at address 2, and an 8-bit width of bit 7 to bit 0 is provided at address 3. This is a case where the output units of the same bit number of each register are connected to the input unit of the same OR circuit, and the output signal lines of these OR circuits are used as output ports. In this case, the output port consists of 32 signal lines. The logical value of each signal line of the output port corresponding to bit 31 to bit 8 is a value obtained by ORing each bit of each register at address 1 and address 2, and for bit 7 to bit 0, address 1 This is a value obtained by ORing the bits of the registers at address, address 2 and address 3.
[0048]
In this way, even when the accessible bit width changes depending on the operation mode of the CPU, for example, one output port can be shared by routines that execute in different operation modes. In addition, when the output port is output to the outside of the microcomputer chip (package) as will be described later, efficient pin assignment without an empty terminal can be performed.
[0049]
The bit width of each register may be the same as in the second aspect. In this way, it can be used as a general-purpose output device, and the bit assignment of the register accessed on the software side can be freely changed. That is, since the bit widths of all the registers are the same, for example, when the control process to be controlled is moved to a routine having a different execution priority, it is only necessary to change the register to be accessed. Especially in an embedded system, since there are many controlled objects and it is used for various purposes, such versatility is required.
[0050]
The output device is preferably integrated on one chip. In this case, the circuit connected to the output device exists inside or outside the chip. That is, a circuit connected to the output port may exist inside the chip or may exist outside the chip. When present inside the chip, each signal line of the output port is connected to each circuit in the chip. On the other hand, if it exists outside the chip, as shown in claim 3, each signal line of the output port may be connected to a pin of the chip. In this way, a circuit outside the chip can be controlled. Further, for example, in order to avoid the problem of multiple access as described above, one output port is occupied for each execution level, and the utilization efficiency of the output terminal of the microcomputer chip is not deteriorated. Therefore, efficient pin assignment without empty terminals is possible.
[0051]
When the output device is integrated on one chip, the output device alone may be integrated on the chip, or the output device and peripheral circuits connected to the output device may be integrated on the chip. Further, according to a fourth aspect of the present invention, the output device may be integrated on one chip together with a CPU that can write to the register of the output device. In this way, a microcomputer having an output port having the above-described characteristics is obtained.
[0052]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments to which the present invention is applied will be described below with reference to the drawings. Needless to say, the embodiments of the present invention are not limited to the following examples, and can take various forms as long as they belong to the technical scope of the present invention.
[0053]
Hereinafter, a description will be given with reference to FIGS.
FIG. 1 shows a hardware configuration of the output device 10 in this embodiment, and FIG. 2 shows a usage example and operation of the output device 10 when turning on the peripheral device. FIG. 3 shows an example of use and operation of the output device 10 when turning off the peripheral device.
[0054]
The microcomputer output device 10 of this embodiment shown in FIG. 1 is integrated in a microcomputer chip 20 together with a CPU (not shown).
The A-1 register 11 in FIG. 1 has the same configuration as the register A described above with reference to FIG. The A-2 register 12 has the same configuration as the register B described above with reference to FIG. Therefore, the description is omitted.
[0055]
However, the output sections of the A-1 register 11 and the A-2 register 12 are not directly connected to the pins of the microcomputer chip as shown in FIG. 4, but are connected to the A-1 register 11 as shown in FIG. Each bit number of the A-2 register 12 is connected to one OR gate of the OR gate group 13, and the output of the OR gate group 13 is connected to each pin through the signal line group 15. Specifically, the bit 0 output unit 17a of the A-1 register 11 and the bit 0 output unit 18a of the A-2 register 12 are connected to the input units 19a and 19b of the OR gate 13a, respectively, and this OR gate 13a. The signal line 15a from the output portion of the microcomputer chip 20 is connected to pin 1 of the microcomputer chip 20. Similarly, the output unit 17b of bit 1 of the A-1 register 11 and the output unit 18b of bit 1 of the A-2 register 12 are connected to the input units 19c and 19d of the OR gate 13b, respectively, and the output of the OR gate 13b. The signal line 15 b from the unit is connected to the 2 pin of the microcomputer chip 20. Hereinafter, as shown in FIG. 1, a similar circuit is configured up to bit 7 of each register.
[0056]
That is, bit n of the A-1 register 11 and bit n of the A-2 register 12 are connected to the input part of one OR gate of the OR gate group 13, and the signal line from the output part of the OR gate is The first output port 14 is connected to the (n + 1) pin of the microcomputer chip 20. In this embodiment, n is 0 to 7.
[0057]
As in the example of FIG. 4, the pin 1 in FIG. 1 is a lamp, the pin 2 is a solenoid 1, the pin 4 is a heater 1, the pin 5 is a heater 2, the pin 6 is a solenoid 2, the pin 7 is A drive circuit for driving the solenoid 4 is connected to the solenoid 3 and 8 pins as a peripheral circuit. Note that pin 2 is unused.
[0058]
Therefore, in the A-1 register 11 and the A-2 register 12, bit 0 is ramp, bit 1 is solenoid 1, bit 2 is unused, bit 3 is heater 1, bit 4 is heater 2, bit 5 is solenoid 2, Bit 6 is a control bit for solenoid 3 and bit 7 is a control bit for solenoid 4. 1, for example, if at least one of bit 0 of the A-1 register 11 and bit 0 of the A-2 register 12 is set to 1, the output of the 1 pin becomes Hi level and the lamp is turned on. Can be made.
[0059]
In addition, the relationship between the term of a present Example and the term described in the claim here is demonstrated easily. Since the same terminology is used basically, different points will be described. In this embodiment, the OR circuit in the claims corresponds to an OR gate, and the microcomputer corresponds to the microcomputer chip 20.
[0060]
In the following, the value of each register when performing the processing described with reference to FIGS. 5 and 6 in the hardware of the present embodiment shown in FIG. 1 will be described with reference to FIG.
The contents of the processing are the same as those in FIGS. 5 and 6, and solenoids 1 to 4 in FIG. 2 must be driven every 4 ms, while lamp, heater 1 and heater 2 have no particular time requirements. The A-1 register 11 is dedicated to access from the base routine, and the A-2 register 12 is dedicated to access from the timer interrupt routine. That is, the A-1 register 11 is controlled from a base routine having a relatively low priority, and the A-1 register 11 is controlled from a timer interrupt routine having a relatively high priority. The timer interruption time is 4 ms.
[0061]
The CPU that accesses the A-1 register 11 and the A-2 register 12 is a CPU that employs a general RISC, and is a type that cannot directly operate specific bits of the register. Therefore, in each routine, it is necessary to perform the above-described read-modify-write operation.
[0062]
The base routine accesses the lamp, heater 1 and heater 2 bits, and the timer interrupt routine accesses the solenoid 1, solenoid 2, solenoid 3 and solenoid 4 bits. In the figure, the hatched bits indicate bits that are not to be manipulated in the respective routines.
[0063]
The example of FIG. 2 is a process for shifting from S120 to the timer interrupt routine by a timer interrupt during the process of turning on the lamp in the base routines S110, S120, and S130. In the timer interrupt routine, processing for turning on the solenoid 1 is performed in S210, S220, and S230.
[0064]
Below, the operation of the CPU, the value of the general-purpose register of the CPU, the value of the A-1 register 11 and the value of the A-2 register 12 will be described. The initial values of the A-1 register 11 and the A-2 register 12 are both 0b00000000, and all the devices are in the OFF state. Hereinafter, “general-purpose register” indicates a general-purpose register of the CPU. 2 and 3, the right vertical column register indicates the value of the general-purpose register, and the central vertical column register indicates the value of the A-1 register 11 or the A-2 register 12. The left column shows the signal level of each output terminal of the first output port 14 in FIG. 1, and the signal level of each bit output is described from the 8th pin to the 1st pin in order from the left.
[0065]
As shown in FIG. 1, the A-1 register 11 is mapped to the address 0xFFFFFA00 in the memory space, and the A-2 register 12 is mapped to the address 0xFFFFFA01. Therefore, hereinafter, the CPU designates these addresses and reads or writes the values of the respective registers.
[0066]
In S110, the value of the A-1 register 11 is read to the general purpose register. Therefore, the value of the general-purpose register is 0b00000000.
In S120, the ramp bit of the general-purpose register is set to 1. That is, the value of bit 0 is modified to 1. Therefore, the value of the general-purpose register is 0b00000001.
[0067]
Here, when a timer interrupt occurs, the processing in the CPU shifts from the base routine to the interrupt routine. In this interrupt routine, the value of the general-purpose register is saved and the processing of S210 to S230 is performed.
In S210, the value of the A-2 register 12 is read to the general purpose register. Therefore, the value of the general-purpose register is 0b00000000.
[0068]
In S220, the bit of solenoid 1 of the general-purpose register is set to 1. That is, bit 1 is modified to 1. Therefore, the value of the general-purpose register is 0b00000010.
In S230, the value of the general-purpose register is written to the A-2 register 12. By this writing, the value of the A-2 register 12 becomes 0b00000010. Therefore, the output level of the A-2 register 12 is LLLLLLLHL when the output level of each bit is expressed from bit 7 to bit 0. On the other hand, the value of the A-1 register 11 remains 0b00000000. Accordingly, the output level of the A-1 register 11 is expressed as LLLLLLLLL in the same way. The above-described circuit configuration of FIG. 1 outputs an ORed level for each corresponding bit number of both registers, so that the signal level of the first output port 14 is LLLLLLLLHL. Therefore, pin 2 becomes Hi level and solenoid 1 is turned on.
[0069]
Subsequently, in order to return from the interrupt routine to the base routine, the saved general register value is restored. The value of the returned general-purpose register is 0b00000001 which is the value in S120, and the process returns to the base routine.
In S130, the value of the general-purpose register is written to the A-1 register 11. Therefore, the value of the A-1 register 11 is 0b00000001, and the output of the A-1 register 11 is LLLLLLLLH. On the other hand, at this time, since the output of the A-2 register 12 remains LLLLLLLHL, the output becomes LLLLLLLLHH by the circuit of FIG. That is, the 1 pin becomes Hi level and the lamp is turned on. Further, Pin 2 remains at the Hi level, and the solenoid 1 remains in the ON state. Therefore, both the lamp turned on in the base routine and the solenoid turned on in the interrupt routine are turned on, and an expected operation is performed.
[0070]
That is, according to this configuration, the output abnormality due to the multiple access as described with reference to FIG. 5 does not occur even if the software interrupt prohibition / cancellation is not performed as described with reference to FIG.
This is the same when the peripheral device is turned off. Hereinafter, an example in which the peripheral device is turned off will be described with reference to FIG.
[0071]
The circuit configuration of FIG. 3 is the same as that of FIG. The same applies to the allocation of each register to the base routine and the interrupt routine.
In FIG. 3, as an initial state, the value of the A-1 register 11 is set to 0b00000001, and the value of the A-2 register 12 is set to 0b10110000. With the circuit of FIG. 1, the level of the output terminal becomes HLHLLLHH, the lamp, solenoid 1, solenoid 2, and solenoid 4 are in the ON state, and heater 1, heater 2, and solenoid 3 are in the OFF state. From this state, the base routine performs processing to turn off the lamp, and the timer interruption routine performs processing to turn off the solenoid 1.
[0072]
Hereinafter, each step of FIG. 3 will be described.
In S310, the value of the A-1 register 11 is read to the general purpose register. Therefore, the value of the general-purpose register is 0b00000001.
In S320, the ramp bit of the general-purpose register is set to zero. That is, the value of bit 0 is modified to 0. Therefore, the value of the general-purpose register is 0b00000000.
[0073]
Here, when a timer interrupt occurs, the processing in the CPU shifts from the base routine to the interrupt routine. In this interrupt routine, the value of the general-purpose register is saved and the processing of S410 to S430 is performed.
In S410, the value of the A-2 register 12 is read to the general purpose register. Therefore, the value of the general-purpose register is 0b10110000.
[0074]
In S420, the bit of solenoid 1 of the general-purpose register is set to 0. That is, bit 1 is modified to 0. Therefore, the value of the general-purpose register is 0b10100000.
In S430, the value of the general-purpose register is written to the A-2 register 12. By this writing, the value of the A-2 register 12 becomes 0b10100000. Therefore, the output level of the A-2 register 12 is HLHLLLLL. On the other hand, the value of the A-1 register 11 remains 0b00000001. Therefore, the output level of the A-1 register 11 is LLLLLLLLH. The above-described circuit configuration of FIG. 1 outputs an ORed level for each corresponding bit number of both registers, so that the signal level of the first output port 14 becomes HLHLLLLLH. Therefore, pin 2 is at a low level and solenoid 1 is turned off.
[0075]
Subsequently, in order to return from the interrupt routine to the base routine, the saved general register value is restored. The value of the restored general-purpose register is 0b00000000, which is the value in S320. Then, the process returns to the base routine.
In S330, the value of the general register is written to the A-1 register 11. Then, the value of the A-1 register 11 becomes 0b00000000, and the output of the A-1 register 11 becomes LLLLLLLLLL. On the other hand, since the output of the A-2 register 12 remains HLHLLLLL at this time, the first output port 14 becomes HLHLLLLL by the circuit of FIG. In other words, the pin 1 becomes low level and the lamp is turned off. Further, pin 2 remains at the low level, and solenoid 1 remains in the OFF state. Therefore, both the solenoid 1 turned off in the interrupt routine and the lamp turned off in the base routine are turned off, and the expected operation is performed.
[0076]
Therefore, according to the present output device 10, it is not necessary to disable / cancel interrupts by software as shown in FIG. 6 regardless of whether the output is turned OFF or ON.
A-1 register 11 is used for the base routine and A-2 register 12 is used for the interrupt routine so that the bits operated by each routine are not the same bit, and the value of the bit not operated by the own routine is fixed to 0. This is because it is not necessary to perform exclusive processing during output processing in each routine.
[0077]
The processing steps in this case are the same as those in FIG. 5 before the exclusion process is added. Therefore, the execution time is equal to that before the countermeasure of FIG. 7A, and overhead due to addition of the interrupt disable / release instruction as shown in FIG. 7B does not occur. In addition, the multiple access problem shown in FIG. 5 does not occur. Therefore, it is possible to reduce the execution time while realizing a normal operation.
[0078]
Further, since the interrupt disable / release instruction is unnecessary, the size of the object code is reduced, and the ROM size can be reduced.
It is not necessary to occupy an output port for each execution level, and at most, registers for the execution level packed in the register of the same port are prepared, and each bit is logically ORed for each same bit number. Output. In addition, since the number of port packings for each execution level can be set arbitrarily, efficient allocation without empty terminals can be realized.
[0079]
Also, for example, when changing the execution level of a routine that manipulates bits, such as when changing the control of the heater 2 that was being executed by the base routine to be performed by a timer interrupt routine, the exclusive processing should be added to the software. It can respond without.
Furthermore, in order to make the conventional software asset of FIG. 6 correspond to this apparatus, the bit arrangement of the register is not changed, and it is not necessary to change the circuit pattern of the external base.
[Another embodiment]
(1) In the above embodiment, the configuration and operation of the two registers, the A-1 register 11 and the A-2 register 12, have been described. However, these registers may be three or more. For example, m registers from A-1 register 11 to Am register are provided, and the output of bit i of each register from A-1 register 11 to Am register is connected to the input part of the OR gate, respectively. The output may be connected to the output terminal. In this way, the peripheral circuit connected to the output terminal can be controlled from the m routines without exclusive control.
[0080]
Also, the bit width of the register need not be fixed to 8 bits, and may be 1 bit or more, such as 16 bits or 32 bits. That is, i in the above example may be an arbitrary number of bits.
(2) In the above-described embodiment, an interrupt is given as an example of multiple access. However, multiple access is not limited to an interrupt but occurs in various situations. For example, in the real-time OS, each routine is executed in accordance with the priority order of tasks, but writing to the same port may occur at this time as well. In such a situation where multiple accesses occur, the present apparatus can be used effectively.
(3) Although the OR gate group 13 is used in the above embodiment, an OR circuit that does not use a gate, such as a wired OR, may be used. In other words, any configuration may be used as long as a logical sum can be obtained.
(4) In the above embodiment, the output of the OR gate group 13 is connected to the pin of the microcomputer chip 20, but it may be connected via various circuits. For example, it may be connected via a driver circuit, a protection circuit or the like, or may be connected via a programmable inverter or the like. A NOR gate may be used to invert the signal level. The same applies to the output of each register. Of course, the pin arrangement may be freely determined.
(5) In the above embodiment, exclusive control is performed by performing different bit operations for each execution level. However, part or all of the circuit of FIG. It can also be used for control other than the example.
[0081]
For example, an LED is connected to pin 3 in FIG. 4 corresponding to bit 2 of register A, which is an unused bit in FIG. 5, and the LED is turned on when either flag 1 or flag 2 is ON (OR condition) I will let you. In such a case, it is conventionally determined by software whether one of the flags is ON, and if the result of the determination is that either flag 1 or flag 2 is ON, register A in FIG. The LED was turned on.
[0082]
However, when the LED is connected to pin 3 in FIG. 1, such flag determination by software is unnecessary, and instead of turning flag 1 ON, bit 2 of A-1 register 11 is set to 1, flag 2 The LED can be turned on only by setting bit 2 of the A-2 register 12 to 1 instead of turning ON. According to such a configuration, determination by software becomes unnecessary, and a delay that occurs until the determination is completed does not occur.
[0083]
Further, if each signal line of the OR gate group 13 is connected to a programmable inverter or the like, it is possible to output in the NAND condition instead of the OR condition. When there are a plurality of registers, for example, a combination of ON / OFF with a plurality of bits OR or ON / OFF with a plurality of bits AND can be used.
(6) In the above embodiment, the output device 10 is integrated on the microcomputer chip 20 together with a CPU (not shown). However, the output device 10 may be integrated as a single unit without including the CPU. If it does in this way, general purpose CPU etc. can be connected and it can utilize as an output device of these CPUs.
[0084]
In the above embodiment, each output port is connected to an output terminal and output to a peripheral circuit outside the chip. However, it may be connected to a peripheral circuit inside the chip. In this way, it is possible to similarly control the peripheral circuits in the chip.
(7) In the above embodiment, only the first output port 14 has been described as the output port, but there may be a plurality of output ports. In this way, it is possible to control a large number of controlled objects.
[0085]
The hardware configuration of each output port may be different. For example, together with the first output port 14, the second output port is provided with circuits each having a 16-bit width B-1 register, B-2 register, and B-3 register, and used together with the first output port 14. Also good. In this way, an optimum configuration can be adopted depending on the number of signal lines to be used and the number of routines to be accessed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram illustrating a hardware configuration of an output device 10 according to an embodiment.
FIG. 2 is an explanatory diagram illustrating a usage example and operation of the output device 10 when turning on the peripheral device according to the embodiment.
FIG. 3 is an explanatory diagram illustrating a usage example and operation of the output device 10 when turning off the peripheral device according to the embodiment.
4 is an explanatory diagram showing a hardware configuration of a conventional output device 10. FIG.
FIG. 5 is an explanatory diagram illustrating an example of output abnormality due to multiple access of a conventional register.
FIG. 6 is an explanatory diagram showing an example in which countermeasures are taken by interrupt prohibition / interruption of a conventional software.
FIG. 7 is an explanatory diagram showing changes in execution time before and after countermeasures by software.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Microcomputer output device 11 ... A-1 register
12 ... A-2 register 13 ... OR gate group
13a, 13b ... OR gate 14 ... First output port
15 ... Signal line group 15a, 15b ... Signal line
17a: Output section of bit 0 of the A-1 register
17b: Output section of bit 1 of the A-1 register
18a: Output section of bit 0 of the A-2 register
18b: Output section of bit 1 of the A-2 register
19a, 19b, 19c, 19d ... OR gate input section
20 ... Microcomputer chip

Claims (4)

A register arranged at a predetermined address and accessible by the CPU by designating this address, and a value written to the register by the CPU via a plurality of signal lines respectively corresponding to each bit of the register in the output device for a microcomputer including an output port for outputting a digital signal,
A plurality of the registers each having a predetermined bit width arranged at different addresses;
Each signal line of the output port is connected to an output part of a different OR circuit,
The input part of the logical sum circuit is connected to the output part of the same bit number in each register,
Each of the registers is accessed by the routine when the CPU executes a plurality of routines that share one output port, and each of the registers is located at a different address . Output device. The microcomputer output device according to claim 1,
The microcomputer output device, wherein the bit widths of the registers arranged at different addresses are all the same. The microcomputer output device according to claim 1 or 2,
Each signal line of the output port is connected to a different pin of the chip. The microcomputer output device according to any one of claims 1 to 3,
A microcomputer comprising: a CPU capable of writing to the register of the output device.

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