JP4180716B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technique, and more particularly, to a semiconductor device having a DRAM type memory element and a manufacturing method thereof.
[0002]
[Prior art]
A DRAM is a semiconductor memory device that can be configured with one transistor and one capacitor. Conventionally, various structures and manufacturing methods for manufacturing a semiconductor memory device with higher density and higher integration have been studied.
In recent years, in the field of manufacturing DRAM-type semiconductor devices, competition among manufacturers has intensified, and it has become an important issue how to manufacture more highly integrated high-performance semiconductor devices at a lower price. . For this reason, a simpler structure is desired for the capacitor, and a structure capable of securing a sufficient capacitance with a simple structure has been studied. One of such capacitor structures uses a columnar conductor as a storage electrode.
[0003]
The present applicant has proposed a semiconductor device using a columnar conductor as a storage electrode in Japanese Patent Application Laid-Open No. 10-189912. According to the semiconductor device and the manufacturing method thereof described in the publication, the manufacturing process is performed. Without increasing the complexity, the capacitance of the capacitor can be increased while suppressing an increase in resistance of the electrode plug formed in the peripheral circuit region.
[0004]
Hereinafter, the structure of a conventional semiconductor device described in Japanese Patent Laid-Open No. 10-189912 will be described with reference to FIG.
On the silicon substrate 100, a memory cell transistor having source / drain diffusion layers 102 and 104 and a gate electrode 106, and a peripheral circuit transistor having a source / drain diffusion layer 108 and a gate electrode 110 are formed.
[0005]
On the silicon substrate 100 on which the memory cell transistor and the peripheral circuit transistor are formed, an interlayer insulating film in which a plug 114 is embedded on the source / drain diffusion layer 102 and a plug 116 is embedded on the source / drain diffusion layer 108. 118 is formed.
A columnar storage electrode 120 is formed on the interlayer insulating film 118 and connected to the source / drain diffusion layer 102 via the plug 114 and protruding on the interlayer insulating film 118. A counter electrode 124 is formed on the side wall and upper surface of the storage electrode 120 via a dielectric film 122, and the space between adjacent storage electrodes 120 is buried by the counter electrode 124. Thus, a capacitor including the storage electrode 120, the dielectric film 122, and the counter electrode 124 is formed.
[0006]
An annular dummy electrode 126 surrounding the cell array region is formed at the periphery of the cell array region in which memory cells made up of memory cell transistors and capacitors are arranged in a matrix.
On the other hand, in the peripheral circuit region adjacent to the memory cell region, a plug 128 connected to the silicon substrate 100 via the plug 116 is formed on the interlayer insulating film 118, and the wiring 136 and the silicon substrate disposed in the upper layer are formed. It plays the role which electrically connects with 100. Note that the plug 128 is formed of the same conductive layer as the storage electrode 120.
[0007]
An interlayer insulating film 130 is formed on the interlayer insulating film 118 in the peripheral circuit region, and a surface constituted by the storage electrode 120, the plug 128, the annular dummy electrode 126, and the interlayer insulating film 130 is flattened.
A wiring 134 connected to the counter electrode 124 is formed on the counter electrode 124 via an interlayer insulating film 132. A wiring 136 connected to the plug 128 is formed on the plug 128 via an interlayer insulating film 132.
[0008]
Thus, a semiconductor device composed of one transistor and one capacitor was constructed.
[0009]
[Problems to be solved by the invention]
However, with the demand for further miniaturization and higher integration of semiconductor devices, the floor area of a region where storage electrodes are formed tends to be further reduced. On the other hand, in the DRAM, it is necessary to maintain a capacitance of about 35 fF throughout the generation in order to cope with the problem of α-ray soft error and the problem of lowering the power supply voltage.
[0010]
For this reason, it is assumed that it is difficult to maintain the above-mentioned capacitance in the conventional semiconductor device shown in FIG. 10, and a semiconductor that can further increase the storage capacity of the capacitor while taking advantage of the semiconductor device shown in FIG. An apparatus structure and a method for manufacturing the same have been desired.
An object of the present invention is to provide a structure of a semiconductor device capable of forming a memory cell by a simple structure and a manufacturing process, having excellent consistency with a contact formation process in a peripheral circuit region, and increasing a storage capacity. It is in providing the manufacturing method.
[0011]
[Means for Solving the Problems]
  The above purpose isForming an insulating film on the base substrate; forming a first opening reaching the first region of the base substrate and a second opening reaching the second region of the base substrate in the insulating film; A first conductive layer having etching characteristics different from those of the insulating film, and a second conductive layer having etching characteristics different from those of the first conductive layer on the base substrate on which the insulating film is formed. Forming, and selectively removing the first conductive layer and the second conductive layer on the insulating film, and the first conductive layer in the first opening and in the second opening And leaving the second conductive layer, selectively removing the insulating film and the second conductive layer in the first region, connected to the first region of the base substrate, and Connected to a cylindrical storage electrode made of one conductive layer and a second region of the base substrate. A step of forming a plug comprising the first conductive layer and the second conductive layer; a step of forming a dielectric film covering an inner surface and an outer surface of the storage electrode; and facing the dielectric film And a step of forming an electrode. This is achieved by a method for manufacturing a semiconductor device.
[0014]
In the method for manufacturing a semiconductor device, in the step of forming the first opening and the second opening, an annular third opening surrounding the first region is further formed, and the first opening is formed. In the step of leaving the first conductive layer and the second conductive layer in the opening and in the second opening, the first conductive layer and the second conductive layer are placed in the third opening. Further, in the step of remaining and removing the insulating film and the second conductive layer in the first region, the first region is formed using the first conductive layer formed in the third opening as a stopper. The insulating film and the second conductive layer may be removed.
[0015]
  In the method for manufacturing a semiconductor device, in the step of removing the insulating film and the second conductive layer in the first region, the insulating film and the second conductive layer in the first region are removed. You may make it remove simultaneously.
  Also,aboveIn the method of manufacturing a semiconductor device, a plurality of the storage electrodes may be formed, and the counter electrode may be formed so as to be embedded in a region between the plurality of adjacent storage electrodes in the counter electrode forming step.
[0016]
In the method of manufacturing a semiconductor device, in the step of removing the insulating film and the second conductive layer in the first region, a mask film that covers the second region and exposes the first region. In the step of selectively removing the insulating film and the second conductive layer in the first region using the mask as a mask and forming the counter electrode, a third conductive layer to be the counter electrode is deposited, The counter electrode may be formed in a self-aligned manner with the mask film by polishing the third conductive layer until the mask film is exposed.
[0017]
In the method of manufacturing a semiconductor device, in the step of removing the insulating film and the second conductive layer in the first region, the insulating film and / or the first conductive film is etched by isotropic etching. The two conductive layers may be removed.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
  A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS.9Will be described. 1A and 1B are a plan view and a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 2 to 9 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
[0019]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 1A is a plan view showing the structure of the semiconductor device according to the present embodiment, and FIG. 1B is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment.
A predetermined region on the semiconductor substrate 10 defined by the element isolation film 12 includes a memory cell transistor having a gate electrode 18 and source / drain diffusion layers 20 and 22, a gate electrode 24, and a source / drain diffusion layer 26. A peripheral circuit transistor is formed.
[0020]
On the semiconductor substrate 10 on which the memory cell transistor and the peripheral circuit transistor are formed, an interlayer insulating film in which a plug 36 is embedded on the source / drain diffusion layer 20 and a plug 40 is embedded on the source / drain diffusion layer 26. 28 is formed.
A cylindrical storage electrode 70 is formed on the interlayer insulating film 28 and is connected to the source / drain diffusion layer 20 through the plug 36 and protrudes on the interlayer insulating film 28. A counter electrode 74 is formed on both sides and an upper surface of the side wall of the storage electrode 70 via a dielectric film 72, and the space between adjacent storage electrodes 72 is buried by the counter electrode 74. Thus, a capacitor including the storage electrode 70, the dielectric film 72, and the counter electrode 74 is configured. The “cylinder shape” in the present specification means that it is formed in a pattern in which the central portion is hollowed out in a cylindrical shape, and the planar shape is limited to a circle or a rectangle. It is not a thing. In addition, a pattern in which the center portion of the annular pattern is cut out like an annular dummy electrode to be described later is also referred to as a “cylinder shape” in this specification.
[0021]
An annular dummy electrode 66 surrounding the cell array region is formed at the periphery of the cell array region in which memory cells made up of memory cell transistors and capacitors are arranged in a matrix. The conductive layer 58 constituting a part of the annular dummy electrode 66 is formed of the same conductive layer as the storage electrode 70. The annular dummy electrode 66 is formed so as to protrude on the interlayer insulating film 28 and has a height substantially equal to that of the storage electrode 70. In the present embodiment, for convenience, this annular structure is referred to as an “annular dummy electrode”, but the annular dummy electrode 66 does not necessarily need to be made of a conductive material. The effect according to the present embodiment can be obtained as long as the material has etching selectivity with respect to interlayer insulating films 42 and 50 and a conductive film 60 described later.
[0022]
On the other hand, in the peripheral circuit region adjacent to the memory cell region, a plug 64 connected to the semiconductor substrate 10 via the plug 40 is formed on the interlayer insulating film 28, and the wiring 80 disposed on the upper layer and the semiconductor substrate 10 is electrically connected. The conductive layer 58 that constitutes a part of the plug 64 is formed of the same conductive layer as the storage electrode 70.
[0023]
Interlayer insulating films 42 and 46, a stopper insulating film 48, and an interlayer insulating film 50 are formed on the interlayer insulating film 28 in the peripheral circuit region. The storage electrode 70, the plug 64, the annular dummy electrode 66, and the interlayer insulating film 50 are formed. The surface to be flattened is flattened.
A wiring 78 connected to the counter electrode 74 is formed on the counter electrode 74 via an interlayer insulating film 76. A wiring 80 connected to the plug 64 is formed on the plug 64 via an interlayer insulating film 76.
[0024]
As described above, in the semiconductor device according to the present embodiment, the annular dummy electrode 66 surrounding the cell array is formed at the peripheral portion of the cell array, and the plug 64 and / or the conductive film forming a part of the annular dummy electrode 66 is formed. A feature is that a cylindrical storage electrode 70 is formed of the same conductive layer. By configuring the semiconductor device in this way, the surface area of the storage electrode 70 can be made extremely wide, so that the capacitance of the capacitor can be greatly increased. Further, as will be described later, there are various merits in the manufacturing process of the semiconductor device.
[0025]
  Next, advantages of the semiconductor device according to the present embodiment will be described in detail along the manufacturing steps of the semiconductor device. 2 and 3 are sectional views of steps in the bit line contact portion, and FIG. 4 to FIG.9Shows cross-sectional process diagrams in the storage electrode contact portion.
  First, the element isolation film 12 is formed on the main surface of the semiconductor substrate 10 by, for example, a normal LOCOS method to define the element regions 14 and 16. Here, the element region 14 indicates a memory cell region that forms a memory cell, and the element region 16 indicates a peripheral circuit region that forms a peripheral circuit.
[0026]
Next, in the same manner as in a normal MOS transistor formation method, a memory cell transistor having a gate electrode 18 and source / drain diffusion layers 20 and 22 in the element region 14 is formed, and a gate electrode 24 and source / drain are formed in the element region 16. A peripheral circuit transistor having the diffusion layer 26 is formed (FIGS. 2A and 4A). The gate electrode 18 of the memory cell transistor also serves as a word line in which the gate electrodes of memory cell transistors (not shown) adjacent in the direction perpendicular to the paper surface are connected.
[0027]
In FIG. 2, the element regions 14 and 16 may be provided in wells formed in the semiconductor substrate 10, and the source / drain diffusion layers 20, 22, and 26 have an LDD structure and other diffusion layer structures. It is good.
Next, a silicon oxide film having a thickness of about 500 nm is deposited on the entire surface by, eg, CVD, and the surface is polished by CMP (Chemical Mechanical Polishing). Thus, an interlayer insulating film 28 made of a silicon oxide film and having a flat surface is formed. Note that the interlayer insulating film 28 is planarized in order to embed plugs in the interlayer insulating film 28 in a later step, and it is not always necessary to planarize the plug when the plug is not formed.
[0028]
Next, using normal lithography and etching techniques, the interlayer insulating film 28 has through holes 30 and 32 opened on the source / drain diffusion layers 20 and 22 of the memory cell transistor, and source / drain of the peripheral circuit transistor. A through hole 34 opened on the diffusion layer 26 is formed (FIGS. 2B and 4B).
[0029]
Next, plugs 36, 38, and 40 are embedded in the through holes 30, 32, and 34 opened in the interlayer insulating film 28 (FIGS. 2C and 4C). For example, a polycrystalline silicon film is deposited by CVD and etched back to leave the polycrystalline silicon film only in the through holes 30, 32, 34, and then doped into the polycrystalline silicon film by ion implantation. The resistance is reduced, and plugs 36, 38, and 40 are formed. For example, when the through holes 30, 32, and 34 have an opening diameter of about 0.15 to 0.2 [mu] m, a plug that fills the through holes 30, 32, and 34 by depositing a polycrystalline silicon film having a thickness of about 300 nm is deposited. 36, 38, 40 can be formed. The plugs 36, 38, and 40 are not necessarily formed, and the plug may be formed only in any one of the through holes. The plug may be formed as necessary depending on the device structure and process conditions.
[0030]
Next, an interlayer insulating film 42 is formed on the interlayer insulating film 28 in which the plugs 36, 38, 40 are embedded. For example, a silicon oxide film having a thickness of about 100 to 150 nm is deposited by the CVD method to form the interlayer insulating film 42. As the interlayer insulating film 42, a silicon oxide film doped with impurities such as a BPSG film or a non-doped silicon oxide film can be applied.
[0031]
Next, a contact hole 43 exposing the plug 38 is formed in the interlayer insulating film 42 by a normal lithography technique and etching technique (FIG. 3A).
Next, a Ti film having a thickness of about 20 nm, a TiN film having a thickness of about 50 nm, and a W film having a thickness of about 50 nm are sequentially deposited and patterned on the entire surface by a method such as CVD, for example. A bit line 44 having a Ti structure and connected to the plug 38 through the contact hole 43 is formed (FIG. 3B).
[0032]
Next, an interlayer insulating film 46 is formed on the interlayer insulating film 42 on which the bit line 44 is formed. For example, a silicon oxide film having a thickness of about 100 to 150 nm is deposited by the CVD method to form the interlayer insulating film 46. As the interlayer insulating film 46, a silicon oxide film doped with impurities such as a BPSG film, a non-doped silicon oxide film, or the like can be applied.
[0033]
Next, the surface of the interlayer insulating film 46 is polished by CMP, and the surface of the interlayer insulating film 46 is planarized.
Next, a stopper insulating film 48 used as an etching stopper in a later process is deposited on the interlayer insulating film 46. For example, a silicon nitride film having a thickness of about 10 nm is deposited by the CVD method to form the stopper insulating film 48.
[0034]
Next, an interlayer insulating film 50 made of a material having etching characteristics different from that of the stopper insulating film 48 is formed on the stopper insulating film 48. For example, a BPSG film having a thickness of about 1.0 μm is deposited by the CVD method to form the interlayer insulating film 50. As the interlayer insulating film 50, it is desirable to select an insulating film having substantially the same etching characteristics as the interlayer insulating film 42. For example, a silicon oxide film doped with an impurity such as BPSG, a non-doped silicon oxide film, or the like is applied. Can do.
[0035]
Next, the surface of the interlayer insulating film 50 is polished by CMP to planarize the surface of the interlayer insulating film 50 (FIGS. 3C and 5A).
Next, the interlayer insulating film 50, the stopper insulating film 48, and the interlayer insulating films 46 and 42 are patterned by a normal lithography technique and etching technique, and an opening 52 that exposes the plug 36, an opening 54 that exposes the plug 40, and an opening An annular opening 56 surrounding the cell array region in which 52 is formed is formed (FIG. 5B).
[0036]
Next, a conductive film 58 having a thickness that does not completely fill the openings 52, 54, and 56 is deposited on the interlayer insulating film 50 in which the openings 52, 54, and 56 are formed. For example, a Ru (ruthenium) film is deposited by the CVD method to form the conductive film 58. When the width in the short direction of the openings 52, 54, and 56 is about 0.2 μm, it is desirable to form a conductive film 58 by depositing a Ru film having a thickness of about 10 to 50 nm.
[0037]
The conductive film 58 is used as a stopper when the interlayer insulating film 50 is etched in a later process, and is made of a material having a different etching characteristic from the material of the interlayer insulating film 50. In addition, the conductive film 58 is a film that finally functions as a part of the storage electrode and the wiring plug, and is preferably compatible with the capacitor dielectric film and is made of a low-resistance conductive material. As the conductive film 58, in addition to a Ru film, for example, a RuO (ruthenium oxide) film, a SRO (SrRuO) is used._Three) Film, W (tungsten) film, Pt (platinum) film, doped polysilicon film, and the like can also be applied. However, it is not limited to these materials, and other conductive materials may be used.
[0038]
Next, a conductive film 60 having etching characteristics different from those of the conductive film 58 is deposited on the interlayer insulating film 50 on which the conductive film 58 is formed (FIG. 6A). For example, a conductive film 60 is formed by depositing a W (tungsten) film having a thickness of about 200 nm by a CVD method. The conductive film 60 has a thickness sufficient to completely fill the openings 52, 54, and 56. Note that the conductive film 60 is a film that finally functions as a part of the wiring plug, and it is desirable to use a low-resistance conductive material. As the conductive film 60, in addition to the W film, for example, a Ti (titanium) film, a TiN (titanium nitride) film, a Ta (tantalum) film, an Al (aluminum) film, a Cu (copper) film, a Ni (nickel) film, A Cr (chromium) film or the like can be applied. However, the conductive film is not limited to these films, and other conductive materials may be used as long as the conductive film has a different etching characteristic from the conductive film 58.
[0039]
  Next, the conductive films 58 and 60 on the interlayer insulating film 50 are selectively removed by, for example, a CMP method or an etch back method, and the conductive films 58 and 60 are left only in the openings 52, 54 and 56. Thus, the columnar conductor 62 embedded in the opening 52 and made of the conductive films 58 and 60 and connected to the plug 36 and the conductive film 58 and 60 buried in the opening 54 and the plug40And the annular dummy electrode 66 formed of the conductive films 58 and 60 is formed (FIG. 6B).
[0040]
In this embodiment, the openings 52, 54, and 56 are simultaneously opened, and the insides of these openings are simultaneously filled with the conductive films 58 and 60. However, the openings may be opened separately and the conductive films may be buried separately. The columnar conductor 62, the plug 64, and the annular dummy electrode 66 are formed of different materials when the etching characteristics in the openings 52, 54, and 56 are different from each other, or because of the compatibility of the dielectric film and the demand for lower resistance of the plug. This is particularly important when necessary.
[0041]
  Next, the interlayer insulating film 50 and the conductive film 60 in the cell array region surrounded by the annular dummy electrode 66 are selectively removed. For example, a mask 68 that covers a region other than the cell array region is formed (FIGS. 7A and 7B), and the interlayer insulating film 50 and the conductive film 60 are selectively removed by isotropic wet etching. As the mask 68, for example, a resist mask or a mask made of a material other than the resist transferred by the resist mask can be used. By etching these films in this manner, the source / drain diffusion layer 2 is made of the conductive film 58 through the plug 36 in the cell array region.0A cylindrical storage electrode 70 connected to is formed (FIGS. 8A and 8B).
[0042]
This etching can be achieved by etching the interlayer insulating film 50 and the conductive film 60 under etching conditions that can ensure selectivity with respect to the stopper insulating film 48 and the conductive film 58. For example, when the interlayer insulating film 50 is formed of a silicon oxide film, the conductive film 58 is formed of a Ru film, and the conductive film 60 is formed of a W film, etching is performed using a hydrofluoric acid-based aqueous solution. The interlayer insulating film 50 can be etched without damaging the stopper insulating film 48 and the conductive film 58, and then the conductor film 60 can be removed by etching with heated sulfuric acid. When the stopper insulating film 48 is formed of a silicon nitride film, the conductive film 58 is formed of a Ru film, and the conductive film 60 is formed of a TiN film, etching is performed using a hydrofluoric acid aqueous solution. Thus, the interlayer insulating film 50 and the conductive film 60 can be etched without damaging the stopper insulating film 48 and the conductive film 58. Ru has etching resistance against hydrofluoric acid and sulfuric acid, whereas TiN has some resistance against hydrofluoric acid and phosphoric acid, but is removed by long-time etching. It is. Although it is desirable to etch the interlayer insulating film 50 and the conductive film 60 at the same time from the viewpoint of simplifying the process, the interlayer insulating film 50 and the conductive film 60 may be etched separately.
[0043]
Since the cell array region is surrounded by the annular dummy electrode 66, there is no place where the interlayer insulating film 50 in the cell array region is connected to the interlayer insulating film 50 outside the cell array region. Therefore, by causing the annular dummy electrode 66 to function as an etching stopper, only the interlayer insulating film 50 in the cell array region can be selectively removed (see FIGS. 8A and 8B). Since the stopper insulating film 48 is formed on the interlayer insulating film 46, the interlayer insulating films 46 and 28 are not etched.
[0044]
In the above etching, wet etching is used, for the following reason. That is, in anisotropic etching such as dry etching, the etching progresses gradually from the upper surface, so that a very long etching corresponding to the thickness of the interlayer insulating film 50 is required, and the upper surface of the conductive film 58 serving as the storage electrode is in the meantime. This is because there is a risk of deformation due to exposure to etching ions. In addition, if the shape of the columnar conductor 62 is inversely tapered, the interlayer insulating film 50 may remain as a sidewall in this portion. Therefore, dry etching can be applied as well as wet etching as long as the etching conditions do not cause such a problem.
[0045]
Next, a dielectric film 72 that covers the surface of the storage electrode 70 is formed. For example, Ta film having a film thickness of about 10 nm is formed by CVD.₂O_FiveA film is deposited, and a dielectric film 72 having a thickness of, for example, about 0.5 to 1 nm is formed in terms of oxide film. The dielectric film 72 is formed of Ta₂O_FiveIn addition to the film, SrBi₂Ta₂O₉(SBT), BaSrTiO_ThreeA high dielectric film such as (BST) may be used.
[0046]
  Next, the counter electrode 74 is formed on the storage electrode 70 covered with the dielectric film 72. For example, a Ru film having a film thickness of about 100 nm is deposited by the CVD method, and the Ru film is formed in the gap between the storage electrodes 70 covered with the dielectric film 72 and the inner region of the storage electrode 70 where the conductive film 60 has been formed. Then, the Ru film is patterned to form a counter electrode 74 made of the Ru film. The gap between the storage electrodes 70 and the area inside the storage electrode 70 are extreme in layout.NarrowAlso, to fill this gap, the film thickness is about half that of the gap.RuSince the film is sufficient, the surface step formed by the counter electrode 74 is small (FIG. 9A). In addition to the Ru film, an electrode material such as a TaON film or a Pt film can also be applied as the material constituting the counter electrode 74.
[0047]
If an insulating film such as a silicon nitride film is applied as the mask 68 when etching the interlayer insulating film 50 in the memory cell region, the manufacturing process of the counter electrode 74 can be further simplified. That is, for example, as shown in FIG. 7A, after forming a mask 68 made of a silicon nitride film, the interlayer insulating film 50 and the conductive film 60 are removed by the same method as described above, and then the mask 68 is not removed. A conductive film to be the dielectric film 72 and the counter electrode 74 is deposited, and then the conductive film to be the counter electrode 74 and the dielectric film 72 are removed by a CMP method or the like until the mask 68 is exposed. That is, the counter electrode 74 can be formed in a self-aligned manner in the memory cell region. By doing so, the lithography process when forming the counter electrode 74 is reduced, and the manufacturing process can be simplified.
[0048]
Next, in the same manner as a normal wiring formation process, wirings such as a wiring 78 connected to the counter electrode 74 through the interlayer insulating film 76 and a wiring 80 connected to the plug 64 through the interlayer insulating film 76 are formed. . At this time, since the interlayer insulating film 76 substantially maintains the flatness of the interlayer insulating film 50, in the opening of the contact hole for connecting the wirings 76 and 78, the depth of focus is made shallow and fine patterning is performed. This can be done (FIG. 9B).
[0049]
Thus, a DRAM comprising one transistor and one capacitor can be manufactured.
As described above, according to the present embodiment, the conductive layer for forming the storage electrode 70 and the plug 64 includes the conductive layer 58 having different etching characteristics from the interlayer insulating film 50, and the conductive layer having different etching characteristics from the conductive layer 58. 60, the conductive layer 60 in the memory cell region can be selectively removed when the interlayer insulating film 50 in the memory cell region is selectively removed. Thereby, the cylindrical storage electrode 70 can be formed without increasing the resistance value of the plug 64. In addition, the capacitance of the capacitor can be greatly increased without complicating the manufacturing process.
[0050]
The basic structure and manufacturing method of the semiconductor device according to the present embodiment are the same as those described in Japanese Patent Laid-Open No. 10-189912, and various effects achieved by the semiconductor device can also be obtained. There is a merit that you can.
For example, in the semiconductor device according to the present embodiment, an opening is provided after the interlayer insulating film 50 having excellent global flatness is formed, and the storage electrode 70 and the plug 64 are formed by embedding the conductive films 58 and 60 in the opening. Therefore, the surface flatness of the interlayer insulating film 50 can be improved as compared with the case where the storage electrode 70 and the plug 64 are formed first. Thereby, the formation of the wiring formed on the interlayer insulating film 50 is facilitated.
[0051]
Further, since the storage electrode 70 and the plug 64 of the peripheral circuit are formed in the same process, the manufacturing process can be shortened and the manufacturing cost can be reduced.
In the semiconductor device according to the above-described embodiment, as shown in FIG. 1, since the potential of the annular dummy electrode 66 is in a floating state, there is a possibility that parasitic capacitance is generated between the adjacent counter electrode 74. In order to prevent such parasitic capacitance, it is desirable to maintain the annular dummy electrode 66 and the counter electrode 74 at the same potential.
[0052]
【The invention's effect】
As described above, according to the present invention, in a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, the memory cell transistor formed in the memory cell region and one diffusion layer of the memory cell transistor are connected. A capacitor having a cylindrical storage electrode made of the first conductive layer formed; a dielectric film covering the inner surface and the outer surface of the storage electrode; a counter electrode formed on the dielectric film; A cylinder-shaped first conductor made of the same conductive layer as the conductive layer; a second conductor made of the second conductive layer and embedded in the center of the cylinder of the first conductor; Since the semiconductor device is configured by the plug connected to the circuit region, a DRAM having a cylinder type capacitor can be configured without complicating the manufacturing process. As a result, the capacitance of the capacitor can be increased to nearly twice the same floor area without significantly increasing the manufacturing cost.
[0053]
In addition, an insulating film is formed on the base substrate, and a first opening reaching the first region of the base substrate and a second opening reaching the second region of the base substrate are formed in the insulating film. Forming a first conductive layer having etching characteristics different from those of the insulating film and a second conductive layer having etching characteristics different from those of the first conductive layer on the base substrate on which the insulating film is formed; Selectively removing the first conductive layer and the second conductive layer on the insulating film, and leaving the first conductive layer and the second conductive layer in the first opening and the second opening; The insulating film and the second conductive layer in the first region are selectively removed, connected to the first region of the base substrate, and the cylindrical storage electrode made of the first conductive layer and the first electrode of the base substrate. A step of forming a plug made of a first conductive layer and a second conductive layer connected to the second region, and a storage electrode Since the semiconductor device is manufactured by the step of forming the dielectric film covering the side surface and the outer surface and the step of forming the counter electrode on the dielectric film, the second conductive layer is formed in the conventional manufacturing method of the semiconductor device. A cylinder-type capacitor can be formed only by adding a process to be performed. Therefore, it is possible to increase the capacitance of the capacitor to nearly twice the same floor area without significantly increasing the manufacturing cost.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;
FIG. 3 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 4 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 5 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 6 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 7 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 8 is a process cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 9 is a process cross-sectional view (No. 8) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view showing the structure of a conventional semiconductor device.
[Explanation of symbols]
10 ... Silicon substrate
12 ... element isolation film
14: Element region
16: Element region
18 ... Gate electrode
20 ... Source / drain diffusion layer
22 ... Source / drain diffusion layer
24 ... Gate electrode
26: Source / drain diffusion layer
28 ... Interlayer insulating film
30 ... Through hole
32 ... Through hole
34 ... Through hole
36 ... Plug
38 ... Plug
40 ... Plug
42. Interlayer insulating film
43 ... Contact hole
44: Bit line
46. Interlayer insulating film
48 ... Stopper insulating film
50. Interlayer insulating film
52 ... Opening
54 ... Opening
56 ... Opening
58. Conductive film
60 ... conductive film
62 ... Columnar conductor
64 ... Plug
66 ... annular dummy electrode
68 ... Mask
70 ... Storage electrode
72. Dielectric film
74 ... Counter electrode
76 ... interlayer insulating film
78 ... Wiring
80 ... Wiring
100: Silicon substrate
102: Source / drain diffusion layer
104: Source / drain diffusion layer
106 ... Gate electrode
108: Source / drain diffusion layer
110 ... Gate electrode
114 ... Plug
116 ... plug
118 ... Interlayer insulating film
120 ... Storage electrode
122 ... Dielectric film
124 ... Counter electrode
126 ... annular dummy electrode
128 ... Plug
130: Interlayer insulating film
132 ... interlayer insulating film
134 ... wiring
136: Wiring

Claims (6)

Forming an insulating film on the base substrate;
Forming a first opening reaching the first region of the base substrate and a second opening reaching the second region of the base substrate in the insulating film;
Forming a first conductive layer having etching characteristics different from those of the insulating film and a second conductive layer having etching characteristics different from those of the first conductive layer on the base substrate on which the insulating film is formed; ,
The first conductive layer and the second conductive layer on the insulating film are selectively removed, and the first conductive layer and the second conductive layer are removed in the first opening and the second opening. Leaving the conductive layer; and
A cylindrical storage electrode formed by selectively removing the insulating film and the second conductive layer in the first region, connected to the first region of the base substrate, and comprising the first conductive layer; Forming a plug made of the first conductive layer and the second conductive layer connected to the second region of the base substrate;
Forming a dielectric film covering an inner surface and an outer surface of the storage electrode;
Forming a counter electrode on the dielectric film. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1 ,
In the step of forming the first opening and the second opening, an annular third opening surrounding the first region is further formed,
In the step of leaving the first conductive layer and the second conductive layer in the first opening and in the second opening, the first conductive layer and the second conductive layer in the third opening. More conductive layer of
In the step of removing the insulating film and the second conductive layer in the first region, the insulating film in the first region using the first conductive layer formed in the third opening as a stopper And removing the second conductive layer. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device of Claim 1 or 2 ,
In the step of removing the insulating film and the second conductive layer in the first region, the insulating film and the second conductive layer in the first region are simultaneously removed. Production method. In the manufacturing method of the semiconductor device according to any one of claims 1 to 3 ,
A method of manufacturing a semiconductor device, comprising: forming a plurality of the storage electrodes, and forming the counter electrodes so as to be embedded in a region between the plurality of adjacent storage electrodes in the counter electrode forming step. In the manufacturing method of the semiconductor device of any one of Claims 1 thru / or 4 ,
In the step of removing the insulating film and the second conductive layer in the first region, the insulation of the first region is masked using a mask film that covers the second region and exposes the first region. Selectively removing the film and the second conductive layer;
In the step of forming the counter electrode, a third conductive layer to be the counter electrode is deposited, and the third conductive layer is polished until the mask film is exposed, thereby self-aligning the mask film. A method for manufacturing a semiconductor device, comprising forming a counter electrode. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5 ,
In the step of removing the insulating film and the second conductive layer in the first region, the insulating film and / or the second conductive layer is removed by wet etching in which isotropic etching proceeds. A method of manufacturing a semiconductor device.

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