JP4186489B2 - Cleaning treatment method and semiconductor device manufacturing method - Google Patents

Description

【００８０】
第四の実施例
本実施例では、第三の実施例と同様の実験を、ガス流量比を変化させて行ったものである。
【００８１】
図１と同様のサンプル構造において第二の成長界面１０４での表面清浄処理条件としては、エッチングガスであるＴＢＣｌの供給量を１９．４μｍｏｌ／ｍｉｎ（ＩｎＰのエッチング速度にして２０．５ｎｍ／ｍｉｎ相当）、ＰＨ_３供給量を２．６８ｍｍｏｌ／ｍｉｎと一定にし、ＴＭＩｎの供給量を０〜３０μｍｏｌ／ｍｉｎの間で変化させて、１０分間表面清浄処理を行い、続けてアンドープＩｎＰ層１０５を成長した。続けてＳＩＭＳ分析により第２界面の残留Ｓｉ濃度について調べた。
【００８２】
図８は、第三の実施例における試料２のＴＭＩｎ流量を変化させたもの（図中、「残留Ｓｉ（連続型）」と表示）と、第三の実施例における試料３のＴＭＩｎ流量を変化させたもの（図中、「残留Ｓｉ（間欠型）」と表示）とが示されている。
【００８３】
図９は、第三の実施例における試料４のＴＭＩｎ流量を変化させたものが示されている。
【００８４】
図８および図９には、残留Ｓｉの面密度と共に、ＴＢＣｌ及びＴＭＩｎによるＩｎＰの成長速度（即ちアンドープＩｎＰ層１０３（第一の半導体層）の膜厚変化速度）を成長を正、エッチングを負として示した。
【００８５】
いずれの系においてもＴＭＩｎの供給量と共に残留Ｓｉ濃度が減少し、成長速度が０ｎｍ／ｓｅｃになる付近で、残留Ｓｉ濃度は最小値を示し、さらにＴＭＩｎ流量を増やすと、再び残留Ｓｉ濃度は上昇した。これは、エッチングガスのＴＢＣｌのみを第二の成長界面１０４に供給した場合、表面の残留Ｓｉは揮発性の塩化物ＳｉＣｌ_ｘとして一旦は表面から脱離するものの、Ｓｉ−Ｃｌの結合が、Ｓｉ−Ｐの結合に比べて弱く、Ｓｉ−Ｃｌの結合がすぐに切れてまた表面に際付着してしまうが、ＴＭＩｎをＴＢＣｌと同時に供給すると、ＳｉがＳｉＣｌ_ｘとして表面から脱離すると同時に、それまでＳｉが占有していた安定なＩＩＩ族サイトがＩｎで埋まり、一旦表面から脱離したＳｉが再びＩｎＰ表面に付着出来ずに表面から脱離していくためと考えられる。従ってＳｉの脱離効率はＴＢＣｌによるＩｎＰのエッチング速度とＴＭＩｎによるＩｎＰの成長速度が丁度釣り合うあたりで最大となる。ＴＭＩｎによるＩｎＰの成長速度がＴＢＣｌによるＩｎＰのエッチング速度を上回ると、今度はＳｉが脱離する前に、ＩｎＰ層が成長してしまい、表面の清浄処理が行われなくなるため第二の成長界面１０４での残留Ｓｉ濃度が上昇するものと考えられる。
【００８６】
図８および図９の結果から、０．１ｎｍ／ｓｅｃ以内の層厚変化速度とした場合、特に層厚変化が実質的にない場合に、残留Ｓｉ密度が顕著に低減されることが判明した。
【００８７】
以上、実施例に基づいて本発明を説明したが、本発明は上記各実施例に限定されず、本発明の技術思想の範囲内において、各実施例は適宜変更され得ることは明らかである。
【００８８】
たとえば上記実施例では、エッチング作用を有する原料として、ＴＢＣｌ、ビスジメチルアミノホスフィンクロライド（［（ＣＨ_３）_２］Ｎ_２ＰＣｌ）を用いたが、他のＣｌ系原料、例えば塩化水素（ＨＣｌ）や、塩化メチル（ＣＨ_３Ｃｌ）、四塩化炭素（ＣＣｌ_４）、ビスジメチルアミノアルシンクロライド（［（ＣＨ_３）_２］Ｎ_２ＡｓＣｌ）、三塩化燐（ＰＣｌ_３）、三塩化砒素ＡｓＣｌ_３、塩素（Ｃｌ_２）や、同様のＢｒ系原料、Ｉ系原料、Ｆ系原料を用いてもよい。他の原料を用いる場合、原料の分解効率やエッチング効率は原料によって異なるが、基本的には上記実施例に示したようにエッチング原料による半導体層のエッチング速度と結晶成長原料による半導体層の成長速度をバランスさせることで最大のエッチング効率が得られ、同様の効果が得られる。
【００８９】
また上記実施例では、結晶成長法としてＭＯＶＰＥ法を使った場合を例として説明したが、他の成長手法、たとえば分子線エピタキシー（ＭＢＥ）法やガスソースＭＢＥ（ＧＳＭＢＥ）法、有機金属ＭＢＥ（ＭＯＭＢＥ）法、化学ビーム成長（ＣＢＥ）法などを使っても良い。また上記実施例では、ＩｎＰ系材料について説明したが、本発明はこれに制限されるものではなく、ＧａＡｓ、ＩｎＡｓ、ＧａＰ、ＧａＮなどの他のＩＩＩ−Ｖ族化合物半導体やＩＩ‐ＶＩ族化合物半導体などの半導体材料に適用可能である。
【００９０】
また基板温度については、上記実施例では、６２５℃としたが、通常の結晶成長が可能な温度範囲例えばＩｎＰであれば４００℃〜７００℃程度の間、ＧａＡｓであれば４００℃から８００℃の間であればよく、エッチング原料による半導体層のエッチング速度や結晶成長原料による半導体層の成長速度の基板温度による変化を補正して、両者がバランスさせることで最大のエッチング効率が得られ、同様の効果がある。
【００９１】
また、上記実施例では半導体層に対してエッチング作用を有するエッチング性物質を含む第一のガスと結晶成長原料を含む第二のガスとを同時に半導体層表面に供給したが、これらを交互に供給する方式とすることもできる。この場合、半導体層の成長が過度に進行してしまうと充分な清浄度を実現することが困難となるため、１〜３原子層程度の厚みの成長が進行した後、エッチングが行われるというように、成長ガスとエッチングガスの切り替えを迅速に行うことが望ましい。
【００９２】
【発明の効果】
以上説明したように、本発明によれば、もとの半導体層中の不純物拡散や結晶欠陥の発生を誘発することなく、また形状変化を最小限にして、結晶成長前の半導体基板表面や再成長前の半導体表面の不純物汚染や物理的ダメージを再現性良く安定的に除去することが可能であり、成長界面を有する半導体素子の性能改善に大きな効果がある。
【図面の簡単な説明】
【図１】実施例で作製した半導体層の構造を示す図である。
【図２】実施例における残留不純物濃度のＳＩＭＳ測定結果を示す図である。
【図３】実施例における残留不純物濃度のＳＩＭＳ測定結果を示す図である。
【図４】実施例における残留不純物濃度のＳＩＭＳ測定結果を示す図である。
【図５】実施例における残留不純物濃度のＳＩＭＳ測定結果を示す図である。
【図６】実施例における残留不純物濃度のＳＩＭＳ測定結果を示す図である。
【図７】実施例における残留不純物濃度のＳＩＭＳ測定結果を示す図である。
【図８】実施例における残留Ｓｉ濃度のＴＭＩｎ供給量依存性を示す図である。
【図９】実施例における残留Ｓｉ濃度のＴＭＩｎ供給量依存性を示す図である。
【図１０】第二の実施例における埋め込み型半導体レーザ構造を示す図である。
【符号の説明】
１０１ ＩｎＰ基板
１０２ 第一の成長界面
１０３ アンドープＩｎＰ層
１０４ 第二の成長界面
１０５ アンドープＩｎＰ層
３０１ ｎ型ＩｎＰ基板
３０２ ｐ型ＩｎＰ層
３０３ ｎ型ＩｎＰ層
３０４ ｐ型ＩｎＰ層
３０５ ｐ型ＩｎＰクラッド層
３０６ ｐ−ＩｎＧａＡｓコンタクト層
３０７ ＩｎＧａＡｓＰ／ＩｎＧａＡｓＰ量子井戸
３０８ 第一の再成長界面
３０９ 第二の再成長界面
３１０ メサストライプ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for cleaning the surface of a semiconductor layer.
[0002]
[Prior art]
In the manufacturing process of a semiconductor device, a crystal growth process of the same or different kinds of semiconductor layers on a semiconductor substrate, a patterning process by photolithography and chemical etching or dry etching using a dielectric material as a mask, a current blocking structure and optical confinement Often, the same or different semiconductor layer regrowth steps for the structure are repeated. In this case, the surface of the substrate before crystal growth and the surface of the semiconductor growth layer before regrowth are easily subject to impurity contamination and physical damage due to atmospheric exposure, etching, cleaning, and other processes. The device characteristics and life will be greatly deteriorated. For this reason, in order to remove impurity contamination and a physically damaged layer, a method has been used in which etching is performed in a crystal growth chamber and then crystal growth is continued.
[0003]
As such a technique, in Japanese Patent No. 3158651, trimethylgallium (TMG) and arsine (AsH) are used as growth raw materials.₃), By etching in the growth chamber immediately before GaAs regrowth using hydrogen chloride (HCl) as an etching gas, impurities such as carbon (C), oxygen (O), silicon (Si) can be removed, Further, if TMG is simultaneously supplied together with HCl during etching, deviation from stoichiometry that occurs on the crystal surface due to etching is compensated, and carrier accumulation at the regrowth interface is suppressed.
[0004]
Japanese Patent Application Laid-Open No. 59-65434 discloses that in vapor phase growth of a GaAs semiconductor, a group III element alkyl compound and a group V element hydroxide or alkyl compound vapor are simultaneously introduced together with hydrogen chloride to form a semiconductor layer. A technique for etching is disclosed. As for the etching rate, an example of an etching rate of 0.1 μm per minute is shown. By doing so, it is said that the base surface before the start of growth can be made into a mirror surface.
[0005]
Japanese Laid-Open Patent Publication No. 51-74580 discloses that vapor phase etching of a semiconductor material composed of a group III-V element is performed in an inert gas atmosphere containing a halide of a group V element and a hydroxide thereof. A technique for simultaneously introducing a hydroxide of a group element is described. According to the publication, it is described that a substrate surface that is flat and excellent in specularity can be obtained.
[0006]
[Problems to be solved by the invention]
However, in the above prior art, contaminants whose etching rate is slower than the constituent elements of the semiconductor crystal are likely to remain on the surface. For example, I Triple E Journal of Selected Topics in Quantum Electronics Vol. 3, No. 3, pages 845 to 853 As reported in the eyes (IEEE Journal of Selected Topics in Quantum Electronics, Vol. 3, N0.3, p845-p853), the etching gas is PCl.₃Even if the InP surface is etched in the growth chamber using Si, Si is hardly etched and remains on the surface. Further, according to the experimental results of the present inventors, it is found that residual Si at the regrowth interface is removed near the normal crystal growth temperature even if etching is performed in the crystal growth chamber as shown in Japanese Patent No. 3158651. It was not easy. In addition, if the substrate temperature is raised too much to remove residual Si, or if etching is performed too deeply, impurity diffusion and crystal defects will occur inside the original semiconductor layer, and the shape will change due to etching, resulting in a device as designed. There was a problem that the structure could not be produced.
[0007]
The present invention has been made in view of the above circumstances, and its purpose is to induce impurity diffusion and generation of crystal defects in the original semiconductor layer, and minimize shape change, An object of the present invention is to provide a technique for stably removing impurity contamination and physical damage on a semiconductor substrate surface before crystal growth and a semiconductor surface before regrowth with good reproducibility.
[0008]
[Means for Solving the Problems]
The present inventors inferred the reason why it is difficult to remove specific contaminants attached to the semiconductor surface as follows. When an etchable substance is allowed to act on a contaminant adhered to the surface of the semiconductor layer, the etchable substance and the specific contaminant cause a chemical reaction. However, the bonding force of the bond generated by this chemical reaction is relatively weak. Even if the contaminant binds with the etching substance to form a compound and desorbs from the semiconductor surface, the bond immediately breaks and reappears on the semiconductor surface. It is expected to adhere. Thus, it is speculated that the specific contaminants attached to the semiconductor surface are difficult to remove because they reattach to the semiconductor layer.
[0009]
Based on such inference, the present inventor efficiently brought contaminants into contact with the surface of the semiconductor layer to be cleaned by contacting both the raw material having an etching action and the crystal growth raw material while suppressing reattachment. The inventors found that it can be removed by etching, and completed the present invention.
[0010]
  According to the present invention, there is provided a cleaning method for removing contaminants adhering to the surface of a semiconductor layer, wherein an etching substance having an etching action on the semiconductor layer and a crystal growth material are simultaneously or alternately used. And a cleaning process step of contacting the semiconductor layer, wherein the sign of the layer thickness change rate of the semiconductor layer is defined as positive when the layer thickness increases and negative when the layer thickness decreases, and the cleaning process R is the layer thickness change rate of the semiconductor layer when the process is performed, and r is the layer thickness change rate of the semiconductor layer when only the etching substance is brought into contact with the semiconductor layer.₁The change in layer thickness of the semiconductor layer when only the crystal growth raw material is brought into contact with the semiconductor layer is r₂When the absolute value of these layer thickness change rates is | R | <| r₂| <| R₁|The residual Si concentration at the growth interface of the semiconductor layer is the surface density of 2.5 × 10 ¹¹ atoms / cm ² IsA cleaning method is provided.
  With the above configuration, the supply balance of the etching substance and the crystal growth raw material becomes appropriate, the contaminants adhering to the surface of the semiconductor layer are efficiently removed, and the reattachment of the detached contaminants to the semiconductor layer is suppressed. Can do.
[0011]
  Moreover, according to the present invention,A cleaning method for removing contaminants adhering to a surface of a semiconductor layer, wherein an etching substance having an etching action on the semiconductor layer and a crystal growth raw material are simultaneously or alternately applied to the semiconductor layer. Including a cleaning treatment step for contact, and the sign of the rate of change in layer thickness of the semiconductor layer is defined as positive when the layer thickness increases and negative when the layer thickness decreases, and when the cleaning processing step is performed The layer thickness change rate of the semiconductor layer is R, and the layer thickness change rate of the semiconductor layer when only the etching substance is brought into contact with the semiconductor layer is r. ₁ The change in layer thickness of the semiconductor layer when only the crystal growth raw material is brought into contact with the semiconductor layer is r ₂ When the absolute value of these layer thickness change rates is | R | <| r ₂ | <| R ₁ |, And | R | is 0.1 nm / sec or less.Is provided.
  With the above configuration, the supply balance of the etching substance and the crystal growth raw material becomes appropriate, the contaminants adhering to the surface of the semiconductor layer are efficiently removed, and the reattachment of the detached contaminants to the semiconductor layer is suppressed. Can do.
[0013]
When the etching substance acts on the surface of the semiconductor layer, the contaminant attached to the surface of the semiconductor layer is detached from the surface. However, some of the desorbed contaminants may adhere to the semiconductor layer surface again. In order to increase the cleanliness of the semiconductor layer, it is necessary to sufficiently suppress the reattachment of such contaminants. Therefore, in the present invention, the etching substance and the crystal growth raw material are brought into contact with the surface of the semiconductor layer, and the contaminant is efficiently removed by etching while suppressing reattachment. Although the reason why the re-adhesion of the contaminants can be prevented by such a method is not necessarily clear, after the contaminants are desorbed from the surface of the semiconductor layer, the sites occupied by the contaminants can be quickly removed by the crystal growth raw material. Presumed to be due to being occupied.
[0014]
In the cleaning treatment method of the present invention, the first gas and the second gas can be intermittently supplied. By doing so, contamination on the surface of the semiconductor layer can be more efficiently removed.
[0015]
In the cleaning method of the present invention, the semiconductor layer may have a thickness difference of 100 nm or less before and after performing the cleaning process. By doing so, a sufficiently high cleanliness can be realized.
[0016]
In the cleaning method of the present invention, the thickness of the semiconductor layer may not be substantially reduced when the cleaning process is performed. Here, “substantially does not decrease” means that the layer thickness of the semiconductor layer does not decrease at all, or even if there is a slight decrease in the layer thickness, the layer thickness change rate is 0.1 nm / sec or less. Say. By configuring so that the thickness of the semiconductor layer does not substantially decrease, a sufficiently high cleanliness can be realized with respect to the surface of the semiconductor layer.
[0017]
As described above, sufficiently high cleanliness can be realized by controlling the change in the thickness of the semiconductor layer to be cleaned. The reason for this is not necessarily clear, but it is assumed that after the contaminants are detached from the surface of the semiconductor layer, the sites previously occupied by the contaminants are surely occupied by the crystal growth raw material.
Such a change in the thickness of the semiconductor layer can be controlled, for example, by adjusting the quantity ratio of the etching substance and the crystal growth raw material. For example, by appropriately adjusting the quantity ratio of the etching gas and the raw material gas and supplying the gas to the surface of the semiconductor layer, the semiconductor layer to be cleaned is not substantially etched, and a new layer is formed on the semiconductor layer. The semiconductor layer can be prevented from growing substantially.
If the balance between the etching substance and the crystal growth raw material is lost and tilted toward the etching side, the etched substance may be reattached and sufficient cleanliness may not be obtained. On the other hand, when the film is inclined toward the film formation, a new semiconductor layer is stacked without sufficiently removing contaminants, and sufficient cleanliness cannot be obtained.
[0020]
In the cleaning treatment method of the present invention, it may be configured such that R <0. By doing so, a sufficiently high cleanliness can be realized on the surface of the semiconductor layer.
[0021]
In the cleaning method of the present invention, a configuration in which | R | is 0.1 nm / sec or less can be employed. By doing this, the supply balance of the etching substance and the crystal growth raw material becomes more appropriate, and the contaminants adhering to the surface of the semiconductor layer are efficiently removed, and the reattachment of the detached contaminants to the semiconductor layer is suppressed. can do. In addition, the device structure can be easily designed.
[0022]
In the cleaning treatment method of the present invention, the crystal growth raw material may include an organic metal.
[0023]
In the cleaning method of the present invention, the etching substance may be a halogen element or a compound thereof.
[0024]
In the cleaning treatment method of the present invention, the semiconductor layer may be composed of a compound semiconductor.
[0025]
In the cleaning treatment method of the present invention, the semiconductor layer may be made of a III-V group compound semiconductor.
[0026]
When the crystal growth raw material is a compound containing a group III element constituting the semiconductor layer, the vacancies in the semiconductor layer formed by the etching substance can be occupied by the constituent elements of the semiconductor layer, and the surface It is possible to prevent the formation of a metamorphic layer.
[0027]
The group III element constituting the semiconductor layer may be one kind. By doing so, it is possible to suppress the formation of the metamorphic layer and the composition change during the cleaning process of the surface of the semiconductor layer.
[0028]
In the cleaning treatment method of the present invention, the group III element constituting the semiconductor layer may be indium (In). In the vapor phase growth of InP, a growth temperature of 600 ° C. to 650 ° C. is usually employed. This is to prevent the diffusion of phosphorus, which is a group V element, and to prevent diffusion of impurities such as zinc intentionally added to give conductivity to the crystal, and to obtain an impurity profile as designed. belongs to. However, when such a relatively low growth temperature is employed, it becomes more difficult to clean the growth interface. In general, in the cleaning treatment of the growth interface with an etching gas, the removal efficiency increases as the atmospheric temperature is increased. However, in the InP semiconductor system, since there is an upper limit on the cleaning temperature, contamination at the growth interface is difficult to remove, and silicon contamination is a serious problem. According to the present invention, the problem of contamination at the growth interface can be effectively solved.
[0029]
Furthermore, according to the present invention, the following method for manufacturing a semiconductor device is provided. Here, the semiconductor device includes an optical element such as a light emitting element, a light receiving element, and an optical modulator, and an electronic element such as a field effect transistor and a bipolar transistor.
[0030]
  According to the present invention, the step of forming the first semiconductor layer on the semiconductor substrate, the step of cleaning the surface of the first semiconductor layer, and the second semiconductor layer on the first semiconductor layer The step of cleaning the surface of the first semiconductor layer includes an etching substance having an etching action on the semiconductor layer, and a crystal growth raw material. The sign of the layer thickness change rate of the semiconductor layer is defined as positive when the layer thickness increases and negative when the layer thickness decreases, and the cleaning process is performed when the cleaning process is performed. R is the thickness change rate of the semiconductor layer, and r is the thickness change rate of the semiconductor layer when only the etching substance is brought into contact with the semiconductor layer.₁The change in layer thickness of the semiconductor layer when only the crystal growth raw material is brought into contact with the semiconductor layer is r₂When the absolute value of these layer thickness change rates is | R | <| r₂| <| R₁|The residual Si concentration at the growth interface of the semiconductor layer is the surface density of 2.5 × 10 ¹¹ atoms / cm ² IsA method for manufacturing a semiconductor device is provided. With the above configuration, the supply balance of the etching substance and the crystal growth raw material becomes more appropriate, the contaminants attached to the surface of the semiconductor layer are efficiently removed, and the reattachment of the detached contaminants to the semiconductor layer is suppressed. be able to.
[0031]
  Also according to the invention,Forming a first semiconductor layer on the semiconductor substrate; cleaning a surface of the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer. And the step of cleaning the surface of the first semiconductor layer includes a step of bringing an etching substance having an etching action on the semiconductor layer and a crystal growth raw material into contact with the surface of the semiconductor layer. The sign of the layer thickness change rate of the semiconductor layer is defined as positive when the layer thickness increases and negative when the layer thickness decreases, and the layer thickness change of the semiconductor layer when the cleaning process is performed R is the rate, and r is the thickness change rate of the semiconductor layer when only the etching substance is brought into contact with the semiconductor layer. ₁ The change in layer thickness of the semiconductor layer when only the crystal growth raw material is brought into contact with the semiconductor layer is r ₂ When the absolute value of these layer thickness change rates is | R | <| r ₂ | <| R ₁ |, And | R | is 0.1 nm / sec or less.Is provided. With the above configuration, the supply balance of the etching substance and the crystal growth raw material becomes more appropriate, the contaminants attached to the surface of the semiconductor layer are efficiently removed, and the reattachment of the detached contaminants to the semiconductor layer is suppressed. be able to.
[0033]
When the etching substance acts on the surface of the semiconductor layer, the contaminant attached to the surface of the semiconductor layer is detached from the surface. However, some of the desorbed contaminants may adhere to the semiconductor layer surface again. In order to increase the cleanliness of the semiconductor layer, it is necessary to sufficiently suppress the reattachment of such contaminants. Therefore, in the present invention, the etching substance and the crystal growth raw material are brought into contact with the surface of the semiconductor layer, and the contaminant is efficiently removed by etching while suppressing reattachment. Although the reason why the re-adhesion of the contaminants can be prevented by such a method is not necessarily clear, after the contaminants are desorbed from the surface of the semiconductor layer, the sites occupied by the contaminants can be quickly removed by the crystal growth raw material. Presumed to be due to being occupied.
[0034]
In the method for manufacturing a semiconductor device of the present invention, the first gas and the second gas can be intermittently supplied. By doing so, contamination on the surface of the semiconductor layer can be more efficiently removed.
[0035]
In the method for manufacturing a semiconductor device of the present invention, the difference in layer thickness of the first semiconductor layer before and after performing the step of cleaning the surface of the first semiconductor layer is 100 nm or less. Can do. By doing so, a sufficiently high cleanliness can be realized.
[0036]
In the method for manufacturing a semiconductor device of the present invention, when the step of cleaning the surface of the first semiconductor layer is performed, the layer thickness of the first semiconductor layer is not substantially reduced. can do. Here, “substantially does not decrease” means that the layer thickness change rate of the first semiconductor layer does not decrease at all or the layer thickness change rate is 0.1 nm / sec or less even if there is a slight decrease in the layer thickness. Say something. By configuring so that the layer thickness of the first semiconductor layer does not substantially decrease, a sufficiently high cleanliness can be realized on the surface of the semiconductor layer.
[0037]
As described above, sufficiently high cleanliness can be realized by controlling the change in the thickness of the first semiconductor layer to be cleaned. The reason for this is not necessarily clear, but it is assumed that after the contaminants are detached from the surface of the semiconductor layer, the sites previously occupied by the contaminants are surely occupied by the crystal growth raw material. Such a change in the thickness of the first semiconductor layer can be controlled, for example, by adjusting the amount ratio of the etching substance and the crystal growth raw material. For example, by appropriately adjusting the quantity ratio of the etching gas and the raw material gas and supplying the gas to the surface of the semiconductor layer, the semiconductor layer to be cleaned is not substantially etched, and a new layer is formed on the semiconductor layer. The semiconductor layer can be prevented from growing substantially.
If the balance between the etching substance and the crystal growth raw material is lost and tilted toward the etching side, the etched substance may be reattached and sufficient cleanliness may not be obtained. On the other hand, when the film is inclined toward the film formation, a new semiconductor layer is stacked without sufficiently removing contaminants, and sufficient cleanliness cannot be obtained.
[0039]
In the method for manufacturing a semiconductor device of the present invention, a configuration in which R <0 can be adopted. By doing so, a sufficiently high cleanliness can be realized on the surface of the semiconductor layer.
[0040]
In the method for manufacturing a semiconductor device of the present invention, | R | may be 0.1 nm / sec or less. By doing this, the supply balance of the etching substance and the crystal growth raw material becomes more appropriate, and the contaminants adhering to the surface of the semiconductor layer are efficiently removed, and the reattachment of the detached contaminants to the semiconductor layer is suppressed. can do.
[0041]
In the method for manufacturing a semiconductor device of the present invention, the crystal growth raw material may include an organic metal.
[0042]
In the method for manufacturing a semiconductor device of the present invention, the etching substance may be a halogen element or a compound thereof.
[0043]
In the method for manufacturing a semiconductor device of the present invention, the first semiconductor layer may be made of a compound semiconductor.
[0044]
In the method for manufacturing a semiconductor device of the present invention, the first semiconductor layer may be made of a III-V group compound semiconductor. At this time, the crystal growth raw material may be a compound containing a group III element constituting the first semiconductor layer. Moreover, the group III element which comprises a 1st semiconductor layer shall consist of one type. By doing so, it is possible to suppress the formation of the metamorphic layer and the composition change during the cleaning process of the surface of the semiconductor layer.
[0045]
In the semiconductor device manufacturing method of the present invention, the group III element constituting the first semiconductor layer may be indium (In). In the vapor phase growth of InP, a growth temperature of 600 ° C. to 650 ° C. is usually employed. This is for preventing phosphorus, which is a group V element, from desorbing and preventing diffusion of impurity zinc, and obtaining an impurity profile as designed. However, when such a relatively low growth temperature is employed, it becomes more difficult to clean the growth interface. In general, in the cleaning treatment of the growth interface with an etching gas, the removal efficiency increases as the atmospheric temperature is increased. However, in the InP semiconductor system, since there is an upper limit on the cleaning temperature, contamination at the growth interface is difficult to remove, and silicon contamination is a serious problem. According to the present invention, the problem of contamination at the growth interface can be effectively solved.
[0046]
In the method for manufacturing a semiconductor device of the present invention, the first semiconductor layer and the second semiconductor layer can be formed by vapor phase growth.
[0047]
In the method for manufacturing a semiconductor device of the present invention, after the step of forming the first semiconductor layer, a mask is formed on the first semiconductor layer, and then the mask is removed, and then the first semiconductor It can be set as the structure which implements the said process of carrying out the cleaning process of the surface of a layer. When these steps are performed, the surface of the first semiconductor layer becomes a regrowth surface, and many impurities are likely to adhere to the surface due to contamination by the atmosphere, remaining mask material, and the like. According to the present invention, such impurities can be efficiently removed.
[0048]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor layer to be cleaned in the present invention is
III-V group compound semiconductors such as InP, such as InGaAs, InGaAsP, AlGaInAs, InAsP, GaAs, such as AlGaAs, InGaP, AlGaInP, GaAsSb, InGaAsN, and GaN, such as GaN, AlGaN, GaInN, AlGaInN, and BAlGaInN;
II-VI group compound semiconductors such as ZnSe, ZnTe, MgZnSSe, MgZnCdSe, MgZnSeTe, ZnSeTe, ZnO, MgZnO, MgCdZnO;
In addition to a compound semiconductor such as silicon, a semiconductor such as silicon and a compound thereof, germanium and a compound thereof, and the like.
The semiconductor layer to be cleaned in the present invention may have a ternary system or a quaternary or higher composition.
[0049]
Of these, when the present invention is applied to the surface of the III-V compound semiconductor layer by removing the contaminants adhering to the element fabrication process or exposure to the atmosphere, a remarkable effect is obtained. In particular, the present invention is particularly effective when applied to the removal of silicon, which has been difficult to remove sufficiently by the prior art.
[0050]
Examples of the etching substance in the present invention include a halogen element or a compound thereof which forms a volatile compound by combining with a majority of elements. Of these, a raw material containing chlorine (Cl) is preferably used because it is easy to handle.
[0051]
As an etching substance in the present invention, t-butyl chloride ((CH₃)₃CCl: TBCl), bisdimethylaminophosphine chloride ([(CH₃)₂] N₂PCl: BDMAPCl), hydrogen chloride (HCl), methyl chloride (CH₃Cl), carbon tetrachloride (CCl₄), Bisdimethylaminoarsine chloride ([(CH₃)₂] N₂AsCl), phosphorus trichloride (PCl)₃), Arsenic trichloride AsCl₃, Chlorine (Cl₂And similar Br-based materials, I-based materials, and F-based materials. Among these, when t-butyl chloride is used, etching can be effectively performed while maintaining the stoichiometry of the semiconductor layer to be cleaned relatively well. For example, when the semiconductor layer is a group III-V semiconductor and the etching gas contains a specific group V element, the semiconductor layer to be cleaned is a different type of group V element from that contained in the etching gas. However, since t-butyl chloride does not contain a group V element, a modified layer may be formed during the cleaning process. Not preferred. In addition, when bisdimethylaminophosphine chloride is used, the temperature dependency of the etching ability is relatively suppressed, so that a stable cleaning process can be performed.
[0052]
In addition, when the group III element constituting the semiconductor layer to be cleaned is composed of one kind, it is preferable that the formation of the metamorphic layer and the composition change are difficult to occur during the surface treatment of the present invention. More significant effect when the constituent group III element is indium (In), such as InP, InAs, InN, InSb, etc., or gallium (Ga), such as GaAs, GaP, GaN, GaSb, etc. Appears.
[0053]
According to the present invention, when a semiconductor layer is grown using a vapor phase growth apparatus, a remarkable effect is obtained, and a metal organic vapor phase epitaxy (MOCVD) method using an organic metal as a growth material. In this case, a more remarkable effect appears. In this case, the hydrogen compound and the organometallic gas which are the raw materials for crystal growth are not particularly limited, and a hydrogen compound and an organometallic compound gas necessary for obtaining a desired compound semiconductor may be used.
[0054]
【Example】
In order to clarify the above and other objects, features and advantages of the present invention, examples of the present invention will be described in detail below with reference to the accompanying drawings. It is not limited to examples.
[0055]
First embodiment
In the present embodiment, residual impurity removal at the growth interface in the case where InP is regrown on InP by using the MOVPE method will be described. As a raw material having an etching action, t-butyl chloride ((CH₃)₃CCl: TBCl) is used, and as crystal growth materials, trimethylindium (TMIn) and phosphine (PH₃) Was used. As shown in FIG. 1, an undoped InP layer 103 is grown as a first growth layer by 1.0 μm on a Sn-doped {001} InP substrate 101 by a reduced pressure (60 Torr) MOVPE method. Exposure to the atmosphere for hours. Wet processing is not performed. Thereafter, this wafer was again put into the MOVPE furnace, and an undoped InP layer 105 of 0.5 μm was grown and regrown as the second growth layer.
[0056]
TBCl, TMIn, and PH in the MOVPE furnace at the second growth interface 104 immediately before the second growth start.₃Was supplied to the surface of the wafer for 10 minutes to perform surface cleaning treatment (Sample A). The amount of TBCl supplied during the surface cleaning treatment is 19.4 μmol / min, which corresponds to an InP etching rate of 20.5 nm / min, and the amount of TMIn supplied is 15.08 μmol / min, PH₃Is 2.68 mmol / min, which corresponds to an InP growth rate of 20.5 nm / min. Therefore, the etching rate of InP by TBCl and TMIn and PH₃The growth rate of InP is equal, and there is no change in the thickness of the undoped InP layer 103 grown for the first time during this surface cleaning process. The substrate temperature during the surface cleaning treatment was 625 ° C.
[0057]
For comparison, TBCl, TMIn, and PH at the second growth interface 104 immediately before the start of the second growth of the InP layer are performed.₃A sample (sample B) in which the growth of the second undoped InP layer 105 was started without performing the surface cleaning treatment by the above was also produced.
[0058]
The residual impurity concentration at the regrowth interface of the two samples A and B was analyzed in the depth direction while sputtering the undoped InP layer 105 using secondary ion mass spectrometry (SIMS).
[0059]
TBCl, TMIn, and PH at the second growth interface 104₃In the sample B that was not subjected to the surface cleaning treatment by C, C, O, and Si were detected as residual impurities at the second growth interface 104, and the concentrations thereof were respectively expressed as areal densities C: 6.4 × 10¹⁰atoms / cm², O: 6.9 × 10¹¹atoms / cm², Si: 1.2 × 10¹²atoms / cm²It was considerable. On the other hand, at the second growth interface 104, TBCl (19.4 μmol / min), TMIn (15.08 μmol / min), and PH₃In sample A subjected to the surface cleaning treatment with (2.68 mmol / min), residual impurities such as C, O, and Si at the second growth interface 104 were all below the detection limit. Here, the lower limit of detection in this measurement is C: 6 × 10, respectively.⁷atoms / cm², O: 6 × 10⁸atoms / cm², Si: 6 × 10⁷atoms / cm²  It was considerable. Further, Cl introduced as an etching gas was not detected at all. Here, the lower limit of detection of Cl is 3 × 10.⁷atoms / cm²It was about.
[0060]
In this embodiment, the cleaning process for the second growth interface 104 has been described as an example. However, the present invention can also be applied to the cleaning process for the first growth interface 102.
[0061]
Second embodiment
In this embodiment, the present invention is applied to an InP semiconductor laser element. In this embodiment, after forming a semiconductor multilayer film with the active layer as the uppermost layer, a mask covering a part of the surface of the active layer is formed, and both sides of the mask are removed by etching to provide a mesa stripe. . Then, after removing the mask by wet etching, the cleaning process according to the present invention is performed on the surface of the active layer. In addition, after the mesa stripe is provided, the cleaning treatment according to the present invention is also performed on the surface thereof. Hereinafter, the present embodiment will be described with reference to FIG.
[0062]
First, a double heterostructure having an InGaAsP / InGaAsP quantum well 307 as an active layer is formed on an n-type InP substrate 301 by a normal crystal growth process, and SiO 2₂As a mask, a mesa stripe 310 having a width of about 2 μm and a width of about 2 μm was formed by dry etching. Thereafter, the wafer is introduced into a MOVPE furnace, and the first regrowth interface 308 is subjected to the surface cleaning treatment of the present invention under the same conditions as in the first embodiment, and then the p-type InP layer 302, the n-type InP. A layer 303 and a p-type InP layer 304 were sequentially stacked to form a current block structure.
[0063]
Next, this wafer is taken out of the MOVPE furnace and SiO 2 is removed.₂After removing the mask by a normal wet etching process, it was again put into the MOVPE furnace, and the above surface cleaning treatment of the present invention was performed again on the second regrowth interface 309 under the same conditions as in the first embodiment. Thereafter, a p-type InP clad layer 305 and a p-InGaAs contact layer 306 were formed. Thereafter, a normal electrode formation process and an element separation process were performed to complete an embedded laser element.
[0064]
When the voltage-current characteristics and current-light output characteristics of this element were measured, the slope efficiency was significantly improved and the power at the time of high light output compared to the conventional element not using the surface cleaning treatment of the present invention- It was confirmed that the light output conversion characteristics were greatly improved and the driving voltage required to obtain the same light output was greatly reduced. This is because the surface cleaning treatment of the present invention reduces n-type residual impurities such as Si at the first regrowth interface 308 before forming the current blocking layer, thereby reducing leakage current and before forming the cladding and contact layers. This is considered to be due to the effect that the current barrier is removed and the driving voltage is lowered due to the decrease in n-type residual impurities such as Si at the second regrowth interface 309.
In the present embodiment, both the first regrowth interface 308 and the second regrowth interface 309 are subjected to surface cleaning treatment, but only one of them, for example, the second regrowth interface 309 is cleaned. Processing may be performed.
[0065]
Third embodiment
In this example, a semiconductor multilayer structure is produced in the same manner as in the first example except that the conditions for the cleaning treatment are changed, and the residual impurity density of C, O, Si, etc. at the second growth interface 104 is set. It was measured. The conditions for the cleaning treatment are shown in Table 1. Each item in “Processing conditions” in Table 1 will be described below.
[0066]
(I) Gas type
t-Butyl chloride ((CH₃)₃CCl: TBCl), bisdimethylaminophosphine chloride ([(CH₃)₂] N₂PCl: BDMAPCl) was used.
(Ii) Gas flow rate
The amount of gas supplied into the MOVPE furnace is shown.
(Iii) Etching rate
The etching rate when only the etching gas is supplied at the flow rate shown in the table is shown. This value is obtained by a preliminary experiment.
(Iv) Growth rate
The growth rate when only the growth gas is supplied at the flow rate shown in the table is shown. This value is obtained by a preliminary experiment.
(V) Film thickness change index
The case where the layer thickness increases was defined as positive, the case where the layer thickness decreased was defined as negative, and the sum of the growth rate and the etching rate was defined as the “film thickness change index”. It becomes an index of the layer thickness change before and after the cleaning process.
(Vi) Gas supply method
The continuous method is a method in which an etching gas and a growth gas are continuously supplied for a predetermined time. The intermittent method is a method in which an etching gas and a growth gas are intermittently supplied for a fixed time, and the gas supply time and the gas supply time are alternately repeated.
(Vii) Wet etching
When an etching process using an etching solution was performed before the cleaning process of the undoped InP layer 103, the wet etching was indicated as “present”.
[0067]
(Samples 1 to 4)
As a raw material having an etching action, t-butyl chloride ((CH₃)₃CCl: TBCl) or bisdimethylaminophosphine chloride ([(CH₃)₂] N₂PCl: BDMAPCl) is used, and the raw materials for crystal growth are trimethylindium (TMIn) and phosphine (PH₃) Was used. As shown in FIG. 1, an undoped InP layer 103 is grown as a first growth layer by 1.0 μm on a Sn-doped {001} InP substrate 101 by a reduced pressure (60 Torr) MOVPE method. Exposure to the atmosphere for hours. Thereafter, the surface of the undoped InP layer 103 was wet-etched with a sulfuric acid-containing liquid, and then rinsed with pure water.
[0068]
Thereafter, this wafer was again put into the MOVPE furnace, and after cleaning treatment was performed under the conditions shown in Table 1, an undoped InP layer 105 of 0.5 μm was regrown as a second growth layer.
[0069]
The cleaning process for each sample is as follows.
[0070]
Sample 1 was not cleaned.
[0071]
In sample 2, TBCl, TMIn, and PH in the MOVPE furnace at the second growth interface 104 immediately before the start of the second growth.₃Was supplied to the surface of the wafer for 10 minutes to perform surface cleaning treatment. The supply amount of each gas is as shown in Table 1. The gas supply was a continuous system. The substrate temperature during the cleaning process was 625 ° C. No change in layer thickness of the undoped InP layer 103 was observed before and after the treatment.
[0072]
In Sample 3, the following treatment was performed in the MOVPE furnace at the second growth interface 104 immediately before the start of the second growth. (I) TBCl, TMIn and PH₃Is supplied to the surface of the wafer for 1 minute, and then (ii) PH for 15 seconds.₃The step of supplying a large amount of and purging was repeated 20 times. The supply amount of each gas is as shown in Table 1. The substrate temperature during the cleaning process was 625 ° C. The thickness change of the undoped InP layer 103 before and after the treatment was 100 nm or less.
[0073]
In sample 4, bisdimethylaminophosphine chloride (BDMACCl), TMIn, and PH in the MOVPE furnace at the second growth interface 104 immediately before the start of the second growth.₃Was supplied to the surface of the wafer for 10 minutes to perform surface cleaning treatment. The supply amount of each gas is as shown in Table 1. The gas supply was a continuous system. The substrate temperature during the cleaning process was 625 ° C. No change in layer thickness of the undoped InP layer 103 was observed before and after the treatment.
[0074]
(Samples 5-6)
As a raw material having an etching action, t-butyl chloride ((CH₃)₃CCl: TBCl) or bisdimethylaminophosphine chloride ([(CH₃)₂] N₂PCl: BDMAPCl) is used, and the raw materials for crystal growth are trimethylindium (TMIn) and phosphine (PH₃) Was used. As shown in FIG. 1, an undoped InP layer 103 is grown as a first growth layer by 1.0 μm on a Sn-doped {001} InP substrate 101 by a reduced pressure (60 Torr) MOVPE method, and then the wafer is once taken out from the MOVPE furnace. Exposure to the atmosphere for hours. Thereafter, this wafer was again put into the MOVPE furnace without performing wet etching, and a cleaning process was performed under the conditions shown in Table 1. Thereafter, an undoped InP layer 105 of 0.5 μm was regrown as a second growth layer.
[0075]
The cleaning process for each sample is as follows.
[0076]
Sample 5 was not cleaned.
[0077]
In sample 6, TBCl, TMIn, and PH in the MOVPE furnace at the second growth interface 104 immediately before the start of the second growth.₃Was supplied to the surface of the wafer for 10 minutes to perform surface cleaning treatment. The supply amount of each gas is as shown in Table 1. The gas supply was a continuous system. The substrate temperature during the cleaning process was 625 ° C. No change in layer thickness of the undoped InP layer 103 was observed before and after the treatment.
[0078]
The change in the layer thickness during the cleaning treatment of each sample was 100 nm or less.
About each said sample, it carried out similarly to the 1st Example, and measured the residual impurity cotton density by SIMS. The results are shown in Table 1 and FIGS. 2 to 7 correspond to the measurement results of samples 1 to 6, respectively. In Table 1, “nd” means that detection was not possible. Sample No. In No. 5, although the concentration corresponding to the corresponding peak was calculated, it was difficult to distinguish it from noise, so a numerical value was shown as a reference value. 2 to 7, the impurity concentration (unit: atoms / cm³The numerical value (vertical axis) calculated as) is converted as the surface density, and this value is shown in the figure corresponding to the corresponding peak (unit: atoms / cm).²).
[0079]
From the results obtained, the following became clear. That is, the residual impurity surface density is significantly reduced by adjusting the supply ratio of the etching gas and the growth gas so that the film thickness change index is 6 nm or less (0.1 nm / sec or less). In particular, Si is effectively removed. Moreover, the intermittent method is effective as the gas supply method. The residual impurity density is significantly reduced by intermittent supply. If the wet etching before the cleaning treatment is not performed, the residual impurity density is small.
[Table 1]

[0080]
Fourth embodiment
In this example, an experiment similar to that of the third example was performed by changing the gas flow rate ratio.
[0081]
In the sample structure similar to that of FIG. 1, the surface cleaning treatment condition at the second growth interface 104 is 19.4 μmol / min (corresponding to 20.5 nm / min corresponding to the InP etching rate), which is the etching gas TBCl. ), PH₃The supply amount was kept constant at 2.68 mmol / min, the supply amount of TMIn was changed between 0 to 30 μmol / min, surface cleaning treatment was performed for 10 minutes, and then the undoped InP layer 105 was grown. Subsequently, the residual Si concentration at the second interface was examined by SIMS analysis.
[0082]
FIG. 8 shows a change in the TMIn flow rate of the sample 2 in the third embodiment (shown as “residual Si (continuous type)” in the figure) and a change in the TMIn flow rate of the sample 3 in the third embodiment. (Represented as “residual Si (intermittent type)” in the figure).
[0083]
FIG. 9 shows the sample 4 in the third embodiment with the TMIn flow rate changed.
[0084]
In FIGS. 8 and 9, the growth rate of InP by TBCl and TMIn (that is, the rate of change in film thickness of the undoped InP layer 103 (first semiconductor layer)) is positive and the etching is negative, along with the surface density of residual Si. As shown.
[0085]
In any system, the residual Si concentration decreases with the supply amount of TMIn, and the residual Si concentration shows the minimum value near the growth rate of 0 nm / sec. When the TMIn flow rate is further increased, the residual Si concentration increases again. did. This is because when only the etching gas TBCl is supplied to the second growth interface 104, the surface residual Si is volatile chloride SiCl._xAlthough the Si—Cl bond is weaker than that of the Si—P bond, the Si—Cl bond is broken immediately and adheres to the surface. When supplied simultaneously, Si becomes SiCl._xAs soon as it desorbs from the surface, the stable group III site previously occupied by Si is filled with In, and once desorbed from the surface, it cannot be attached to the InP surface again and desorbs from the surface. Conceivable. Accordingly, the Si desorption efficiency is maximized when the InP etching rate by TBCl and the InP growth rate by TMIn are just balanced. When the growth rate of InP by TMIn exceeds the etching rate of InP by TBCl, the InP layer grows before Si is desorbed, and the surface is not cleaned. It is considered that the residual Si concentration at this point increases.
[0086]
From the results of FIGS. 8 and 9, it was found that when the layer thickness change rate is within 0.1 nm / sec, the residual Si density is significantly reduced, particularly when there is substantially no change in the layer thickness.
[0087]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to said each Example, It is clear that each Example can be suitably changed within the range of the technical idea of this invention.
[0088]
For example, in the above embodiment, TBCl, bisdimethylaminophosphine chloride ([(CH₃)₂] N₂PCl), but other Cl-based materials such as hydrogen chloride (HCl) and methyl chloride (CH₃Cl), carbon tetrachloride (CCl₄), Bisdimethylaminoarsine chloride ([(CH₃)₂] N₂AsCl), phosphorus trichloride (PCl)₃), Arsenic trichloride AsCl₃, Chlorine (Cl₂) Or similar Br-based materials, I-based materials, and F-based materials. When other raw materials are used, the decomposition efficiency and etching efficiency of the raw materials differ depending on the raw materials, but basically, as shown in the above embodiment, the etching rate of the semiconductor layer by the etching raw material and the growth rate of the semiconductor layer by the crystal growth raw material The maximum etching efficiency can be obtained by balancing the two, and the same effect can be obtained.
[0089]
In the above-described embodiment, the case where the MOVPE method is used as the crystal growth method has been described as an example. ) Method, chemical beam growth (CBE) method, or the like may be used. In the above embodiments, the InP-based material has been described. However, the present invention is not limited to this, and other III-V group compound semiconductors such as GaAs, InAs, GaP, and GaN, and II-VI group compound semiconductors. It is applicable to semiconductor materials such as
[0090]
Further, the substrate temperature is 625 ° C. in the above embodiment, but a temperature range in which normal crystal growth is possible, for example, about 400 ° C. to 700 ° C. for InP, and 400 ° C. to 800 ° C. for GaAs. It is sufficient that the etching rate of the semiconductor layer by the etching raw material and the change in the growth rate of the semiconductor layer by the crystal growth raw material due to the substrate temperature are corrected and the maximum etching efficiency can be obtained by balancing the two. effective.
[0091]
In the above embodiment, the first gas containing the etching substance having an etching action on the semiconductor layer and the second gas containing the crystal growth raw material are simultaneously supplied to the surface of the semiconductor layer, but these are alternately supplied. It is also possible to adopt a method. In this case, if the growth of the semiconductor layer proceeds excessively, it becomes difficult to achieve a sufficient cleanliness, so that the etching is performed after the growth of the thickness of about 1 to 3 atomic layers has progressed. In addition, it is desirable to quickly switch between the growth gas and the etching gas.
[0092]
【The invention's effect】
As described above, according to the present invention, the surface of a semiconductor substrate before crystal growth and re-generation can be minimized without inducing impurity diffusion and generation of crystal defects in the original semiconductor layer and minimizing shape change. Impurity contamination and physical damage on the semiconductor surface before growth can be stably removed with good reproducibility, which has a great effect on improving the performance of a semiconductor element having a growth interface.
[Brief description of the drawings]
FIG. 1 is a diagram showing a structure of a semiconductor layer manufactured in an example.
FIG. 2 is a diagram showing SIMS measurement results of residual impurity concentration in Examples.
FIG. 3 is a diagram showing SIMS measurement results of residual impurity concentration in Examples.
FIG. 4 is a diagram showing SIMS measurement results of residual impurity concentration in Examples.
FIG. 5 is a diagram showing SIMS measurement results of residual impurity concentration in Examples.
FIG. 6 is a diagram showing SIMS measurement results of residual impurity concentration in Examples.
FIG. 7 is a diagram showing SIMS measurement results of residual impurity concentration in Examples.
FIG. 8 is a graph showing the dependency of residual Si concentration on TMIn supply amount in Examples.
FIG. 9 is a graph showing the dependency of residual Si concentration on TMIn supply amount in Examples.
FIG. 10 is a view showing a buried semiconductor laser structure in a second embodiment.
[Explanation of symbols]
101 InP substrate
102 First growth interface
103 Undoped InP layer
104 Second growth interface
105 Undoped InP layer
301 n-type InP substrate
302 p-type InP layer
303 n-type InP layer
304 p-type InP layer
305 p-type InP cladding layer
306 p-InGaAs contact layer
307 InGaAsP / InGaAsP quantum well
308 First regrowth interface
309 Second regrowth interface
310 Mesa Stripe

Claims (32)

A cleaning method for removing contaminants adhering to a surface of a semiconductor layer, wherein an etching substance having an etching action on the semiconductor layer and a crystal growth raw material are simultaneously or alternately applied to the semiconductor layer. Including a cleaning process to make contact,
The sign of the thickness change rate of the semiconductor layer is defined as positive when the layer thickness increases and negative when the layer thickness decreases, and the layer thickness change rate of the semiconductor layer when the cleaning process is performed R,
R ₁ , the rate of change in thickness of the semiconductor layer when only the etching substance is brought into contact with the semiconductor layer,
The layer thickness change of the semiconductor layer when only the crystal growth raw material is brought into contact with the semiconductor layer is represented by r _2.
The absolute value of these layer thickness change rates is
_{| R | <| r 2 |} <| r 1 | der is,
A cleaning treatment method, wherein a residual Si concentration at a growth interface of the semiconductor layer is an area density of 2.5 × 10 ¹¹ atoms / cm ² or less . The cleaning method according to claim 1, wherein | R | is 0.1 nm / sec or less. A cleaning method for removing contaminants adhering to the surface of a semiconductor layer, wherein an etching substance having an etching action on the semiconductor layer and a crystal growth raw material are simultaneously or alternately applied to the semiconductor layer. Including a cleaning process to make contact,
The sign of the thickness change rate of the semiconductor layer is defined as positive when the layer thickness increases and negative when the layer thickness decreases, and the thickness change rate of the semiconductor layer when the cleaning process is performed R,
The layer thickness change rate of the semiconductor layer when only the etching substance is brought into contact with the semiconductor layer is expressed as r. ₁ ,
The thickness change of the semiconductor layer when only the crystal growth raw material is brought into contact with the semiconductor layer is expressed as r. ₂
The absolute value of these layer thickness change rates is
| R | <| r ₂ | <| R ₁ |, And | R | is 0.1 nm / sec or less. In the cleaning method according to any one of claims 1 to 3, the cleaning treatment method the difference in thickness of the semiconductor layer before and after carrying out the cleaning process, characterized in that at 100nm or less. In the cleaning method according to any one of claims 1 to 4, cleaning processing method in performing the cleaning treatment step, the layer thickness of the semiconductor layer is characterized in that so as not substantially reduced. 6. The cleaning method according to claim 1 , wherein a change in the thickness of the semiconductor layer is controlled by adjusting a quantity ratio of the etching substance and the crystal growth raw material. . In the cleaning method according to any one of claims 1 to 6, cleaning treatment method which is a R <0. In the cleaning method according to any of claims 1 to 7, cleaning treatment wherein said crystal growth material, characterized in that it comprises an element constituting the semiconductor layer. In the cleaning method according to any one of claims 1 to 8, wherein the crystal growth material is, cleaning treatment method which comprises the organometallic. In the cleaning method according to any one of claims 1 to 9, cleaning treatment wherein said etching material is characterized in that it is a halogen element or a compound thereof. In the cleaning method according to any one of claims 1 to 10, cleaning processing method characterized in that said semiconductor layer is made of a compound semiconductor. 12. The cleaning method according to claim 11 , wherein the semiconductor layer is made of a III-V group compound semiconductor. The cleaning method according to claim 12 , wherein the crystal growth raw material is a compound containing a group III element constituting the semiconductor layer. In the cleaning method according to claim 12 or 13, cleaning processing method III element constituting the semiconductor layer is characterized in that it consists of one type. In the cleaning method according to any one claims 12 to 14, cleaning treatment wherein the group III element forming the semiconductor layer is indium (an In). Forming a first semiconductor layer on top of the semiconductor substrate, cleaning the surface of the first semiconductor layer,
Forming a second semiconductor layer on the first semiconductor layer,
The step of cleaning the surface of the first semiconductor layer includes a step of bringing an etching substance having an etching action on the semiconductor layer and a crystal growth raw material into contact with the surface of the semiconductor layer,
The sign of the thickness change rate of the semiconductor layer is defined as positive when the layer thickness increases and negative when the layer thickness decreases, and the layer thickness change rate of the semiconductor layer when the cleaning process is performed R,
R ₁ , the rate of change in thickness of the semiconductor layer when only the etching substance is brought into contact with the semiconductor layer,
The layer thickness change of the semiconductor layer when only the crystal growth raw material is brought into contact with the semiconductor layer is represented by r _2.
The absolute value of these layer thickness change rates is
_{| R | <| r 2 |} <| r 1 | der is,
A method of manufacturing a semiconductor device, wherein a residual Si concentration at a growth interface of the semiconductor layer is an area density of 2.5 × 10 ¹¹ atoms / cm ² or less . 17. The method of manufacturing a semiconductor device according to claim 16, wherein | R | is 0.1 nm / sec or less. Forming a first semiconductor layer on top of the semiconductor substrate, cleaning the surface of the first semiconductor layer, and
Forming a second semiconductor layer on the first semiconductor layer,
  The step of cleaning the surface of the first semiconductor layer includes a step of bringing an etching substance having an etching action on the semiconductor layer and a crystal growth raw material into contact with the surface of the semiconductor layer,
The sign of the thickness change rate of the semiconductor layer is defined as positive when the layer thickness increases and negative when the layer thickness decreases, and the thickness change rate of the semiconductor layer when the cleaning process is performed R,
The layer thickness change rate of the semiconductor layer when only the etching substance is brought into contact with the semiconductor layer is expressed as r. ₁ ,
The thickness change of the semiconductor layer when only the crystal growth raw material is brought into contact with the semiconductor layer is expressed as r. ₂
The absolute value of these layer thickness change rates is
| R | <| r ₂ | <| R ₁ |, And | R | is 0.1 nm / sec or less. The method of manufacturing a semiconductor device according to any one claims 16 to 18, the difference of the layer thickness of the first semiconductor layer before and after carrying out said step of cleaning treatment of the surface of said first semiconductor layer, 100 nm A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to any one claims 16 to 19, in performing the step of cleaning treatment of the surface of said first semiconductor layer, said first layer thickness of the semiconductor layer is substantially A method of manufacturing a semiconductor device, characterized in that it does not decrease. The method of manufacturing a semiconductor device according to claim 19 or 20, characterized by controlling the thickness change of the first semiconductor layer by adjusting the ratio of the etch resistant material and the crystal growth material A method for manufacturing a semiconductor device. 22. The method for manufacturing a semiconductor device according to claim 16 , wherein R <0. . The method of manufacturing a semiconductor device according to any one of claims 16 to 22, wherein the crystal growth material is, the method of manufacturing a semiconductor device which comprises an element constituting the first semiconductor layer. The method of manufacturing a semiconductor device according to any one claims 16 to 23, wherein the crystal growth material is, the method of manufacturing a semiconductor device which comprises an organic metal. The method of manufacturing a semiconductor device according to any one claims 16 to 24, a method of manufacturing a semiconductor device, wherein the etching material is a halogen element or a compound thereof. The method of manufacturing a semiconductor device according to any one claims 16 to 25, a method of manufacturing a semiconductor device, characterized in that said first semiconductor layer is made of a compound semiconductor. 27. The method of manufacturing a semiconductor device according to claim 26 , wherein the first semiconductor layer is made of a III-V group compound semiconductor. 28. The method of manufacturing a semiconductor device according to claim 27 , wherein the crystal growth raw material is a compound containing a group III element constituting the semiconductor layer. 29. The method of manufacturing a semiconductor device according to claim 28 , wherein the group III element constituting the semiconductor layer is one kind. 30. The method of manufacturing a semiconductor device according to claim 29 , wherein the group III element constituting the semiconductor layer is indium (In). The method of manufacturing a semiconductor device according to any one claims 16 to 30, wherein the method of manufacturing a semiconductor device of the first semiconductor layer and the second semiconductor layer and forming by vapor phase growth. The method of manufacturing a semiconductor device according to any one claims 16 to 31, after the step of forming the first semiconductor layer, a mask is formed on the first semiconductor layer, and removing the mask followed Then, the method of cleaning the surface of the first semiconductor layer is performed. A method for manufacturing a semiconductor device, comprising:

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