JP4188965B2 - Gray binary conversion apparatus and gray binary conversion method - Google Patents

Description

The present invention relates to a gray binary conversion apparatus and a gray binary conversion method .
In recent years, A / D converters are used in various electronic devices, and an increase in the A / D conversion speed has been increasingly demanded. Parallel type and serial parallel type A / D converters advantageous for high-speed operation mainly convert a plurality of comparators for comparing an analog input signal and an analog reference voltage, and convert the output signal of the comparator into a multi-bit digital signal. It consists of an encoder. In order to increase the A / D conversion speed and improve the A / D conversion accuracy, it is necessary to increase the operation speed and the operation accuracy of the encoder.

  A parallel or series-parallel A / D converter, which is one type of A / D converter, is superior to other types of A / D converters in its A / D conversion speed. A general parallel A / D converter includes a comparator unit, a logical boundary detection unit that detects a logical boundary of an output signal of the comparator, and an encoder unit. A ROM-type circuit based on Wired OR is widely used in the encoder section.

FIG. 39 shows a parallel A / D converter that outputs a 5-bit digital output signal as a first conventional example of a parallel A / D converter.
Thirty-two resistors R are connected in series between the high potential side reference voltage VRH and the low potential side reference voltage VRL. In the resistor R, the resistance values of the resistors located at both ends are set to ½ of the resistance values of the other resistors.

  The resistors R are connected to one input terminals of 31 comparators CM1 to CM31, respectively. Therefore, the reference voltages VR1 to VR31 obtained by dividing the reference voltages VRH and VRL by the resistor R are input to the comparators CM1 to CM31, respectively.

  An analog input signal Ain is input to the other input terminals of the comparators CM1 to CM31. Each of the comparators CM1 to CM31 compares the reference voltages VR1 to VR31 with the analog input signal Ain based on a control signal output from a control circuit (not shown).

  When the potential of the analog input signal Ain is lower than the reference voltages VR1 to VR31, the comparators CM1 to CM31 output H level output signals S1 to S31 and L level output signals and bars S1 to S31.

When the potential of the analog input signal Ain is higher than the reference voltages VR1 to VR31, the L level output signals S1 to S31 and the H level output signals S1 to S31 are output.
Therefore, for example, when the potential of the analog input signal Ain is higher than the reference voltage VR4 and lower than the reference voltage VR5, the comparators CM1 to CM4 have the output signals S1 to S4 at the L level and the output signals / bars S1 to S4 at the H level. Output thermometer code. The comparators CM5 to CM31 output thermometer codes in which the output signals S5 to S31 are H level and the output signals and bars S5 to S31 are L level. The comparator unit 1 is constituted by the comparators CM1 to CM31 and the resistor R.

The output signals S1, bars S1 to S31, and bar S31 of the comparators CM1 to CM31 are input to 32 NOR circuits DE0 to DE31 that operate as address decoders.
That is, the output signals S1 to S31 of the comparators CM1 to CM31 are input to one input terminal of the NOR circuits DE1 to DE31, and the output signals of the comparators CM1 to CM31 and the bars S1 to S31 are output from the NOR circuits DE0 to DE30. Input to the other input terminal. One input terminal of the NOR circuits DE0 and DE31 is connected to the ground GND.

  With such a configuration, each of the NOR circuits DE0 to DE31 outputs an H level signal when both of the input signals are at the L level, and the NOR circuit that outputs the H level signal depends on the operation of the comparators CM1 to CM31. Thus, the logical boundary detection unit 2 is configured.

  The output signals of the NOR circuits DE0 to DE31 are output to the word lines WL0 to WL31 of the encoding unit 3a composed of ROM. The encoding unit 3a is provided with five bit lines BL0 to BL4 corresponding to the 5-bit digital output signals B0 to B4.

  ROM cells 4 for outputting output signals B0 to B4 based on binary codes are connected to predetermined positions between the word lines WL0 to WL31 and the bit lines BL0 to BL4, respectively. As shown in FIG. 40, the ROM cell 4 is composed of an N-channel MOS transistor, the gate of which is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the ground GND. The

  The bit lines BL0 to BL4 are connected to the power source VDD via switch circuits SW0 to SW4, respectively. When the switch circuits SW0 to SW4 are closed, the bit lines BL0 to BL4 are precharged. Switch circuits SW0 to SW4 are formed of P channel MOS transistors.

  Then, when any of the word lines becomes H level after the switch circuits SW0 to SW4 are opened, the ROM cell 4 connected to the word line is turned on, and the bit line connected to the ROM cell 4 is turned on. L level.

  Therefore, for example, when the word line WL0 becomes H level, the digital output signals B0 to B4 become “00000”, and when the word line WL2 becomes H level, the digital output signals B0 to B4 become “01000”.

  In the A / D converter as described above, a ROM-type circuit that requires a precharge operation is used for the encoding unit 3a, but the operation speed of the comparator unit 1 is slower than the operation speed of the encoding unit 3a. Therefore, since it is not the encoding unit 3a but the comparator unit 1 that determines the conversion speed, such an encoding unit 3a is employed.

In such an A / D converter, when the output signal of the comparator unit 1 is normal, a thermometer code having only one logical boundary is output or all have the same logic.
However, a bubble error may occur in the thermometer code. The most probabilistic bubble error is one in which one output logic is inverted as "..11101000 .." in the output signals S1 to S31 of the comparators CM1 to CM31. When such a bubble error is input to the NOR circuits DE0 to DE31, the two word lines simultaneously become H level, and normal output signals B0 to B4 are not output.

  In particular, in the encoding unit 3a configured to output the binary code output signals B0 to B4, a large error may occur in the output signals B0 to B4 due to the bubble error. That is, when the word lines WL14 and WL16 shown in FIG. 41 simultaneously become H level due to the bubble error, the output signals B0 to B4 are all 0, and only the word line WL14 becomes H level or the word line WL15. A large error occurs as compared with the output signals B0 to B4 when only the signal becomes H level.

  In order to solve such a problem, an A / D converter in which the logical boundary detection unit 2 is configured as shown in FIG. 42 has been proposed. In this A / D converter, if the NOR circuits DE0 to DE31 constituting the logic boundary detection unit 2 have a three-input configuration and the nth NOR circuit is a NOR circuit DEn, the NOR circuit DEn has an output signal Sn of the comparator CMn. The output signals of the higher-order comparators CM (n + 1) and CM (n + 2) and the bars S (n + 1) and S (n + 2) are input.

  With such a configuration, when a bubble error occurs in which one different logic is sandwiched between thermometer codes as described above, it is possible to prevent the bubble error portion from being determined as a logical boundary. Only the word line WL becomes H level, and normal values or values close to normal values are output as the output signals B0 to B4.

  However, even if the NOR circuits DE0 to DE31 have a three-input configuration as described above, in the output signal bars S1 to S31 of the comparators CM1 to CM31, for example, “•• 111001000 ••” or “•• 111011000 ••” In addition, when a bubble error occurs in which the output logic is inverted by two or more, the two word lines separating the two word lines may be simultaneously at the H level.

  For example, when the word lines WL14 and WL17 shown in FIG. 41 are simultaneously at the H level, the output signals B0 to B4 are all 0, and the output signals B0 to B4 when any of the word lines WL14 to WL17 is at the H level. A large error occurs.

  In order to solve such a problem, as shown in FIG. 43, an A / D converter including an encoding unit 3b that can output a gray code (alternate binary signal) instead of a binary code has been proposed. Yes.

  The encoding unit 3b is different from the encoding unit 3a that outputs binary code output signals B0 to B4 in the position of the ROM cell 4, and any one of the word lines WL is set to the H level, so that the 5-bit Gray code output signals G0 to G4 are output. When the thermometer code is recognized as a decimal number (Decimal), the binary code (Binary) output signals B0 to B4 corresponding to the thermometer code and the gray code (Gray) output signals G0 to G4 are shown in FIG. 47. The output signals G0 to G4 are output to the next stage circuit through a conversion circuit that converts the gray code into a binary code.

  In the A / D converter as described above, even if a bubble error is output from the comparator unit 1 and the logical boundary detection unit 2 causes the word lines WL14 and WL17 to simultaneously become H level in FIG. Output signals G0 to G4 are the same as when only the word line WL14 is at the H level. Therefore, even if the most probable value is when the word line WL15 or the word line WL16 is at the H level, an output signal in which a large error occurs like the binary code encoder 3a is not output.

  As described above, in the A / D converter including the logic boundary detection unit 2 including the three-input NOR circuit and the encoding unit 3b that outputs the gray code output signals G0 to G4, the output signal of the comparator unit 1 is Even if a bubble error as described above occurs, it is possible to suppress an error occurring in the digital output signal as shown in FIGS.

  In FIG. 50, a bubble error “· 11101000 ··” of type b1 in which the output logic of the thermometer code is inverted by one is input to the logic boundary detection unit 2 composed of a two-input NOR circuit. The operation when the output signal of the boundary detection unit 2a is converted into a gray code by the encoding unit 3b is shown, the horizontal axis is a decimal value of a normal thermometer code, and the vertical axis is the gray value output from the encoding unit 3b. This is a value obtained by replacing the code output signal with a decimal number.

  In FIG. 51, a b2H type bubble error “· 111001000 ··” in which the output logic of the thermometer code is inverted by two is input to the logic boundary detection unit 2 composed of a three-input NOR circuit. The operation when the output signal of the boundary detection unit 2 is converted into a gray code by the encoding unit 3b is shown, the horizontal axis is a decimal value of a normal thermometer code, and the vertical axis is the gray output from the encoding unit 3b. This is a value obtained by replacing the code output signal with a decimal number.

  In FIG. 52, the output error of the thermometer code “1” is separated from the logical boundary by two and inverted to “0”, and the type b2L bubble error “· 111011000 ···” is configured by a three-input NOR circuit. An operation when the output signal of the logical boundary detection unit 2 is input to the logical boundary detection unit 2 and converted into a gray code by the encoding unit 3b is shown, and the horizontal axis is a decimal value of a normal thermometer code, The vertical axis represents the value obtained by replacing the output signal of the gray code output from the encoding unit 3b with a decimal number.

  As described above, the encoding unit that outputs the gray code can suppress the error as compared with the encoding unit that outputs the binary code. Therefore, a conversion circuit that converts the gray code into the binary code is necessary. Regardless, it is widely used. However, there is still an error with respect to the value that seems most likely.

  In order to solve this problem, an A / D converter has been proposed in which the thermometer code output from the comparator unit is subjected to logic processing by a majority circuit, but the majority circuit is mounted on the A / D converter. This increases the circuit scale. Therefore, in order to suppress an increase in circuit scale, it has been proposed to configure the majority circuit with an analog circuit (Non-Patent Document 1). However, even such a majority circuit has not been sufficiently effective against a bubble error in which the output logic is inverted by two as shown in the type b2H and type b2L.

  Also, an irregular decoding logic is set in the logic boundary detection part of the thermometer code so that the most probable digital output signal is output even if a bubble error occurs (Non-Patent Document 2), or the thermometer code Boundary detection performed between adjacent outputs is divided into upper and lower bits (Non-Patent Document 3), and one logical comparison of thermometer codes is performed in the logical boundary detection unit. An apparatus that suppresses the occurrence of a bubble error by performing it every other time (Non-Patent Document 4) has been proposed.

Each of the A / D converters eliminates or corrects a bubble error generated in the thermometer code by a logical boundary detection unit.
On the other hand, in the configuration in which the bubble error is corrected by the encoder unit, the twin encoder type in which the average of the output signals of the encoder configured by the P channel MOS transistor and the encoder configured by the N channel MOS transistor is taken. However, the circuit scale of the encoder is doubled (Non-Patent Document 5).

In addition, in order to reduce the number of logical stages of the conversion circuit for converting gray code into binary code, an encoder that outputs a quasi gray code is employed to improve the operation speed as an encoder (non- There exists patent document 6).
J.van de Valburg and RJvan de Plassche, "An 8-bit 650-MHz folding ADC", IEEE Journal of Solid-State Circuits, vol. 27, Dec. 1992, pp. 1662-1666 CWMangelsdorf, "A 400-MHz Input Flash Converter with Error Correction", Journal of Solid-State Circuits, vol. 25, Feb. 1990, pp. 184-191 Y. Gendai et al., "An 8b 500-MHz ADC", Digest of International Solid-State Circuit Conference, TPM 10.5, Feb. 1991, pp. 172-173 A. Matsuzawa et al., "An 8b 600-MHz Flash A / D with mutistage deplex gray coding", Symp. VLSI Circ. Dig. Tech. Papers, May. 1991, pp. 113-114 M. Ito et al., "A 10bit 20MS / s 3V Supply CMOS AD Converter", 1994 Journal of Solid-State Circuits, vol. 25, Feb. 1990, pp. 184-191 Y. Akazawa, "A 400MSPS 8b Flash A / D Conversion LSI", ISSCC Digest of Tecnical Papers, Feb. 1987, pp. 98-99

  As described above, all the encoding units of the parallel A / D converter are configured in the ROM format by the wired OR circuit. In this configuration, a precharge operation is required for each cycle operation, and the precharge operation takes approximately half of the cycle operation time. Therefore, this is an obstacle to improving the operation speed of the encoding unit.

  Further, since the encoding unit does not have a function of correcting an error due to a bubble error occurring in the thermometer code, the correction of the bubble error is mainly corrected by the logical boundary detection unit. However, in such a configuration, there is a problem that even if an encoding unit that outputs a gray code with a low error level is used, an error in an output signal due to a bubble error cannot be completely removed.

The twin encoder type has a configuration in which a bubble error is corrected by the encoding unit, but has a problem that the circuit scale of the encoding unit is doubled.
The object of the invention is to provide a gray-binary conversion method and gray binary conversion equipment that can improve the operation speed of the encoder with a correction function of the bubble errors in the thermometer code input.

The gray-binary conversion method for generating a binary code of the least significant bit in a gray-binary conversion circuit for generating a binary code of a plurality of bits from a plurality of gray codes, wherein the gray code of the least significant bit is The decomposed multi-bit decomposed gray code is first logically processed to generate a first binary code, and a plurality of signals inputted to generate a binary code of a bit different from the least significant bit are converted into a second A logical process is performed to generate a second binary code, and the first and second binary codes are subjected to a third logical process to generate the least significant bit binary code.
According to a second aspect of the present invention, in the second logical process, a plurality of signals including a gray code of a bit different from the least significant bit are processed.
According to a third aspect of the present invention, in the second logical processing, an encoder that generates a gray code of at least 3 bits by detecting a logical boundary of a thermometer code, is generated when the gray code is generated, and the third bit from the least significant bit is generated. A plurality of signals including a signal corresponding to a binary code are processed.

According to claim 4, the decomposition Gray code of a plurality of bits by logic processing, generates a logic circuit for generating a plurality of binary code of the same bit, the binary code of 1-bit logically processing the plurality of binary code logic Circuit.
The signal input to the second logic circuit includes a gray code of a bit different from the least significant bit.
The signal input to the second logic circuit according to claim 6 is generated when the gray code is generated in an encoding unit that generates a gray code of at least 3 bits by detecting a logical boundary of a thermometer code. To a signal corresponding to the binary code of the third bit.

This invention can provide a gray-binary conversion method and gray binary conversion equipment that can improve the operation speed of the encoder with a correction function of the bubble errors in the thermometer code input.

(First embodiment)
First, the principle of error correction in the encoder of the present invention will be described.
FIG. 47 shows code values when decimal values (Decimal) are normally converted into 5-bit binary codes B0 to B4 and gray codes G0 to G4.

  The gray codes G0 to G4 are generated, for example, by performing a logical boundary detection on a thermometer code as a decimal value in a gray code format with a bit-independent decoding encoder based on the gray code shown in FIG. The specific configuration of the ROM cell CE shown in FIG. 45 is shown in FIG. 46, and the thermometer code is “1” in order from the lower order.

  In the gray codes G0 to G4, G0 is the least significant bit and G4 is the most significant bit, and in a code corresponding to an adjacent decimal value, only one bit signal is an inverted binary code. B0 to B4 are binary codes corresponding to G0 to G4, where B0 is the least significant bit and B4 is the most significant bit.

  In the normal encoder shown in FIG. 45, G0 to G4 are output from a wired OR circuit using one bit line BL0 to BL4, respectively. For example, in the combination of G0 and G1, “00” “10” “ Since all combinations of “01” and “11” exist, the presence or absence of an error cannot be detected from the combination even if at least one of G0 and G1 is erroneous data.

  Therefore, since G0 is generated by ORing the output signals of the nine ROM cells CE connected to the bit line BL0, G0 is decomposed into the output signals Z1 to Z8 of the nine ROM cells CE.

Similarly, when G1 and G2 are decomposed, G1 = Y1 + Y2 + Y3 + Y4 and G2 = X1 + X2. Note that W1 = G3 and V1 = G4.
At this time, focusing on the relationship between X1 and Z2, when Z2 = 1, X1 = 1. Therefore, when Z2 = 1, if X1 = 0, an error is detected, and the encoder is operating with a thermometer code including a bubble error.

  Similarly, when Z3 = 1, X1 = 1, when Z4 = 1, W1 = 1, when Z5 = 1, W1 = V1 = 1, and when Z6 = 1, X2 = W1 = V1 = 1. When Z7 = 1, X2 = V1 = 1, and when Z8 = 1, V1 = 1. When these conditions are not satisfied, it can be detected that a bubble error exists in the thermometer code. .

  On the other hand, for example, in codes corresponding to the decimal values “3” and “4”, Z1 to Z8 are simultaneously “0”, and such a specific relationship as described above cannot be found. That is, the above specific relationship can be found when Z1 to Z8 are the target logical side “1”, but the above specific relationship is found when Z1 to Z8 are the non-target logical side “0”. I can't.

  Therefore, in order to develop the above principle over the whole range of decimal values including the non-target logic side, when Z1 to Z8 are used as table codes, back codes P1 to P7 of Z1 to Z8 are set. .

  45. As shown in FIG. 45, P1 to P7 are codes output from ROM cells CEb connected between the ROM cells CE connected to the bit line BL0 of the least significant bit. Accordingly, the back codes P1 to P7 are codes in which the logical boundary of the thermometer code that is not detected in each ROM cell CE connected to the bit line BL0 of the least significant bit is detected in the ROM cell CEb.

  With the back cord as described above, when P1 = 1, Y1 = 1, when P2 = 1, X1 = 1, when P3 = 1, Y2, W1 = 1, and when P4 = 1, W1 = 1, P5 = 1, Y3, W1, V1 = 1, P6 = 1, X2, V2 = 1, and P7 = 1, Y4, V1 = 1.

By setting the front code and the back code as described above, it is possible to detect whether or not a bubble error is included in the thermometer code over the entire range of the thermometer code.
FIG. 48 shows the value of each code when the thermometer code corresponding to each decimal value includes “..110100 ..”, that is, the type b1 bubble error. In the figure, the shaded portion is a portion that can be detected as an error only by the table code of the gray code. The pre-correction Dout is obtained by replacing the error-uncorrected encoder output with a decimal value.

  When this shaded portion is inverted, the detected error is corrected to the most probable value, and the corrected encoder output is shown in FIG. In FIG. 53, the horizontal axis represents the analog value input to the A / D converter, and the vertical axis represents the encoder output converted into an analog value.

  FIG. 49 shows a corrected code obtained by performing error detection on the code shown in FIG. 48 using the front code and the back code, and inverting the shaded portion detected as an error. As a result, the corrected gray code is corrected to the most probable value and matches the normal gray code shown in FIG. FIG. 54 shows the output of the encoder based on the corrected code shown in FIG.

Next, an encoder having a function of correcting a bubble error included in the thermometer code will be described based on the above principle.
FIG. 2 shows a schematic configuration of an encoder that generates and outputs 5-bit binary code digital signals B0Z to B4Z based on the input of thermometer codes e1 to e31 output from the comparator unit similar to the conventional example. Show.

  The encoder includes first to fourth encoding units 11 to 14 that generate a 5-bit gray code based on the thermometer codes e1 to e31, and thermometer codes e1 to e31 based on the generated gray code. An error signal generation unit 15 that detects the presence or absence of a bubble error and outputs an error signal when a bubble error exists, an error correction unit 16 that corrects an error in the gray code based on the error signal, And a gray / binary converter 17 for generating a binary code from the corrected gray code.

  A specific configuration of the first encoding unit 11 is shown in FIG. The seventeen logical boundary detection circuits 18a to 18q have three input terminals IB, IA, and IX. Of the thermometer codes e1 to e31, odd-numbered thermometer codes e1, e3... E31 are input to the input terminals IA of the logic boundary detection circuits 18a to 18p, respectively. Further, the ground GND level is supplied to the input terminals IA and IB of the uppermost logic boundary detection circuit 18q.

  The odd-numbered thermometer codes e1, e3,... E31 are input to the input terminals IX of the logic boundary detection circuits 18b to 18q, respectively. The power supply Vcc is supplied to the input terminal IX of the lowest logical boundary detection circuit 18a.

  A specific configuration of the logic boundary detection circuits 18a to 18p is shown in FIG. The input terminals IB and IA are connected to the input terminal of the NOR circuit 19. The input terminal IX is input to the input terminal of the inverter circuit 20, and the output terminal of the inverter circuit 20 is connected to the NOR circuit 19.

  In such logic boundary detection circuits 18b to 18q, the output signal O becomes H level only when the input levels of the input terminals IB and IA are L level and the input level of the input terminal IX is H level.

  The output signals O of the logic boundary detection circuits 18a to 18q are respectively input to the terminals A of the ROM cells 21a to 21q, and the terminals C of the ROM cells 21a to 21q are connected to any of the bit lines BL0a to BL0Xb, Terminal B is connected to ground GND.

  As shown in FIG. 11, the ROM cells 21a to 21q are composed of an N-channel MOS transistor CT, the terminal A is connected to the gate, the terminal C is connected to the drain, and the terminal B is connected to the source.

  Therefore, when the output signal O of the logic boundary detection circuits 18a to 18q becomes H level, the N channel MOS transistors CT of the ROM cells 21a to 21q to which the output signal O is input are turned on, and the ROM cells 21a to 21q are turned on. Gray codes g0a, g0b, g0Xa, and g0Xb output from the connected bit lines BL0a, BL0b, BL0Xa, and BL0Xb become the ground GND level.

  Every four ROM cells 21e, 21i, 21m, and 21q are connected to the bit line BL0a with the ROM cell 21a at the bottom. Every fourth ROM cell 21g, 21k, 21o is connected to the bit line BL0b with the ROM cell 21c at the bottom.

  Every four ROM cells 21f, 21j, and 21n are connected to the bit line BL0Xa with the ROM cell 21b at the bottom. Every four ROM cells 21h, 21l, and 21p are connected to the bit line BL0Xb with the ROM cell 21d at the bottom.

A specific configuration of the second encoding unit 12 is shown in FIG. The nine logical boundary detection circuits 22a to 22i have the same configuration as the logical boundary detection circuits 18a to 18q.
Of the thermometer codes e1 to e31, even-numbered thermometer codes e2, e6, e10, e14, e18, e22, e26, and e30 are input to the input terminals IA of the logic boundary detection circuits 22a to 22h, respectively. The The ground GND level is supplied to the input terminals IA and IB of the uppermost logic boundary detection circuit 22i.

Even-numbered thermometer codes e4, e8, e12, e16, e20, e24, e28 are input to the input terminals IB of the logic boundary detection circuits 22a to 22g, respectively.
An inverted signal of the NOR logic of the thermometer codes e2 and e4, that is, an OR logic is input to the input terminal IX of the logic boundary detection circuit 22b. Similarly, OR logics of thermometer codes e6, e8, e10, e12, e14, e16, e18, e20, e22, e24, e26, e28 are input to the input terminals IX of the logic boundary detection circuits 22c to 22h, respectively. The

The power supply Vcc is input to the input terminal IX of the logic boundary detection circuit 22a, and the thermometer code e30 is input to the input terminal IX of the logic boundary detection circuit 22i.
The output signals O of the logic boundary detection circuits 22a to 22i are respectively input to the terminals A of the ROM cells 23a to 23i, and the terminals C of the ROM cells 23a to 23i are connected to any of the bit lines BL1 to BL1X. Terminal B is connected to ground GND.

The ROM cells 23a to 23i are configured similarly to the ROM cells 21a to 21q.
Therefore, when the output signal O of the logic boundary detection circuits 22a to 22i becomes H level, the N channel MOS transistor CT of the ROM cells 23a to 23i to which the output signal O is input is turned on, and the ROM cells 23a to 23i are turned on. Gray code signals g1 and g1X output from the connected bit lines BL1 to BL1X are at the ground GND level.

  Every other ROM cell 23c, 23e, 23g, 23i is connected to the bit line BL1 with the ROM cell 23a at the bottom. Every other ROM cell 23d, 23f, 23h is connected to the bit line BL1X with the ROM cell 23b at the bottom.

A specific configuration of the third encoding unit 13 is shown in FIG. The eight logical boundary detection circuits 24a to 24h have the same configuration as the logical boundary detection circuits 18a to 18q.
Of the thermometer codes e1 to e31, even-numbered thermometer codes e4, e8, e12, e16, e20, e24, and e28 are input to the input terminals IA of the logic boundary detection circuits 24a to 24g, respectively. The ground GND level is supplied to the input terminals IA and IB of the uppermost logic boundary detection circuit 24h.

  Even-numbered thermometer codes e6, e10, e14, e18, e22, e26, e30 are input to the input terminals IB of the logic boundary detection circuits 24a to 22g, respectively.

  An NOR logic inversion signal of thermometer codes e4 and e6, that is, an OR logic is input to the input terminal IX of the logic boundary detection circuit 24b. Similarly, OR logic of thermometer codes e8, e10, e12, e14, e16, e18, e20, e22, e24, e26, e28, e30 are input to the input terminals IX of the logic boundary detection circuits 24c to 24h, respectively. The The power supply Vcc is input to the input terminal IX of the logic boundary detection circuit 24a.

  The output signals O of the logic boundary detection circuits 24a to 24h are output as output signals ga to gh and also input to terminals A of the ROM cells 25a to 25h, respectively. The terminals C of the ROM cells 25a to 25h are connected to any one of the bit lines BL2a to BL2b, and the terminal B is connected to the ground GND.

The ROM cells 25a to 25h are configured similarly to the ROM cells 21a to 21q.
Therefore, when the output signal O of the logic boundary detection circuits 24a to 24h becomes H level, the N-channel MOS transistor CT of the ROM cells 25a to 25h to which the output signal O is input is turned on, and the ROM cells 25a to 25h are turned on. The binary code signals g2a and g2b output from the connected bit lines BL2a to BL2b are at the ground GND level.

  Every other ROM cell 25c, 25e, 25g is connected to the bit line BL2a with the ROM cell 25a at the bottom. Every other ROM cell 25d, 25f, 25h is connected to the bit line BL2a with the ROM cell 25b at the bottom.

  The fourth encoding unit 14 will be described with reference to FIG. The output signals g0Xa and g0Xb of the bit lines BL0Xa and BL0Xb are input to the NAND circuit 27a, and the output signal of the NAND circuit 27a is inverted by the inverter circuit 28a to generate the gray code g0X.

  The output signals g0a and g0b of the bit lines BL0a and BL0b are input to the NAND circuit 27b, and the output signal of the NAND circuit 27b is inverted by the inverter circuit 28b to generate the gray code g0.

  The output signals gb and gc of the logic boundary detection circuits 24b and 24c are input to the NOR circuit 26a, and the output signals gf and gg of the logic boundary detection circuits 24f and 24g are input to the NOR circuit 26b. The output signals of the NOR circuits 26a and 26b are input to the NAND circuit 27c, and the gray code g2 is output from the NAND circuit 27c.

  The output signals gc and gd of the logical boundary detection circuits 24c and 24d are input to the NOR circuit 26c, and the output signals ge and gf of the logical boundary detection circuits 24e and 24f are input to the NOR circuit 26d to detect the logical boundary detection. The output signals gg and gh from the circuits 24g and 24h are input to the NOR circuit 26e.

  The output signal of the NOR circuit 26c is input to the NAND circuit 27d, the output signal of the NOR circuit 26d is input to the NAND circuits 27d and 27e, and the output signal of the NOR circuit 26e is input to the NAND circuit 27e. .

Then, the gray code g3 is output from the NAND circuit 27d, and the gray code g4 is output from the NAND circuit 27e.
A specific configuration of the error signal generator 15 will be described with reference to FIG. The output signal g1 of the bit line BL1 is input to the NAND circuit 29a, and the output signal g0a of the bit line BL0a is inverted by the inverter circuit 28c and input to the NAND circuit 29a.

  The output signal g1X of the bit line BL1X is input to the NAND circuit 29b, and the output signal g0b of the bit line BL0b is inverted by the inverter circuit 28d and input to the NAND circuit 29b.

  The output signal ER1A of the NAND circuit 29a and the output signal ER1A of the NAND circuit 29b are input to the NAND circuit 29e, and the error signal er1 is output from the NAND circuit 29e.

  The output signal g2a of the bit line BL2a is input to the NAND circuit 29c, and the output signal g0Xa of the bit line BL0Xa is inverted by the inverter circuit 28e and input to the NAND circuit 29c.

  The output signal g2b of the bit line BL2b is input to the NAND circuit 29d, and the output signal g0Xb of the bit line BL0Xb is inverted by the inverter circuit 28f and input to the NAND circuit 29d.

  The output signal ER2A of the NAND circuit 29c and the output signal ER2B of the NAND circuit 29d are input to the NAND circuit 29f, and the error signal er2 is output from the NAND circuit 29f.

The error signals er1 and er2 are output to the error correction unit 16 and output from an output terminal provided in the error signal generation unit 15 to the outside as shown in FIG.
A specific configuration of the error correction unit 16 will be described with reference to FIG. The error signal er2 and the signal g1X are input to the NAND circuit 30a, and the gray code g2 is inverted by the inverter circuit 33a and input to the NAND circuit 30a.

  The output signal of the NAND circuit 30a and the gray code g4 are input to the EOR circuit 32a, and the output signal of the EOR circuit 32a is inverted by the inverter circuit 33c and output as a corrected gray code g4Z.

The error signal er2, the signal g1X, and the gray code g2 are input to the NAND circuit 30b.
The output signal of the NAND circuit 30b and the gray code g3 are input to the EOR circuit 32b, and the output signal of the EOR circuit 32b is inverted by the inverter circuit 33d and output as a corrected gray code g3Z.

The error signal er2 and the gray code g1 are input to the NAND circuit 30c.
The output signal of the NAND circuit 30c and the gray code g2 are input to the EOR circuit 32c, and the output signal of the EOR circuit 32c is inverted by the inverter circuit 33e and output as a corrected gray code g2Z.

The error signal er1 is inverted by the inverter circuit 33b and input to the EOR circuit 32d, and the gray code signal g1 is input to the EOR circuit 32d.
The output signal of the EOR circuit 32d is inverted by the inverter circuit 33f and output as the corrected gray code g1Z.

  The error signals er2 and er1 are input to the NOR circuit 31, and the output signal of the NOR circuit 31 and the gray code signal g0 are input to the EOR circuit 32e. The output signal of the EOR circuit 32e is inverted by the inverter circuit 33g and output as a corrected gray code g0Z.

  A specific configuration of the gray binary conversion unit 17 is shown in FIG. The corrected gray code g4Z is input to the EOR circuit 35a and output as a binary code B4Z through the two-stage inverter circuits 34a and 34b.

  The corrected gray code g3Z is input to the EOR circuit 35a, and the output signal of the EOR circuit 35a is output as a binary code B3Z and also input to the EOR circuit 35b.

  The corrected gray code g2Z is input to the EOR circuit 35b, and an output signal of the EOR circuit 35b is output as a binary code B2Z and also input to the EOR circuit 35c.

  The corrected gray code g1Z is input to the EOR circuit 35c, and an output signal of the EOR circuit 35c is output as a binary code B1Z and also input to the EOR circuit 35d.

The corrected gray code g0Z is input to the EOR circuit 35d, and the output signal of the EOR circuit 35d is output as a binary code B0Z.
The gray / binary conversion unit 17 is generally used as a circuit for converting a gray code into a binary code.

  Any of the precharge circuits 36 and 37 shown in FIGS. 12 and 14 is connected between the bit lines BL1 and BL1X. A similar precharge circuit is connected between BL2a and BL2b.

  In the precharge circuit 36, the sources of the pair of P-channel MOS transistors Trp1 and Trp2 are connected to the power supply Vcc, and the gates of the transistors Trp1 and Trp2 are connected to the drains of each other.

  A plurality of N-channel MOS transistors Trn are connected in parallel between the drain of the transistor Trp1 and the power source Vss, and a logic boundary for controlling the bit line BL1 via the ROM cell is connected to the gate of each transistor Trn. The output signals of the detection circuits 23a, 23c, 23e, 23g, and 23i are input as the gate signal V1, respectively.

  A plurality of N-channel MOS transistors Trnx are connected in parallel between the drain of the transistor Trp2 and the power supply Vss, and a logical boundary for controlling the bit line BL1X via the ROM cell is connected to the gate of each transistor Trnx. The output signals of the detection circuits 23b, 23d, 23f, and 23h are input as the gate signal V1X, respectively.

The drain of the transistor Trp1 is connected to the bit line BL1, and the drain of the transistor Trp2 is connected to the bit line BL1X.
In the precharge circuit 36 configured in this way, as shown in FIG. 13, for example, one of the gate signals V1 of the transistor Trn1 becomes H level and any of the transistors Trn1 is turned on, and the gate of the transistor Trnx is turned on. When all the signals V1X become L level, the transistor Trp1 is turned off and the transistor Trp2 is turned on. Then, the bit line BL1 becomes L level, the bit line BL1X becomes H level, and the bit line BL1X is precharged to the power supply Vcc level.

  When any one of the gate signals V1X of the transistor Trnx becomes H level and any of the transistors Trnx is turned on, and when all the gate signals V1 of the transistors Trn become L level, the transistor Trp1 is turned on and Trp2 is turned off. Then, the bit line BL1 becomes H level, the bit line BL1X becomes L level, and the bit line BL1 is precharged to the power supply Vcc level.

  The precharge circuit 37 shown in FIG. 14 is different from the precharge circuit 36 in that the gates of the transistors Trp1 and Trp2 are connected to each other and are connected to the drain of the transistor Trp1.

  In the precharge circuit 37, one of the bit lines BL1 and BL1X is precharged after one of the bit lines BL1 and BL1X falls in the precharge circuit 36, as shown in FIG. Since the other is precharged simultaneously with the fall of, the response speed of the precharge operation is increased.

Precharge circuits 38a to 38d shown in FIG. 16 are connected to the bit lines BL0a, BL0b, BL0Xa, and BL0Xb of the first encoding unit 11, respectively.
The precharge circuit 38a is composed of three P-channel MOS transistors connected in parallel between the bit line BL0a and the power source Vcc, and the gray codes g0b, g0Xa, and g0Xb are respectively input to the gates of the transistors. Is done.

  When the gray code g0a does not become L level, any one of the gray codes g0b, g0Xa, g0Xb becomes L level, so that the bit line BL0a is precharged to the power supply Vcc level.

  The precharge circuit 38b is composed of three P-channel MOS transistors connected in parallel between the bit line BL0b and the power source Vcc, and the gray codes g0a, g0Xa, and g0Xb are respectively input to the gates of the transistors. Is done.

  When the gray code g0b does not become L level, any one of the gray codes g0a, g0Xa, g0Xb becomes L level, so that the bit line BL0b is precharged to the power supply Vcc level.

  The precharge circuit 38c is composed of three P-channel MOS transistors connected in parallel between the bit line BL0Xa and the power source Vcc, and the gray codes g0a, g0b and g0Xb are input to the gates of the transistors, respectively. Is done.

  When the gray code g0Xa does not become L level, any one of the gray codes g0a, g0b, and g0Xb becomes L level, so that the bit line BL0Xa is precharged to the power supply Vcc level.

  The precharge circuit 38d is composed of three P-channel MOS transistors connected in parallel between the bit line BL0Xb and the power source Vcc, and the gray codes g0a, g0b, g0Xa are respectively input to the gates of the transistors. Is done.

  When the gray code g0Xb does not become L level, any one of the gray codes g0a, g0b, and g0Xa becomes L level, so that the bit line BL0Xb is precharged to the power supply Vcc level.

Next, the operation of the encoder configured as described above will be described.
The first encoding unit 11 generates gray codes g0a, g0b, g0Xa, and g0Xb for generating the lowest gray code g0 when generating the 5-bit gray codes g0 to g4 from the thermometer codes e1 to e31. It is generated by the bit independent decoding method.

  The odd numbered thermometer codes e1 to e31 are input to the logic boundary detection circuits 18a to 18q in order of three from the lower order. When normal thermometer codes e1 to e31 are input to the logical boundary detection circuits 18a to 18q, gray codes as shown in FIG. 17 are generated from the bit lines BL0a, BL0b, BL0Xa, and BL0Xb of the first encoding unit 11. g0a, g0b, g0Xa, g0Xb are output.

  The gray code g0a corresponds to the signal obtained by ORing the signals Z1, Z3, Z5, and Z7 shown in FIG. 47, and the gray code g0b takes the OR logic of the signals Z2, Z4, Z6, and Z8 shown in FIG. It corresponds to the signal.

  The gray code g0Xa is a back code for the gray code g0a, and corresponds to the one obtained by taking the OR logic of the signals P1, P3, P5, and P7 shown in FIG. The gray code g0Xb is a back code for the gray code g0b, and corresponds to the OR logic of the signals P2, P4, and P6 shown in FIG.

And any one of the gray codes g0a, g0b, g0Xa, and g0Xb becomes L level based on the thermometer codes e1 to e31.
The logic as described above is generated by sequentially connecting the ROM cells 21a to 21q driven by the logic boundary detection circuits 18a to 18q to the bit lines BL0a, BL0Xa, BL0b, and BL0Xb. That is, every four logic boundary detection circuits are connected to each bit line BL0a, BL0Xa, BL0b, BL0Xb via ROM cells, and four logics are sequentially connected to each bit line BL0a, BL0Xa, BL0b, BL0Xb. If the boundary detection circuit has one cycle, the logical boundary detection circuits 18a to 18q are connected to the bit lines BL0a, BL0Xa, BL0b, and BL0Xb at intervals of one cycle.

  When thermometer codes e1 to e31 including b1 type bubble errors are input to the first encoding unit 11, as shown in FIG. 18, gray codes g0a, g0b, g0Xa are entered. , G0Xb includes an error due to the bubble error.

  When the thermometer codes e1 to e31 including the b2H type bubble error are input to the first encoding unit 11, odd numbers are input to the logical boundary detection circuits 18a to 18q. Since three thermometer codes e1 to e31 are input in order from the lower order, as shown in FIG. 19, the gray codes g0a, g0b, g0Xa, and g0Xb have the same errors as in the case of the b1 type bubble error. Corrected to include signal.

  When the thermometer codes e1 to e31 including the b2L type bubble error are input to the first encoding unit 11, as shown in FIG. 20, gray codes g0a and g0b are input. , G0Xa, and g0Xb are corrected to be equal to the gray codes g0a, g0b, g0Xa, and g0Xb by the thermometer codes e1 to e31 not including the bubble error shown in FIG.

  Note that one of the gray codes g0a, g0b, g0Xa, and g0Xb is L level in any of the above cases, and the other is H level. Therefore, of the bit lines BL0a, BL0Xa, BL0b, and BL0Xb, the bit line that does not output the L level gray code is precharged to the power source Vcc in parallel with the encoding operation by the operation of the precharge circuits 38a to 38d. The

  When the second encoding unit 12 generates the 5-bit gray codes g0 to g4 from the thermometer codes e1 to e31, the second gray code g1 from the lower order and the complementary signal g1X are bit-independently generated. It is generated by the decoding method.

  Signals based on the even-numbered thermometer codes e2 to e30 are input to the logical boundary detection circuits 22a to 22i in order of three from the lower order. When normal thermometer codes e2 to e30 are input to the logical boundary detection circuits 22a to 22i, gray codes g1 and g1X as shown in FIG. 17 are generated from the bit lines BL1 and BL1X of the second encoding unit 12. Is output.

The gray code g1 corresponds to the gray code G1 shown in FIG. 47, and the gray code g1X is a back code of the gray code g1 and is complementary to each other.
The logic as described above is generated by alternately connecting the ROM cells 23a to 23i driven by the logic boundary detection circuits 22a to 22i to the bit lines BL1 and BL1X. That is, every other logical boundary detection circuit is connected to each bit line BL1, BL1X via a ROM cell, and two logical boundary detection circuits alternately connected to each bit line BL1, BL1X are defined as one cycle. Then, the logic boundary detection circuits 22a to 22i are connected to the bit lines BL1 and BL1X at intervals of one cycle.

  When the thermometer codes e2 to e30 including the b1 type bubble error are input to the second encoding unit 12, gray codes g1 and g1X have gray codes g1 and g1X as shown in FIG. , Errors due to that bubble error are included.

  When the thermometer codes e2 to e30 including the b2H type bubble error are input to the second encoding unit 12, an even number is input to the logical boundary detection circuits 22a to 22i. Since three signals based on the thermometer codes e2 to e30 are inputted in order from the lower order, as shown in FIG. 19, the gray codes g1 and g1X include an error similar to the case of the b1 type bubble error. Corrected to signal.

  When the thermometer codes e2 to e30 including the b2L type bubble error are input to the second encoding unit 12, as shown in FIG. 20, gray codes g1, g1X Is corrected to be equal to the gray codes g1 and g1X by the thermometer codes e2 to e30 not including the bubble error shown in FIG.

  The gray codes g1 and g1X are complementary signals in either case. Accordingly, of the bit lines BL1 and BL1X, the bit line that does not output the L level gray code is precharged to the power supply Vcc level in parallel with the encoding operation by the operation of the precharge circuit 36 or the precharge circuit 37. The

  When the third encoding unit 13 generates the 5-bit gray codes g0 to g4 from the thermometer codes e1 to e31, a logical boundary for generating the third to fifth gray codes g2 to g4 from the lower order The detection signals ga to gh and the binary codes g2a and g2b are generated by the bit independent decoding method.

  Signals based on the even-numbered thermometer codes e4 to e30 are input to the logic boundary detection circuits 24a to 24h in order of three from the lower order. When normal thermometer codes e4 to e30 are input to the logical boundary detection circuits 24a to 24h, binary codes g2a and g2b as shown in FIG. 17 are generated from the bit lines BL2a and BL2b of the third encoding unit 13. Is output.

  The binary codes g2a and g2b are in a complementary relationship with each other, and are the values obtained by shifting the gray codes g1 and g1X by two higher-order decimal values in FIG. That is, g2a corresponds to the binary code B2.

  The logic as described above is generated by alternately connecting the ROM cells 25a to 25h driven by the logic boundary detection circuits 24a to 24h to the bit lines BL2a and BL2b. In other words, every other logical boundary detection circuit is connected to each bit line BL2a, BL2b via a ROM cell, and two logical boundary detection circuits alternately connected to each bit line BL2a, BL2b are defined as one cycle. Then, the logic boundary detection circuits 24a to 24h are connected to the bit lines BL2a and BL2b at intervals of one cycle.

Also, logical boundary detection signals ga to gh are output from the logical boundary detection circuits 24a to 24h.
When the thermometer codes e4 to e30 including the b1 type bubble error are input to the third encoding unit 13, as shown in FIG. 18, the binary codes g2a and g2b include , Errors due to that bubble error are included.

  When the thermometer codes e4 to e30 including the b2H type bubble error are input to the third encoding unit 13, even numbers are input to the logic boundary detection circuits 24a to 24h. Since three signals based on the thermometer codes e4 to e30 are input in order from the lower order, as shown in FIG. 19, the binary codes g2a and g2b include errors similar to those of the b1 type bubble error. Corrected to signal.

  When the thermometer codes e4 to e30 including the b2L type bubble error are input to the third encoding unit 13, as shown in FIG. 20, binary codes g2a and g2b are input. Is corrected to be equal to the binary codes g2a and g2b by the thermometer codes e4 to e30 not including the bubble error shown in FIG.

  The binary codes g2a and g2b are complementary signals in either case. Therefore, of the bit lines BL2a and BL2b, the bit line that does not output the L level binary code is precharged to the power supply Vcc level in parallel with the encoding operation by the operation of the precharge circuit 36 or the precharge circuit 37. The

  The fourth encoding unit 14 generates the lowest gray codes g0 and g0X based on the logical processing of the gray code signals g0a, g0b, g0Xa, and g0Xb, and generates the logic of the logical boundary detection signals gb to gh. This is a logic circuit that generates the third to fifth gray codes g2 to g4 from the lower order based on the processing.

  When normal gray code signals g0a, g0b, g0Xa, g0Xb and logical boundary detection signals gb-gh by normal thermometer codes e1-e31 are input to the fourth encoding unit 14 as shown in FIG. In this way, gray codes g0, g2 to g4 that do not include an error are generated. The second lowest gray code g1 is generated by the second encoding unit 12.

  When the gray code signals g0a, g0b, g0Xa, g0Xb and the logic boundary detection signals gb to gh including errors based on the b1 type bubble error are input to the fourth encoding unit 14. As shown in FIG. 18, the gray codes g0 to g4 include errors due to the bubble error.

  Further, the gray code signals g0a, g0b, g0Xa, g0Xb including the error based on the b2H type bubble error and the logical boundary detection signals gb to gh are input to the fourth encoding unit 13. Then, as shown in FIG. 19, the gray codes g0 to g4 are signals including an error similar to the case of the b1 type bubble error.

  Further, the gray code signals g0a, g0b, g0Xa, g0Xb and the logical boundary detection signals gb to gh including errors based on the b2L type bubble error are input to the fourth encoding unit 14. Then, as shown in FIG. 20, the gray codes g0 to g4 are signals that do not include an error, and are the same as those in FIG.

  The error signal generator 15 detects whether the gray code signals g0a, g0b, g0Xa, g0Xb, g1, g1X and the binary codes g2a, g2b satisfy the relationship between the gray codes shown in FIG. If not satisfied, H level error signals er1 and er2 are output.

  That is, when normal gray codes g1 and g0a are input to the NAND circuit 29a, as shown in FIG. 17, when the gray code g0a is at the L level, the gray code g1 is at the L level, so the output signal ER1A is It must be H level.

  In the NAND circuit 29b, when normal gray codes g1X and g0b are input, when the gray code g0b is at L level, the gray code g1X is at L level, so the output signal ER1B is always at H level.

  Therefore, when normal gray codes g1, g1X, g0a, and g0b are input, the output signals ER1A and ER1B of the NAND circuits 29a and 29b are both H level, and the error signal er1 output from the NAND circuit 29e is L. Become a level.

  Similarly, in the NAND circuit 29c, when the normal binary code g2a and the gray code g0Xa are input, when the gray code g0Xa is at the L level, the binary code g2a is at the L level, so the output signal ER2A is always at the H level. It becomes.

  In the NAND circuit 29d, when the normal binary code g2b and the gray code g0Xb are input, when the gray code g0Xb is at the L level, the binary code g2b is at the L level, so the output signal ER2b is always at the H level.

  Therefore, when normal gray codes g2a, g2b, g0Xa, and g0Xb are input, the output signals ER2A and ER2B of the NAND circuits 29c and 29d are both H level, and the error signal er2 output from the NAND circuit 29f is L. Become a level.

  On the other hand, when the gray code signals g0a, g0b, g0Xa, g0Xb, g1, g1X and the binary codes g2a, g2b include errors as shown in FIGS. In some cases, the output signals ER1A to ER2B of the NAND circuits 29a to 29d become L level. In this case, the error signals er1 and er2 become H level.

  The error correction unit 16 shown in FIG. 8 operates so as to correct the gray codes g0 to g4 including errors to a probable value based on the error signals er1 and er2. In the correcting operation, as shown in the correcting principle, the code in which the error is detected is inverted among the gray codes g0 to g4.

  That is, as shown in FIGS. 18 and 19, when the gray code g4 outputs an error, the error signal er2 and the gray code signal g1X are at the H level and the gray code signal g2 is at the L level, and the output of the NAND circuit 30a The signal becomes L level. Then, the corrected gray code g4Z obtained by inverting the gray code g4 is output by the operations of the EOR circuit 32a and the inverter circuit 33c.

  When the error signal er2 and the gray code signals g1X and g2 are other than the above, the gray code g4 is normal and the output signal of the NAND circuit 30a is at the H level, so the corrected gray code g4Z is the gray code g4. Be in phase.

  When the gray code g3 outputs an error, the error signal er2 and the gray code signals g1X and g2 are at H level, and the output signal of the NAND circuit 30a is at L level. Then, the corrected gray code g3Z obtained by inverting the gray code g3 is output by the operations of the EOR circuit 32b and the inverter circuit 33d.

  When the error signal er2 and the gray code signals g1X and g2 are other than the above, the gray code g3 is normal and the output signal of the NAND circuit 30b is at the H level, so the corrected gray code g3Z is the gray code g3. Be in phase.

  When the gray code g2 outputs an error, the error signal er2 and the gray code signal g1 are at H level, and the output signal of the NAND circuit 30c is at L level. Then, the corrected gray code g2Z obtained by inverting the gray code g2 is output by the operations of the EOR circuit 32c and the inverter circuit 33e.

  When the error signal er2 and the gray code signal g1 are other than the above, the gray code g2 is normal and the output signal of the NAND circuit 30c is at the H level, so the corrected gray code g2Z is in phase with the gray code g2. Become.

  When the gray code g1 outputs an error, the error signal er1 becomes H level and the output signal of the inverter circuit 33b becomes L level. Then, the corrected gray code g1Z obtained by inverting the gray code g1 is output by the operations of the EOR circuit 32d and the inverter circuit 33f.

  When the error signal er2 is at L level, the gray code g1 is normal and the output signal of the inverter circuit 33b is at H level, so that the corrected gray code g1Z is in phase with the gray code g1.

  When the gray code g0 outputs an error, at least one of the error signals er1 and er2 becomes H level, and the output signal of the NOR circuit 31 becomes L level. Then, the corrected gray code g0Z obtained by inverting the gray code g0 is output by the operations of the EOR circuit 32e and the inverter circuit 33g.

  When the error signals er1 and er2 are both at the L level, the gray code g0 is normal and the output signal of the NOR circuit 31 is at the H level, so the corrected gray code g0Z is in phase with the gray code g0.

  9 outputs the corrected gray code g4Z as the binary code B4Z, outputs the EOR logic of the corrected gray codes g4Z and g3Z as the binary code B3Z, and outputs the binary code B3Z and the corrected gray code g2Z. The EOR logic of the binary code B2Z and the corrected gray code g1Z is output as the binary code B1Z, and the EOR logic of the binary code B1Z and the corrected gray code g0Z is output as the binary code B0Z. Output as.

By such an operation, the corrected gray codes g0Z to g4Z are converted into binary codes B0Z to B4Z.
With the encoder configured as described above, the following operational effects can be obtained.

  (1) Even if b1 type, b2H type, or b2L type bubble errors are included in the input thermometer codes e1 to e31, binary codes B0Z to B4Z in which the bubble errors are corrected can be generated.

  (2) The logical boundary detection circuit constituting the first encoding unit 11 is constituted by a three-input circuit including an inverter circuit and a NOR circuit, and an odd-numbered thermometer code among the thermometer codes e1 to e31 is input. Therefore, b1 type bubble error is not corrected, b2H type bubble error can be corrected to be equivalent to the case where b1 type bubble error is input, and b2L type bubble error is a probable value. Can be corrected.

  (3) The logical boundary detection circuit constituting the second and third encoding units 12 and 13 is composed of a three-input circuit including an inverter circuit and a NOR circuit, and an even-numbered thermometer among the thermometer codes e1 to e31. Since the meter code and the OR logic of the thermometer code are input, the b1 type bubble error is not corrected, and the b2H type bubble error is corrected to be equivalent to the case where the b1 type bubble error is input. The b2L type bubble error can be corrected to a probable value.

  (4) In the first encoding unit 11, the ROM cells 21a to 21q that operate based on the output signals of the logic boundary detection circuits 18a to 18q are sequentially connected to the bit lines BL0a, BL0b, BL0Xa, and BL0Xb. Table codes g0a and g0b obtained by decomposing the gray code g0 and back codes g0Xa and g0Xb can be generated.

  (5) In the second encoding unit 12, the ROM cells 23a to 23i that operate based on the output signals of the logic boundary detection circuits 22a to 22i are sequentially connected to the bit lines BL1 and BL1X, so that the second gray level from the bottom is obtained. The code g1 and the back code g1X can be generated.

  (6) In the third encoding unit 13, the ROM cells 23a to 23i that operate based on the output signals of the logic boundary detection circuits 24a to 24h are sequentially connected to the bit lines BL1 and BL1X, so that the second gray level from the lower order is displayed. A signal obtained by shifting the code g1 and the back code g1X by two in the decimal value, that is, a signal equivalent to the binary code B2 can be generated. Further, the logical boundary detection signals ga to gh can be output from the logical boundary detection circuits 24a to 24h.

  (7) The fourth encoding unit 14 performs logic processing on the logical boundary detection signals gb to gh generated by the third encoding unit 13 to generate the third to fifth gray codes g2 to g4 from the lower order. be able to. Further, the lowest gray code g0 can be generated by logically processing the gray codes g0a, g0b, g0Xa, and g0Xb generated by the first encoding unit 11.

  (8) The error signal generation unit 15 performs error detection on the basis of the error detection principle shown in FIG. 47 by logically processing the output signals of the first to third encoding units 11, 12, and 13, and an error is detected. When present, the H level error signals er1 and er2 can be generated.

  (9) The error correction unit 16 corrects the gray codes g0 to g4 including the type b1 error based on the error signals er1 and er2 and the gray code signals g1, g1X, and g2, thereby correcting the corrected gray code. g0Z to g4Z can be generated.

(10) The gray / binary conversion unit 17 can convert the corrected gray codes g0Z to g4Z into binary codes B0Z to B4Z.
(11) The precharge circuits 38a to 38d are connected to the four bit lines BL0a, BL0b, BL0Xa, and BL0Xb of the first encoding unit 11, and the L level output from any one bit line The other three bit lines are precharged to the power supply Vcc level by the gray code. Accordingly, the bit line precharge operation can be performed in parallel with the operation of encoding the thermometer codes e1 to e31 into the gray codes g0a, g0b, g0Xa, and g0Xb.

  (12) Each of the bit lines BL1, BL1X, BL2a, BL2b of the second and third encoding units 12, 13 is connected to one of the precharge circuits 36, 37, and is output from one bit line. The other bit line is precharged based on the level signal. Accordingly, the bit line precharge operation can be performed in parallel with the operation of encoding the thermometer codes e2 to e30 into the gray codes g1 and g1X and the binary codes g2a and g2b.

  (13) Since the thermometer code encode operation and the bit line precharge operation can be performed in parallel, it is not necessary to set a precharge time during one cycle of the encode operation. Therefore, the encoding operation can be speeded up.

  (14) In the first encoding unit 11, the bit lines are divided into four, and the same number of ROM cells are connected to each bit line, so the number of ROM cells connected to each bit line is reduced. Therefore, the load on each ROM cell can be reduced, and the encoding operation can be speeded up. In addition, unlike the encoding unit shown in FIGS. 42 and 43, in the above embodiment, one ROM cell is connected to each logical boundary detection circuit, so that the load on each logical boundary detection circuit is constant. Therefore, it is possible to prevent the occurrence of an error based on the difference in load conditions of each logical boundary detection circuit.

  (15) Compared to the normal gray code encoder shown in FIG. 45, in the above embodiment, the number of logic boundary detection circuits and ROM cells is set in order to set the back codes of gray codes g0a, g0b, and g1. However, since the number of logic boundary detection circuits and ROM cells is reduced in a normal gray code encoder as compared with an encoder that directly outputs a binary code, the encoder of the above embodiment is not directly binary. It does not increase the number of elements and the circuit area compared to an encoder that outputs a code.

  (16) The error signals er1 and er2 generated by the error signal generation unit 15 are output from the error signal output terminal to the outside. Then, when performing an operation test of the A / D converter, the error signals er1 and er2 are detected by a test device, thereby easily detecting whether or not an error has occurred in the thermometer codes e1 to e31. can do.

  In a conventional A / D converter operation test, the presence or absence of an error in a thermometer code is detected based on a binary code digital output signal. That is, by detecting the linearity of the digital output signal due to the thermometer code error or the deterioration of the S / N ratio by performing a fast Fourier transform process for obtaining the spectrum of the frequency component, the error of the thermometer code from the digital output signal is detected. Is detected.

  Therefore, in this embodiment, the operation test of the A / D converter can be performed without performing complicated processing such as the conventional fast Fourier transform processing, so that the test cost can be reduced.

(Second embodiment)
FIG. 21 shows a second embodiment of an encoder embodying the present invention. This embodiment includes first to fourth encoding units 41 to 44, an error signal generation unit 45, and a gray binary conversion unit 46.

  Since the first to third encoding units 41 to 43 and the error signal generation unit 45 have the same configuration as that of the first embodiment, description thereof is omitted. The fourth encoding unit 44 shown in FIG. 23 logically processes the logical boundary detection signals gb, gc, gf, and gg output from the third encoding unit 43 by the NOR circuits 47a and 47b and the NAND circuit 48. The gray code g2 is generated, and is the same as the circuit that generates the gray code g2 in the fourth encoding unit 14 of the first embodiment.

  The gray binary conversion unit 46 has the functions of the error correction unit 16 and the gray binary conversion unit 17 of the first embodiment, and the first to fourth encoding units 41 to 44 and Based on the signal generated by the error signal generator 45, binary codes B0Z to B4Z are generated.

  As shown in FIG. 22, the gray code g2 is inverted by the inverter circuit 49a and input to the NAND circuit 50a, and the gray code g1X and the error signal er2 are input to the NAND circuit 50a. The output signal of the NAND circuit 50a is input to the EOR circuit 52a.

  The logical boundary detection signals gf and ge are input to the NOR circuit 51a, the logical boundary detection signals gh and gg are input to the NOR circuit 51b, and the logical boundary detection signals gd and gc are input to the NOR circuit 51c. The

  The output signals of the NOR circuits 51a and 51b are input to the NAND circuit 50b, and the output signal of the NAND circuit 50b is input to the EOR circuit 52a. The output signal of the EOR circuit 52a is inverted by the inverter circuit 49b and output as a binary code B4Z. The NAND circuits 50a and 50b output a binary code for generating a binary code B4Z in which an error is corrected.

The output signals of the NOR circuits 51b and 51c are input to the NAND circuit 50c, and the output signal of the NAND circuit 50c is input to the EOR circuit 52b.
The gray code g1X and the error signal er2 are input to the NAND circuit 50d, and the output signal of the NAND circuit 50d is input to the EOR circuit 52b. The output signal of the EOR circuit 52b is inverted by the inverter circuit 49c and output as a binary code B3Z.

The NAND circuits 50c and 50d output a binary code for generating a binary code B3Z in which an error is corrected.
The binary code g2a generated by the third encoding unit 43 is input to the EOR circuit 52c, and the error signal er2 is inverted by the inverter circuit 49d and input to the EOR circuit 52c.

The output signal of the EOR circuit 52c is inverted by the inverter circuit 49f and output as the binary code B2Z and also input to the EOR circuit 52e.
The gray code g1 is input to the EOR circuit 52d, and the error signal er1 is inverted by the inverter circuit 49e and input to the EOR circuit 52d. The output signal of the EOR circuit 52d is inverted by the inverter circuit 49g and input to the EOR circuit 52e. A binary code B1Z is output from the EOR circuit 52e.

Inverter circuit 49f, 49 g outputs a binary code to generate a binary code B1Z.
The gray codes g0a and g0b generated by the first encoding unit 41 are input to the NAND circuit 50e, and the output signal of the NAND circuit 50e is input to the EOR circuit 52g.

  The binary code g2a and the gray code g1 are input to the EOR circuit 52f, and the output signal of the EOR circuit 52f is inverted by the inverter circuit 49h and input to the EOR circuit 52g. A binary code B0Z is output from the EOR circuit 52g.

The NAND circuit 50e and the inverter circuit 49h output a binary code for generating the binary code B0Z.
Further, based on the gray codes g0b, g0a, g0Xa, g0Xb, g1 and the binary code g2a, the binary code B0 is output based on the logical processing of the inverter circuits 49i and 49j, the NOR circuits 51d to 51i, and the NAND circuit 50f. . Even if the binary code B0 includes an error based on a bubble error in the signals generated by the first to third encoding units 41 to 43, the error is not corrected.

  Next, the operation of the encoder configured as described above will be described. As in the operation of the first to fourth encoding units 11 to 14 of the first embodiment, the first to fourth encoding units 41 to 44 are of type b2H bubble error as shown in FIG. When a thermometer code e1 to e31 including is input, a signal equivalent to that when a type b1 bubble error shown in FIG. 25 is input is output, and as shown in FIG. 27, a thermostat including a type b2L bubble error is output. When meter codes e1 to e31 are input, a signal in which the error is completely corrected is output. When thermometer codes e1 to e31 including a bubble error of type b1 are input as shown in FIG. A signal containing is output.

Further, the error signal generation unit 45 generates error signals er1 and er2 similar to the error signal generation unit 15 of the first embodiment.
In the gray / binary conversion unit 46, a binary code is generated by logical processing of the NOR circuits 51a and 51b and the NAND circuit 50b based on the logical boundary detection signals gf, ge, gh, and gg. As shown in FIG. 24, when a bubble error is not included in the input thermometer codes e1 to e31, the error signal er2 becomes L level, so that the output signal of the NAND circuit 50a becomes H level. Then, a signal in phase with the output signal of the NAND circuit 50b is output as the binary code B4Z.

  Further, as shown in FIGS. 22 and 25, when the error signal er2 becomes H level, the gray code g2 becomes L level, and the gray code g1X becomes H level, the output signal of the NAND circuit 50b is inverted. Are output as binary code B4Z. When the gray codes g2 and g1X and the error signal er2 are other than the above conditions, a signal in phase with the output signal of the NAND circuit 50b is output as the binary code B4Z.

  If a binary code is generated by the logical processing of the NOR circuits 51b and 51c and the NAND circuit 50c based on the logical boundary detection signals gh, gg, gd, and gc, and the error signal er2 is at the L level, the output signal of the NAND circuit 50c An in-phase signal is output as a binary code B3Z.

  As shown in FIGS. 22 and 25, when both the error signal er2 and the gray code g1X become H level, the output signal of the NAND circuit 50c is inverted and output as the binary code B3Z.

  The binary code B2Z is a signal in phase with the binary code g2a when the error signal er2 is at the L level, and becomes an inverted signal of the binary code g2a when the error signal er2 is at the H level.

  The binary code B1Z becomes an inverted signal of the gray code g1 when the binary code B2Z is at the H level and the error signal er1 is at the L level, and becomes a signal in phase with the gray code g1 when the error signal er1 is at the H level. . When the binary code B2Z is at L level and the error signal er1 is at L level, the signal is in phase with the gray code g1, and when the error signal er1 is at H level, it is an inverted signal of the gray code g1.

  The binary code B0Z is at the H level when both the gray code g1 and the binary code g2a are at the H level or the L level, and when both the gray codes g0a and g0b are at the H level, and at least one of the gray codes g0a and g0b is present. When it becomes L level, it becomes L level.

  Further, when one of the gray code g1 and the binary code g2a is at the H level and the other is at the L level, the gray code g0a and g0b are both at the L level, and at least one of the gray codes g0a and g0b is at the L level. Then, it becomes H level.

  By the above operation, as shown in FIGS. 24 to 27, even if the thermometer codes e1 to e31 include a bubble error, binary codes B0Z to B4Z in which the error is corrected are output.

A precharge circuit 53 shown in FIG. 28 is connected to the bit lines BL1 and BL1X and the bit lines BL2a and BL2b of the second and third encoding units 42 and 43, respectively.
The precharge circuit 53 is configured by adding N-channel MOS transistors 54 to 57 to the precharge circuit 36. The drain and gate of the transistor 54 are connected to the bit line BL1, and the drain and gate of the transistor 55 are connected to the bit line BL1X.

The source of the transistor 57 is connected to the bit line BL1, and the source of the transistor 55 is connected to the bit line BL1X.
The sources of the transistors 54 and 56 and the drains of the transistors 55 and 57 are connected to each other and to the gates of the transistors 55 and 57.

  In such a precharge circuit 53, for example, when the bit line BL1 becomes H level and the bit line BL1X becomes L level by the operation, the transistors 54 and 55 are turned on and the transistors 56 and 57 are turned off. At this time, since the drains and the gates of the transistors 54 and 55 are connected, they operate as diodes, and the potential difference between the bit lines BL1 and BL1X is clamped to the threshold value of the transistors 54 and 55.

  When the bit line BL1 is at L level and the bit line BL1X is at H level, the transistors 54 and 55 are turned off and the transistors 56 and 57 are turned on. At this time, since the drains and the gates of the transistors 56 and 57 are connected, they operate as diodes, and the potential difference between the bit lines BL1 and BL1X is clamped to the threshold value of the transistors 56 and 57.

The precharge circuit 53 can also be used as a precharge circuit for bit lines of the second and third encoding units 12 and 13 of the first embodiment.
In the encoder configured as described above, the following operational effects can be obtained in addition to the operational effects obtained by the encoder of the first embodiment.

  (1) In parallel with error correction based on the signals generated by the first to fourth encoding units 41 to 44 without generating the corrected gray codes G0Z to G4Z generated in the first embodiment. , Binary codes B0Z to B4Z can be generated. Therefore, since the binary codes B0Z to B4Z can be generated without the need for the gray / binary conversion unit 17 as shown in FIG. 9, the circuit scale can be reduced.

  (2) In the gray / binary conversion unit 17 shown in FIG. 9, the number of logic circuit stages increases as the lower bits of the binary codes B0Z to B4Z, and the output speed decreases, and the operation speed of the encoder depends on the output speed of the least significant bit. However, in this embodiment, since the binary codes B0Z to B4Z can be generated without using the gray / binary conversion unit 17, the operation speed of the encoder can be increased.

  (3) The gray / binary conversion unit 46 is based on the decomposition gray code and the decomposition binary code within 3 bits among the decomposition gray code and the decomposition binary code generated by the first to fourth encoding units 41 to 44. , Binary codes B0Z to B4Z can be generated. Accordingly, since the lower binary code can be generated in parallel with the generation of the upper binary code, the operation speed of the encoder can be increased.

  (4) Since the amplitude of the bit line precharged by the precharge circuit 53 is clamped below the threshold value of two N-channel MOS transistors, the bit line potential pulling speed of the ROM cell can be improved. it can. Therefore, the operation speed of the encoder can be improved.

  The clamp level of the bit line can be adjusted by changing the number of diode-connected N channel MOS transistors. Further, a PN junction diode may be used in place of the N-channel MOS transistor.

(Third embodiment)
In this embodiment, the error correction operation of the first embodiment is performed using a computer that operates based on a program. For convenience, a 3-bit binary code digital signal B0Z˜ This will be described as an encoder that generates B3Z.

  FIG. 29 shows an outline of the encoder of this embodiment. Thermometer codes e1 to e7 are input to the encoding unit 61. The encoding unit 61 generates and outputs 3-bit gray code digital signals G0 to G2 based on the thermometer codes e1 to e7. The encoder 61 has, for example, the encoder shown in FIG. 43 or 45 having a 3-bit configuration and does not have a function of correcting bubble errors included in the thermometer codes e1 to e7.

  The gray codes G0 to G3 output from the encoding unit 61 are input to an arithmetic processing unit 62 formed by a computer. A program storage unit 63 that stores a processing program is connected to the arithmetic processing unit 62.

  The arithmetic processing unit 62 operates based on the processing program, and the decomposed gray code generating means for decomposing the lower bits of the gray codes G0 to G3 has a specific relationship between the decomposed lower bits and the upper bits. An error detecting means for detecting whether or not an error exists in the generated gray code, an error correcting means for correcting the detected error, and the corrected gray code as a binary code. It operates as a gray binary conversion means for outputting as digital signals B0 to B2.

Based on the program stored in the program storage unit 63, the arithmetic processing unit 62 performs an error correction operation by one of the following operations.
<First action>
30 to 32 show a first operation of the arithmetic processing unit 62. When the gray codes G0 to G2 are input from the encoding unit 61 to the arithmetic processing unit 62, the arithmetic processing unit 62 converts the lowest gray code G0 into a table code decomposition gray code g0a, Decompose into g0b (step 1).

  As shown in FIG. 31, the program storage unit 63 corresponds to each code when the lowest gray code G0 among the normal gray codes G0 to G2 is decomposed into the decomposed gray codes g0a and g0b and the gray code. Binary code to be stored is stored in advance.

  In FIG. 31, when the separation gray code g0b is “1”, the gray code G2 is always “0”, and when the separation gray code g0a is “1”, the gray code G2 is always “1”. Therefore, the presence or absence of an error can be detected depending on whether or not this condition is satisfied.

When normal gray codes G0 to G2 are input, the normal decomposition gray codes g0a and g0b and the gray codes G1 and G2 shown in FIG. 32 are obtained.
Next, the arithmetic processing unit 62 generates an error signal based on the separated gray codes g0a and g0b and the gray code G2 (step 2). In this error signal generation process, error signals Ea and Eb are calculated by the following equations.

Ea = g0a × G2 bar
Eb = g0b × G2
{X indicates AND logic}
That is, the error signal Ea is a signal obtained by ANDing the same g0a and G2 bar when the separated gray code g0a is “1”, and the error signal Eb is the same g0b when the separated gray code g0b is “1”. This signal is the AND logic of G2.

If each gray code is normal, the error signals Ea and Eb are both “0”, and if there is an error, one of the error signals Ea and Eb is “1”.
Next, the arithmetic processing unit 62 determines the presence or absence of an error depending on whether or not at least one of the error signals Ea and Eb is “1” (step 3).

  When the error signals Ea and Eb are both “0” and it is determined that there is no error, the arithmetic processing unit 62 sets the input gray codes G0 to G2 as corrected gray codes g0Z to g2Z (step 4).

  Next, the arithmetic processing unit 62 performs gray / binary conversion on the corrected gray codes g0Z to g2Z, generates corrected binary codes B0Z to B2Z (step 5), and ends the error correction operation. In the gray / binary conversion, the arithmetic processing unit 62 performs the logical processing performed in the logic circuit shown in FIG. 9 in the first embodiment.

  On the other hand, if at least one of the error signals Ea and Eb becomes “1” in step 3 and it is determined that there is an error, the arithmetic processing unit 62 corrects the error bit (step 6).

  In this correction operation, as shown in FIG. 32, the gray codes g0a, g0b, G2 in which the error signals Ea, Eb are “1” are processed by the following expression to generate corrected gray codes g0Z, g2Z.

g2Z = (Ea + Eb) @ G2
g0Z = (Ea + Eb) @ (g0a + g0b)
{+ Indicates OR logic, @ indicates EOR logic}
That is, if at least one of the error signals Ea and Eb is “1”, G2 is inverted to generate g2Z, and g0a or g0b that has become “1” is inverted to generate g0Z. In other words, both corrected bits are inverted, and corrected gray codes g0Z and g2Z are generated.

  Next, the gray code G1 is directly used as the corrected gray code g1Z, the corrected gray codes g0Z to g2Z are generated, the gray binary conversion is performed, and the corrected binary codes B0Z to B2Z are generated (steps 4 and 5). .

  By such an operation, as shown in FIG. 32, the corrected binary codes B0Z to B2Z are more likely values than the uncorrected binary codes B0 to B2 generated based on the uncorrected gray codes G0 to G2. Become.

<Second operation>
33 to 35 show a second operation of the arithmetic processing unit 62. FIG. When the gray codes G0 to G2 are input from the encoding unit 61 to the arithmetic processing unit 62, the arithmetic processing unit 62 converts the lowest gray code G0 into a reverse code decomposition gray code g0Xa, as in the first embodiment. Decompose into g0Xb (step 11).

  As shown in FIG. 34, the program storage unit 63 corresponds to each code and its gray code when the lowest gray code G0 among the normal gray codes G0 to G2 is decomposed into the decomposed gray codes g0Xa and g0Xb. Binary code to be stored is stored in advance.

  In FIG. 34, when the separation gray code g0Xa is “1”, the gray code G1 is always “0”, and when the separation gray code g0Xb is “1”, the gray code G1 is always “1”. Therefore, the presence or absence of an error can be detected depending on whether or not this condition is satisfied.

When normal gray codes G0 to G2 are input, normal gray codes g0Xa and g0Xb and gray codes G1 and G2 shown in FIG. 35 are obtained.
Next, the arithmetic processing unit 62 performs error signal generation processing based on the separated gray codes g0Xa, g0Xb and the gray code G1 (step 12). In this error signal generation process, the error signals EXa and EXb are calculated by the following equations.

EXa = g0Xa × G1
EXb = g0Xb × G1 bar
{X indicates AND logic}
That is, the error signal EXa is an AND logic of the same g0Xa and G1 when the decomposition gray code g0Xa is “1”, and the error signal EXb is the same g0Xb and G1 when the decomposition gray code g0Xb is “1”. It is a signal that takes the AND logic of the bar.

If each gray code is normal, the error signals EXa and EXb are both “0”, and if there is an error, one of the error signals EXa and EXb is “1”.
Next, the arithmetic processing unit 62 determines the presence or absence of an error based on whether or not at least one of the error signals EXa and EXb is “1” (step 13).

  If the error signals EXa and EXb are both “0” and it is determined that there is no error, the arithmetic processing unit 62 sets the input gray codes G0 to G2 as corrected gray codes g0Z to g2Z (step 14).

  Next, the arithmetic processing unit 62 performs gray / binary conversion on the corrected gray codes g0Z to g2Z, generates corrected binary codes B0Z to B2Z (step 15), and ends the error correction operation.

  On the other hand, if at least one of the error signals EXa and EXb becomes “1” in step 13 and it is determined that there is an error, the arithmetic processing unit 62 corrects the error bit (step 16).

  In this correction operation, as shown in FIG. 35, the gray codes g0Xa, g0Xb, and G1 in which the error signals EXa and EXb are “1” are subjected to processing represented by the following expression to generate corrected gray codes g0Z and g1Z.

g1Z = (EXa + EXb) @ G1
g0Z = [(EXa + EXb) @ (g0Xa + g0Xb)] bar
{+ Indicates OR logic, @ indicates EOR logic, and bar indicates inverted logic}
That is, if at least one of the error signals EXa and EXb is “1”, G1 is inverted to generate g1Z, and g0Xa or g0Xb that has become “1” is inverted to generate g0Z. In other words, both corrected bits are inverted and corrected gray codes g0Z and g1Z are generated.

  Next, the gray code G2 is directly used as the corrected gray code g2Z, the corrected gray codes g0Z to g2Z are generated, the gray binary conversion is performed, and the corrected binary codes B0Z to B2Z are generated (steps 14 and 15). .

  By such an operation, as shown in FIG. 35, the corrected binary codes B0Z to B2Z are more likely values than the uncorrected binary codes B0 to B2 generated based on the uncorrected gray codes G0 to G2. It becomes.

<Third operation>
36 to 38 show a third operation of the arithmetic processing unit 62. When the gray codes G0 to G2 are input from the encoding unit 61 to the arithmetic processing unit 62, the arithmetic processing unit 62 converts the lowest gray code G0 into the gray code for the front and back codes similar to that of the first embodiment. The code is decomposed into g0a, g0b, g0Xa, and g0Xb (step 21).

  As shown in FIG. 37, the program storage unit 63 stores each code when the lowest gray code G0 among the normal gray codes G0 to G2 is decomposed into decomposed gray codes g0a, g0b, g0Xa, and g0Xb, and the codes thereof. A binary code corresponding to the gray code is stored in advance.

  In FIG. 37, when the separation gray code g0b is “1”, the gray code G2 is always “0”, and when the separation gray code g0a is “1”, the gray code G2 is always “1”. When the separation gray code g0Xa is “1”, the gray code G1 is always “0”, and when the separation gray code g0Xb is “1”, the gray code G1 is always “1”. Whether or not there is an error can be detected depending on whether or not the condition is satisfied.

When normal gray codes G0 to G2 are input, normal gray codes g0a, g0b, g0Xa, g0Xb and gray codes G1, G2 shown in FIG. 38 are obtained.
Next, the arithmetic processing unit 62 generates an error signal based on the separated gray codes g0Xa and g0Xb and the gray codes G1 and G2 (step 22). In this error signal generation process, the error signals Er and ErX are calculated by the following equation.

Er = (g0a × G2 bar) + (g0b × G2 = 1)
ErX = (g0Xa × G1) + (g0Xb × G1 bar)
{X represents AND logic, + represents OR logic, and bar represents inverted logic}
If each gray code is normal, the error signals Er and ErX are both “0”, and if there is an error, one of the error signals Er and ErX is “1”.

Next, the arithmetic processing unit 62 determines the presence or absence of an error based on whether or not at least one of the error signals Er and ErX is “1” (step 23).
If the error signals Er and ErX are both “0” and it is determined that there is no error, the arithmetic processing unit 62 sets the input gray codes G0 to G2 as corrected gray codes g0Z to g2Z (step 14).

  Next, the arithmetic processing unit 62 performs gray / binary conversion on the corrected gray codes g0Z to g2Z, generates corrected binary codes B0Z to B2Z (step 25), and ends the error correction operation.

  On the other hand, if at least one of the error signals Er and ErX becomes “1” in step 23 and it is determined that there is an error, the arithmetic processing unit 62 corrects the error bit (step 26).

  In this correction operation, as shown in FIG. 38, the processing shown in the following equation is performed on the decomposed gray codes g0a, g0b, g0Xa, g0Xb in which the error signals Er, ErX are “1”, and the gray codes G1, G2. Correction gray codes g0Z to g2Z are generated.

g2Z = (Er @ G2) bar
g1Z = (ErX @ G1) bar
g0Z = (Er + ErX) @ (g0a + g0b)
{+ Indicates OR logic, @ indicates EOR logic, and bar indicates inverted logic}
That is, both of the bits in error are inverted, and corrected gray codes g0Z to g2Z are generated.

Next, the corrected binary codes B0Z to B2Z are generated by performing the gray binary conversion on the corrected gray codes g0Z to g2Z (steps 24 and 25).
By such an operation, as shown in FIG. 38, the corrected binary codes B0Z to B2Z are more likely values than the uncorrected binary codes B0 to B2 generated based on the uncorrected gray codes G0 to G2. Thus, the value is more probable than the corrected binary codes B0Z to B2Z based on the first and second operations.

  In the encoder that operates as described above, a binary code in which a bubble error included in the input thermometer code is corrected is generated at high speed by the arithmetic processing unit 62 that operates based on the program stored in the program storage unit 63. be able to.

It is a principle explanatory view of the present invention. It is a block diagram which shows 1st embodiment. It is a circuit diagram which shows a 1st encoding part. It is a circuit diagram which shows a 2nd encoding part. It is a circuit diagram which shows a 3rd encoding part. It is a circuit diagram which shows a 4th encoding part. It is a circuit diagram which shows an error signal generation part. It is a circuit diagram which shows an error correction part. It is a circuit diagram which shows a gray binary conversion part. It is a circuit diagram which shows a logic boundary detection circuit. It is a circuit diagram which shows a ROM cell. It is a circuit diagram which shows a precharge circuit. FIG. 13 is a waveform diagram showing an operation of the precharge circuit of FIG. 12. It is a circuit diagram which shows a precharge circuit. FIG. 15 is a waveform diagram showing an operation of the precharge circuit of FIG. 14. It is a circuit diagram which shows a precharge circuit. It is a wave form diagram which shows operation | movement (no bubble error) of 1st embodiment. It is a wave form diagram which shows operation | movement when b1 type bubble error is input. It is a wave form diagram which shows operation | movement when b2H type bubble error is input. It is a wave form diagram which shows operation | movement when a b2L type bubble error is input. It is a block diagram which shows 2nd embodiment. It is a circuit diagram which shows a gray binary conversion part. It is a circuit diagram which shows a 4th encoding part. It is a wave form diagram which shows operation | movement (no bubble error) of 2nd embodiment. It is a wave form diagram which shows operation | movement when b1 type bubble error is input. It is a wave form diagram which shows operation | movement when b2H type bubble error is input. It is a wave form diagram which shows operation | movement when a b2L type bubble error is input. It is a circuit diagram which shows a precharge circuit. It is a block diagram which shows the encoder of 3rd embodiment. It is a flowchart figure which shows the 1st operation | movement of 3rd embodiment. It is explanatory drawing which shows the decomposition | disassembly gray code | cord | chord of a 1st operation | movement. It is explanatory drawing which shows the code produced | generated in the process of a 1st operation | movement. It is a flowchart figure which shows the 2nd operation | movement of 3rd embodiment. It is explanatory drawing which shows the decomposition | disassembly gray code | cord | chord of a 2nd operation | movement. It is explanatory drawing which shows the code | symbol produced | generated in the process of a 2nd operation | movement. It is a flowchart figure which shows the 3rd operation | movement of 3rd embodiment. It is explanatory drawing which shows the decomposition | disassembly gray code | cord | chord of a 3rd operation | movement. It is explanatory drawing which shows the code | symbol produced | generated in the process of a 3rd operation | movement. It is a circuit diagram which shows a prior art example. It is a circuit diagram which shows a ROM cell. It is explanatory drawing which shows the connection of the ROM cell in an encoding part. It is a circuit diagram which shows a prior art example. It is a circuit diagram which shows a prior art example. It is explanatory drawing which shows the connection of the ROM cell in an encoding part. It is a circuit diagram which shows the encoder which outputs a gray code. FIG. 46 is a circuit diagram showing a logic boundary detection circuit and a ROM cell of FIG. 45. It is explanatory drawing which shows the relationship between a gray code and a binary code. It is explanatory drawing which shows the relationship between the gray code at the time of encoding the thermometer code containing b1 type bubble error, and a binary code. It is explanatory drawing which shows the relationship between the gray code at the time of correcting an error, and a binary code. It is explanatory drawing which shows the input / output value at the time of encoding the thermometer code containing b1 type bubble error by a gray code system. It is explanatory drawing which shows the input / output value at the time of encoding the thermometer code containing a b2H type bubble error by a gray code system. It is explanatory drawing which shows the input / output value at the time of encoding the thermometer code containing a b2L type bubble error by a gray code system. It is explanatory drawing which shows the input / output value at the time of correcting the thermometer code containing b1 type bubble error only with the table code | cord | chord of a gray code. It is explanatory drawing which shows the input / output value at the time of correcting the thermometer code containing b1 type bubble error using the front code and back code | cord | chord of a gray code.

Explanation of symbols

41 to 44 Encoding unit 45 Error signal generation unit (error detection unit)
46 Gray Binary Conversion Unit (Error Correction Unit)
e1-e31 Thermometer code G0-G3 Gray code B0Z-B4Z Binary code

Claims (6)

A gray binary conversion method for generating a binary code of a least significant bit in a gray binary conversion circuit that generates a multi-bit binary code from a multi-bit gray code,
A first logical processing of the multi-bit decomposed gray code obtained by decomposing the least significant bit gray code to generate a first binary code ;
A plurality of signals input to generate a binary code having a bit different from the least significant bit to perform a second logical process to generate a second binary code;
A gray-binary conversion method, wherein the first and second binary codes are subjected to a third logical process to generate the least significant bit binary code. Processing a plurality of signals including a gray code of a bit different from the least significant bit in the second logic processing;
The gray binary conversion method according to claim 1, wherein:   In the second logic processing, an encoder that generates a gray code of at least 3 bits by detecting a logic boundary of the thermometer code corresponds to a binary code of the third bit from the lower order that is generated when the gray code is generated. Processing multiple signals, including signals,
The gray binary conversion method according to claim 1 or 2, wherein   A gray binary conversion circuit that generates a multi-bit binary code from a multi-bit gray code,
  A first logic circuit that logically processes a multi-bit decomposed gray code obtained by decomposing the least significant bit gray code to generate a first binary code;
  A second logic circuit for logically processing a plurality of input signals to generate a binary code of a bit different from the least significant bit to generate a second binary code;
  A third logic circuit that logically processes the first and second binary codes to generate the least significant bit binary code;
A gray binary conversion device characterized by comprising:   The signal input to the second logic circuit includes a gray code of a bit different from the least significant bit;
The gray binary conversion apparatus according to claim 4, wherein:   A signal input to the second logic circuit is generated when the gray code is generated in an encoding unit that generates a gray code of at least 3 bits by detecting a logic boundary of a thermometer code. Including a signal equivalent to a binary code,
The gray binary conversion apparatus according to claim 4 or 5, characterized in that:

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