JP4188980B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a liquid crystal display device equipped with a thin film transistor (hereinafter referred to as TFT) and a method for manufacturing the same.

In recent years, liquid crystal display devices equipped with TFTs have been used in a wide range of applications such as notebook personal computers, desktop displays, and portable terminals by taking advantage of their thinness, light weight, and low power consumption. ing.
A liquid crystal display device equipped with a conventional TFT has a TFT and pixel electrodes formed around a gate electrode, a source electrode, a semiconductor layer, and the like arranged in a matrix on an insulating substrate, and an electrode wiring formed around the pixel electrode. A first substrate (TFT array substrate) having (gate electrode wiring, source electrode wiring), a black matrix (hereinafter referred to as BM) on another insulating substrate, and a second substrate having a counter electrode (counter substrate) ) Are opposed to each other and bonded together, and a liquid crystal material is injected between the first substrate and the second substrate.

In order to extend the advantages of the liquid crystal display device such as thinness, light weight, and low power consumption, it is effective to increase the effective display area of the pixel portion of the liquid crystal display panel, that is, to improve the aperture ratio of the pixel. Conventionally, in a TFT array using TN liquid crystal, which is most widely used, an alignment abnormality due to a step such as a TFT or electrode wiring, or an electric field different from the electric field of the pixel electrode due to the electrode wiring formed around the pixel electrode. Since light leaks due to the occurrence, it is necessary to widen the formation region of the BM provided on the counter substrate in order to prevent these display defects, and it is difficult to increase the aperture ratio of the pixels.
As a method for solving the above problem, after forming TFTs and electrode wirings on an insulating substrate, an interlayer insulating film is formed so as to cover them, and then flattened. A method of forming a pixel electrode having a large area on an interlayer insulating film by overlapping is proposed. For example, Japanese Patent Laid-Open No. 9-127553 discloses a high aperture ratio using an interlayer insulating film made of a transparent resin. A TFT array structure is disclosed.

FIG. 23 is a schematic plan view showing an example of a TFT array substrate of a liquid crystal display device having a conventional high aperture ratio TFT array structure. FIG. 23A shows a terminal conversion portion outside the display area, and FIG. A pixel portion in the region is shown. 24 is a cross-sectional view showing a manufacturing process of the part along the line AB in FIG. 23, FIG. 25 is the part along the line CD in FIG. 23, and FIG. FIG. In the figure, 1 is a transparent insulating substrate such as a glass substrate, 2 is a gate electrode wiring formed on the transparent insulating substrate 1, 2a is a gate electrode formed by extending from the gate electrode wiring 2, and 3 is a transparent insulating substrate. Common wiring formed on the conductive substrate 1, 4 is a gate insulating film formed on the gate electrode 2a layer, 5 is an amorphous silicon (hereinafter referred to as a-Si) film formed on the gate insulating film 4, and A semiconductor layer made of a low-resistance amorphous silicon (hereinafter referred to as n ⁺ -a-Si) film doped with impurities, 6 is a source electrode wiring, 6a is a source electrode formed extending from the source electrode wiring 6, 7 Is a drain electrode paired with the source electrode 6, 8 is a common lead wiring formed in the same layer as the source electrode wiring 7, 9 is a channel portion, 10 is an interlayer insulating film, and 11 is a drain constituting a storage capacitor 14. A contact hole formed on the emission electrode 7, 12 is a pixel electrode formed on the interlayer insulating film 10, it is electrically connected to the drain electrode 8 through the contact hole 11. Reference numeral 13 denotes a TFT, 14 denotes a storage capacitor, 15 denotes a terminal converter provided outside the display area of the common wiring 3, and the common wiring 3 is connected to the common lead-out wiring 8 in the terminal converter 15. Reference numeral 16 denotes a wiring intersection between the gate electrode wiring 2 or the common wiring 3 and the source electrode wiring 6 or the common lead-out wiring 8. 28 is a contact hole formed on the common lead wire 8 of the terminal converter 15, 29 is a contact hole formed on the common wire 3 of the terminal converter 15, and 30 is an ITO film formed simultaneously with the formation of the pixel electrode 12. Reference numeral 31 denotes a passivation film formed on the TFT 13.

Next, a manufacturing process of a TFT array substrate of a conventional liquid crystal display device will be described with reference to FIGS.
First, as shown in FIG. 24A, FIG. 25A, and FIG. 26A, a Cr film was formed on the surface of the transparent insulating substrate 1 using a sputtering method or the like, and was formed by a photolithography method. The gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 are formed by patterning using a resist.
Next, as shown in FIG. 24B, FIG. 25B, and FIG. 26B, silicon nitride, a-Si, n ⁺ -a constituting the gate insulating film 4 using a plasma CVD method or the like. After sequentially forming -Si, the n.sup. ⁺ -A-Si film and the a-Si film are patterned using a resist formed by photolithography to form an a-Si film and an n.sup. ⁺ -A-Si film. The semiconductor layer 5 is formed.
Next, as shown in FIG. 24C, FIG. 25C, and FIG. 26C, a Cr film is formed by sputtering and patterned using a resist formed by photolithography to form a source electrode. A wiring 6, a source electrode 6a, a drain electrode 7, and a common lead wiring 8 are formed, and a portion of the n ⁺ -a-Si film on the gate electrode 2a that is not covered with the source electrode 6a and the drain electrode 7 is dry-etched. Etching is performed to form the channel portion 9 to form the TFT 13.

Next, a passivation film 31 is formed by depositing silicon nitride.
Next, an acrylic transparent resin having photosensitivity is applied so as to absorb the level difference caused by the TFT 13 and the wiring and the surface is flattened, and is patterned by photolithography to face the common wiring 3 of the drain electrode 7. Contact holes 28 and 29 are formed on the contact hole 11 and the common lead-out wiring 8 and the common wiring 3 of the terminal conversion unit 15 on the portion constituting the storage capacitor 14. Thereafter, baking is performed to form the interlayer insulating film 10. Subsequently, using the interlayer insulating film 10 as a mask, the passivation film 31 on the drain electrode 7 and the common lead-out wiring 8 exposed by the contact holes 11, 28 and 29, and the passivation film 31 and the gate insulating film 4 on the common wiring 3 are formed. Etching is performed to expose the drain electrode 7 in the contact hole 11, the common extraction wiring 8 in the contact hole 28, and the common wiring 3 in the contact hole 29 (FIGS. 24D, 25D, and 26D). .
Next, as shown in FIGS. 24E, 25E, and 26E, an ITO film is formed by a sputtering method, and then patterned using a resist formed by a photolithography method to form a pixel. The electrode 12 and the connection wiring 30 are formed. At this time, the pixel electrode 12 is electrically connected to the drain electrode 7 through the contact hole 11, and the common lead-out wiring 8 and the common wiring 3 of the terminal converter 15 are electrically connected through the contact holes 28 and 29 and the connection wiring 30. Connected. The TFT array substrate is formed by the above process.

A conventional liquid crystal display device having a high aperture ratio TFT array structure is configured as described above, and includes a gate electrode wiring 2 and the like under the interlayer insulating film 10 and a pixel electrode 12 formed on the interlayer insulating film 10. In order to make an electrical connection, it is necessary to pattern the interlayer insulating film 10 and then etch the gate insulating film 4 on the common wiring 3 using the interlayer insulating film 10 as a mask. The interlayer insulating film 10 is a gate insulating film. Since the etching selectivity with respect to the gate insulating film 4 is small, the interlayer insulating film 10 is also etched during the etching of the gate insulating film 4, resulting in a reduction in film thickness. There was a problem. In addition, the overlapping capacity between the pixel electrode 12 on the interlayer insulating film 10 and the underlying source electrode wiring 6 and gate electrode wiring 2 is increased, causing display defects such as luminance change, crosstalk, and shot unevenness.
As a method for solving the above problem, a method of increasing the thickness of the interlayer insulating film is conceivable. However, in a large substrate, it is difficult to increase the thickness while maintaining in-plane uniformity. Although a transparent resin having photosensitivity is used, the transparent resin having photosensitivity is expensive, and increasing the film thickness causes an increase in cost.

  The present invention has been made to solve the above-described problems, and suppresses a reduction in the thickness of an interlayer insulating film made of a resin used for planarization, and has a high aperture ratio with good display characteristics. An object of the present invention is to obtain a liquid crystal display device with a high yield. Furthermore, it aims at providing the manufacturing method suitable for this apparatus.

The liquid crystal display device according to the present invention includes an insulating substrate, a scanning electrode, a scanning electrode wiring and a common wiring formed on the insulating substrate, covering the scanning electrode, and a predetermined number of the scanning electrode wiring and the common wiring. a semiconductor layer formed so as to cover the portion, formed under the above insulating substrate of the semiconductor layer is etched by the same mask and the semiconductor layer, the non-formation region of the semiconductor layer, its etching A first electrode, a second electrode, and a first electrode constituting a semiconductor element together with an insulating film whose portion is a residual film that is thinner than a formation region of the semiconductor layer, and a semiconductor layer on the scan electrode; The first electrode wiring connected to the first electrode, and the scanning electrode, the scanning electrode wiring, the common wiring, the semiconductor layer, the first electrode, the first electrode wiring, and the second electrode are formed in an upper layer. Made of resin A pixel electrode made of a conductive film formed on the interlayer insulating film and electrically connected to the second electrode through a first contact hole formed in the interlayer insulating film; A common lead wire formed on the insulating substrate in the same layer as the first electrode wire and the same material as the pixel electrode, and electrically connects the common lead wire and the common wire. A first substrate having a terminal conversion portion outside the display region including a connection wiring to be connected, and a second substrate sandwiching a liquid crystal material together with the first substrate, the semiconductor layer comprising the semiconductor element component, And the storage capacitor portion formed at the intersection of the scan electrode wiring or the common wiring and the first electrode wiring or the common lead-out wiring, the common wiring facing the second electrode. Shape Sarezu, the thickness of thin residual film of the insulating film is formed, characterized in that the storage capacitor by a thin residual film of this thickness has been formed.

In the liquid crystal display device manufacturing method according to the present invention, the first and second insulating substrates are bonded to each other, and a liquid crystal material is sandwiched between the first and second insulating substrates. In the manufacturing method of the liquid crystal display device, the step of forming the scan electrode, the scan electrode wiring and the common wiring on the first insulating substrate, and the first electrode so as to cover the scan electrode, the scan electrode wiring and the common wiring An insulating film is formed on the insulating substrate, and a semiconductor film is formed on the insulating film. Then, the semiconductor film is patterned using the same mask to cover the scanning electrode, and to the scanning electrode wiring and the common wiring. Forming a semiconductor layer covering a predetermined portion of the insulating layer, etching the insulating film, and forming the etched portion as a residual film having a thickness smaller than that of the semiconductor layer forming portion. The membrane A step of covering the common wiring with a terminal conversion portion outside the display area of the insulating substrate, and a first electrode, a second electrode, and a first electrode constituting a semiconductor element together with a semiconductor layer on the scan electrode A step of forming a common lead wire in the connected first electrode wire and the terminal converter, and the first electrode, the first electrode wire, the second electrode, and the common lead wire so as to cover A photosensitive resin is applied on the first insulating substrate, exposed to light and developed to form a first contact hole on the second electrode, and a second contact on the common lead wiring of the terminal converter. Forming an interlayer insulating film having a third contact hole on the common wiring of the hole and the terminal converter, and using the interlayer insulating film as a mask, the insulating film exposed by the third contact hole. Etching the remaining thin film, forming a conductive film on the interlayer insulating film and in the first, second and third contact holes, and patterning the second electrode. And a pixel electrode electrically connected via the first contact hole, and a connection for electrically connecting the common lead wire and the common wire via the second contact hole and the third contact hole. A step of forming a wiring, wherein the semiconductor layer is formed at the intersection of the semiconductor element component and the scanning electrode wiring or the common wiring and the first electrode wiring or the common lead wiring. In the storage capacitor portion where the wiring faces the second electrode, the semiconductor film is removed to form a thin residual film of the insulating film, and the thin residual film forms the storage capacity. It is characterized by being made.

According to the present invention, in a TFT array having an interlayer insulating film formed on a TFT or wiring and flattening a step due to the TFT or wiring, the gate insulating film is formed in the same region as the semiconductor layer, and the semiconductor layer forming region is formed. In other cases, patterning as a residual film having a smaller thickness than the formation region of the semiconductor layer reduces the reduction in the thickness of the interlayer insulating film in the etching process of the gate insulating film using the interlayer insulating film as a mask. A high aperture ratio liquid crystal display device with good display characteristics can be obtained with a high yield, which can prevent a short circuit through a pinhole of the film and an increase in the overlap capacitance between the pixel electrode on the interlayer insulating film and the lower layer wiring. Can do.
In addition, since the film thickness of the interlayer insulating film is reduced , it is possible to previously form a thin film of expensive photosensitive resin, and the manufacturing cost can be reduced.
Further, the liquid crystal display device according to the present invention does not require an increase in the number of processes or a new process as compared with the conventional one . Further, by thinning the gate insulating film of the storage capacitor component, the overlapping area between the common wiring and the second electrode for forming the same storage capacitor can be reduced, so the thin wire of the common wiring of the storage capacitor component reduction can be, thereby improving the aperture ratio.
The TFT array structure of this configuration can also be applied to a structure having a passivation film, and the same effect can be obtained.
The TFT array structure of this configuration can also be applied to a reflective liquid crystal display device.

Embodiment 1 FIG.
Hereinafter, a liquid crystal display device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic plan view showing a TFT array substrate of a liquid crystal display device in which TFTs are mounted as switching elements according to Embodiment 1 of the present invention. FIG. 1 (a) is a terminal conversion unit outside the display area, and FIG. ) Indicates a pixel portion in the display area. 2 is a cross-sectional view showing a manufacturing process of a part taken along line AB in FIG. 1, FIG. 3 is a part taken along line CD in FIG. 1, and FIG. FIG.
In the figure, 1 is a transparent insulating substrate such as a glass substrate, 2 is a scanning electrode wiring (gate electrode wiring in the present embodiment) formed on the transparent insulating substrate 1, and 2 a is extended from the gate electrode wiring 2. The formed scanning electrode (in this embodiment, a gate electrode), 3 is a common wiring formed on the transparent insulating substrate 1, and 4 is a gate formed on the gate electrode wiring 2, the gate electrode 2a and the common wiring 3. The insulating film 5 includes an amorphous silicon (hereinafter referred to as a-Si) film formed on the gate insulating film 4 and a low-resistance amorphous silicon (hereinafter referred to as n ⁺ -a-Si) film doped with impurities. 6 is a first electrode wiring (source electrode wiring in the present embodiment), 6a is a first electrode formed extending from the source electrode wiring 6 (source electrode in the present embodiment), 7 Is A second electrode (a drain electrode in this embodiment) that forms a pair with the source electrode 6, 8 is a common lead wiring formed in the same layer as the source electrode wiring 7, 9 is a channel portion, 10 is an interlayer insulating film, 11 Is a first contact hole (hereinafter referred to as contact hole 11) formed on the drain electrode 7 constituting the storage capacitor 14, and 12 is a pixel electrode formed on the interlayer insulating film 10 via the contact hole 11. Are electrically connected to the drain electrode 7. Reference numeral 13 denotes a TFT, 14 denotes a storage capacitor, 15 denotes a terminal converter provided outside the display area of the common wiring 3, and the common wiring 3 is connected to the common lead-out wiring 8 in the terminal converter 15. Reference numeral 16 denotes a wiring intersection between the gate electrode wiring 2 or the common wiring 3 and the source electrode wiring 6 or the common lead-out wiring 8.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIGS. 2 (a), 3 (a), and 4 (a), Al, Cr, Mo, W, Ti, Ta, and the like are formed on the surface of the transparent insulating substrate 1 using a sputtering method or the like. One of Cu, an alloy containing these as a main component, or a laminated film thereof is formed and patterned using a resist formed by a photolithography method to form the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 Form.
Next, as shown in FIGS. 2B, 3B, and 4B, the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 are covered using a plasma CVD method or the like. Then, silicon nitride, a-Si, and n ⁺ -a-Si constituting the gate insulating film 4 are sequentially formed on the transparent insulating substrate 1 and then sequentially patterned into the same pattern using a resist formed by photolithography. Then, the patterned gate insulating film 4 and the semiconductor layer 5 composed of the a-Si film and the n ⁺ -a-Si film are formed. Note that the patterned gate insulating film 4 and the semiconductor layer (a-Si film and n ⁺ -a-Si film) 5 having the same shape cover the gate electrode 2 a and form the storage capacitor 14 on the common wiring 3. The gate electrode wiring 2, the wiring intersection 16 between the common wiring 3 and the source electrode wiring 6, and the intersection 16 between the gate electrode wiring 2 and the common extraction wiring 8 are covered. As shown in FIG. 4, the common wiring 3 and the common lead-out wiring 8 are not formed in the terminal conversion portion 15 where they intersect.

Next, as shown in FIGS. 2C, 3C, and 4C, the gate electrode wiring 2 and the like are formed on the transparent insulating substrate so as to cover the patterned semiconductor layer 5 by sputtering. A metal thin film (Al, Cr, Mo, W, Ti, Ta and Cu, or an alloy containing these as a main component, or a laminated film thereof) that can be selectively etched with the metal constituting Then, patterning is performed using a resist formed by a photolithography method to form the source electrode wiring 6, the source electrode 6a, the drain electrode 7, and the common lead-out wiring 8, and is not covered with the source electrode 6a and the drain electrode 7. The n ⁺ -a-Si film on the partial gate electrode 2a is etched by a dry etching method or the like to form the channel portion 9, and the TFT 13 is formed. The source electrode 6a and the drain electrode 7 form a TFT 13 together with the semiconductor layer 5 on the gate electrode 2a, and the common lead-out line 8 is formed outside the display area so as to intersect the gate electrode line 2 and the common line 3. The common lead wire 8 is directly electrically connected to the common wire 3 in the terminal converter 15.

Next, as shown in FIGS. 2 (d), 3 (d), and 4 (d), an acrylic transparent resin having photosensitivity so as to absorb the level difference caused by the TFT 13 and the wiring and to flatten the surface. Then, a contact hole 11 is formed on a portion of the drain electrode 7 facing the common wiring 3 and constituting the storage capacitor 14. Thereafter, baking is performed to form the interlayer insulating film 10.
Next, as shown in FIGS. 2 (e), 3 (e), and 4 (e), a transparent conductive film such as ITO, indium oxide, tin oxide or the like is formed using a sputtering method or the like. The pixel electrode 12 is formed by patterning using a resist formed by lithography. At this time, the pixel electrode 12 is electrically connected to the drain electrode 7 through the contact hole 11. As shown in FIG. 1B, the pixel electrode 12 is formed so as to overlap the gate electrode wiring 2, the gate electrode 2a, the source electrode wiring 6, and the source electrode 6a.

The TFT array substrate (first substrate) and the counter substrate (second substrate) formed by the above steps are bonded together, and a liquid crystal material is injected therebetween, and an image signal is applied to the gate electrode wiring 2 and the source electrode wiring 6. Is connected, and a backlight unit is attached to form a desired liquid crystal display device.
In the liquid crystal display device formed in this way, the step due to the TFT 13 and the wiring is flattened by the interlayer insulating film 10, so that no alignment abnormality due to the step occurs. In addition, since the pixel electrode 12 is overlapped with the source electrode wiring 6 and the gate electrode wiring 2 via the interlayer insulating film 10, there is no alignment abnormality caused by the electric field of the electrode wiring.

  FIG. 5 shows an equivalent circuit of the TFT array. In the figure, 17 is a gate terminal (G1, G2,... Gn) formed at the substrate end extending from the gate electrode wiring 2, and 18 is a source formed at the substrate end extending from the source electrode wiring 6. Terminals (S1, S2,... Sn), 19 are common terminals formed at the end of the substrate extending from the common lead wiring 8. 22 is a liquid crystal capacitor formed between the pixel electrode 12 and the counter electrode on the counter substrate, 23 and 24 are overlapping capacities of the pixel electrode 12 and the source electrode wiring 6, and 23 is the source electrode wiring 6 in the same pixel. The overlapping capacitances Cds1, 24 are the overlapping capacitance Cds2 with the source electrode wiring 6 of the adjacent pixel. 25 and 26 are overlapping capacitances between the pixel electrode 12 and the gate electrode wiring 2, 25 is an overlapping capacitance Cgd1 with the gate electrode wiring 2 in the same pixel, and 26 is an overlapping capacitance Cgd2 with the gate electrode wiring 2 of the adjacent pixel. .

In this embodiment, since the gate insulating film 4 is patterned in the same shape as the semiconductor layer 5, the step in this portion becomes large, and there is a high possibility that the step will be cut off in the source electrode wiring 6 and the like formed in the upper layer. Become. In order to prevent this, it is desirable to use taper etching in the etching process of the gate insulating film 4.
In this embodiment, the case where the storage capacitor 14 is formed by the common wiring 3 and the drain electrode 7 has been described. However, the storage capacitor 14 is formed by overlapping the gate electrode wiring and the drain electrode without having the common wiring. The present invention can also be applied to a liquid crystal display device having a structure.
Further, in this embodiment, the pixel electrode 12 is formed so as to overlap both the gate electrode wiring 2 and the source electrode wiring 6, but the liquid crystal display device has a structure that overlaps only one electrode wiring or does not overlap. Applicable.
In this embodiment mode, a liquid crystal display device having a channel etch type TFT array structure has been described. However, the present invention can also be applied to a liquid crystal display device having an etching stopper type TFT array structure.

According to the present invention, the gate insulating film 4 is patterned with the same mask as the semiconductor layer 5, and is a region other than the electrode wiring intersection 16, the TFT 13 formation region on the gate electrode 2 a and the storage capacitor 14 formation region on the common wiring 3. Therefore, the gate insulating film 4 is not formed on the common wiring 3 of the terminal converter 15, and the common lead-out wiring 8 can be directly formed on the common wiring 3 to be electrically connected. This eliminates the need for the etching process of the gate insulating film 4 using the interlayer insulating film 10 as a mask, which has been conventionally required in the terminal conversion unit 15, and does not reduce the thickness of the interlayer insulating film 10. It does not induce a yield reduction due to a short circuit through a hole or an increase in overlap capacitances 23, 24, 25, 26 between the pixel electrode 12 on the interlayer insulating film 10 and the lower gate electrode wiring 2 or source electrode wiring 6, Occurrence of display defects such as luminance change, crosstalk, and shot unevenness can be suppressed. In addition, since it is not necessary to consider the reduction in the thickness of the interlayer insulating film 10, it is possible to previously form a thin transparent resin film having high photosensitivity, thereby reducing the manufacturing cost.
Further, the liquid crystal display device according to the present embodiment does not require an increase in the number of processes or a new process as compared with the conventional one.

Embodiment 2. FIG.
FIG. 6 is a schematic plan view showing a TFT array substrate of a liquid crystal display device in which a TFT is mounted as a switching element according to Embodiment 2 of the present invention. FIG. 6 (a) is a terminal conversion unit outside the display area, and FIG. ) Indicates a pixel portion in the display area. 7 is a cross-sectional view showing a manufacturing process of a portion along the line AB in FIG. 6, FIG. 8 is a portion along the line CD in FIG. 6, and FIG. 9 is a cross-sectional view showing a manufacturing process of the portion along the line EF in FIG. FIG.
In the figure, 28 is a second contact hole (hereinafter referred to as contact hole 28) formed on the common lead wire 8 of the terminal converter 15, and 29 is a second contact hole formed on the common wire 3 of the terminal converter 15. Three contact holes (hereinafter referred to as contact holes 29) and 30 are connection wirings made of an ITO film formed at the same time as the pixel electrode 12 is formed. In addition, the same code | symbol is attached | subjected to FIG. 1-4 same part, and description is abbreviate | omitted.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIGS. 7 (a), 8 (a), and 9 (a), a Cr film having a thickness of 400 nm is formed on the surface of the transparent insulating substrate 1 by sputtering or the like, and is formed by photolithography. The gate electrode wiring 2, the gate electrode 2a and the common wiring 3 are formed by patterning using the resist.
Next, as shown in FIGS. 7B, 8B, and 9B, using a plasma CVD method or the like, the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 are covered. On the transparent insulating substrate 1, 400 nm of silicon nitride, 150 nm of a-Si, and 30 nm of n ⁺ -a-Si are sequentially formed on the transparent insulating substrate 1, and then the same pattern is formed using a resist formed by photolithography. Then, the semiconductor layer 5 composed of the gate insulating film 4 and the a-Si film and the n ⁺ -a-Si film is formed. At this time, the semiconductor layer 5 is patterned, and the etched portion of the gate insulating film 4 is etched until the remaining film thickness reaches 200 nm with respect to the film thickness of 400 nm. Note that the gate insulating film 4 and the semiconductor layer 5 having the same shape and a thickness of 400 nm cover the gate electrode 2a and the portion on the common wiring 3 where the storage capacitor 14 is formed, and the gate electrode wiring 2 and the common wiring 3 Although formed so as to cover the wiring intersection 16 with the source electrode wiring 6 and the intersection 16 between the gate electrode wiring 2 and the common lead-out wiring 8, as shown in FIG. 3 is covered with a thin remaining film portion of the etched gate insulating film 4.

Next, as shown in FIG. 7C, FIG. 8C, and FIG. 9C, a Cr film is formed to a thickness of 400 nm using a sputtering method or the like, and patterned using a resist formed by a photolithography method. Then, the source electrode wiring 6, the source electrode 6a, the drain electrode 7, and the common lead wiring 8 are formed, and the n ⁺ -a-Si film on the gate electrode 2a that is not covered with the source electrode 6a and the drain electrode 7 Is etched by a dry etching method or the like to form the channel portion 9 and the TFT 13 is formed. The source electrode 6a and the drain electrode 7 form a TFT 13 together with the semiconductor layer 5 on the gate electrode 2a. As shown in FIG. 9C, the common lead-out wiring 8 is formed on the thin remaining film portion of the gate insulating film 4 in the terminal conversion portion 15.

  Next, as shown in FIGS. 7 (d), 8 (d), and 9 (d), an acrylic transparent resin having photosensitivity so as to absorb the level difference caused by the TFT 13 and the wiring to flatten the surface. And is patterned by photolithography, and is common to the contact hole 11 and the common lead-out wiring 8 of the terminal converter 15 on the portion of the drain electrode 7 facing the common wiring 3 and forming the storage capacitor 14. Contact holes 28 and 29 are formed on the wiring 3. Thereafter, baking is performed to form the interlayer insulating film 10. Subsequently, using the interlayer insulating film 10 as a mask, the gate insulating film 4 on the common wiring 3 exposed through the contact hole 29 is etched to expose the common wiring 3 in the contact hole 29.

  Next, as shown in FIGS. 7 (e), 8 (e), and 9 (e), ITO is deposited to a thickness of 100 nm using a sputtering method or the like, and then patterned using a resist formed by a photolithography method. Thus, the pixel electrode 12 and the connection wiring 30 are formed. At this time, the pixel electrode 12 is electrically connected to the drain electrode 7 through the contact hole 11, and the common lead-out wiring 8 and the common wiring 3 of the terminal converter 15 are electrically connected through the contact holes 28 and 29 and the connection wiring 30. Connected. As shown in FIG. 6B, the pixel electrode 12 is formed with an overlap portion having a width of 3 μm via the gate electrode wiring 2 and the source electrode wiring 6 and the interlayer insulating film 10.

The TFT array substrate (first substrate) and the counter substrate (second substrate) formed by the above steps are bonded together, and a liquid crystal material is injected therebetween, and an image signal is applied to the gate electrode wiring 2 and the source electrode wiring 6. Is connected, and a backlight unit is attached to form a desired liquid crystal display device.
In the liquid crystal display device formed in this way, the step due to the TFT 13 and the wiring is flattened by the interlayer insulating film 10, so that no alignment abnormality due to the step occurs. In addition, since the pixel electrode 12 is overlapped with the source electrode wiring 6 and the gate electrode wiring 2 via the interlayer insulating film 10, there is no alignment abnormality caused by the electric field of the electrode wiring.

In this embodiment, the two gate electrode wiring layers are formed using a 400 nm Cr film, but the film thickness and material are not limited to these, and the film thickness is 100 nm to 500 nm, and the material is Al. Any of Mo, W, Ti, Ta and Cu, an alloy containing these as a main component, or a laminated film thereof may be used. The same applies to the six layers of source electrode wiring. Further, in order to prevent the upper layer from being cut off at the portion where the wiring intersects, it is desirable to use taper etching in the patterning process of the two gate electrode wiring layers.
In this embodiment, the film thickness of the gate insulating film 4 is 400 nm and the remaining film thickness after etching is 200 nm. However, the film thickness is not particularly limited, and the film thickness is 200 nm to 600 nm. The remaining film thickness may be 300 nm or less. Note that this film thickness is a case where a silicon nitride film is used as the material of the gate insulating film 4, and is different when another material such as a silicon oxide film or an organic insulating film is used. Similarly, the thicknesses of the a-Si film and the n ⁺ -a-Si film constituting the semiconductor layer 5 are not limited.

In this embodiment, since the gate insulating film 4 is patterned with the same mask as the semiconductor layer 5, the step in this portion becomes large, and there is a high possibility that a step break will occur in the source electrode wiring 6 and the like formed in the upper layer. Become. In order to prevent this, it is desirable to use taper etching in the etching process of the gate insulating film 4.
In this embodiment, the case where the storage capacitor 14 is formed by the common wiring 3 and the drain electrode 7 has been described. However, the storage capacitor 14 is formed by overlapping the gate electrode wiring and the drain electrode without having the common wiring. The present invention can also be applied to a liquid crystal display device having a structure.
Further, in this embodiment, the pixel electrode 12 is formed so as to overlap both the gate electrode wiring 2 and the source electrode wiring 6, but the liquid crystal display device has a structure that overlaps only one electrode wiring or does not overlap. Applicable.
In this embodiment mode, a liquid crystal display device having a channel etch type TFT array structure has been described. However, the present invention can also be applied to a liquid crystal display device having an etching stopper type TFT array structure.

In the present embodiment, a contact hole 29 is formed in the interlayer insulating film 10 in order to connect the common wiring 3 and the common lead-out wiring 8 using the connection wiring 30 formed simultaneously with the pixel electrode 12 in the terminal converter 15. After that, the gate insulating film 4 is etched using the interlayer insulating film 10 as a mask. This portion of the gate insulating film 4 is etched to a residual film thickness of about 200 nm when the semiconductor layer 5 is patterned as shown in FIG. Therefore, the etching time is shorter than in the conventional process in which the gate insulating film 4 is not patterned, and the film loss of the interlayer insulating film 10 during the etching of the gate insulating film 4 is small. Decrease in yield due to short-circuiting, and overlap capacitance between the pixel electrode 12 on the interlayer insulating film 10 and the lower gate electrode wiring 2 and source electrode wiring 6 Without inducing increased, luminance variation and crosstalk, the display defective shot unevenness can be suppressed. In addition, since it is not necessary to consider the reduction in the thickness of the interlayer insulating film 10, it is possible to previously form a thin transparent resin film having high photosensitivity, thereby reducing the manufacturing cost.
Further, the liquid crystal display device according to the present embodiment does not require an increase in the number of processes or a new process as compared with the conventional one.

Embodiment 3 FIG.
FIG. 10 is a schematic plan view showing a TFT array substrate of a liquid crystal display device in which TFTs are mounted as switching elements according to Embodiment 3 of the present invention. FIG. 10 (a) is a terminal conversion unit outside the display area, and FIG. ) Indicates a pixel portion in the display area. 11 is a section taken along line AB in FIG. 10, FIG. 12 is a section taken along line CD in FIG. 10, and FIG. 13 is a cross-sectional view showing a manufacturing process of the part taken along line EF in FIG. FIG.
In the figure, 2b is an upper layer wiring of the gate electrode wiring 2 (in this embodiment, a gate upper layer wiring), 3b is an upper layer wiring of the common wiring 3 (in this embodiment, a common upper layer wiring), and 6b is a source electrode wiring 6. Lower layer wiring (source lower layer wiring in this embodiment). In addition, the same code | symbol is attached | subjected to FIGS. 1-4 and the same part, and description is abbreviate | omitted.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIGS. 11 (a), 12 (a), and 13 (a), Al, Cr, Mo, W, Ti, Ta, and the like are formed on the surface of the transparent insulating substrate 1 using a sputtering method or the like. One of Cu, an alloy containing these as a main component, or a laminated film thereof is formed and patterned using a resist formed by a photolithography method to form the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 Form. At this time, the source lower layer wiring 6 b is simultaneously formed in the formation region of the source electrode wiring 6 excluding the TFT 13 formation region and the wiring intersection 16.
Next, as shown in FIG. 11B, FIG. 12B, and FIG. 13B, silicon nitride, a-Si, and n ⁺ -a constituting the gate insulating film 4 using a plasma CVD method or the like. After sequentially forming -Si, a gate insulating film 4 and a semiconductor layer 5 composed of an a-Si film and an n ⁺ -a-Si film are formed by sequentially patterning in the same pattern using a resist formed by photolithography. Form. Note that the gate insulating film 4 and the semiconductor layer 5 having the same shape are formed on the gate electrode 2 a, the common wiring 3 forming the storage capacitor 14, and the wiring intersection 16.

Next, as shown in FIGS. 11 (c), 12 (c), and 13 (c), a metal thin film (Al, Cr) that can be selectively etched with the metal constituting the gate electrode wiring 2 and the like by sputtering. , Mo, W, Ti, Ta and Cu, or an alloy containing these as a main component, or a laminated film of these), and patterning using a resist formed by a photolithography method, Electrode wiring 6, source electrode 6a, drain electrode 7 and common lead-out wiring 8 are formed. At this time, the gate upper layer wiring 2 b and the common upper layer wiring 3 b are simultaneously formed on the gate electrode wiring 2 and the common wiring 3 excluding the formation region of the TFT 13 and the storage capacitor 14 and the wiring intersection 16. Thereby, the gate electrode wiring 2, the common wiring 3 and the source electrode wiring 6 excluding the TFT 13 formation region and the wiring intersection 16 have a two-layer film structure.
Subsequently, the n ⁺ -a-Si film on the portion of the gate electrode 2a not covered with the source electrode 6a and the drain electrode 8 is etched by a dry etching method or the like to form the channel portion 9, and the TFT 13 is formed.

Next, as shown in FIG. 11 (d), FIG. 12 (d), and FIG. 13 (d), an acrylic transparent resin having photosensitivity so as to absorb the level difference caused by the TFT 13 and the wiring and to flatten the surface. Then, a contact hole 11 is formed on the portion of the drain electrode 7 facing the common wiring 3 and forming the storage capacitor 14. Thereafter, baking is performed to form the interlayer insulating film 10.
Next, as shown in FIGS. 11 (e), 12 (e), and 13 (e), a transparent conductive film such as ITO, indium oxide, or tin oxide is formed using a sputtering method or the like. The pixel electrode 12 is formed by patterning using a resist formed by lithography. At this time, the pixel electrode 12 is electrically connected to the drain electrode 7 through the contact hole 11. As shown in FIG. 10B, the pixel electrode 12 is formed so as to overlap with the gate electrode wiring 2, the gate electrode 2a, the source electrode wiring 6, and the source electrode 6a.

  The TFT array substrate (first substrate) and the counter substrate (second substrate) formed by the above steps are bonded together, and a liquid crystal material is injected therebetween, and an image signal is applied to the gate electrode wiring 2 and the source electrode wiring 6. Is connected, and a backlight unit is attached to form a desired liquid crystal display device.

In this embodiment, all of the gate electrode wiring 2, the common wiring 3, and the source electrode wiring 7 have a two-layer film structure. However, all of the wirings need not have a two-layer film structure.
In this embodiment mode, a liquid crystal display device having a channel etch type TFT array structure has been described. However, the present invention can also be applied to a liquid crystal display device having an etching stopper type TFT array structure.

  According to the present embodiment, the same effects as in the first embodiment can be obtained, and the gate electrode wiring 2 and the source electrode wiring 6 have a two-layer film structure, so that the wiring resistance is reduced and the electrode wiring is thinned. Therefore, the aperture ratio can be improved and the yield can be prevented from being lowered due to disconnection or the like. Moreover, the metal film which comprises electrode wiring can be made thin, and manufacturing cost can be reduced.

Embodiment 4 FIG.
14 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device mounted with TFTs as switching elements according to Embodiment 4 of the present invention. The source electrode wiring part, TFT part, storage capacitor part, gate electrode wiring part FIG. 2 shows cross sections of the electrode wiring intersection and the common wiring terminal conversion section.
In the figure, reference numeral 31 denotes a passivation film formed on the TFT 13. The same parts as those in FIGS. 2 to 4 are denoted by the same reference numerals and description thereof is omitted.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIG. 14A, the surface of the transparent insulating substrate 1 is made of any one of Al, Cr, Mo, W, Ti, Ta, and Cu by using a sputtering method or the like as a main component. An alloy or a laminated film thereof is formed and patterned using a resist formed by photolithography to form the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3.
Next, as shown in FIG. 14B, silicon nitride, a-Si, and n ⁺ -a-Si constituting the gate insulating film 4 are sequentially formed using a plasma CVD method or the like, and then a photolithography method is used. The semiconductor layer 5 composed of the gate insulating film, the a-Si film, and the n ⁺ -a-Si film is formed by sequentially patterning in the same pattern using the resist formed by the above. The gate insulating film 4 and the semiconductor layer 5 having the same shape are formed on the gate electrode 2a, the common wiring 3 where the storage capacitor 14 is formed, and the wiring intersection 16.

Next, as shown in FIG. 14C, any metal thin film (Al, Cr, Mo, W, Ti, Ta and Cu) that can be selectively etched with the metal constituting the gate electrode wiring 2 and the like by sputtering is used. Or an alloy containing these as a main component, or a laminated film thereof) and patterning using a resist formed by a photolithography method to form a source electrode wiring 6, a source electrode 6a, a drain electrode 7 and A common lead wire 8 is formed, and a channel portion 9 is formed by etching the n ⁺ -a-Si film on the gate electrode 2a that is not covered with the source electrode 6a and the drain electrode 7 by a dry etching method or the like. , TFT 13 is formed.

Next, a silicon nitride film is formed to a thickness of about 100 nm, and a passivation film 31 is formed.
Next, an acrylic transparent resin having photosensitivity is applied so as to absorb the level difference caused by the TFT 13 and the wiring and the surface is flattened, and is patterned by photolithography to face the common wiring 3 of the drain electrode 7. A contact hole 11 is formed on a portion where the storage capacitor 14 is formed. Thereafter, baking is performed to form the interlayer insulating film 10. Subsequently, using the interlayer insulating film 10 as a mask, the passivation film 31 on the drain electrode 7 exposed through the contact hole 11 is etched to expose the drain electrode 7 in the contact hole 11 (FIG. 14D).

  Next, as shown in FIG. 14E, after forming a transparent conductive film such as ITO, indium oxide, tin oxide or the like by sputtering or the like, patterning is performed using a resist formed by photolithography. The pixel electrode 12 is formed. At this time, the pixel electrode 12 is electrically connected to the drain electrode 7 through the contact hole 11. The pixel electrode 12 is formed so as to overlap the gate electrode wiring 2, the gate electrode 2a, the source electrode wiring 6, and the source electrode 6a.

  The TFT array substrate (first substrate) and the counter substrate (second substrate) formed by the above steps are bonded together, and a liquid crystal material is injected therebetween, and an image signal is applied to the gate electrode wiring 2 and the source electrode wiring 6. Is connected, and a backlight unit is attached to form a desired liquid crystal display device.

  Note that in this embodiment mode, a liquid crystal display device having a channel etch type TFT array structure has been described, but the present invention can also be applied to a liquid crystal display device having an etching stopper type TFT array structure.

  According to the present embodiment, the same effects as those of the first embodiment can be obtained, and the passivation film 31 is formed on the TFT 13, so that the TFT characteristics can be stabilized and display defects caused by this can be prevented. . In the etching process of the passivation film 31 using the interlayer insulating film 10 as a mask, the passivation film 31 is composed of a thin film of about 100 nm, so that the etching time is short, and the film thickness of the interlayer insulating film 10 is small. Without causing a decrease in yield due to a short-circuit through the pinholes and an increase in the overlap capacitance between the pixel electrode 12 on the interlayer insulating film 10 and the underlying gate electrode wiring 2 and source electrode wiring 6. The occurrence of display defects such as shot unevenness can be suppressed.

Embodiment 5 FIG.
FIG. 15 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device in which a TFT is mounted as a switching element according to Embodiment 5 of the present invention. The source electrode wiring portion, TFT portion, storage capacitor portion, gate electrode wiring portion FIG. 2 shows cross sections of the electrode wiring intersection and the common wiring terminal conversion section. In addition, since the code | symbol in a figure is the same as FIG. 14, description is abbreviate | omitted.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIGS. 15A, 15B, and 15C, the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 are formed on the transparent insulating substrate 1 by the same method as in the first embodiment. Then, the gate insulating film 4, the semiconductor layer 5, the source electrode wiring 6, the source electrode 6a, the drain electrode 7, the common extraction wiring 8, and the TFT 13 are sequentially formed.

Next, after the TFT 13 is formed and before the resist formed for patterning the source electrode wiring 6 is removed, a silicon nitride film is formed to a thickness of about 100 nm to form a passivation film 31, and then the resist is removed. Then, the silicon nitride film (passivation film 31) on the resist is peeled off simultaneously by the lift-off method, and the silicon nitride film (passivation film 31) on the source electrode wiring 6, the source electrode 6a, the drain electrode 7, and the common extraction wiring 8 is removed. .
Next, an acrylic transparent resin having photosensitivity is applied so as to absorb the level difference caused by the TFT 13 and the wiring and the surface is flattened, and is patterned by photolithography to face the common wiring 3 of the drain electrode 7. A contact hole 11 is formed on the portion where the storage capacitor 14 is formed (FIG. 15D).

  Next, as shown in FIG. 15E, a transparent conductive film made of ITO, indium oxide, tin oxide or the like is formed by sputtering or the like, and then patterned using a resist formed by photolithography. The pixel electrode 12 is formed. At this time, the pixel electrode 12 is electrically connected to the drain electrode 7 through the contact hole 11. The pixel electrode 12 is formed so as to overlap the gate electrode wiring 2, the gate electrode 2a, the source electrode wiring 6, and the source electrode 6a.

  The TFT array substrate (first substrate) and the counter substrate (second substrate) formed by the above steps are bonded together, and a liquid crystal material is injected therebetween, and an image signal is applied to the gate electrode wiring 2 and the source electrode wiring 6. Is connected, and a backlight unit is attached to form a desired liquid crystal display device.

In the present embodiment, the thickness of the passivation film 31 is about 100 nm. However, the effect as a passivation film can be obtained even when the thickness is about 50 nm. Further, by increasing the thickness of the passivation film 31, the effect of flattening the steps due to the pattern of the source electrode wiring 6, the source electrode 6a, and the drain electrode 7 is increased. Therefore, the thickness may be increased to about 400 nm.
Further, the present embodiment may be applied to a TFT array in which the source electrode wiring 6 and the gate electrode wiring 2 shown in the third embodiment have a two-layer film structure. A flattening effect is also obtained for the electrode wiring 2.
In this embodiment mode, a liquid crystal display device having a channel etch type TFT array structure has been described. However, the present invention can also be applied to a liquid crystal display device having an etching stopper type TFT array structure.

  According to the present embodiment, since the passivation film 31 is formed on the channel portion of the TFT 13, the same effects as those of the fourth embodiment can be obtained, and the removal of the passivation film 31 uses the lift-off method. The number of processes does not increase. Further, the step due to the pattern of the source electrode wiring 6, the source electrode 6a, and the drain electrode 7 is flattened by the passivation film 31, so that the film thickness of the interlayer insulating film 10 on the source electrode wiring 6 and the like is effectively increased. The overlapping capacitance between the pixel electrode 12 on the insulating film 10 and the underlying source electrode wiring 6 is reduced. In addition, it is possible to previously form a thin film of expensive photosensitive transparent resin that constitutes the interlayer insulating film 10, thereby reducing the manufacturing cost.

Embodiment 6 FIG.
In the fourth and fifth embodiments, the passivation film 31 is formed in order to stabilize the characteristics of the TFT 13. However, the characteristics of the TFT 13 can also be stabilized by performing an interface treatment such as hydrogenation on the substrate surface after the TFT 13 is formed. Thus, the same effect as in the fourth embodiment can be obtained.
FIG. 16 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device having a TFT mounted as a switching element according to Embodiment 6 of the present invention. The source electrode wiring portion, TFT portion, storage capacitor portion, gate electrode wiring portion FIG. 2 shows cross sections of the electrode wiring intersection and the common wiring terminal conversion section. In addition, since the code | symbol in a figure is the same as that of FIGS. 2-4, description is abbreviate | omitted.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIGS. 16A, 16B, and 16C, the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 are formed on the transparent insulating substrate 1 by the same method as in the first embodiment. Then, the gate insulating film 4, the semiconductor layer 5, the source electrode wiring 6, the source electrode 6a, the drain electrode 7, the common extraction wiring 8, and the TFT 13 are sequentially formed.

Next, after the TFT 13 is formed, the substrate surface is subjected to hydroxylation by exposing it to hydrogen plasma at 300 ° C. for 1 hour.
Thereafter, the interlayer insulating film 10, the contact hole 11 and the pixel electrode 12 are formed by the same method as in the first embodiment to form a TFT array substrate, thereby forming a desired liquid crystal display device.

  In this embodiment, hydrogenation is used by plasma treatment to stabilize the characteristics of the TFT 13, but the interface treatment of the channel portion of the TFT 13 may be performed using other methods.

Embodiment 7 FIG.
FIG. 17 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device in which a TFT is mounted as a switching element according to Embodiment 7 of the present invention. The source electrode wiring portion, TFT portion, storage capacitor portion, gate electrode wiring portion FIG. 2 shows cross sections of the electrode wiring intersection and the common wiring terminal conversion section. In addition, since the code | symbol in a figure is the same as FIGS. 7-9, description is abbreviate | omitted.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIG. 17A, the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 are formed by the same method as in the second embodiment.
Next, as shown in FIG. 17B, 400 nm of silicon nitride, a-Si, and n ⁺ -a-Si are sequentially formed by using a plasma CVD method or the like to form the gate insulating film 4. A gate insulating film 4 and a semiconductor layer 5 made of an a-Si film and an n ⁺ -a-Si film are formed by sequentially patterning in the same pattern using a resist formed by lithography. At this time, the etching portion of the gate insulating film 4 is etched until the remaining film thickness becomes 200 nm with respect to the film thickness of 400 nm. The gate insulating film 4 and the semiconductor layer 5 having the same shape are formed on the gate electrode 2a and at the wiring intersection 16. That is, the semiconductor layer (a-Si film and n ⁺ -a-Si film) 5 on the common wiring 3 constituting the storage capacitor 14 is removed, and only the gate insulating film 4 having a thickness of 200 nm is formed in this portion. .

  Thereafter, as shown in FIGS. 17C, 17D, and 17E, the source electrode wiring 6, the source electrode 6a, the drain electrode 7, and the common lead-out wiring are formed in the same manner as in the second embodiment. 8. A TFT array substrate is formed by forming the TFT 13, the interlayer insulating film 10, the contact holes 11, 28 and 29, the pixel electrode 12, and the connection wiring 30 to constitute a desired liquid crystal display device.

In this embodiment, the case where the storage capacitor 14 is formed by the common wiring 3 and the drain electrode 7 has been described. However, the storage capacitor is not formed by using the common wiring and the gate electrode wiring and the drain electrode are overlapped. The present invention can also be applied to a liquid crystal display device having a structure.
In this embodiment mode, a liquid crystal display device having a channel etch type TFT array structure has been described. However, the present invention can also be applied to a liquid crystal display device having an etching stopper type TFT array structure.

  According to the present embodiment, the same effect as in the second embodiment can be obtained, and the insulating film in the storage capacitor 14 forming portion is formed thin, so that a storage capacitor having the same capacity as that in the second embodiment can be formed. The common wiring 3 and the drain electrode 7 can be reduced in overlapping area, and the common wiring 3 can be thinned, so that the aperture ratio of the pixel can be improved. Furthermore, since the layer structure of the storage capacitor 14 is not metal / insulator / semiconductor, the capacitor does not have voltage dependency.

Embodiment 8 FIG.
FIG. 18 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device mounted with TFTs as switching elements according to an eighth embodiment of the present invention. The source electrode wiring part, TFT part, storage capacitor part, gate electrode wiring part FIG. 2 shows cross sections of the electrode wiring intersection and the common wiring terminal conversion section.
In the figure, reference numeral 31 denotes a passivation film formed on the TFT 13. The same parts as those in FIGS. 7 to 9 are denoted by the same reference numerals and description thereof is omitted.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIGS. 18A, 18B, and 18C, the gate electrode wiring 2, the gate electrode 2a, and the common wiring 3 are formed on the transparent insulating substrate 1 by the same method as in the second embodiment. Then, the gate insulating film 4, the semiconductor layer 5, the source electrode wiring 6, the source electrode 6a, the drain electrode 7, the common extraction wiring 8, and the TFT 13 are sequentially formed.

Next, a passivation film 31 is formed by depositing silicon nitride about 100 nm.
Next, an acrylic transparent resin having photosensitivity is applied so as to absorb the level difference caused by the TFT 13 and the wiring and the surface is flattened, and is patterned by photolithography to face the common wiring 3 of the drain electrode 7. Contact holes 28 and 29 are formed on the contact hole 11 and the common lead-out wiring 8 and the common wiring 3 of the terminal conversion unit 15 on the portion where the storage capacitor 14 is formed. Thereafter, baking is performed to form the interlayer insulating film 10. Subsequently, using the interlayer insulating film 10 as a mask, the passivation film 31 on the drain electrode 7 and the common lead-out wiring 8 exposed by the contact holes 11, 28 and 29, and the passivation film 31 and the gate insulating film 4 on the common wiring 3 are formed. Etching is performed to expose the drain electrode 7 in the contact hole 11, the common lead wiring 8 in the contact hole 28, and the common wiring 3 in the contact hole 29 (FIG. 18D).
Thereafter, as shown in FIG. 18E, the pixel electrode 12 and the connection wiring 30 are formed by the same method as in the second embodiment to form a TFT array substrate, thereby forming a desired liquid crystal display device.

Note that the same effect can be obtained when this embodiment is applied to a TFT array having the structure shown in the seventh embodiment.
In the present embodiment, the thickness of the passivation film 31 is about 100 nm. However, the effect as a passivation film can be obtained even when the thickness is about 50 nm.

  According to the present embodiment, the same effects as those of the second embodiment or the seventh embodiment can be obtained, and the passivation film 31 is formed on the TFT 13, so that the TFT characteristics are stabilized and this is caused. Display defects can be prevented. In the etching process of the passivation film 31 and the gate insulating film 4 using the interlayer insulating film 10 as a mask, the gate insulating film 4 is made of a thin film of about 200 nm and the passivation film 31 is made of a thin film of about 100 nm, and the etching time is short. 10 is small, the yield decreases due to a short circuit through the pinhole of the interlayer insulating film 10, and the overlap capacitance between the pixel electrode 12 on the interlayer insulating film 10 and the gate electrode wiring 2 and the source electrode wiring 6 in the lower layer. The occurrence of display defects such as luminance change, crosstalk, and shot unevenness can be suppressed without inducing an increase in brightness.

Embodiment 9 FIG.
FIG. 19 is a schematic plan view showing a TFT array substrate of a liquid crystal display device in which TFTs are mounted as switching elements according to Embodiment 9 of the present invention. FIG. 19 (a) is a terminal converter outside the display area, and FIG. ) Indicates a pixel portion in the display area. 20 is a section taken along the line AB of FIG. 19, FIG. 21 is a section taken along the line CD of FIG. 19, and FIG. 22 is a cross-sectional view showing a manufacturing process of the part taken along the line EF of FIG. FIG.
In the figure, reference numeral 32 denotes irregularities formed on the surface of the interlayer insulating film 10. In addition, the same code | symbol is attached | subjected to FIG. 1-4 same part, and description is abbreviate | omitted.

Next, the manufacturing process of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIGS. 20 (a), 21 (a), and 22 (a), a 200 nm Al film is formed on the surface of the transparent insulating substrate 1 by sputtering or the like, and formed by photolithography. The gate electrode wiring 2, the gate electrode 2a and the common wiring 3 are formed by patterning using the resist.
Next, as shown in FIG. 20B, FIG. 21B, and FIG. 22B, 400 nm of silicon nitride, 150 nm of a-Si, After n ⁺ -a-Si is sequentially deposited to 30 nm, it is sequentially patterned into the same pattern using a resist formed by photolithography, and the gate insulating film 4, the a-Si film, and the n ⁺ -a-Si film are formed. A semiconductor layer 5 is formed. The gate insulating film 4 and the semiconductor layer 5 having the same shape are formed on the gate electrode 2a, the common wiring 3 where the storage capacitor 14 is formed, and the wiring intersection 16.

Next, as shown in FIG. 20C, FIG. 21C, and FIG. 22C, a Cr film having a thickness of 400 nm is formed by sputtering or the like, and patterning is performed by using a resist formed by photolithography. Then, the source electrode wiring 6, the source electrode 6 a, the drain electrode 7, and the common lead wiring 8 are formed, and the n ⁺ -a-Si on the portion of the gate electrode 2 a not covered with the source electrode 6 a and the drain electrode 7 is formed. The film is etched by a dry etching method or the like to form the channel portion 9 to form the TFT 13.
Next, as shown in FIGS. 20 (d), 21 (d), and 22 (d), an acrylic transparent resin having photosensitivity so as to absorb the level difference caused by the TFT 13 and the wiring and to flatten the surface. Is applied and patterned by photolithography to form a contact hole 11 on the portion of the drain electrode 7 facing the common wiring 3 and forming the storage capacitor 14, and at the same time, the surface of the interlayer insulating film 10 in the display region Minute irregularities 32 are formed on the surface. Thereafter, baking is performed to form the interlayer insulating film 10.

  Next, as shown in FIGS. 20 (e), 21 (e), and 22 (e), Al is deposited to a thickness of 100 nm using a sputtering method or the like, and then patterned using a resist formed by a photolithography method. Thus, the pixel electrode 12 is formed. At this time, the pixel electrode 12 is electrically connected to the drain electrode 7 through the contact hole 11. The pixel electrode 12 also serves as a reflective electrode due to the irregularities 32 formed in the interlayer insulating film 10. Further, as shown in FIG. 19B, the pixel electrode 12 is formed to have an overlapping portion with the gate electrode wiring 2 and the source electrode wiring 6 and the interlayer insulating film 10 interposed therebetween.

The TFT array substrate (first substrate) and the counter substrate (second substrate) formed by the above steps are bonded together, and a liquid crystal material is injected therebetween, and an image signal is applied to the gate electrode wiring 2 and the source electrode wiring 6. A desired reflection type liquid crystal display device is configured by connecting a circuit for transmitting the signal.
In the reflection type liquid crystal display device thus formed, the step due to the TFT 13 and the wiring is flattened by the interlayer insulating film 10, so that no alignment abnormality due to the step occurs. In addition, since the pixel electrode 12 is overlapped with the source electrode wiring 6 and the gate electrode wiring 2 via the interlayer insulating film 10, there is no alignment abnormality caused by the electric field of the electrode wiring.

In the present embodiment, the gate electrode 2a layer is formed using a 200 nm Al film, but the film thickness and material are not limited to this, and the film thickness is 100 nm to 500 nm, and the material is Al, Cr. , Mo, W, Ti, Ta and Cu, alloys containing these as main components, or laminated films thereof may be used. The same applies to the source electrode 6a, the drain electrode 7 layer, and the pixel electrode 12, but the material constituting the source electrode wiring 6 is a material that can be selectively etched with the material constituting the gate electrode wiring 2 and the like. Use. However, this is not the case when applied to a TFT array having a configuration in which a part of the gate insulating film 4 is left. The film thickness of the pixel electrode 12 is desirably 20 nm to 200 nm.
Further, in order to prevent the upper layer from being cut off at the portion where the wiring intersects, it is desirable to use taper etching in the patterning process of the two gate electrode wiring layers and the gate insulating film 4.
Further, as a material constituting the interlayer insulating film 10, since it is a reflection type liquid crystal display device, a photosensitive opaque resin such as a resist may be used.
Further, an opaque insulating substrate may be used instead of the transparent insulating substrate 1 as the support substrate.

In this embodiment, the case where the storage capacitor 14 is formed by the common wiring 3 and the drain electrode 7 has been described. However, the storage capacitor 14 is formed by overlapping the gate electrode wiring and the drain electrode without having the common wiring. The present invention can also be applied to a liquid crystal display device having a structure.
Further, in this embodiment, the pixel electrode 12 is formed so as to overlap both the gate electrode wiring 2 and the source electrode wiring 6, but the liquid crystal display device has a structure that overlaps only one electrode wiring or does not overlap. Applicable.
In this embodiment mode, a liquid crystal display device having a channel etch type TFT array structure has been described. However, the present invention can also be applied to a liquid crystal display device having an etching stopper type TFT array structure.

According to the present embodiment, the same effect as in the first embodiment can be obtained in the reflective liquid crystal display device. Further, since there is no etching process using the interlayer insulating film 10 having minute irregularities 32 on the surface as a mask, the surface state of the irregularities 32 is maintained, and the reflection characteristics of the reflective electrode are not subject to process fluctuations. Improvement can be achieved.
In this embodiment mode, the case where the TFT array having the configuration described in Embodiment Mode 1 is applied to a reflective liquid crystal display device is described. However, the configuration shown in Embodiment Modes 2 to 8 is used. For the TFT array, minute irregularities 32 are formed on the surface of the interlayer insulating film 10, and the pixel electrode 12 is made of any one of Al, Cr, Mo, W, Ti, Ta and Cu, or these as a main component. The present invention can be applied by forming an alloy or a laminated film thereof, and the same effects can be obtained.

It is a schematic plan view which shows the TFT array substrate of the liquid crystal display device by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 1 of this invention. It is a figure which shows the equivalent circuit of the liquid crystal display device of this invention. It is a schematic plan view which shows the TFT array substrate of the liquid crystal display device by Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 2 of this invention. It is a schematic plan view which shows the TFT array substrate of the liquid crystal display device by Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 5 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 6 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 7 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 8 of this invention. It is a schematic plan view which shows the TFT array substrate of the liquid crystal display device by Embodiment 9 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 9 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 9 of this invention. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the liquid crystal display device by Embodiment 9 of this invention. It is a schematic plan view which shows the TFT array substrate of this kind of conventional liquid crystal display device. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the conventional liquid crystal display device. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the conventional liquid crystal display device. It is sectional drawing which shows the manufacturing process of the TFT array substrate of the conventional liquid crystal display device.

Explanation of symbols

1 transparent insulating substrate, 2 gate electrode wiring, 2a gate electrode,
2b Gate upper layer wiring, 3 common wiring, 3b common upper layer wiring,
4 gate insulating film, 5 semiconductor layer, 6 source electrode wiring, 6a source electrode,
6b source lower layer wiring, 7 drain electrode, 8 common lead wiring,
9 channel part, 10 interlayer insulation film, 11 contact hole,
12 pixel electrodes, 13 TFTs, 14 holding capacitors, 15 terminal converters,
16 wiring intersection, 17 gate terminal, 18 source terminal, 19 common terminal,
22 Liquid crystal capacity, 23, 24, 25, 26 Overlap capacity,
28, 29 Contact hole, 30 Connection wiring,
31 Unevenness of passivation film, 32 interlayer insulation film.

Claims (2)

An insulating substrate;
A scanning electrode, a scanning electrode wiring and a common wiring formed on the insulating substrate;
A semiconductor layer formed to cover the scan electrode and to cover a predetermined portion of the scan electrode wiring and the common wiring;
Formed in the semiconductor layer underlying the above insulating substrate is etched by the same mask and the semiconductor layer, the non-formation region of the semiconductor layer, etching portions of that is compared to the formation region of the semiconductor layer An insulating film having a thin residual film;
A first electrode constituting a semiconductor element together with a semiconductor layer on the scan electrode, a second electrode, and a first electrode wiring connected to the first electrode;
An interlayer insulating film made of a resin formed above the scan electrode, scan electrode wiring, common wiring, semiconductor layer, first electrode, first electrode wiring and second electrode;
A pixel electrode made of a conductive film formed on the interlayer insulating film and electrically connected to the second electrode through a first contact hole formed in the interlayer insulating film;
A common lead wire formed on the insulating substrate in the same layer as the first electrode wire and the same material as the pixel electrode, and electrically connects the common lead wire and the common wire. A first substrate having a terminal conversion portion outside the display area including the connection wiring to be connected, and a second substrate sandwiching a liquid crystal material together with the first substrate,
The semiconductor layer is formed at an intersection of the semiconductor element component and the scanning electrode wiring or the common wiring and the first electrode wiring or the common lead wiring, and the common wiring is connected to the second electrode. The liquid crystal is characterized in that the semiconductor layer is not formed on the opposing storage capacitor portion, but a thin residual film of the insulating film is formed, and a storage capacitor is formed by the thin residual film. Display device. In the method for manufacturing a liquid crystal display device in which the first and second insulating substrates are bonded to face each other, and a liquid crystal material is sandwiched between the first and second insulating substrates.
Forming a scan electrode, a scan electrode wiring and a common wiring on the first insulating substrate;
An insulating film and a semiconductor film are formed on the first insulating substrate so as to cover the scanning electrode, the scanning electrode wiring, and the common wiring, and then the semiconductor film is patterned using the same mask. And forming a semiconductor layer covering the scan electrode and covering a predetermined portion of the scan electrode wiring and the common wiring, etching the insulating film, and comparing the etched portion with the formation portion of the semiconductor layer. Forming a thin residual film, and covering the common wiring with a terminal conversion portion outside the display area of the first insulating substrate with the thin residual film of the insulating film;
A first electrode, a second electrode, a first electrode wiring connected to the first electrode, and a common lead wiring are formed in the terminal conversion portion together with the semiconductor layer on the scan electrode. Process,
A resin having photosensitivity is applied on the first insulating substrate so as to cover the first electrode, the first electrode wiring, the second electrode, and the common lead-out wiring, and the first insulating substrate is exposed and developed. An interlayer insulating film having a first contact hole on the second electrode, a second contact hole on the common lead wiring of the terminal conversion section, and a third contact hole on the common wiring of the terminal conversion section; Forming, and
Etching the thin remaining film of the insulating film exposed by the third contact hole using the interlayer insulating film as a mask;
A conductive film is formed on the interlayer insulating film and in the first, second, and third contact holes, patterned, and electrically connected to the second electrode through the first contact hole. Forming a connection wiring for electrically connecting the pixel electrode, the common lead-out wiring, and the common wiring through the second contact hole and the third contact hole,
The semiconductor layer is formed at an intersection of the semiconductor element component and the scanning electrode wiring or the common wiring and the first electrode wiring or the common lead wiring, and the common wiring is connected to the second electrode. The liquid crystal display device is characterized in that the semiconductor film is removed in the opposing storage capacitor portion to form a thin residual film of the insulating film, and a storage capacitor is formed by the thin residual film. Manufacturing method.

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