JP4189591B2 - Radio wave receiver, radio clock, and relay device - Google Patents

Description

  The present invention relates to a radio wave receiver, a radio timepiece, and a relay device.

  At present, time data, that is, a standard radio wave including a time code is transmitted in each country (for example, Germany, the United Kingdom, Switzerland, Japan, etc.). In Japan (Japan), 40 kHz and 60 kHz long wave standard waves modulated with time codes in the format shown in FIG. 9 are transmitted from two transmitting stations (Fukushima Prefecture and Saga Prefecture). According to FIG. 9, the time code is transmitted in a frame of 60 seconds per cycle every time the minute digit of the correct time is updated, that is, every minute.

  A so-called radio timepiece that receives such a standard radio wave and corrects the current time based on the standard radio wave is known. The radio timepiece detects a received signal, reproduces a standard time code, and corrects the current time measured according to the standard time code. That is, in the radio timepiece, it is important to reliably reproduce the standard time code from the received signal. The standard time code is a pulse signal (digital signal) that takes either a high level or a low level, as shown in FIG.

As one of synchronization signal reproduction circuits for reproducing a digital signal included in an input signal, Patent Document 1 discloses a synchronization separation circuit for separating (reproducing) a synchronization signal that is a digital signal from a decoded video signal (input signal). Has been. In such a circuit, the sag (instantaneous voltage drop) is suppressed by clamping the decoded video signal input to the input terminal by the first clamping means, and further, the flutter is obtained by clamping the clamped signal by the second clamping means. The ring is prevented.
Japanese Patent Application No. 2001-157082

  In radio timepieces, the amplification level of this amplifier circuit is adjusted according to the level of the signal level after amplification by the amplifier circuit so that the standard time code can be accurately reproduced in the internal circuit even if the signal level of the received standard radio wave changes. An AGC circuit for adjustment is provided.

  However, for example, in the case of a wristwatch-type radio timepiece worn on the user's arm, when the fluctuation of the electric field strength of the standard radio wave received due to a sudden change in position due to the user's operation or entering or leaving the building becomes large, the AGC circuit However, the adjustment of the degree of amplification alone cannot cope with the problem, and the level of the detection signal greatly fluctuates, which makes it difficult to reproduce the standard time code. However, such a level fluctuation is not taken into consideration in the conventional synchronizing signal reproduction circuit as disclosed in Patent Document 1, for example.

  In view of the above circumstances, an object of the present invention is to realize a radio wave receiver or the like that can reliably reproduce a data signal even if the signal has a large voltage level fluctuation.

In order to solve the above problems, a first aspect of the present invention, detection means for outputting a detection signal containing a data signal which takes either of the High level and the Low level by detecting a received signal received by an antenna ( For example, a radio wave receiving apparatus (including a detection circuit 629 in FIG. 2) and signal reproduction means (for example, the signal reproduction circuit 632 in FIGS. 2 and 3) that outputs a reproduction signal reproduced based on the detection signal ( For example, in FIG. 1 and FIG.
The signal reproducing means includes
Differentiating means for outputting a differential signal whose level changes in response to a rise to a high level and a fall to a low level of a data signal included in the detection signal by differentiating the detection signal (for example, FIG. 3 capacitor C1 and resistor R1),
Integrating means (for example, the resistor R2 and the capacitor C2 in FIG. 3) that integrates the differential signal and outputs an integrated signal;
It has a first input terminal to which the differential signal is input and a second input terminal to which the integral signal is input, and the level of the signal input to the first input terminal is the second input terminal. Comparing means (for example, the differential amplifier AMP in FIG. 3) that outputs a high level signal when the level is higher than the level of the input signal and a low level output signal when the level is lower ;
After the output signal of the comparison means becomes High level, the output signal becomes low level when the level of the differential signal input to the first input terminal falls below the level of the output signal of the comparison means. In the meantime, the first feedback means (for example, the buffer BF2, FIG. 3 in FIG. 3) keeps the level of the first input terminal constant by feeding back the output signal of the comparison means to the first input terminal . Resistor R3, diode D),
A second feedback means (for example, FIG. 3) that suppresses an increase in the level of the integral signal input to the second input terminal by inverting the output signal of the comparison means and feeding it back to the second input terminal . Buffer BF3 and resistor R4), and the output signal of the comparison means is output as a reproduction signal obtained by reproducing the data signal included in the detection signal .

According to the first aspect of the present invention, in the radio wave receiver, the signal reproducing means compares the differential signal obtained by differentiating the detection signal with the integrated signal obtained by integrating the differential signal, and the comparison result is obtained. A first feedback is applied to the differential signal using the comparison signal based thereon, a second feedback is applied to the integral signal using the comparison signal, and the differential signal and the second feedback applied using the first feedback are applied. The reproduced signal obtained by reproducing the data signal included in the detection signal can be generated by comparing the integrated signal.
That is, the differential signal is a signal whose voltage changes greatly at the rising / falling edge portion of the data signal included in the detection signal, and the integral signal is a signal that changes with a delay with respect to the level change of the differential signal. Become. Therefore, by comparing the differential signal and the integral signal, it is possible to detect the rising / falling edge of the data signal and generate a reproduction signal that reproduces the data signal.
Therefore, a signal synchronized with the data signal included in the detection signal can be generated and output as the data signal.

The invention described in claim 2
A radio wave receiving apparatus according to claim 1,
Time code generating means (for example, the time code generating unit 70 in FIG. 1) for generating a standard time code based on the reproduction signal output from the radio wave receiver;
Clocking means for clocking the current time (for example, the clock circuit unit 80 in FIG. 1);
Correction means (for example, the CPU 10 in FIG. 1) for correcting the current time measured by the time measurement means based on the standard time code generated by the time code generation means;
A radio timepiece (for example, the radio timepiece of FIG. 1).

According to the second aspect of the present invention, it is possible to realize a radio timepiece having the same effect as the first aspect of the present invention. In other words, even if the electric field strength of the standard radio wave received due to a sudden change in position, such as a watch-type radio timepiece, fluctuates greatly and the level fluctuation of the detection signal increases, the time code that is a data signal is reliably reproduced. It becomes possible to do.

The invention according to claim 3
A radio wave receiver according to claim 1 ;
Time code generating means (for example, the time code generating unit 70 in FIG. 8) for generating a standard time code based on the reproduction signal output from the radio wave receiver;
Transmission means (for example, the transmission unit 90 in FIG. 8) that modulates and transmits the standard time code generated by the time code generation means;
Is a relay device (for example, the relay device 2 in FIG. 8).

According to the invention described in claim 3 , it is possible to realize a relay device that exhibits the effect of the invention described in claim 1 .

According to the first aspect of the present invention, in the radio wave receiver, the signal reproducing means performs a comparison process on the differential signal obtained by differentiating the detection signal and the integral signal obtained by integrating the differential signal, and based on the comparison result. The first feedback is applied to the differential signal using the comparison signal, the second feedback is applied to the integral signal using the comparison signal, and the differential signal and the second feedback are applied using the first feedback. A reproduction signal obtained by reproducing the data signal included in the detection signal can be generated by performing a comparison process with the integrated signal.
That is, the differential signal is a signal whose voltage changes greatly at the rising / falling edge portion of the data signal included in the detection signal, and the integral signal is a signal that changes with a delay with respect to the level change of the differential signal. Become. Therefore, by comparing the differential signal and the integral signal, it is possible to detect the rising / falling edge of the data signal and generate a reproduction signal that reproduces the data signal.
Therefore, a signal synchronized with the data signal included in the detection signal can be generated and output as the data signal.

Further, according to the invention described in claim 2 , it is possible to realize a radio-controlled timepiece having the same effect as that of the invention described in claim 1 . In other words, even if the electric field strength of the standard radio wave received due to a sudden change in position, such as a watch-type radio timepiece, fluctuates greatly and the level fluctuation of the detection signal increases, the time code that is a data signal is reliably reproduced. It becomes possible to do. Furthermore, according to the invention described in claim 3 , it is possible to realize a relay device that exhibits the effect of the invention described in claim 1 .

The best mode for carrying out the present invention will be described below with reference to the drawings.
In addition, although the case where this invention is demonstrated to a radio wave timepiece below is demonstrated below, application of this invention is not limited to this.

[Radio clock]
FIG. 1 is a block diagram showing a circuit configuration of a radio timepiece 1 to which the present invention is applied. According to the figure, the radio timepiece 1 includes a CPU (Central Processing Unit) 10, an input unit 20, a display unit 30, a ROM (Read Only Memory) 40, a RAM (Random Access Memory) 50, and reception control. The unit 60, the time code generation unit 70, the time measuring circuit unit 80, and the oscillation circuit unit 82 are configured. Each unit excluding the oscillation circuit unit 82 is connected by the bus B. An oscillation circuit unit 82 is connected to the time measuring circuit unit 80.

  The CPU 10 reads out various programs stored in the ROM 40 in accordance with a predetermined timing or an operation signal input from the input unit 20, develops them in the RAM 50, and supplies the various programs in the radio timepiece 1 to each unit based on the programs. Instructions and data transfer are performed. In particular, the CPU 10 controls the reception control unit 60 to execute standard radio wave reception processing at predetermined time intervals, for example, and the time counting circuit unit 80 counts time based on the standard time code input from the time code generation unit 70. Various controls are performed such as correcting the current time data and outputting a display signal based on the corrected time code to the display unit 30 to update the display time.

  The input unit 20 includes a switch for causing the radio timepiece 1 to execute various functions. And when these switches are operated, the operation signal of a corresponding switch is output to CPU10. The display unit 30 is configured by a small liquid crystal display or the like, and digitally displays data from the CPU 10, for example, current time data by the timing circuit unit 80.

  The ROM 40 mainly stores system programs, application programs, data and the like related to the radio timepiece 1. The RAM 50 is used as a work area of the CPU 10 and temporarily stores programs and data read from the ROM 40, data processed by the CPU 10, and the like.

  The reception control unit 60 includes a radio wave receiving device 62. The radio wave receiver 62 cuts out unnecessary frequency components of the standard radio wave received by the antenna, extracts the corresponding frequency signal, converts the extracted frequency signal into a corresponding signal, and outputs it.

  The clock circuit unit 80 counts the signal input from the oscillation circuit unit 82, clocks the current time data, and outputs the clocked current time data to the CPU 10. The oscillation circuit unit 82 is a circuit that always outputs a signal having a constant frequency.

  Based on the signal output from the radio wave receiver 62, the time code generation unit 70 generates a standard time code including data necessary for a clock function such as a standard time code, an integrated date code, and a day of the week code. Output.

[Radio wave receiver]
FIG. 2 is a block diagram showing a circuit configuration of the radio wave receiver 62 using the superheterodyne method in the first embodiment. According to the figure, the radio wave receiver 62 includes an antenna 621, an RF amplifier circuit 622, filter circuits 623, 626, 628, a frequency converter circuit 624, a local oscillator circuit 625, an IF amplifier circuit 627, and a detector. A circuit 629, an AGC (Auto Gain Control) circuit 631, and a signal reproduction circuit 632 are provided.

  The antenna 621 is composed of, for example, a bar antenna, etc., tuned to the frequency of a long wave standard radio wave including a time code (specifically, 40 kHz or 60 kHz), receives this, converts it into a corresponding electric signal, and outputs it. .

  The RF amplifier circuit 622 amplifies (or attenuates) the signal input from the antenna 621 with an amplification degree corresponding to the RF control signal input from the AGC circuit 631 and outputs the amplified signal. The filter circuit 623 is configured by a band-pass filter or the like, and allows a signal input from the RF amplifier circuit 622 to pass a frequency in a predetermined range, and cuts out and outputs a frequency component outside the range.

  The frequency conversion circuit 624 combines the signal output from the filter circuit 623 and the signal output from the local oscillation circuit 625 and outputs the resultant signal as an intermediate frequency signal. The local oscillation circuit 625 generates and outputs a signal having a local oscillation frequency. The filter circuit 626 is configured by a bandpass filter or the like, and allows a frequency in a predetermined range centered on the intermediate frequency to pass through the intermediate frequency signal input from the frequency conversion circuit 624 and blocks out-of-range frequency components. Output.

  The IF amplifier circuit 627 amplifies (or attenuates) the signal input from the filter circuit 626 with an amplification degree corresponding to the IF control signal input from the AGC circuit 631 and outputs the amplified signal. The filter circuit 628 is configured by a band pass filter or the like, and allows a signal input from the IF amplifier circuit 627 to pass a frequency in a predetermined range, and cuts out and outputs a frequency component outside the range.

  The detection circuit 629 detects the signal input from the filter circuit 628 and outputs a detection signal (signal a). The AGC circuit 631 generates an RF control signal as a gain control signal that adjusts the amplification degree of the RF amplifier circuit 622 according to the strength (signal level) of the detection signal (signal a) input from the detection circuit 629. And an IF control signal is generated and output as a gain control signal for adjusting the amplification degree of the IF amplifier circuit 627.

  The signal reproduction circuit 632 generates a pulse signal synchronized with the data signal (time code signal / standard time data signal) based on the detection signal (signal a) input from the detection circuit, and outputs it as a reproduction signal. The reproduction signal output from the signal reproduction circuit 632 is input to the time code generation unit 70, and a standard time code is generated based on this time code. This embodiment is characterized by this signal reproduction circuit 632.

[Configuration of signal regeneration circuit]
The configuration of the signal reproduction circuit 632 will be described.
FIG. 3 is a diagram showing a circuit configuration of the signal reproduction circuit 632. According to the figure, the signal reproduction circuit 632 includes buffers BF1, BF2, and BF3, a differential amplifier AMP, capacitors C1 and C2, resistors R1, R2, R3, and R4, and a diode D. Is done.

  The detection signal (signal a) output from the detection circuit 629 and input to the signal reproduction circuit 632 is input to the buffer BF1. The buffer BF1 converts the input signal a into a low impedance signal and outputs it.

  One end of the capacitor C1 is connected to the output terminal of the buffer BF1, and the other end is connected to the non-inverting input terminal (+) of the differential amplifier AMP. The resistor R1 has one end connected to the other end of the capacitor C1, and the other end to which a bias voltage V1 is applied. Here, a differentiating circuit is formed by the resistor R1 and the capacitor C1, and the signal output from the buffer BF1, that is, the signal a is differentiated by the differentiating circuit.

  The resistor R2 has one end connected to a point b that is a connection point between the capacitor C1 and the resistor R1, and the other end connected to the inverting input terminal (−) of the differential amplifier AMP. The capacitor C2 has one end connected to the other end of the resistor R2 and the other end grounded (GND). Here, an integrating circuit is formed by the capacitor C2 and the resistor R2, and the signal at the point b, that is, a signal obtained by differentiating the signal a is integrated by the integrating circuit.

  In the differential amplifier AMP, the non-inverting input terminal (+) is connected to the point b, and the inverting input terminal (−) is connected to the point c that is a connection point between the resistor R2 and the capacitor C2. The differential amplifier AMP compares the potential of the signal input to the non-inverting input terminal (+) and the signal input to the inverting input terminal (−), and outputs a signal d based on the comparison result. . Specifically, if the level (potential) of the signal input to the non-inverting input terminal (+) is higher than the level (potential) of the signal input to the inverting input terminal (−), the high level signal d is lowered. For example, a low level signal d is output.

  A signal d output from the differential amplifier AMP is input to the buffer BF2. The buffer BF2 converts the input signal d into a low impedance signal and outputs it as a signal e. This signal e becomes a reproduction signal output from the signal reproduction circuit 632.

  The resistor R3 is a feedback resistor, and has one end connected to the output terminal of the buffer BF2 and the other end connected to the anode of the diode D.

  The diode D has an anode connected to the other end of the resistor R3 and a cathode connected to the point b. The diode D rectifies and outputs the signal e input from the buffer BF2 via the resistor R3.

  That is, the output terminal of the differential amplifier AMP is connected to the point b through the buffer BF2, the resistor R3, and the diode D, and the signal d output from the differential amplifier AMP is sent to the signal a through the buffer BF2. Is fed back (first feedback) to a signal obtained by differentiating the signal (differential signal).

  The buffer BF3 is an inverting buffer, and receives the signal d output from the differential amplifier AMP. The buffer BF3 inverts the phase (voltage level) of the waveform of the input signal d, converts it to a low impedance signal, and outputs it as a signal f.

  The resistor R4 is a feedback resistor, and one end is connected to the output terminal of the buffer BF3 and the other end is connected to the point c. The resistor R4 forms an integration circuit together with the capacitor C2, and the signal f is integrated by this integration circuit.

  That is, the output terminal of the differential amplifier AMP is connected to the point c via the buffer BF3 and the resistor R4, so that the signal d output from the differential amplifier AMP integrates the signal b via the buffer BF3. Feedback (second feedback) is performed on the processed signal (integrated signal).

[Operation of signal regeneration circuit]
The operation of the signal reproduction circuit 632 will be described.
FIG. 4 is a diagram showing a schematic waveform of each signal in the signal reproduction circuit 632. In the figure, in order from the top, the signal (signal a) input to the signal reproduction circuit 632, the signal at point b (signal b1) when the signal d is not fed back (first feedback), and the signal at point b. (Signal b), signal at point c (signal c), signal d output from the differential amplifier AMP, signal e output from the buffer BF2, and signal f output from the buffer BF3 are shown. ing.

  In the figure, the horizontal axis represents time t common to each signal, and the vertical axis represents the signal level (voltage) of each signal. Further, since the signal regeneration circuit 632 is a feedback circuit in which the signal d is fed back (first feedback / second feedback), the figure shows a steady state after a sufficient time has elapsed after the circuit is driven. The waveform of each signal in the case is shown.

  That is, the signal reproduction circuit 632 receives the detection signal (signal a) output from the detection circuit 629. As shown in the figure, the signal a has a waveform including a fluctuation component (noise component) in which the reference level (reference potential) of the data signal greatly fluctuates. Further, this variation is a relatively slow variation with respect to a change in the data signal. Here, the data signal is a time code of a long wave standard radio wave, and as shown in FIG. 9, this is a pulse signal (digital signal) that takes either a high level or a low level.

  This signal a is input to the buffer BF1. The buffer BF1 outputs a signal having the same waveform and the same level as the signal a. The signal having the same waveform and the same level as the signal a output from the buffer BF1 is subjected to differentiation processing by a differentiation circuit formed by the capacitor C1 and the resistor R1. Therefore, the signal at the point b when the signal d is not fed back via the buffer BF2 (first feedback) is a signal having a waveform like the signal b1.

  That is, at time t1 corresponding to the rising edge portion of the data signal included in the signal a, the potential (level) at the point b rapidly increases. At this time, the potential at the point c rises with a delay from the potential increase at the point b by the integrating circuit formed by the resistor R2 and the capacitor C2. Therefore, immediately after time t1, the potential at the point b becomes higher than the potential at the point c, and the differential amplifier AMP outputs a high level signal d.

  The signal d output from the differential amplifier AMP is input to the buffer BF2, and the buffer BF2 outputs a low-impedance signal e having the same waveform and the same level as the signal d.

  By the way, the potential increase at the point b at the time t1 is instantaneous as the signal at the point b (signal b1) when the signal d is not fed back (first feedback) through the buffer BF2. For this reason, when the potential at the point b decreases again and becomes lower than the level (potential) of the signal e, the diode D becomes conductive. Then, a feedback current flows into the capacitor C1 due to the potential difference between the signal e and the point b, and charging of the capacitor C1 is started. When sufficient charge is accumulated in the capacitor C1, the potential at the point b is kept constant. That is, the signal d is fed back to the point b (first feedback), so that the potential at the point b is kept constant.

  The signal d output from the differential amplifier AMP is input to the buffer BF3. The buffer BF3 outputs a signal f obtained by inverting the phase (voltage level) of the signal d. Then, a signal whose level changes with a delay from the level change of the signal f is applied to the point c by the integrating circuit formed by the resistor R4 and the capacitor C2.

  As described above, the potential at the point c rises following the potential increase at the point b, but the signal f obtained by inverting the phase (voltage level) of the signal d is applied via the buffer BF3. This suppresses the potential rise. That is, the signal d is fed back to the point c (second feedback), thereby suppressing the potential rise at the point c. As a result, the potential at the point b is stabilized in a state higher than the potential at the point c, and the high level signal d is continuously output from the differential amplifier AMP.

  Further, at the time t2 corresponding to the falling portion of the data signal included in the signal a, the potential at the point b rapidly decreases. At this time, the potential at the point c drops with a delay from the potential drop at the point b by the integration circuit formed by the resistor R2 and the capacitor C2. Therefore, immediately after time t2, the potential at the point b becomes smaller than the potential at the point c, and the low level signal d is output from the differential amplifier AMP.

  Then, the signal d output from the differential amplifier AMP is input to the buffer BF2, and the signal e having the same waveform and the same level as the signal d is output from the buffer BF2. That is, the level (potential) of the signal e is low level, which is lower than the potential at the point b. For this reason, the diode D becomes non-conductive and the feedback current does not flow into the capacitor C1. Then, the capacitor C1 is completely discharged, and the potential at the point b drops to V1.

  Further, the potential at the point c decreases to the bias voltage V1 with a delay after the potential decrease at the point b. When the potential at the point c decreases to the bias voltage V1, both the potential at the point b and the potential at the point c become equal, and the differential amplifier AMP outputs, for example, a zero level (Low level) corresponding to the GND potential. A signal d is output.

  Then, the signal d output from the differential amplifier AMP is input to the buffer BF3, and the signal f obtained by inverting the phase (voltage level) of the signal d is output from the buffer BF3. Next, a signal that changes so as to follow the level change of the signal f with a delay is applied to the point c by an integration circuit formed by the resistor R4 and the capacitor C2. Therefore, the data signal included in the signal d output from the differential amplifier AMP is inverted in phase via the buffer BF3 and applied to the point c, and the data signal included in the signal a cancels the data signal component. The level (potential) at point c is set to only the fluctuation component (noise component) other than the data signal. Thereby, the differential amplifier AMP compares the signal (signal b) including the fluctuation component and the data signal with the signal (signal c) as the fluctuation component, and based on the result of the comparison, only the data signal component ( The signal e) is output.

  Further, immediately after time t2, since the low level signal d is output from the differential amplifier AMP, a high level signal f obtained by inverting the phase (voltage level) of the signal d is output from the buffer BF3. , C level is applied with a high level signal. However, the signal applied to the point c is a signal whose level rises with a delay from the level rise of the signal f by the integration circuit formed by the resistor R4 and the capacitor C2. For this reason, prior to the increase in the level of the signal applied to the point c, the potential at the point b decreases to the bias voltage V1, and the zero-level signal d is output from the differential amplifier AMP. After that, a high level signal is applied to the point c, so that a low level signal is stably applied to the point b and a high level signal is applied to the point c, and a zero level signal d is output from the differential amplifier AMP. Continue to be.

  Thereafter, the same circuit operation is performed at time t3 corresponding to the next rising portion of the data signal, and at time t4 corresponding to the falling portion of the data signal.

Therefore, the signal at the point b is ideally a pulse signal in which rising / falling is synchronized with the data signal included in the signal a. Further, the Low level matches the bias voltage V1.
When there is no feedback of the signal d (first feedback), the signal at the point b is the high level / low level at the rising / falling edge of the data signal included in the signal a with the bias voltage V1 as the reference level. This is a signal for generating a pulse.

  The signal at point c is ideally a pulse signal whose rise / fall is synchronized with the data signal included in signal a. The low level of this signal matches the bias voltage V1.

  The signal d is a signal output from the differential amplifier AMP based on the comparison result by comparing the level of the signal at the point b with the level of the signal at the point c, and is synchronized with the data signal (data signal). It is a pulse signal. The low level of this signal matches the zero level.

  The signal e is a pulse signal having the same waveform and the same level as the signal d and having the same voltage fluctuation. This signal e is output from the signal reproduction circuit 632 as a reproduction signal obtained by reproducing the data signal included in the signal a. The signal f is a pulse signal obtained by inverting the phase of the signal d, and the High level matches the zero level.

[Action / Effect]
As described above, according to the present embodiment, the detection signal (signal a) output from the detection circuit 629 is input to the signal reproduction circuit 632. In the signal reproduction circuit 632, the signal at point b is a signal obtained by feeding back (first feedback) the signal d output from the differential amplifier AMP to the signal obtained by differentiating the signal a, and the data included in the signal a. The pulse signal is synchronized with the signal (time code signal / standard time data signal).
The signal at the point c includes a signal including a data signal obtained by integrating the signal at the point b and a signal obtained by inverting the phase of the signal (signal d) including the data signal output from the differential amplifier AMP. The data signal components cancel each other, and only the fluctuation component is extracted.
The differential amplifier AMP compares the potential at the point b with the potential at the point c, and outputs a signal d based on the comparison result. The signal d is a data signal included in the signal a. The reproduced signal is output from the signal reproduction circuit 632 as a reproduced signal.
Therefore, the signal d synchronized with the data signal included in the signal a can be generated and output as a reproduced signal of the data signal. In addition, by applying feedback (first feedback) to point b with signal d and applying feedback (second feedback) to point c via buffer BF3, only the data signal from which the fluctuation component has been deleted is obtained. , Can be detected stably and more reliably.

[Modification]
The application of the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention.

(A) The second feedback is not applied to the inverting input terminal (−) of the differential amplifier AMP. When the level fluctuation of the signal a is not so great, the second feedback is applied to the inverting input terminal (−) of the differential amplifier AMP. It is good not to apply.
FIG. 5 is a diagram showing a circuit configuration of the signal regeneration circuit 633 when the second feedback is not applied to the differential amplifier AMP. In the figure, the same elements as those of the signal reproduction circuit 632 shown in FIG. According to FIG. 5, the signal reproduction circuit 633 includes buffers BF1 and BF2, capacitors C1 and C2, resistors R1, R2, and R3, a differential amplifier AMP, and a diode D.

  FIG. 6 is a diagram showing a schematic waveform of each signal in the signal reproduction circuit 633. In the figure, in order from the top, the signal (signal a) input to the signal reproduction circuit 633, the signal at the point b (signal b), the signal at the point c (signal c), and output from the differential amplifier AMP. Each waveform of the signal d1 is shown.

  In the figure, the horizontal axis represents time t common to each signal, and the vertical axis represents the signal level (potential) of each signal. Further, since the signal regeneration circuit 633 is a feedback circuit in which the signal e (signal d) is fed back (first feedback), each signal when a sufficient time elapses after the circuit is driven and becomes a steady state. The waveform is shown.

  In the signal reproduction circuit 633, the signal a is input to the buffer BF1. The signal at point b is a signal having a waveform synchronized with the data signal included in the data signal a. Further, the signal at the point c is a signal having a waveform obtained by integrating the signal at the point b by an integrating circuit formed by the resistor R2 and the capacitor C2. Further, the potential of the signal at the point c becomes equal to the potential at the point b over time.

  The differential amplifier AMP outputs a signal d1 based on the comparison result between the level of the signal at the point b and the level of the signal at the point c. The signal d1 is a pulse signal synchronized with the signal b. The signal d1 rises in synchronization with the signal at the point b and remains at a high level until the signal c falls. However, it is difficult to output the data signal for a long time, and the signal d1 is pulsed more than the data signal. The width is short.

(B) Application to a straight type radio wave receiver For example, in the above-described embodiment, the superheterodyne type radio wave receiver 62 is used, but this is used as a straight type radio wave receiver 63 shown in FIG. It is also good.

  FIG. 7 is a diagram showing a circuit configuration of the straight-type radio wave receiver 63. In the figure, the same components as those of the radio wave receiving device 62 (see FIG. 2) described above are denoted by the same reference numerals. According to FIG. 7, the radio wave receiver 63 includes a receiving antenna 621, an RF amplifier circuit 622, a filter circuit 623, a detection circuit 631, a signal regeneration circuit 632, and an AGC circuit 629. . In this case, the signal output from the filter circuit 623 is input to the detection circuit 631, and the AGC circuit 629 generates an RF control signal for controlling the amplification degree of the RF amplifier circuit 622.

(C) Application to Relay Device In the above-described embodiment, the case where the present invention is applied to a radio timepiece has been described. However, the present invention may be applied to a relay device. The relay device is a device that is installed near a window of a building such as a steel house where radio waves are difficult to reach inside, receives long wave standard radio waves, obtains accurate time information, and transmits this time information. The radio timepiece installed indoors receives the time information transmitted from the relay device and corrects the time.

  FIG. 8 is a block diagram showing an internal configuration of the relay apparatus 2 to which the present invention is applied. In the figure, the same elements as those of the above-described radio timepiece 1 (see FIG. 1) are denoted by the same reference numerals. According to FIG. 8, the relay device 2 includes a CPU 10, an input unit 20, a display unit 30, a RAM 50, a ROM 40, a reception control unit 60, a time code generation unit 70, a timing circuit unit 80, an oscillation circuit The circuit unit 82 and the transmission unit 90 are provided.

  The transmission unit 90 generates a relay time code based on the current time data timed by the time measuring circuit unit 80, adds a carrier wave to the relay time code to generate a relay radio wave, and transmits the relay time code via a transmission antenna. The carrier wave at this time may be the same as the received long wave standard radio wave, or may be a dedicated radio wave as a relay radio wave. When it is the same as the long wave standard radio wave, the radio wave clock installed in the room or the like may be a normal radio wave clock. In addition, when a dedicated radio wave is used as a relay radio wave, the radio-controlled timepiece needs a means for receiving the radio wave.

The circuit block diagram of the radio timepiece to which the present invention is applied. 1 is a circuit configuration diagram of a superheterodyne radio wave receiver. FIG. The circuit block diagram of a signal reproduction circuit. FIG. 4 is a schematic waveform diagram of each signal in the signal reproduction circuit of FIG. 3. The circuit block diagram of the signal reproduction circuit which does not apply a 2nd feedback. FIG. 6 is a schematic waveform diagram of each signal in the signal reproduction circuit of FIG. 5. The circuit block diagram of the radio wave receiver of a straight system. The circuit block diagram of the relay apparatus to which this invention is applied. Long wave standard time code format.

Explanation of symbols

1 Radio clock 10 CPU
20 Input unit 30 Display unit 40 ROM
50 RAM
60 reception control unit 62 radio wave receiving device 621 antenna 622 RF amplification circuit 623, 626, 628 filter circuit 624 frequency conversion circuit 625 local oscillation circuit 627 IF amplification circuit 629 detection circuit 631 AGC circuit 632, 633 signal reproduction circuit BF1, BF2, BF3 Buffer AMP Differential amplifier C1, C2 Capacitor R1, R2, R3, R4 Resistor D Diode 70 Time code generator 80 Timekeeping circuit 82 Oscillator circuit 2 Relay device 90 Transmitter

Claims (3)

Detection means for detecting a reception signal received by an antenna and outputting a detection signal including a data signal that takes either a high level or a low level; and a signal reproduction means for outputting a reproduction signal reproduced based on the detection signal In a radio wave receiving apparatus comprising:
The signal reproducing means includes
Differentiating means for outputting a differential signal whose level changes in response to a rise to a high level and a fall to a low level of a data signal included in the detection signal by differentiating the detection signal;
Integrating means for integrating the differential signal and outputting an integrated signal;
It has a first input terminal to which the differential signal is input and a second input terminal to which the integral signal is input, and the level of the signal input to the first input terminal is the second input terminal. A comparison means for outputting a high level signal when the level is higher than an input signal level, and a low level output signal when the level is lower ;
After the output signal of the comparison means becomes High level, the output signal becomes low level when the level of the differential signal input to the first input terminal falls below the level of the output signal of the comparison means. In the meantime, first feedback means for holding the level of the first input terminal constant by feeding back the output signal of the comparison means to the first input terminal ;
A second feedback means for suppressing an increase in the level of the integral signal input to the second input terminal by inverting the output signal of the comparison means and feeding it back to the second input terminal;
And outputting the output signal of the comparison means as a reproduction signal obtained by reproducing the data signal included in the detection signal . A radio wave receiver according to claim 1 ;
Time code generating means for generating a standard time code based on a reproduction signal output from the radio wave receiver;
A time measuring means for measuring the current time;
Correction means for correcting the current time measured by the time measuring means based on the standard time code generated by the time code generating means;
A radio-controlled timepiece characterized by comprising: A radio wave receiver according to claim 1 ;
Time code generating means for generating a standard time code based on a reproduction signal output from the radio wave receiver;
Transmission means for amplitude-modulating and transmitting the standard time code generated by the time code generation means;
A relay device comprising:

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