JP4191774B2 - Microcomputer and display control device - Google Patents

Description

  The present invention relates to a technique that is useful when applied to a display control device that performs display output by superimposing a plurality of display surfaces, and particularly relates to a technique that is useful for a navigation system that displays a map of the current position.

  A display system for displaying on a screen of a liquid crystal display panel or a CRT display device generally includes a frame memory for storing image data in which pixel data for one screen is arranged, and a drawing processor or the like is used for the frame memory. While the display dot pixel data is written, the display processing circuit continuously reads out the pixel data of the frame memory, converts it into a display signal in synchronization with the vertical synchronizing signal of the display device, and outputs the display signal.

  There is also a display system in which the above-described frame memory is provided for two screens, and drawing and display output are performed while alternately switching an area for writing image data and an area for reading image data for display output. . By using the frame memory for two screens in this way, a time margin can be obtained for the image data writing process and the display output process, and the screen output caused by the display output being performed during the image data writing process can be obtained. The advantage that flicker can be avoided is obtained.

  In addition, in a display system having a frame memory capable of storing image data for two screens, when there is no need to update display contents over a plurality of display frame periods, a memory area for writing image data and a memory for reading image data There is also a type in which display output is performed by repeatedly using image data in the same memory area without changing the area. In addition, when the next screen drawing process is completed and the display content can be updated, automatic switching is performed to automatically switch the memory area for writing image data and the memory area for reading image data at an appropriate timing. Some display systems have a function (auto-rendering mode). For example, when the drawing circuit fetches a predetermined command indicating the end of the drawing process for one screen, the auto-switching function notifies the display processing circuit that drawing has ended, and the display processing circuit displays This is realized by switching the memory area from which image data is read in accordance with the synchronization signal of the apparatus (for example, Non-Patent Document 1).

“HD64413A Q2SD User Manual” (SuperH RISC engine Peripheral LSI HD64413A Q2SD User ’s Manual), Hitachi, Ltd. (Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd.), May 2000, P47-49

  In recent years, a variety of display systems have been developed in which a plurality of display surfaces (also referred to as display planes or layers, hereinafter referred to as display planes) are provided on a display screen, and the display control is performed such that the display planes are superimposed on each other. Is now required. In such display control, a memory area (hereinafter referred to as an image data storage area) for storing image data is provided for each display plane, and image data written in the image data storage areas of a plurality of display planes is displayed for each display plane. This is realized by converting the display signal after superimposing it in accordance with the display position of the plane. In such a display system, there is a problem that the writing time of the image data is less than that in the display without superimposing and the display output is likely to flicker. Moreover, in order to suppress this, there is a problem that a high-speed processing apparatus is required, resulting in an increase in cost.

  Therefore, the present inventors set an image data storage area for two pages for each display plane in the display memory, an image data storage area for writing image data, an image data storage area for reading image data for display output, I came up with a control to switch between. However, in such a switching control method, it is useful to switch the image data storage area simultaneously for a plurality of display planes depending on the display contents of each display plane, or to perform it at different timing for each display plane. However, various cases are assumed, and if the image data storage area is switched in a uniform pattern, there arises a problem that various display processes cannot be handled.

  Further, since the switching of the image data storage area must be performed in synchronization with the vertical synchronization signal VSYNC of the display device, for example, when switching control is performed at different timings for a plurality of display planes by the control processing of the CPU, The load on the CPU becomes very high and the throughput of the entire system is reduced. Moreover, in the navigation system, there is a restriction that the CPU performance cannot be increased so much for cost reduction, and the load of the CPU cannot be increased for display control. There is also a peculiar problem that switching control must be performed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a display system capable of eliminating display flicker without using a high-speed processing device in a display system that performs display output by superimposing a plurality of display planes, and further superimposing a plurality of display planes. Another object of the present invention is to provide a display system that can switch the optimum image data storage area with high versatility and without waste.

  Another object of the present invention is to provide a display system capable of switching the image data storage area of each display plane without applying a load to a CPU (central processing unit) that performs system control.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Outlines of representative ones of the inventions disclosed in the present application will be described as follows.

  That is, in a display system in which an image data storage area is set in which a plurality of display planes can be stored and image data for a plurality of units (multiple pages) can be stored for each display plane. Display switching enable bits (D0 to D7) indicating whether or not to switch the image data storage area for each display plane, in the attribute bit of the first instruction (for example, TRAP command) indicating the end of the development of the image data of the display plane ) To switch the image data storage area from which image data is read out at the timing synchronized with the next vertical synchronization signal for the display plane whose display switching enable bit (D0 to D7) is “1”. .

  According to such a means, the switching of the image data storage area from which the image data is read can be performed independently for each of the plurality of display planes. Therefore, even when the display content is updated for each display plane, it is useless. It is possible to switch optimally without any problems. In addition, the image data storage area can be controlled to be switched without increasing the load on the CPU, etc., as the image data storage area can be set to be switched during image data expansion processing using a command interpreted and executed in the display control device. It is.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, in a display system in which image data storage areas for a plurality of pages are set for each display plane, only display planes whose display contents have been updated are switched or related two or more. For example, it is possible to perform optimal display switching control that is versatile and wasteful, such as switching the display of the display planes simultaneously.

  Further, since display switching can be set using a command executed by the display control device, there is an effect that display switching can be performed at an appropriate timing without increasing the load on the CPU that performs system control.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing details of the entire system and main parts when the present invention is applied to a car navigation system. Although not particularly limited, in the figure, a plurality of circuit blocks in a region surrounded by reference numeral 2 are formed on one semiconductor substrate such as single crystal silicon.

  The car navigation system according to the present embodiment includes a CPU 1 that performs system control such as calculation of a current position based on position information from a measurement device, input processing from a user, and instructions for display output, and display according to a drawing command generated by the CPU 1. A display control device 2 for performing a drawing process for writing image data to the memory 4 and a display output process for reading out the image data from the display memory 4, converting it into a display signal and outputting it, and a DRAM for providing the CPU 1 with a working memory space ( Direct Random Access Memory), a display memory 4 such as a DRAM that stores drawing commands and image data, a display device 5 such as a liquid crystal display, a flash memory that stores a startup program, a mask ROM, and the like Non-volatile memory 6 that can retain data even after the power is turned off, and map data Etc. a storage device 7 in which the large-capacity storage medium is mounted, such as DVD (digital versatile disc) or a hardware disk storing the composed from the system bus 10 and the display memory bus 11 and the like.

  Although not shown, an input device such as a touch panel is connected to the system bus 10, and current positions such as a GPS (Global Positioning System) receiver, a direction measuring device, and a gas rate sensor are provided. A positioning device that measures the distance is connected. The map data may be received from a computer network via a communication unit without being stored in the storage device 7.

  The car navigation system of this embodiment is configured to be capable of display output in which a plurality of display planes on which different types of display such as wide area map display, detailed map display, and menu display are performed are superimposed. The CPU 1 creates a series of drawing command sequences (hereinafter referred to as display lists) for developing image data in the display memory 4 in accordance with display contents, and stores them in the display memory 4. Then, the drawing unit 20 of the display control device 2 reads out and executes the drawing command from the designated display list based on the designation of the display list and the drawing start instruction from the CPU 1, and the image data is stored in the designated image data storage area of the display plane. Expand. In this embodiment, a TRAP command as a first command indicating the end of drawing is appended to the end of the display list. When the drawing unit 20 reads this TRAP command, the drawing process is interrupted and the CPU 1 is interrupted. It is configured to output a signal and wait for the next drawing start instruction from the CPU 1.

  In the display memory 4, an image data storage area is set for each display plane, and image data of the display plane corresponding to each image data storage area is developed by the drawing unit 20. Further, in this embodiment, the image data storage area is provided for a plurality of pages (for example, 2 pages or 3 pages) for one display plane. The drawing unit 20 has a drawing destination address register for storing the start address of the image data storage area of the drawing destination. The CPU 1 performs drawing from the image data storage areas for a plurality of pages of a plurality of display planes in this register. It is configured such that image data can be expanded in the image data storage area of the designated page of the display plane to be designated by setting the start address of the image data storage area and starting the drawing process.

  FIG. 2 shows a more detailed block configuration diagram of the display control apparatus 2.

  The display control device 2 includes a drawing unit 20 having a drawing processing unit 27 and a buffer unit 28 that interpret and execute drawing commands, a CPU interface unit 21 that is connected to the system bus 10 and performs data input / output from the CPU 1. A display unit 22 that reads out pixel data of a plurality of display planes from the display memory 4 and superimposes them, converts them into video signals, and outputs them; and a memory control unit 23 that controls reading and writing of data to the display memory 4. I have.

  The display control device 2 includes memory buses MDB and MAB to which data and addresses of the display memory 4 are transferred, CPU buses CDB and CAB to which data and addresses on the system bus 10 side are transferred, and these A bus controller 25 that controls access of each block to the bus is provided. The CPU interface unit 21, the display unit 22, and the memory control unit 23 input and output data via the I / O buffers 26a to 26c, respectively, and the drawing processing unit 27 receives drawing commands via the buffer unit 28. Fetching and pixel data writing are performed.

  The display unit 22 reads the image data of the designated page of each display plane from the display memory 4 in accordance with the display timing, and displays the pixel data of each display plane so as to overlap with the display position of each display plane. A display plane generating unit 24 that converts the signal into a signal and outputs the signal is provided. The drawing processing unit 27 is provided with various registers such as a drawing attribute register (DAR) 201, a control register, and a status register.

  FIG. 3 shows the configuration and some functions of the drawing attribute register 201 provided in the drawing processing unit 27.

  The drawing processing unit 27 sequentially reads and executes drawing commands from the display list for each display plane generated by the CPU 1 and stored in the display memory 4, but sets drawing attributes globally for a plurality of drawing commands. For this purpose, the drawing attribute register 201 is provided in the drawing processing unit 27 as described above, and a drawing command is executed in accordance with the attribute contents set in the drawing attribute register 201. . The drawing command that can be decoded by the display control apparatus 2 of this embodiment also includes a drawing attribute value, and the attribute value set in the drawing attribute register 201 is different from the drawing attribute value included in each drawing command. If it is a value, any attribute value is given priority according to a value preset in a control register (not shown) or the like.

  As shown in FIG. 3, the drawing attribute register 201 is provided with eight auto switching mode enable bits D00 to D07 indicating whether or not automatic display switching control is permitted for each of a plurality of (for example, eight) display planes. It has been. Here, the automatic display switching control will be described in detail later, but after the drawing process of one display plane is completed, an image for display output is displayed from the next display frame period based on display switching enable bits D0 to D7 described later. This is control processing for switching the page of the image data storage area from which data is read to the next page.

  The drawing attribute register 201 is configured such that the CPU 1 can directly write an attribute value, or the drawing processing unit 27 can write the attribute value by a control command that can be interpreted by the drawing processing unit 27. Yes.

  The auto switching mode enable bits D00 to D07 are not included in the drawing attribute register 201 of the drawing processing unit 27, but may be included in a display-related register provided in the display unit 22, for example. It may be included in a setting register outside the drawing processing unit 27 or the display unit 22.

  FIG. 4 is a bit configuration diagram showing an example of a TRAP command indicating the end of drawing processing of one display plane which is one of control commands.

  In the display list stored in the display memory 4, in addition to the original drawing command for performing drawing processing such as lines and polygons, a control command for writing a value in the drawing attribute register 201 or for performing drawing end processing. Is included.

  The TRAP command indicates the end of processing of each display list generated for each display plane. The drawing processing unit 27 sets, for example, predetermined bits of a control register that controls the operation of the drawing processing unit 27 based on the TRAP command. “0” is set to stop the operation of the drawing processing unit 27, and a predetermined bit of the status register is set to “1” to output an interrupt signal to the CPU 1 to notify the CPU 1 of the end of the drawing process. .

  Further, in the display control apparatus 2 according to this embodiment, as shown in FIG. 4, an image data storage area for reading out image data of each display plane is provided in the drawing attribute part of the TRAP command for performing drawing end processing. Display switching enable bits D0 to D7 for switching to a page are provided, and are used for switching control of the image data storage area of the display plane.

  FIG. 5 shows a schematic configuration diagram of the display plane generation unit 24 included in the display unit 22.

  The display plane generating unit 24 is provided corresponding to each of the display planes, one display compositing unit 241 for processing pixel data to obtain an image obtained by superimposing images of a plurality of display planes. A plurality of (for example, eight) display plane processing units are provided. Each display plane processing unit includes a pixel data buffer (line buffer) 242A, a buffer control unit 242B, a selection circuit 243, a display address register 244, and a selection signal generation state machine 245 as a first register.

  The display composition unit 241 is input from the plurality of pixel data buffers 242A on the basis of the information regarding the blend ratio of the pixel data of each display plane set in the attribute register (not shown) and the information indicating the vertical relationship of each display plane. An arithmetic process for superimposing the obtained pixel data is performed and output. Then, the output pixel data is converted into an analog display signal or the like and output to the display device 5 to perform display output in which a plurality of display planes are superimposed at a predetermined position. When the blend ratio is 1: 0, the display output is such that the upper surface is completely hidden from the lower surface, and when the blend ratio is, for example, 3: 1, the lower surface is a display output that is slightly transparent. In addition, it is possible to configure so that any of the operations to be performed can be selected by using a logical operation such as OR, AND, and Ex-OR.

  The pixel data buffer 242A is a buffer memory having a size capable of storing, for example, one-tenth of pixel data of pixel data for one display line.

  The buffer control unit 242B counts a high-frequency clock signal generated internally in synchronization with the vertical synchronization signal VSYNC of the display device 5, and at a timing that matches the display position of the corresponding display plane, The pixel data is read from the display memory 4, stored in the pixel data buffer 242A, and output so that the data is output to the display composition unit 241.

  The display address register 244 stores the start address (display information) of the image data storage area for a plurality of pages of the corresponding display plane. In this display address register 244, for example, when the number of display planes is increased or decreased or the size of the display plane is changed, the CPU 1 writes the start address of each image data storage area changed accordingly. Note that the value of the display address register 244 is preferably rewritten when the vertical synchronizing signal VSYNC of the display device 5 falls.

  The selection circuit 243 is configured to selectively supply any one of a plurality of head addresses stored in the display address register 244 to the buffer control unit 242B based on a display destination selection control signal described later. The buffer control unit 242B can read the image data of any page in the image data storage area for a plurality of pages based on the head address.

  The selection signal generation state machine 245 indicates one of a plurality of pages of image data storage areas set in the corresponding display plane, and is synchronized with the vertical synchronization signal VSYNC of the display device 5 (for example, the synchronization signal VSYNC At the time of falling), a signal indicating the page of the image data storage area used at that time is output to the selection circuit 243. This signal becomes a display destination selection control signal of the selection circuit 243.

  The state machine 245 receives the corresponding display plane bit from the display switching enable bits D0 to D7 of the TRAP command, and when the value is “1”, the state machine 245 changes the state by one to indicate the next page. On the other hand, when the value is “0”, the state is not changed while pointing to the same page as before. The indicated page is shifted in the same order as the page order in which the drawing process is executed. The display switching enable bits D0 to D7 are sent from the drawing unit 20 to the display unit 22 via the signal line L0 and input to the selection signal generation state machine. Such a state machine 245 can be composed of, for example, a shift register and a logic circuit that performs signal discrimination and the like.

  Even when the display switching enable bits D0 to D7 of the corresponding display plane are “1”, the value of the corresponding display plane of the auto switching mode enable bits D00 to D01 set in the drawing attribute register 201 is “0”. In the case of "", the state transition is not performed.

  As described above, the selection signal generation state machine 245 of each display plane transitions according to the enable bits D0 to D7 output at the end of drawing of one display plane, and the page of each display plane is synchronized with the vertical synchronization signal VSYNC. It has become to switch.

  The selection signal generation state machine 245, the display address register 244, the selection circuit 243, the pixel data buffer 242A, and the buffer control unit 242B can select any one of the image data storage areas for a plurality of pages associated with each display plane. The image data is read out from the image and subjected to display output processing, and the page to be displayed and output in the next display frame is switched for each display plane based on the display switching enable bits D0 to D7 of the TRAP command. Independent display switching control is possible for each display plane.

  Next, the drawing process and the display switching control by the display control device 2 having the above-described configuration will be described in detail with reference to some patterns.

  6 to 8 are time charts of first to third examples for explaining the timing of drawing processing and display switching. In the figure, VSYNC is a vertical synchronizing signal of the display device 5. In the time charts of FIGS. 6 to 8, it is assumed that two pages of image data storage areas are set for each display plane.

  In the display system according to this embodiment, page switching for reading out image data for display output is independently performed for each display plane by a TRAP command executed when drawing of any one display plane is completed. Further, the actual reading page of the image data is switched after the switching setting at a timing synchronized with the vertical synchronization signal VSYNC of the display device 5.

  The time chart of FIG. 6 sets the page switching of the first display plane “0” at the end of the drawing process of the first display plane “0” and at the end of the drawing process of the second display plane “1”. This shows a pattern in which the page switching setting of the second display plane “1” is performed.

  In such a control pattern, in the period of the display frames T1 and T2 in which drawing is performed in the image data storage area of the first address “ADR00” of the first display plane “0”, drawing has already been completed. The image data is read from the image data storage area of the address “ADR01”, the display output process is performed, and the switching setting is performed during the period of the display frames T3 to T6 that starts after the page switching setting at the end of the rendering process is performed. The image data in the image data storage area of the head address “ADR00” is read and the display output process is performed.

  Similarly, in the second display plane “1”, the image data of “ADR11” that has already been drawn is stored in the display frames T1 to T4 during or before drawing in the image data storage area of the head address “ADR10”. The display output process of the area and the display output process of the image data storage area of “ADR10” that has finished drawing in the period of display frames T5 and T6 that are started after the page switching setting at the end of drawing is made. Done.

  The control pattern for performing the page switching setting for the display frame that has been rendered in this way is useful when it is desired to update the display immediately after the rendering is completed.

  In the time chart of FIG. 7, the page switching setting is not performed at the end of drawing of the first display plane “0”, and the page switching setting of the 0th and first display planes is not performed at the end of drawing of the second display plane “1”. This is the pattern that was done.

  In this pattern, the read page is not switched in the display frames T3 and T4 after the drawing of the first display plane “0” is finished, and the display frame T5 is started from the display frame T5 that is started after the drawing of the second display plane “1” is finished. The page switching between the first display plane “0” and the second display plane “1” is performed simultaneously.

  Such a control pattern is useful when it is desired to simultaneously switch the display of a plurality of display planes.

  The time chart in FIG. 8 is a control pattern for setting page switching for a display plane that has been drawn, and shows a case where drawing processing of a plurality of display planes has been completed during the period of one display frame T1. .

  In such a case, since the page switching is set for each of the first to third display planes during the period of one display frame T1, the display of the first to third display planes is performed in the next display frame T2. It can be switched at the same time.

  In such a control pattern, for example, when the drawing processing time is extended and the drawing end timing of the third display plane “2” is shifted to the period of the display frame T2, the first and second display planes “ Only the display of 1 ”is switched at the same time, and the display of the third display plane“ 2 ”is switched in the next display frame.

  As described above, according to the display system according to this embodiment, since the page to be displayed and output can be switched independently for each display plane, the display contents are updated on only some display planes. In such a case, only the display plane that has been updated can be switched, so that an optimal display process without waste is possible. Further, when it is desired to switch the display of a plurality of display planes at the same timing, it can be handled by the control pattern shown in FIG.

  In general, it is convenient to have an image data storage area for three pages in order to input and output an analog video signal. However, in a display plane for displaying a graphic image that has been drawn, two pages are stored. Even if an image data storage area with a different number of pages is set for each display plane, such as setting an image data storage area for 3 pages and setting an image data storage area for 3 pages on the display plane for video output Switching control is possible.

  Further, according to the display system according to the present embodiment, the page switching setting is performed using the command interpreted or executed by the drawing unit 20 or the value set in the register, so that the CPU 1 controls the display switching. Does not increase the load. Particularly, in the case of a system configuration in which the drawing unit 20 performs drawing processing according to a display list generated in advance for each display plane as in a car navigation system and generates image data, display switching control is performed without using drawing commands. In other words, it is necessary to control which display plane the CPU 1 performs display switching at the end of one display list drawing process, which increases the load on the CPU 1. In the navigation system, since the CPU 1 always performs measurement of the current position, input / output control, etc., there is a situation that it is not desired to take much time for the display control processing. Therefore, it is very effective to perform display switching control without increasing the load on the CPU 1 as in the above-described embodiment.

  The invention made by the present inventor has been specifically described on the basis of the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

  For example, in the embodiment, the switching setting of the page from which image data is read is performed by the TRAP command indicating the end of the drawing process, but the same switching setting is performed by another command or a dedicated control command. You can also.

  In the embodiment, the drawing attribute register 201 is provided with auto switching mode enable bits D00 to D07 for determining the validity of the display switching enable bits D0 to D7 of the TRAP command. Only the display switching enable bits D0 to D7 may be set to switch pages for reading image data.

  Alternatively, the display switching enable bit D0 to D7 of the TRAP command may be eliminated, and the display switching setting may be performed only with the auto switching mode enable bits D00 to D07 of the drawing attribute register 201. In this case, page switching may be automatically performed at the end of drawing for a display plane in which the auto switching mode enable bits D00 to D07 are set to enable “1”.

  Further, in the above embodiment, it is assumed that each bit of the display switching enable bits D0~D7 and auto-switching mode enable bit D00~D07 is fixed or corresponding in advance which display plane, display each bit and a plurality of A setting register for setting the correspondence with the plane may be provided so that the correspondence can be changed dynamically or statically.

  FIG. 9 shows another configuration example of the display system to which the present invention is applied.

  In the above embodiment, the display control device 2 in FIG. 1 has been described as having a single chip configuration. However, as shown in FIG. You may make it mount in a navigation system. At that time, the nonvolatile memory 6 and the display memory 4 can be mounted in the microcomputer 100. Further, the semiconductor memory 3 that provides the work area of the CPU 1 and the display memory 4 can be configured as a single memory without being configured separately.

  In the above embodiment, the drawing unit 20 is exemplified as the image data generating means. For example, MPEG (Motion Picture Experts) capable of developing image data of a plurality of videos in image data storage areas of a plurality of display planes. Various configurations such as (Group) decoder 29 can also be applied. When the present invention is applied using the MPEG decoder 29 as the image data generation means, for example, the page switching setting of each display plane can be performed independently at the end of the development process of image data for one screen. do it.

  In addition, even in a display system that performs composite display of drawing graphics, MPEG video, and video input on a plurality of display planes, it is possible to independently set read page switching settings for each display plane. Similar effects can be obtained. For example, when video display of video input is performed at different display speeds, or when video of MPEG moving images with different frame rates is displayed depending on the compression method, the page switching timing differs for each display plane. Is effective.

  In the above description, the case where the invention made mainly by the present inventor is applied to the car navigation system, which is the field of use behind it, has been described. However, the present invention is not limited to this, and a handy navigation system or PDA ( It can be widely used for various display systems such as Personal Digital Assistant).

1 is a block diagram showing an overall configuration of a car navigation system to which the present invention is applied. It is a block diagram which shows the detail of the display control apparatus of FIG. It is a figure which shows a part of drawing attribute register provided in the drawing part of FIG. It is a bit block diagram which shows an example of the TRAP command of an Example. It is a figure which shows schematic structure of the display plane production | generation part of FIG. It is a time chart which shows the 1st operation example of a drawing process and display switching. It is a time chart which shows the 2nd operation example of a drawing process and display switching. It is a time chart which shows the 3rd operation example of a drawing process and display switching. It is a block diagram which shows the other structural example of the display system to which this invention is applied.

Explanation of symbols

1 CPU
2 Display control device 4 Display memory 5 Display device 7 Storage device 20 Drawing unit (image data generation means, image data storage means, drawing circuit)
22 Display unit (display processing circuit)
24 Display plane generating unit 27 Drawing processing unit 29 MPEG decoder (image data generating means)
201 Attribute Register 241 Display Composition Unit 242A Pixel Data Buffer 242B Buffer Control Unit 243 Selection Circuit 244 Display Address Register 245 Selection Signal Generation State Machine (First Register)
VSYNC Vertical sync signal (display transition sync signal)

Claims (4)

A microcomputer having a central processing unit and a display control device for performing drawing processing and display control, and capable of connecting a memory capable of storing image data to the outside,
The display control device has a display unit for controlling display information indicating a storage destination of image data for outputting a display signal to a display device connected to the outside,
The display unit includes a plurality of display plane processing units each handling image data of a plurality of display surfaces that can be displayed superimposed on a display screen, and a display synthesis unit .
The display plane processing unit has a plurality of display information indicating address information of the memory that is a storage destination of image data of a corresponding display surface,
The display composition unit reads image data of a plurality of display surfaces from the memory according to the display information, and further superimposes the read image data to output to the display device. processing the signal,
The display control device receives a first command at the end of each drawing process on the plurality of display surfaces,
The first instruction has an enable bit for switching the display information to a storage area for data to be displayed next,
The display control device can update the display information used in the plurality of display plane processing units in accordance with the enable bit after receiving the first instruction. .   2. The microcomputer according to claim 1, wherein display information used in the plurality of display plane processing units is updated at a timing synchronized with a vertical synchronization signal of the display device.   3. The microcomputer according to claim 1, wherein two or more pieces of display information used in the display plane processing unit can be updated simultaneously.   4. The microcomputer according to claim 3, wherein the first instruction has a plurality of enable bits corresponding to a plurality of display surfaces.

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