JP4192305B2 - Solid-state image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state image pickup device, and more particularly to an amplification type solid-state image pickup device in which a large number of pixels each having an amplification unit that outputs a signal corresponding to incident light and a control unit that controls the amplification unit are arranged. It is.
[0002]
[Prior art]
Conventionally, an amplification type solid-state imaging device that amplifies a signal generated in each pixel in response to incident light and outputs the amplified signal has been proposed.
FIG. 19 is a circuit diagram showing a main configuration of a conventional solid-state imaging device.
The conventional solid-state imaging device includes a plurality of pixels Px1-1 to Px3-4 arranged in a two-dimensional matrix, a vertical scanning circuit 7 that drives each pixel Px1-1 to Px3-4 for each row, and each pixel. Px1-1 to Px3-4 are composed of vertical signal lines 22a to 22d, a horizontal signal line 27, and a horizontal scanning circuit 8 connected to each column.
[0003]
Each pixel generates and stores a charge corresponding to incident light, and a junction field effect transistor (hereinafter referred to as JFET) that outputs a signal corresponding to the charge from a source (S) by a source follower operation. 2, a transfer gate 3 for transferring the charge from the photodiode 1 to the JFET 2, a control region 4 for controlling the JFET 2, and a control gate 5.
[0004]
The source (S) of each JFET 2 is connected to the vertical signal lines 22a to 22d for each column, and the drain (D) of each JFET 2 is connected to the drain power supply VD in common for all pixels.
The transfer gate 3 is connected to the transfer gate lines 20a to 20c for each row and is driven for each row by pulses φTG1 to φTG3 sent from the vertical scanning circuit 7.
[0005]
The control region 4 is connected to the control region wirings 24a to 24c for each row, and is driven for each row by pulses φRD1 to φRD3 sent from the vertical scanning circuit 7.
The control gates 5 are connected to each row by the control gate lines 21a to 21c, and are connected in common by connecting these lines, and are driven by the drive pulse φRG.
[0006]
For the vertical signal lines 22a to 22d, constant current sources 26a to 26d serving as loads of the JFET 2, reset transistors TRV1 to TRV4 for fixing the vertical signal line to a constant voltage (VRV), and an operating band of the JFET 2 are limited. Are connected to vertical load capacitors Cv1 to Cv4, column buffer amplifiers 29a to 29d, clamp capacitors Cc1 to Cc4, and clamp transistors TC1 to TC4. The vertical signal lines 22a to 22d are connected to the horizontal signal line 27 via column selection transistors TH1 to TH4.
[0007]
An output buffer amplifier 28 and a reset transistor TRH are connected to the horizontal signal line 27.
FIG. 20 is a pulse timing chart for explaining the operation of the circuit diagram shown in FIG. The operation of the conventional solid-state image sensor will be described with reference to this figure. As will be described later, since the transfer gate 3 and the control gate 5 constituting each pixel are P-channel type (see FIGS. 22 and 23), they are in a conductive (ON) state when a pulse applied to them is at a low level. Thus, when these pulses are at high level, they are cut off (off).
[0008]
In FIG. 20, the period from t11 to t15 corresponds to the readout operation of the pixels in the first row, and the periods from t21 to t25 and t31 to t35 are respectively shown in the second row and the third row. It corresponds.
First, in a period t11, φRG is set to a low level, and the control gates 5 of all the pixels are turned on (on). Further, the drive pulse φRD1 is set to a high level (φRD2 and φRD3 remain at a low level), and a high level voltage is applied from the control region 4 to the gate region of the JFET 2 of the pixel in the first row via the control gate 5. A low level voltage is supplied to the gate region of JFET 2 in the second and subsequent rows. That is, the JFET 2 in the first row is supplied with a high-level voltage to the gate region via the control region 4 to put the JFET 2 into an operating (selected) state. Further, the JFET 2 in the second and subsequent rows is supplied with a low level voltage to the gate region via the control region 4 so that the JFET 2 is in a non-operating (non-selected) state.
[0009]
At the end of the period t11, when the drive pulse φRG is set to the high level and the control gates 5 of all the pixels are turned off (off), the JFET 2 in the first row is in the operating (selected) state, and the JFETs 2 in the second row and thereafter are The floating state is maintained while maintaining the non-operating (non-selected) state. That is, in the period t11, the row selection operation and the JFET 2 initialization operation are performed.
[0010]
In the period t12, the drive pulse φRV is set to the low level, the reset transistors TRV1 to TRV4 are cut off (off), and the JFET 2 in the first row performs the source follower operation. Accordingly, the output (dark output) voltage corresponding to the potential immediately after the initialization of the gate region of JFET 2 is clamped capacitor Cc 1 from the source (S) of JFET 2 through vertical signal lines 22 a to 22 d and column buffer amplifiers 29 a to 29 d. ˜Cc4 is applied to one end (vertical signal lines 22a to 22d side, hereinafter referred to as an input end). Further, the drive pulse φC is at a high level, and the clamp transistors TC1 to TC4 are in a conductive (ON) state, and the other ends of the clamp capacitors Cc1 to Cc4 (the horizontal signal line 27 side, hereinafter referred to as an output end) are at the ground potential. is there.
[0011]
At the end of the period t12, when the drive pulse φC is set to the low level and the clamp transistors TC1 to TC4 are cut off (off), the output (dark output) voltage is held in the clamp capacitors Cc1 to Cc4, and the clamp capacitor Cc1 The output terminal of .about.Cc4 is in a floating state. That is, the dark output voltage is clamped.
[0012]
In the period t13, the driving pulse φTG1 is set to the low level (the driving pulses φTG2 and φTG3 remain at the high level), and the transfer gates 3 of the pixels in the first row are turned on, and the photodiodes in the first row are set. The signal charge generated and stored in 1 is transferred to the gate region of JFET 2. Note that the potential of the gate region of JFET 2 after the transfer of the signal charge changes (in this case, increases) by the amount of the signal charge / gate capacitance.
[0013]
At the end of the period t13, when the drive pulse φTG1 is set to the high level to turn off the transfer gate 3, the photodiode 1 in the first row enters the next signal charge accumulation operation by photoelectric conversion. In FIG. 20, tLI indicates the charge accumulation time of the photodiode 1.
In the period t14, similarly to the period t12, the drive pulse φRV is set to the low level to turn off the reset transistors TRV1 to TRV4, and the JFET 2 in the first row performs the source follower operation. This time, the output (signal output) voltage corresponding to the potential after transferring the signal charge to the gate region of JFET 2 is supplied from the source (S) of JFET 2 through vertical signal lines 22a to 22d and column buffer amplifiers 29a to 29d. Applied to the input ends of the clamp capacitors Cc1 to Cc4.
[0014]
At this time, the voltage at the output terminal of the clamp capacitors Cc1 to Cc4 is from the output (signal output) voltage by the source follower operation of the JFET 2 after the signal charge transfer in the period t14, before the charge transfer in the period t12 (after the gate region initialization). This is a voltage obtained by subtracting the output (dark output) voltage by the source follower operation of JFET2.
The output (signal output) voltage of the source follower operation of JFET2 in the period t14 includes an optical signal component and a noise component, and only the noise component is included in the output (dark output) voltage of the source follower operation of JFET2 in the period t12. It is included. Accordingly, the voltage at the output terminal of the clamp capacitors Cc1 to Cc4 obtained by subtracting both (so-called correlated double sampling processing) is an output voltage corresponding to only the optical signal component.
[0015]
Noise components included in both of them include fixed pattern noise due to variations in threshold voltage of each JFET 2, reset noise generated when the gate region of JFET 2 is initialized from the control region 4 through the control gate 5, and constant JFET 2. There are 1 / f noise generated during source follower operation by the current sources (26a to 26d) and fixed pattern noise due to variations in offset voltages of the column buffer amplifiers 29a to 29d.
[0016]
That is, the voltage at the output end of the clamp capacitors Cc1 to Cc4 in the period t14 becomes a video signal only of the optical signal component from which the noise component is removed, and the S / N ratio is improved.
In the period t15, the horizontal scanning circuit 8 sequentially outputs the drive pulses φH1 to φH4, thereby transferring the output voltage corresponding to only the optical signal component appearing at the output terminals of the clamp capacitors Cc1 to Cc4 to the horizontal signal line 27. Then, the video signal is output from the output terminal 35 through the output buffer amplifier 28. Further, the horizontal signal line 27 is reset by sequentially outputting the drive pulse φRH.
[0017]
The reading operation of the first row for the periods t11 to t15 is repeated in the same manner for the second row and the third row in the periods t21 to t25 and the periods t31 to t35, respectively.
Next, a pixel structure of a conventional solid-state image sensor will be described with reference to the drawings. 21 is a pixel plan view of a conventional solid-state imaging device, FIG. 22 is a sectional view taken along line Xa-Xb in FIG. 21, FIG. 23 is a sectional view taken along line Ya-Yb in FIG. FIG. 22 is a sectional view taken along line Yc-Yd in FIG. 21.
[0018]
A pixel of a conventional solid-state imaging device includes a photodiode 1, JFET 2, transfer gate 3, control region 4, and control gate 5.
As shown in FIGS. 23 and 24, the photodiode 1 includes an N-type well region 11, a P-type charge accumulation region 12, and a high-concentration N-type semiconductor region 13 formed on a P-type semiconductor substrate 10. . As a result, a buried photodiode is formed with an NPNP vertical overflow drain structure. That is, a structure in which the embedded photodiode (N, P, N) and the vertical overflow drain structure (P, N, P) are combined is formed. With this structure, dark current, afterimage, reset noise, blooming, and smear are suppressed.
[0019]
The JFET 2 is an N-channel type, and includes an N-type source region 14, a P-type gate region 15, an N-type drain region 16, and an N-type channel region 17, as shown in FIGS. The N-type source region 14 is connected to the vertical signal line 22 (corresponding to the vertical signal lines 22a to 22d in FIG. 19) for each column (see FIGS. 21 and 22). The N-type drain region 16 is continuously formed in a mesh shape so as to surround the periphery of the pixel, and the drain power supply VD is shared by all the pixels around the pixel region (a region where a plurality of pixels are arranged in a matrix). They are connected (see FIG. 19).
[0020]
As shown in FIG. 23, the transfer gate 3 is formed on the boundary region between the photodiode 1 and the JFET 2 via an insulating film 33. A P-channel MOS transistor is configured in which the P-type charge storage region 12 of the photodiode 1 and the P-type gate region 15 of the JFET 2 are used as source or drain regions and the transfer gate 3 is used as a gate electrode. As shown in FIG. 21, the transfer gate 3 is connected to a transfer gate line 20 (corresponding to the transfer gate lines 20a to 20c in FIG. 19).
[0021]
As shown in FIGS. 21 and 22, the P-type control region 4 is formed in the N-type well region 11 and connected to the control region wiring 24 (corresponding to the control region wirings 24a to 24c in FIG. 19). . The control region wiring 24 also serves as a light shielding film that shields a region other than the photodiode 1.
As shown in FIG. 22, the control gate 5 is formed on the boundary region between the JFET 2 and the P-type control region 4 via an insulating film 33. A P-channel MOS transistor is configured in which the P-type gate region 15 and the P-type control region 4 of the JFET 2 are used as source or drain regions, and the control gate 5 is used as a gate electrode. As shown in FIG. 21, the control gate 5 is connected to a control gate line 21 (corresponding to the control gate lines 21a to 21c in FIG. 19).
[0022]
As described above, the conventional solid-state imaging device shown in FIGS. 19 to 24 in which the pixels including the photodiode 1, JFET 2, transfer gate 3, control region 4, and control gate 5 are arranged in a matrix form is a vertical type. Since the buried photodiode 1 is employed in the overflow drain structure, dark current, afterimage, reset noise, blooming and smear are suppressed, and the narrow band of the JFET 2 using the vertical load capacitors Cv1 to Cv4 as loads. Noise during the amplification operation is suppressed by the source follower operation. Further, the output voltage of each source follower operation before and after the signal charge transfer is subtracted through the clamp capacitors Cc1 to Cc4 (correlated double sampling process), so that the fixed voltage due to variations in the threshold voltage of JFET2 is fixed. Pattern noise, reset noise generated when the gate region of JFET 2 is initialized, 1 / f noise during source follower operation, and fixed pattern noise due to variations in offset voltages of the column buffer amplifiers 29a to 29d are suppressed. Therefore, a video signal with high sensitivity and low noise (high S / N ratio) can be obtained.
[0023]
[Problems to be solved by the invention]
However, although the conventional solid-state imaging device has the above-described excellent operational effects, there is a problem that the manufacturing yield is low.
Further, in the case of forming an optical black (optical black portion: a plurality of pixel portions including light-shielded photodiodes 1), the conventional solid-state imaging device has to additionally form a light-shielding film, and the number of manufacturing steps is increased. It has increased. For this reason, there also existed a problem of the raise of the manufacturing cost accompanying the increase in the number of manufacturing processes, and the further fall of a yield.
[0024]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device having a high manufacturing yield.
Furthermore, another object of the present invention is to provide a solid-state imaging device capable of forming an optical black (optical black portion) without increasing the number of manufacturing steps.
[0025]
[Means for Solving the Problems]
The present inventor has found that the cause of reducing the manufacturing yield is a short circuit between wirings (control region wirings) for supplying a voltage to the control region. As shown in FIGS. 21 and 22, the control region 4 of each pixel is connected in common in the row direction by a control region wiring 24 (control region wirings 24 a to 24 c in FIG. 19) and connected to the vertical scanning circuit 7. Yes. Then, it is driven for each row by pulses φRD1 to φRD3 sent from the vertical scanning circuit 7 (see FIG. 19). The control region wiring 24 also serves as a light shielding film that shields a region other than the photodiode 1 and is formed in parallel to each other in the row direction at a relatively narrow interval compared to other wiring intervals.
[0026]
    For this reason, when particles having a size equal to or larger than the wiring interval adhere in the formation process of the control region wiring 24 (wiring metal film deposition process and photolithography etching process), the two adjacent via the particles. The wiring of the book was short-circuited and the manufacturing yield was reduced. The solid-state imaging device according to claim 1, wherein an amplification unit that outputs a signal according to incident light, a control region that controls the amplification unit, and a control that controls an electrical connection state between the amplification unit and the control region. A solid-state imaging device in which a number of pixels each having a gate are arranged,A MOS type transistor having the control gate as a gate electrode and the control region as one of a source and a drain is configured, the amplifying unit is a field effect transistor, and the gate is the source of the MOS transistor. Or the other of the drain and the source and drain of the MOS transistor have a conductivity type opposite to the source and drain of the field effect transistor,Each control region is commonly connected to a power source, the control gate is driven by a pulse voltage for each row, and in the row in which the control gate is turned on by the pulse voltage, the control regionField effect transistorA constant voltage is supplied to theField effect transistorIn a row in which the control gate is cut off by the pulse voltage,Field effect transistorAnd the control region is electrically disconnected, the control gate and theField effect transistorDue to capacitive coupling ofField effect transistorIs in an operating state.
[0027]
  In the first aspect of the present invention, a field effect transistor is arranged in the amplifying unit.With this configuration, since the control regions of the pixels are connected in common, the problem that the wirings connecting the control regions are short-circuited with each other is solved, and the manufacturing yield is improved accordingly. Further, the wiring connecting the control regions can be used as a light shielding film for the entire pixel, and an optical black (optical black portion) can be formed without increasing the number of manufacturing steps.
[0028]
  Furthermore, the configuration of claim 1 makes it possible to select a row using capacitive coupling, thereby reducing drive pulses (input pulses to the image sensor) and simplifying the vertical scanning circuit of the image sensor accordingly. It becomes possible.
  The solid-state imaging device according to claim 2,Solid-state imaging in which a large number of pixels each having an amplifying unit that outputs a signal according to incident light, a control region that controls the amplifying unit, and a control gate that controls an electrical connection state between the amplifying unit and the control region are arranged A MOS type transistor having the control gate as a gate electrode and the control region as one of a source and a drain, the amplifying unit being a junction field effect transistor, the gate being the MOS Connected to the other of the source or drain of the type transistor, the gate of the junction field effect transistor has the same conductivity type as the source and drain of the MOS type transistor, and each control region is commonly connected to a power source, The control gate is driven by a pulse voltage for each row, and the control gate is turned on by the pulse voltage. In the row in which a constant voltage is supplied from the control region to the junction field effect transistor, the junction field effect transistor becomes inactive, and the control gate is cut off by the pulse voltage, the junction type The field effect transistor and the control region are electrically cut off, and the junction field effect transistor is activated by capacitive coupling between the control gate and the junction field effect transistor.It is characterized by that.
  According to the second aspect of the present invention, a junction field effect transistor is disposed in the amplifying unit. With this configuration, the control region of each pixel is connected in common, so that the wirings connecting the control region are short-circuited to each other. Is eliminated and the production yield is improved accordingly. Further, the wiring connecting the control regions can be used as a light shielding film for the entire pixel, and an optical black (optical black portion) can be formed without increasing the number of manufacturing steps.
  Furthermore, the configuration according to claim 2 makes it possible to select a row using capacitive coupling, thereby reducing drive pulses (input pulses to the image sensor) and simplifying the vertical scanning circuit of the image sensor accordingly. It becomes possible.
[0029]
  A solid-state imaging device according to a third aspect is the second aspect.2 is characterized in that the other of the gate of the junction field effect transistor and the source or drain of the MOS transistor is the same semiconductor region.
[0030]
  With this configuration, the wiring connected to the gate of the junction field effect transistor and the diffusion region are reduced. For this reason, the parasitic capacitance resulting from these wirings and diffusion regions is reduced, and the output signal is increased. Further, since the size can be further reduced, the aperture ratio is improved.
  Claim 4The solid-state imaging device described inSolid-state imaging in which a large number of pixels each having an amplifying unit that outputs a signal according to incident light, a control region that controls the amplifying unit, and a control gate that controls an electrical connection state between the amplifying unit and the control region are arranged A MOS transistor having a control gate as a gate electrode and a control region as one of a source and a drain; the amplifying unit is a bipolar transistor; and a base of the MOS transistor Connected to the other of the source and drain, the base of the bipolar transistor has the same conductivity type as the source and drain of the MOS transistor, the control regions are connected to a power supply in common, and the control gate is connected to each row In a row that is driven by a pulse voltage and the control gate is rendered conductive by the pulse voltage, In a row in which a constant voltage is supplied from the control region to the bipolar transistor so that the bipolar transistor is in an inoperative state and the control gate is cut off by the pulse voltage, the bipolar transistor and the control region are electrically connected to each other. In addition to being shut off, the bipolar transistor is activated by capacitive coupling between the control gate and the bipolar transistor.It is characterized by that.
[0031]
  This claimIn the amplification sectionA bipolar transistor is placed.However, since the control regions of the respective pixels are connected in common with this configuration, the problem that the wirings connecting the control regions are short-circuited with each other is solved, and the manufacturing yield is improved accordingly. Further, the wiring connecting the control regions can be used as a light shielding film for the entire pixel, and an optical black (optical black portion) can be formed without increasing the number of manufacturing steps.
  Furthermore, according to the configuration of the fourth aspect, it is possible to select a row by using capacitive coupling, and it is possible to reduce drive pulses (input pulses to the image sensor) and to simplify the vertical scanning circuit of the image sensor. It becomes possible.
  Claim 5The solid-state imaging device described inClaim 42 is characterized in that the other of the base of the bipolar transistor and the source or drain of the MOS transistor is the same semiconductor region. With this configuration, the wiring and diffusion region connected to the base of the bipolar transistor are reduced. For this reason, the parasitic capacitance resulting from these wirings and diffusion regions is reduced, and the output signal is increased. Further, since the size can be further reduced, the aperture ratio is improved.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each figure, the same code | symbol shows the same or an equivalent part, and the overlapping description is abbreviate | omitted.
Embodiment 1
FIG. 1 is a circuit diagram showing a configuration of a solid-state imaging device according to Embodiment 1 of the present invention. The solid-state imaging device of Embodiment 1 includes a plurality of pixels Px1-1 to Px3-4 arranged in a two-dimensional matrix, a vertical scanning circuit 7 that drives each pixel Px1-1 to Px3-4 for each row, Each pixel Px1-1 to Px3-4 includes vertical signal lines 22a to 22d, a horizontal signal line 27, and a horizontal scanning circuit 8 connected to each column.
[0033]
Each pixel, for example, Px1-1 includes a photodiode 1 that generates and accumulates charges according to incident light, and an N-channel junction type that outputs a signal according to the charges from the source (S) by a source follower operation. A field effect transistor (hereinafter referred to as JFET) 2, a transfer gate 3 for transferring the charge from the photodiode 1 to the JFET 2, a control region 4 for controlling the JFET 2, and a control gate 5.
[0034]
The source (S) of each JFET 2 is connected to the vertical signal lines 22a to 22d for each column, and the drain (D) of each JFET 2 is connected to the drain power supply VD in common for all pixels.
The transfer gate 3 is connected to the transfer gate lines 20a to 20c for each row and is driven for each row by pulses φTG1 to φTG3 sent from the vertical scanning circuit 7.
[0035]
The control region 4 is connected to each row by control region wirings 24a to 24c, and is further connected in common by connecting these wirings, and is connected to a power source (voltage VG).
The control gate 5 is connected to the control gate lines 21 a to 21 c for each row, and is driven for each row by pulses φRG 1 to φRG 3 sent from the vertical scanning circuit 7.
[0036]
For the vertical signal lines 22a to 22d, constant current sources 26a to 26d serving as loads of the JFET 2, reset transistors TRV1 to TRV4 for fixing the vertical signal line to a constant voltage (VRV), and an operation band of the JFET 2 are limited. Are connected to vertical load capacitors Cv1 to Cv4, column buffer amplifiers 29a to 29d, clamp capacitors Cc1 to Cc4, and clamp transistors TC1 to TC4. The vertical signal lines 22a to 22d are connected to the horizontal signal line 27 via column selection transistors TH1 to TH4.
[0037]
The horizontal signal line 27 is connected to a reset transistor TRH that resets the output buffer amplifier 28 and the horizontal signal line 27 to a constant voltage (here, GND).
FIG. 2 is a pulse timing chart for explaining the operation of the solid-state imaging device according to the first embodiment. The operation of the solid-state imaging device according to the first embodiment shown in FIG. 1 will be described with reference to FIG. As will be described later, the transfer gate 3 and the control gate 5 constituting each pixel are P-channel type (see FIGS. 5 and 6). Therefore, φTG1 to φTG3 and φRG1 to φRG3 are in a conductive (on) state when the corresponding transfer gate 3 or control gate 5 is at a low level, and are cut off (off) when these pulses are at a high level. It becomes. The other gates are N-channel type, and are turned on (on) when the corresponding pulse is at a high level, and turned off (off) when the corresponding pulse is at a low level.
[0038]
In FIG. 2, the period from t11 to t15 corresponds to the reading operation of the pixels in the first row, and the periods from t21 to t25 and t31 to t35 are respectively shown in the second row and the third row. It corresponds.
First, in the period t11, φRG1 to φRG3 are at a low level, and the control gates 5 of all the pixels are in a conductive (ON) state. Therefore, the gate regions of the JFETs 2 of all the pixels are initialized by applying the voltage VG from the control region 4 through the control gate 5.
[0039]
At the end of the period t11, the drive pulse φRG1 is set to the high level (the drive pulses φRG2 and φRG3 remain at the low level), and the control gate 5 in the first row is turned off (off). When this operation is performed, the potential of the gate region of the JFET 2 in the first row rises to VG + ΔVG due to capacitive coupling between the control gate 5 and the gate region of the JFET 2 (the amount of change is ΔVG). The JFET 2 in the first row becomes an operation (selection) state when the gate region is in a floating state and the gate voltage (exactly, the gate-source voltage) is increased from other rows.
[0040]
On the other hand, the control gates 5 in the second and subsequent rows are in a conductive (ON) state, and the voltage region VG is still applied to the gate region of the JFET 2. Therefore, the gate voltage (more precisely, the gate-source voltage) of the JFET 2 in the second and subsequent rows is lower than the gate voltage in the first row. For this reason, the JFETs 2 on and after the second row remain in a non-operating (non-selected) state.
[0041]
Here, the row selection operation in the period t11 will be described in more detail.
3A and 3B are explanatory diagrams of the row selection operation of the solid-state imaging device according to the first embodiment, where FIG. 3A is an equivalent circuit diagram of the pixel, and FIG. 3B is a graph illustrating changes in the voltage applied to the control gate 5 and the gate voltage of the JFET 2. FIG. As shown in the equivalent circuit diagram of FIG. 3A, the pixel of the solid-state imaging device of Embodiment 1 includes a photodiode 1, a JFET 2, a transfer gate 3, a control region 4, and a control gate 5. A constant voltage (VG) is applied. The gate region (G) of the JFET 2 and four adjacent regions (see FIGS. 4 to 7 described later), that is, the source region (S), the drain region (D), the transfer gate 3, and the control gate 5 There are capacities CGS, CGD, CG (TG), and CG (RG), respectively.
[0042]
Further, as shown in FIG. 3B, the P-channel control gate 5 is changed from the conductive (ON) state to the cutoff (OFF) state, that is, the drive pulse φRG is changed from the low level (VRGL) to the high level (VRGH). In the process of changing to (), the gate region (G) of JFET 2 is in an electrically floating state, and at the same time, the gate voltage rises by ΔVG due to capacitive coupling and becomes VG + ΔVG. Although this voltage change amount ΔVG is shown in FIG. 3 as equation (1), the amplitude of the drive pulse φRG (specifically, the value of VRGH−VT in FIG. 3B) and the capacitance ratio CG (RG) / Determined by the product of CG (total). Note that VT is the threshold voltage of the control gate 5, and CG (total) is the total capacity (formula (2)) of the four capacity components.
[0043]
Thus, the value of ΔVG can be appropriately selected according to the equation (1) in FIG. In this way, when the P-channel control gate 5 changes from the conductive state to the cut-off state, the N-channel JFET 2 changes from the non-operating state to the operating state.
On the other hand, if the P-channel control gate 5 continues to be in a conductive (on) state, that is, if the drive pulse φRG remains at the low level (VRGL), the voltage of the gate region (G) of JFET 2 is from VG. It does not change. Therefore, JFET2 remains in a non-selected state.
[0044]
Therefore, the amplitude of the φRG pulse and the capacitance ratio CG (RG) / CG (total) (which changes depending on the pixel structure and operating point) are appropriately selected, and the change amount ΔVG of the gate voltage of JFET 2 due to capacitive coupling is set to an appropriate value. A row selection operation can be performed by setting.
In the period t11 of the timing chart of FIG. 2, the row selection operation of JFET 2 is performed using this. That is, the gate region of the JFET 2 in the first row is in a floating state and the gate voltage is VG + ΔVG, and the gate voltage of the JFET 2 in the second row and thereafter is fixed to the power supply voltage VG. Since the source regions (S) of the respective JFETs 2 arranged in the column direction are commonly connected by the vertical signal lines 22a to 22b, the JFET 2 in the first row having a large gate-source voltage is in an operating (selected) state. Thus, the JFETs 2 in the second and subsequent rows having a small gate-source voltage are in a non-operating (non-selected) state. In this embodiment, VRGH-VT is 7V and ΔVG is 0.7V.
[0045]
Note that in the period t11, the drive pulse φRV is set to the high level, and the reset transistors TRV1 to TRV4 are turned on. Thereby, the voltages of the vertical signal lines 22a to 22d are fixed to a constant value (VRV). This is to ensure the above-described row selection operation, that is, to assist the row selection operation. However, this is not always necessary if ΔVG is large and the JFET row selection operation is easy. The case where ΔVG is large is when VRGH−VT is large or when CG (RG) / CG (total) is large, as can be understood from the equation (1).
[0046]
Returning to FIG. In the period t12, the drive pulse φRV is set to the low level, the reset transistors TRV1 to TRV4 are cut off (off), and the JFET 2 in the first row performs the source follower operation. Accordingly, the output (dark output) voltage corresponding to the potential immediately after the initialization of the gate region of JFET 2 is clamped capacitor Cc 1 from the source (S) of JFET 2 through vertical signal lines 22 a to 22 d and column buffer amplifiers 29 a to 29 d. ˜Cc4 is applied to one end (vertical signal lines 22a to 22d side, hereinafter referred to as an input end). Further, the drive pulse φC is at a high level, and the clamp transistors TC1 to TC4 are in a conductive (ON) state, and the other ends of the clamp capacitors Cc1 to Cc4 (on the horizontal signal line 27 side, hereinafter referred to as output ends) are grounded. Potential.
[0047]
At the end of the period t12, when the drive pulse φC is set to the low level and the clamp transistors TC1 to TC4 are cut off (off), the output (dark output) voltage is held in the clamp capacitors Cc1 to Cc4, and the clamp capacitor Cc1 The output terminal of .about.Cc4 is in a floating state. That is, the dark output voltage is clamped.
[0048]
In the period t13, the driving pulse φTG1 is set to the low level (the driving pulses φTG2 and φTG3 remain at the high level), and the transfer gates 3 of the pixels in the first row are turned on, and the photodiodes in the first row are set. The signal charge generated and stored in 1 is transferred to the gate region of JFET 2. Note that the potential of the gate region of JFET 2 after the transfer of the signal charge changes (in this case, increases) by the amount of the signal charge / gate capacitance.
[0049]
At the end of the period t13, when the drive pulse φTG1 is set to the high level to turn off the transfer gate 3, the photodiode 1 in the first row enters the next signal charge accumulation operation by photoelectric conversion. In FIG. 2, tLI indicates the charge accumulation time of the photodiode 1.
Note that in the period t13, similarly to the period t11, the drive pulse φRV is set to the high level so that the reset transistors TRV1 to TRV4 are turned on. This is to perform the above transfer operation with certainty, that is, to assist the transfer operation. This facilitates complete transfer of the signal charge from the photodiode 1 to the JFET 2. However, these transistors are unnecessary when complete transfer is performed without using the reset transistors TRV1 to TRV4 due to conditions such as the area of the photodiode 1 and the impurity concentration. Accordingly, when both φRV and the associated operations of the reset transistors TRV1 to TRV4 are not required in the period t11 and the period t13, the solid-state imaging device of the first embodiment is shown in the circuit diagram (FIG. 1) and the timing chart (FIG. 2). The drive pulse φRV, the reset transistors TRV1 to TRV4, and the power supply (VRV) may be deleted.
[0050]
In the period t14, similarly to the period t12, the drive pulse φRV is set to the low level to turn off the reset transistors TRV1 to TRV4, and the JFET 2 in the first row performs the source follower operation. This time, the output (signal output) voltage corresponding to the potential after transferring the signal charge to the gate region of JFET 2 is supplied from the source (S) of JFET 2 through vertical signal lines 22a to 22d and column buffer amplifiers 29a to 29d. Applied to the input ends of the clamp capacitors Cc1 to Cc4.
[0051]
At this time, the voltage at the output terminal of the clamp capacitors Cc1 to Cc4 is from the output (signal output) voltage by the source follower operation of the JFET 2 after the signal charge transfer in the period t14, before the charge transfer in the period t12 (after the gate region initialization). This is a voltage obtained by subtracting the output (dark output) voltage by the source follower operation of JFET2.
The output (signal output) voltage of the source follower operation of JFET2 in the period t14 includes an optical signal component and a noise component, and only the noise component is included in the output (dark output) voltage of the source follower operation of JFET2 in the period t12. It is included. Accordingly, the voltage at the output terminal of the clamp capacitors Cc1 to Cc4 obtained by subtracting both (so-called correlated double sampling processing) is an output voltage corresponding to only the optical signal component.
[0052]
Noise components included in both of them include fixed pattern noise due to variations in threshold voltage of each JFET 2, reset noise generated when the gate region of JFET 2 is initialized from the control region 4 through the control gate 5, and constant JFET 2. There are 1 / f noise generated during source follower operation by the current sources (26a to 26d) and fixed pattern noise due to variations in offset voltages of the column buffer amplifiers 29a to 29d.
[0053]
That is, the voltage at the output end of the clamp capacitors Cc1 to Cc4 in the period t14 becomes a video signal only of the optical signal component from which the noise component is removed, and the S / N ratio is improved.
In the period t15, the horizontal scanning circuit 8 sequentially outputs the drive pulses φH1 to φH4, thereby transferring the output voltage corresponding to only the optical signal component appearing at the output terminals of the clamp capacitors Cc1 to Cc4 to the horizontal signal line 27. Then, the video signal is output from the output terminal 35 through the output buffer amplifier 28. Further, the horizontal signal line 27 is reset by sequentially outputting the drive pulse φRH. Note that the source follower operation in the period t14 continues also in the period t15.
[0054]
In addition, the period t11 to the period t14 are performed during the horizontal blanking period.
The reading operation of the first row for the periods t11 to t15 is repeated in the same manner for the second row and the third row in the periods t21 to t25 and the periods t31 to t35, respectively.
As described above, the row selection operation of the solid-state imaging device according to the first embodiment can be summarized as follows.
1. The source of the JFET 2 of each pixel is connected to the same constant current source for each column and operates as a source follower. The source voltage of JFET 2 is the same for each column.
2. On the other hand, of each row, a row having a large gate-source voltage of JFET 2 is selected, and a signal is output from JFET 2 of the row.
3. The control gate 5 is connected to each row and operates. In the row where the control gate 5 is turned on, the gate voltage of the JFET 2 becomes VG. In the row where the control gate 5 is turned off, the gate voltage of the JFET 2 becomes VG + ΔVG due to capacitive coupling.
4). Therefore, when the JFET 2 is operated as a source follower, a signal is output from the row in which the control gate 5 is turned off. That is, it becomes possible to select a row.
[0055]
As described above, according to the present invention, not only the yield is improved, but also row selection can be made by skillfully using capacitive coupling. For this reason, drive pulses (input pulses to the image sensor) are reduced, and the vertical scanning circuit of the image sensor is simplified. In addition, the drive timing is simplified and the operation speed is improved. In addition, since the difference between the gate voltage or the base voltage between the selected pixel and the non-selected pixel can be set smaller than the conventional one, transfer characteristics (afterimage characteristics) and saturation charge amount (overflow characteristics) are improved. Further, the voltage value on the low level side of the pulse voltage (φRG) of the control gate 5 increases, and the drive voltage of the element can be decreased as a whole.
[0056]
Next, the pixel structure of the solid-state imaging device according to the first embodiment will be described. 4 is a pixel plan view of the solid-state imaging device according to the present embodiment, FIG. 5 is a cross-sectional view taken along line X1-X2, FIG. 6 is a cross-sectional view taken along line Y1-Y2, and FIG. It is sectional drawing along the Y3-Y4 line.
A pixel of the solid-state imaging device according to the first embodiment includes a photodiode 1, JFET 2, transfer gate 3, control region 4, and control gate 5.
[0057]
As shown in FIGS. 6 and 7, the photodiode 1 includes an N-type well region 11, a P-type charge storage region 12, and a high concentration N-type semiconductor region 13 formed on a P-type semiconductor substrate 10. . As a result, a buried photodiode is formed with an NPNP vertical overflow drain structure. That is, a structure in which the embedded photodiode (N, P, N) and the vertical overflow drain structure (P, N, P) are combined is formed. With this structure, dark current, afterimage, reset noise, blooming, and smear are suppressed.
[0058]
JFET 2 is an N-channel type, and is composed of an N-type source region 14, a P-type gate region 15, an N-type drain region 16, and an N-type channel region 17, as shown in FIGS. The N-type source region 14 is connected to the vertical signal line 22 (corresponding to the vertical signal lines 22a to 22d in FIG. 1) for each column (see FIGS. 4 and 5). The N-type drain region 16 is continuously formed in a mesh shape so as to surround the periphery of the pixel, and the drain power supply VD is shared by all the pixels around the pixel region (a region where a plurality of pixels are arranged in a matrix). Connected (see FIG. 1).
As shown in FIG. 6, the transfer gate 3 is formed on the boundary region between the photodiode 1 and the JFET 2 via an insulating film 33. A P-channel MOS transistor is configured in which the P-type charge storage region 12 of the photodiode 1 and the P-type gate region 15 of the JFET 2 are used as source or drain regions and the transfer gate 3 is used as a gate electrode. As shown in FIG. 4, the transfer gate 3 is connected to a transfer gate line 20 (corresponding to the transfer gate lines 20a to 20c in FIG. 1).
[0059]
4 and 5, the P-type control region 4 is formed in the N-type well region 11, and is connected to the control region wiring 24 (corresponding to the control region wirings 24a to 24c in FIG. 1). . The interval between the control region wirings 24 is the same as that of the conventional art. However, as is apparent from FIG. 1, all the control area wirings of the present invention are connected in common. For this reason, even if particles adhere between the control area wirings, since the same voltage is applied to all the control area wirings, it does not become defective. Therefore, the yield is improved.
[0060]
The control region wiring 24 also serves as a light shielding film that shields the region other than the photodiode 1.
As shown in FIG. 5, the control gate 5 is formed on the boundary region between the JFET 2 and the P-type control region 4 via an insulating film 33. Then, a P-channel MOS transistor is configured in which the control gate 5 is a gate electrode, the P-type control region 4 is one of the source and drain regions, and the P-type gate region 15 of the JFET 2 is the other of the source and drain regions. Yes. As shown in FIG. 4, the control gate 5 is connected to a control gate line 21 (corresponding to the control gate lines 21a to 21c in FIG. 1). As is apparent from FIG. 1, the control gate is connected to each row and driven for each row. Therefore, the row selection operation described above can be performed.
[0061]
The source and drain of the P-channel MOS transistor (that is, the control region 4 and the gate region 15 of JFET 2) are P-type semiconductor regions. On the other hand, the source / drain of JFET 2 has the opposite conductivity type (that is, N-type semiconductor region). The gate of JFET 2 has the same conductivity type (P-type semiconductor region) as the source / drain of the P-channel MOS transistor. Thus, if the conductivity type of each semiconductor region is selected, the gate voltage of JFET 2 increases by ΔVG by turning off the control gate. Therefore, the row selection operation described above can be performed.
[0062]
The P-type gate region 15 of JFET 2 and the other of the source or drain region of the P-channel MOS transistor are the same semiconductor region. In this way, unnecessary wiring and diffusion regions can be deleted. For this reason, not only the parasitic capacitance is reduced and the output signal is increased, but also miniaturization is possible.
Finally, the structure of optical black (optical black portion) will be described with reference to FIG.
[0063]
FIG. 8 is a partial plan view showing a boundary region between pixels constituting the imaging unit of the solid-state imaging device according to Embodiment 1 and pixels constituting the optical black (optical black part). As shown at the right end of FIG. 8, the optical black pixels (the pixels in the OB portion) are shielded from light by the control region wiring 24. That is, in the solid-state imaging device of the first embodiment, since the control region 4 of each pixel is connected in common, the entire pixel including the photodiode 1 can be formed by the control region wiring 24 without adding a new light shielding film. Can be shielded from light.
[0064]
As described above, since the solid-state imaging device according to the first embodiment employs the buried photodiode 1 with a vertical overflow drain structure, dark current, afterimage, reset noise, blooming, and smear are suppressed. In addition, the noise during the amplification operation is suppressed by the narrow band source follower operation of JFET 2 using the vertical load capacitors Cv1 to Cv4 as loads. Further, the output voltage of each source follower operation before and after the signal charge transfer is subtracted through the clamp capacitors Cc1 to Cc4 (correlated double sampling process), so that the fixed voltage due to variations in the threshold voltage of JFET2 is fixed. Pattern noise, reset noise generated when the gate region of JFET 2 is initialized, 1 / f noise during source follower operation, and fixed pattern noise due to variations in offset voltages of the column buffer amplifiers 29a to 29d are suppressed. Therefore, a high-sensitivity and low-noise (high S / N ratio) video signal can be obtained as in the conventional solid-state imaging device (FIGS. 19 to 24).
[0065]
In the solid-state imaging device according to the first embodiment, since the control regions 4 of the pixels are connected in common, problems such as overcurrent due to short-circuiting of the control region wirings 24 are solved, and the manufacturing yield is improved.
In addition, the solid-state imaging device of the first embodiment can shield the entire pixel including the photodiode 1 by the control region wiring 24, and can form an optical black (optical black portion) without increasing the number of manufacturing steps. .
[0066]
Here, a constant current source is used as the load of the source follower circuit for each of the vertical signal lines 22a to 22b. However, the present invention is not limited to this. For example, a resistor may be used as a load of the source follower circuit.
In addition, here, the configuration in which the voltage signal is extracted by the source follower operation has been described, but the present invention is not limited to this. A configuration may be adopted in which the source current or drain current of JFET 2 is taken out as a signal. More specifically, a configuration in which a vertical signal line is connected to a current-voltage conversion circuit or the like (via a column selection transistor) to extract the source current of JFET 2, or the source of JFET 2 is connected to ground or a current source and the drain of JFET 2 is connected. There is a configuration in which the drain current is taken out by connecting to the vertical signal line.
[0067]
Furthermore, the conductivity type of each semiconductor region and the polarity of the drive pulse may be reversed.
[Embodiment 2]
FIG. 9 is a circuit diagram showing a configuration of a solid-state imaging device according to Embodiment 2 of the present invention.
The difference between the solid-state imaging device of the second embodiment and the solid-state imaging device of the first embodiment is in the pixel structure, and the control region 4 is connected in common or the row selection using capacitive coupling is performed. This is the same as the first embodiment. First, the pixel structure of the solid-state imaging device according to the second embodiment will be described with reference to the drawings.
[0068]
10 is a pixel plan view of the solid-state imaging device according to the present embodiment. FIG. 11 is a cross-sectional view taken along line X3-X4, FIG. 12 is a cross-sectional view taken along line Y5-Y6, and FIG. It is sectional drawing along the Y7-Y8 line.
Each pixel includes a photodiode 1, JFET 2, transfer gate 3, control region 4, two control gates 5 per pixel, and two overflow control regions 9 per pixel.
[0069]
The photodiode 1, JFET 2, control region 4, and overflow control region 9 are formed in the N-type semiconductor layer 101 on the high-concentration N-type semiconductor substrate 100. The transfer gate 3 and the control gate 5 are formed on the N-type semiconductor layer 101 with an insulating film 33 interposed therebetween.
As shown in FIGS. 12 and 13, the photodiode 1 includes an N-type semiconductor layer 101, a P-type charge accumulation region 12, and a high-concentration N-type semiconductor region 13 formed on a high-concentration N-type semiconductor substrate 100. Composed. Therefore, an NPN embedded photodiode is formed in each pixel of this embodiment.
[0070]
JFET 2 is an N-channel type as shown in FIGS. 11 and 12, and N-type source region 14, P-type gate region 15, N-type drain region 16, and N-type channel region 17 are on high concentration N-type semiconductor substrate 100. Are formed in the N-type semiconductor layer 101. Accordingly, it is possible to provide a contact around the pixel region (a region where a plurality of pixels are arranged in a matrix) and supply the drain voltage VD (see FIG. 9) to the drain region 16 of the JFET 2 via the semiconductor substrate 100. It is.
[0071]
As shown in FIGS. 10 and 11, the control gate 5 is formed at a rate of two per pixel. Therefore, a P-channel MOS transistor is formed in which the control gate 5 is a gate electrode, the P-type control region 4 is one of the source and drain regions, and the P-type gate region 15 of the JFET 2 is the other of the source and drain regions. . Each control gate 5 is connected in series in the row direction by a control gate line 21 (corresponding to the control gate lines 21a to 21c in FIG. 9), and is driven for each row.
[0072]
Further, since the control gate 5 is formed on both sides of the P-type gate region 15 of the JFET 2, the capacitance CG (RG) (see FIG. 3) between the P-type gate region 15 and the control gate 5 increases. On the other hand, with the addition of the control gate 5, the shape of the N-type drain region 16 of the JFET 2 changes, the contact area between the P-type gate region 15 and the N-type drain region 16 decreases, and the capacitance CGD (see FIG. 3) decreases. That is, the capacitance ratio CG (RG) / CG (total) increases in the JFET 2 of the solid-state imaging device of the second embodiment.
[0073]
When this capacity ratio increases, ΔVG increases from equation (1) in FIG. For this reason, it becomes easy to drive the selected row and the non-selected row, and it is possible to reliably select a desired row. Further, if ΔVG is made constant, the value of VRGH−VT can be reduced as the capacitance ratio increases. For this reason, if VT is set to a constant value, the value of VRGH can be set low, so that power consumption can be reduced.
[0074]
In the present embodiment, VRGH-VT can be set to 5V, and ΔVG can be set to 1V.
As shown in FIGS. 10 and 13, the overflow control region 9 is formed at a ratio of two per pixel in the boundary region between the photodiode 1 and the control region 4, and charges generated excessively by the photodiode 1 are controlled in the control region. The overflow operation discharged to 4 is controlled. That is, the NPN type buried photodiode 1, the overflow control region 9, and the control region 4 form a buried type photodiode with a lateral overflow drain structure. Therefore, the control region 4 also has a function as an overflow drain.
[0075]
The solid-state imaging device of the present embodiment has the above pixels arranged in a matrix. The gate region of the JFET 2 and the control region 4 of the pixels arranged in the row direction are connected in series via two control gates 5 per pixel. Accordingly, as can be seen from FIG. 9, in a certain pixel, the release mode failure in which the connection between the control region 4 and the control region wirings 24a to 24c (corresponding to the control region wiring 24 in FIGS. 10 and 11) is incomplete. Even if this occurs, the JFET 2 of the pixel can be controlled from the control region 4 of the other pixel.
[0076]
Other configurations are the same as those of the solid-state imaging device according to the first embodiment shown in FIGS.
Therefore, the solid-state imaging device of Embodiment 2 can improve the manufacturing yield similarly to the solid-state imaging device of Embodiment 1, and can form optical black without increasing the number of manufacturing steps.
In the solid-state imaging device according to the second embodiment, since the JFET 2 can be controlled even when a failure in the release mode in which the connection to the control region 4 is incomplete occurs, the manufacturing yield is further improved.
[0077]
In addition, since the control gates 5 are formed on both sides of the gate region 15 of the JFET 2, it becomes easier to select a desired row as the capacitance ratio CG (RG) / CG (total) increases. .
Further, since the drain voltage VD can be supplied to the N-type drain region 16 of the JFET 2 via the high-concentration (low-resistance) N-type semiconductor substrate 100, the fluctuation of the drain voltage for each pixel is reduced. , Fixed pattern noise is reduced.
[0078]
Further, since the P-type charge accumulation region 12 of the photodiode 1 and the N-type semiconductor substrate 100 of the opposite conductivity type are used, signal charges (holes in this case) generated in the deep part of the photodiode 1 are also reflected in the photodiode 1. Therefore, the sensitivity is improved.
[Embodiment 3]
FIG. 14 is a circuit diagram showing a configuration of a solid-state imaging device according to Embodiment 3 of the present invention.
The solid-state imaging device according to the third embodiment includes a bipolar transistor 50 in the amplification unit of each pixel. Similarly to the solid-state imaging devices of the first and second embodiments, the control region 4 is connected to each row and driven by a pulse voltage for each row, and all the control gates 5 are connected in common.
[0079]
15 is a pixel plan view of the solid-state imaging device according to the present embodiment. FIG. 16 is a cross-sectional view taken along line X5-X6, FIG. 17 is a cross-sectional view taken along line Y9-Y10, and FIG. It is sectional drawing along the Y11-Y12 line. The bipolar transistor 50 is an NPN type, and includes an N-type emitter region 52, a P-type base region 53, a high-concentration N-type semiconductor substrate 100, an N-type semiconductor layer 101, and an N-type semiconductor region 54 as collector regions. Yes.
[0080]
In the operation explanatory diagram shown in FIG. 3 (row selection operation in the first embodiment), the JFET 2 is used as the bipolar transistor 50, the gate capacitors CGS, CGD, CG (TG), and CG (RG) as the base capacitors CBE, CBC, CB ( By replacing the gate voltage VG with the base voltage VB and the drain voltage VD with the collector voltage VC in TG) and CB (RG), the row selection operation of the solid-state imaging device of this embodiment can be similarly described.
[0081]
As shown in FIGS. 15 and 16, the control gate 5 is formed at a rate of two per pixel. Therefore, a P-channel MOS transistor having the control gate 5 as the gate electrode, the P-type control region 4 as one of the source and drain regions, and the P-type base region 53 of the bipolar transistor 50 as the other of the source and drain regions is constituted. Is done. Each control gate 5 is connected in series in the row direction by a control gate line 21 (corresponding to the control gate lines 21a to 21c in FIG. 14), and is driven for each row.
[0082]
The source / drain of the P-channel MOS transistor (that is, the control region 4 and the base region 53 of the bipolar transistor 50) is a P-type semiconductor region. On the other hand, the emitter region 52 and the collector region 54 of the bipolar transistor 50 are of the opposite conductivity type (N-type semiconductor region). The base region 53 of the bipolar transistor 50 has the same conductivity type (P-type semiconductor region) as the source / drain of the P-channel MOS transistor. Thus, if the conductivity type of each semiconductor region is selected, the base voltage of the bipolar transistor 50 increases by ΔVB by turning off the control gate. Therefore, the row selection operation described above can be performed.
[0083]
The P-type base region 53 of the bipolar transistor 50 and the other of the source or drain region of the P-channel MOS transistor are the same semiconductor region. In this way, unnecessary wiring and diffusion regions can be deleted. For this reason, not only the parasitic capacitance is reduced and the output signal is increased, but also miniaturization is possible.
[0084]
Other configurations are the same as those of the solid-state imaging device of the second embodiment. Therefore, the solid-state image sensor of Embodiment 3 has the same characteristics as the solid-state image sensor of Embodiment 2.
Further, since the solid-state imaging device of the third embodiment employs the bipolar transistor 50 in the amplifying unit, the structure is simplified and the degree of integration is improved.
[0085]
【The invention's effect】
As described above, in the solid-state imaging device according to the present invention, since the control regions of each pixel are connected in common, problems such as overcurrent due to short-circuiting of wirings connecting the control regions are solved, and the manufacturing yield is increased. Has the effect of improving.
Further, in the solid-state imaging device according to the present invention, since the entire pixel can be shielded by the wiring connecting the control regions, there is an effect that the optical black can be formed without increasing the number of manufacturing steps.
[0086]
In addition, the solid-state imaging device according to the present invention has an effect that fixed pattern noise is reduced because a drain voltage can be supplied via a semiconductor substrate having a high concentration (low resistance).
In addition, the solid-state imaging device according to the present invention employs a semiconductor substrate having a conductivity type opposite to that of the photodiode, and thus has an effect of improving sensitivity.
[0087]
Further, in the present invention, it becomes possible to select a row by using capacitive coupling, and the drive pulse (input pulse to the image sensor) is reduced, and the vertical scanning circuit of the solid-state image sensor is simplified accordingly. There is also.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration of a solid-state imaging element according to Embodiment 1 of the present invention.
FIG. 2 is a pulse timing chart for explaining the operation of the solid-state imaging device according to the first embodiment.
3A and 3B are explanatory diagrams of a row selection operation of the solid-state imaging device according to the first embodiment, in which FIG. 3A is an equivalent circuit diagram of a pixel, and FIG. FIG.
FIG. 4 is a plan view illustrating a schematic configuration of a pixel of the solid-state imaging element according to the first embodiment of the present invention.
5 is a cross-sectional view taken along line X1-X2 of FIG.
6 is a cross-sectional view taken along line Y1-Y2 of FIG.
7 is a cross-sectional view taken along line Y3-Y4 of FIG.
FIG. 8 is a partial plan view showing a boundary region between pixels constituting an imaging unit of the solid-state imaging element according to Embodiment 1 and pixels constituting an optical black (optical black part).
FIG. 9 is a circuit diagram showing a configuration of a solid-state imaging element according to Embodiment 2 of the present invention.
10 is a pixel plan view of a solid-state imaging device according to Embodiment 2. FIG.
11 is a cross-sectional view taken along line X3-X4 of FIG.
12 is a sectional view taken along line Y5-Y6 of FIG.
13 is a cross-sectional view taken along line Y7-Y8 of FIG.
FIG. 14 is a circuit diagram showing a configuration of a solid-state imaging element according to Embodiment 3 of the present invention.
FIG. 15 is a pixel plan view of a solid-state imaging element according to a third embodiment.
16 is a cross-sectional view taken along line X5-X6 of FIG.
17 is a cross-sectional view taken along line Y9-Y10 of FIG.
18 is a cross-sectional view taken along line Y11-Y12 in FIG.
FIG. 19 is a circuit diagram showing a schematic configuration of a conventional solid-state image sensor.
20 is a pulse timing chart of the circuit diagram shown in FIG.
FIG. 21 is a plan view showing a schematic configuration of a pixel of a conventional solid-state image sensor.
22 is a cross-sectional view taken along line Xa-Xb in FIG.
23 is a cross-sectional view taken along the line Ya-Yb in FIG.
24 is a cross-sectional view taken along line Yc-Yd of FIG.
[Explanation of symbols]
1 Photodiode
2 JFET
3 Transfer gate
4 Control area
5 Control gate
7 Vertical scanning circuit
8 Horizontal scanning circuit
9 Overflow control area
10 P-type semiconductor substrate
11 N-type well region
12 P-type charge storage region
13 High-concentration N-type semiconductor region
14 N-type source region
15 P-type gate region
16 N-type drain region
17 N-type channel region
20, 20a-20c Transfer gate wiring
21, 21a to 21c Control gate wiring
22, 22a-22d Vertical signal line
24, 24a-24c Control area wiring
26a-26d constant current source
27 Horizontal signal line
28 Output buffer amplifier
29a-29d column buffer amplifier
33 Insulating film
35 Output terminal
50 Bipolar transistor
52 N-type emitter region
53 P-type base region
54 N-type semiconductor region
100 High-concentration N-type semiconductor substrate
101 N-type semiconductor layer

Claims (5)

Solid-state imaging in which a large number of pixels each having an amplifying unit that outputs a signal corresponding to incident light, a control region that controls the amplifying unit, and a control gate that controls an electrical connection state between the amplifying unit and the control region are arranged An element,
A MOS transistor having the control gate as a gate electrode and the control region as one of a source and a drain is configured;
The amplifying unit is a field effect transistor, and a gate thereof is connected to the other of the source and the drain of the MOS transistor,
The source and drain of the MOS transistor have a conductivity type opposite to the source and drain of the field effect transistor,
Each control region is commonly connected to a power source,
The control gate is driven by a pulse voltage for each row,
In a row in which the control gate is turned on by the pulse voltage, a constant voltage is supplied from the control region to the field effect transistor , and the field effect transistor becomes inoperative.
Wherein a pulse line said control gate is in the blocked state by the voltage, the with the control region and the field effect transistor are electrically disconnected, the field effect due to capacitive coupling of the field-effect transistor and the control gate A solid-state imaging device, wherein a type transistor is in an operating state. Solid-state imaging in which a large number of pixels each having an amplifying unit that outputs a signal corresponding to incident light, a control region that controls the amplifying unit, and a control gate that controls an electrical connection state between the amplifying unit and the control region are arranged An element,
A MOS transistor having the control gate as a gate electrode and the control region as one of a source and a drain is configured;
The amplifying part is a junction field effect transistor, the gate of which is connected to the other of the source and drain of the MOS transistor,
The gate of the junction field effect transistor has the same conductivity type as the source and drain of the MOS transistor,
Each control region is commonly connected to a power source,
The control gate is driven by a pulse voltage for each row,
In a row in which the control gate is made conductive by the pulse voltage, a constant voltage is supplied from the control region to the junction field effect transistor , so that the junction field effect transistor becomes non-operational.
In the row in which the control gate is cut off by the pulse voltage, the junction field effect transistor and the control region are electrically cut off, and the control gate and the junction field effect transistor are capacitively coupled. A solid-state imaging device, wherein a junction field effect transistor is in an operating state. 3. The solid-state imaging device according to claim 2 , wherein the other of the gate of the junction field effect transistor and the source or drain of the MOS transistor is the same semiconductor region. Solid-state imaging in which a large number of pixels each having an amplifying unit that outputs a signal corresponding to incident light, a control region that controls the amplifying unit, and a control gate that controls an electrical connection state between the amplifying unit and the control region are arranged An element,
A MOS transistor having the control gate as a gate electrode and the control region as one of a source and a drain is configured;
The amplifying unit is a bipolar transistor, and its base is connected to the other of the source and drain of the MOS transistor,
The base of the bipolar transistor has the same conductivity type as the source and drain of the MOS transistor,
Each control region is commonly connected to a power source,
The control gate is driven by a pulse voltage for each row,
In a row in which the control gate is made conductive by the pulse voltage, a constant voltage is supplied from the control region to the bipolar transistor , and the bipolar transistor becomes inoperative.
In the row in which the control gate is cut off by the pulse voltage, the bipolar transistor and the control region are electrically cut off, and the bipolar transistor is in an operating state by capacitive coupling of the control gate and the bipolar transistor. A solid-state imaging device. 5. The solid-state imaging device according to claim 4 , wherein the other of the base of the bipolar transistor and the source or drain of the MOS transistor is the same semiconductor region.

Images