JP4192336B2 - Pattern generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pattern generation circuit that is mounted on a test apparatus such as a semiconductor memory and generates a test pattern for addresses and data, and more particularly, a pattern generation having a scramble function for converting a test pattern generated according to programming into physical data. Regarding the circuit.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor memory such as a DRAM has memory cells for storing one bit, which is the minimum unit of data, arranged in a matrix of rows and columns, and each memory cell has a logical value of stored data. Correspondingly, a high-level or low-level potential is held. When data is stored in the semiconductor memory, it is only necessary that the external data and the potential held in the memory cell correspond to each other. The data having the logical value “1” is not necessarily stored as the high-level “H” potential. There is no necessity to store the data of the value “0” as the low level “L” potential.
[0003]
That is, for example, when storing data of logical value “1”, it is arbitrary whether to hold the data as a high level “H” potential or a low level “L” potential inside the semiconductor memory. In general, the relationship between data and potential is determined for the convenience of designing a semiconductor memory. For this reason, even if the data has the same logical value, the potential state of the memory cell may differ depending on the data storage address.
[0004]
Here, when analyzing a failure of this type of semiconductor memory, knowing what potential state the internal memory cell holds becomes a major clue in analyzing the cause of the failure. . Therefore, when evaluating a semiconductor memory, in order to convert the data generated in the pattern generation circuit into physical data so that the test pattern data described by programming and the potential held in the memory cell are apparently matched. Data scramble processing is performed.
[0005]
By performing this data scrambling process, the relationship between the external data and the internal potential is matched over the entire address space, and analysis can be easily performed. Usually, a pattern generation circuit mounted on an IC tester for testing a semiconductor memory or the like has a function of converting a test pattern described by programming into physical data that matches the physical arrangement relationship of memory cells in the semiconductor memory, That is, it has a data scramble function.
[0006]
FIG. 3 shows an example of a conventional pattern generation circuit.
In FIG. 3, 11 is a sequence control unit for controlling the order of pattern generation instructions described in a test program (not shown). The sequence control unit 11 is connected to an address pattern generation unit 12 and a data pattern generation unit 13, which will be described later, through control lines C12 and C13. The control line C12 is used to cause the address pattern generation unit 12 to perform an operation. An operation instruction is output, and an operation instruction for causing the data pattern generation unit 13 to perform an operation is output to the control line C13.
[0007]
The address pattern generation unit 12 and the data pattern generation unit 13 are input with operation commands output from the sequence control unit 11 via the control lines C12 and C13, respectively. The address pattern generation unit 12 and the data pattern generation unit 13 have a circuit that performs a dedicated four arithmetic operation for generating a test pattern, and performs an operation specified by an operation instruction input from the sequence control unit 11 to perform a test. Output the pattern.
[0008]
The data scrambler 15 is connected to the address pattern generator 12 through a signal line A12, and is connected to the data pattern generator 13 through a signal line D13. The data scrambler 15 receives the address signal calculated by the address pattern generator 12 via the signal line A12 and the data signal calculated by the data pattern generator 13 via the signal line D13. The The data scrambler 15 converts the data signal input from the data pattern generator 13 into physical data suitable for the semiconductor memory to be measured (not shown) in correspondence with the address signal input from the address pattern generator 12. Convert and output.
[0009]
The phase adjustment unit 16 is connected to the address pattern generation unit 12 through a signal line A12, and inputs an address signal calculated by the address pattern generation unit 12 through the signal line A12. The phase adjustment unit 16 outputs the address signal calculated by the address pattern generation unit 12 in accordance with the phase of the output data signal of the data scramble circuit 15.
[0010]
The operation of the pattern generation circuit according to this conventional technique will be described below.
FIG. 4 is a time chart of the pattern generation circuit. In the figure, a1, a2, ... are address signals, d1, d2, ... are data signals, and ds1, ds2, ... are physical data converted by the data scrambler 15. For example, the data for the address a1 is d1, and the converted data is ds1.
[0011]
In the above configuration, when the pattern generation circuit starts operation, the sequence control unit 11 sends an arithmetic command for generating a test pattern according to a preset test program to the address pattern generation unit 12, the data pattern generation unit 13, and the like. Respectively.
When receiving an operation instruction from the sequence control unit 11, the address pattern generation unit 12 performs an operation according to the instruction to generate an address signal as shown in FIG. 4 (the uppermost waveform). The data is output to the data scrambler 15 and the phase adjuster 16.
[0012]
On the other hand, when the data pattern generation unit 13 receives a calculation command from the sequence control unit 11, the data pattern generation unit 13 performs a calculation according to the calculation command and generates a data signal as shown in FIG. 4 (second waveform from the top). Then, this data signal is output to the data scrambler 15.
When the data scrambler 15 receives the address signal from the address pattern generator 12 and receives the data signal from the data pattern generator 13, the data scrambler 15 associates the data signal with the address signal, and displays the waveform in FIG. Convert to physical data as shown in The converted physical data becomes data supplied to the object to be measured.
[0013]
When the phase adjustment unit 16 receives the address signal from the address pattern generation unit 12, the phase of the address signal is output from the data scramble unit 15 as shown in FIG. The address signal is output after adjusting to match the phase of the signal. The address signal whose phase is adjusted becomes an address supplied to the object to be measured.
When the sequence control unit 11 sequentially outputs operation instructions at preset time intervals according to the test program, the pattern generation circuit repeats a series of operations and outputs test patterns one after another.
[0014]
According to this conventional pattern generation circuit, the data scrambler 15 receives an address signal and a data signal from the address pattern generation circuit 12 and the data pattern generation circuit 13 each time, and associates them with physical data. Therefore, it is necessary to match the phases output from the address pattern generation circuit 12 and the data pattern generation circuit 13. For this reason, physical conversion of data is possible only for addresses calculated in the same phase.
[0015]
[Problems to be solved by the invention]
Incidentally, some objects to be measured such as semiconductor memories require data whose phase is delayed with respect to an input address. In such a case, when trying to cope by programming, various operation instructions are given to the sequence control circuit 11 so that the phase of the data generated by the data pattern generation circuit 13 is delayed with respect to the address generated by the address pattern generation circuit 12. Will be generated. However, in this case, since the phase of the address signal and the data signal input from the data pattern generation circuit 13 to the data scrambler 15 do not match, there is a problem that physical data corresponding to each address cannot be generated correctly. .
[0016]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a pattern generation circuit capable of correctly converting data into physical data even when the phase of the address and data does not match. .
[0017]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configuration.
That is, the pattern generation circuit according to the present invention includes sequence control means (for example, a component corresponding to a sequence control unit 1 described later) that outputs an address pattern generation instruction and a data pattern generation instruction in accordance with a sequence described in a program; Address pattern generation means (for example, a component corresponding to an address pattern generation section 2 described later) that generates an address pattern based on an address pattern generation command output from the sequence control means and sequentially outputs addresses forming the address pattern; A data pattern generating means for generating a data pattern corresponding to the address pattern on the basis of a data pattern generating command output from the sequence controller and sequentially outputting data forming the data pattern (for example, a data pattern generating to be described later) The corresponding components of) the 3, a plurality of storage registers for storing an address sequentially output from the address pattern generation unit according to the pattern store instruction output from the sequence control unit, the sequence control from among the storage register And a selection circuit for selecting a storage register according to a pattern selection instruction output from the means, and an address storage means (for example, address storage described later) for sequentially outputting addresses stored in the storage register selected by the selection circuit Data scrambling means (for example, described later) for converting the data output from the data pattern generating means into physical data suitable for the measurement target based on the address output from the address storage means. Component corresponding to the data scramble unit 5) and the previous Phase adjusting means for adjusting the phase of the address output from the address pattern generating means with respect to the data output from the data scramble means (for example, a component corresponding to a phase adjusting unit 6 described later). A characteristic pattern generation circuit.
[0018]
According to this invention, the address pattern generated by the address pattern generation means is temporarily stored in the storage register provided in the address storage means in accordance with the pattern storage command output from the sequence control means, and the pattern selection output from the sequence control means The address stored in the storage register selected by the selection circuit according to the instruction is output. Therefore, since the output timing of the address from the address storage means can be appropriately adjusted by the pattern selection instruction, the timing of the data output from the data pattern generation means is delayed with respect to the address output from the address pattern generation means. Even so, it is possible to generate appropriate physical data corresponding to this address.
[0019]
Furthermore, in the pattern generation circuit according to the present invention, for example, the sequence control means outputs the pattern selection command so that the phase of the address output from the address storage means matches the phase of the corresponding data. And Thus, the data scramble means receives an address and data in phase with each other, and generates a physical address corresponding to this address.
[0022]
Furthermore, the pattern generation circuit according to the present invention is characterized in that, for example, the data scramble means inverts data output from the data pattern generation means in accordance with an address output from the address storage means.
According to this, when the physical data has an address dependency, the physical data can be obtained by inverting the data generated by the data pattern generating means according to the address.
[0023]
Furthermore, in the pattern generation circuit according to the present invention, for example, the phase adjustment unit delays the phase of the address output from the address pattern generation unit in accordance with the pattern storage command and the pattern selection command. .
According to this, when a delay occurs in the data scrambler, the delay in the data scrambler is canceled by delaying the phase of the address output from the address pattern generator in accordance with the pattern storage command and the pattern selection command. The address and its physical data can be generated at a timing according to programming.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration example of a pattern generation circuit according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a sequence control unit which controls the order of various pattern generation instructions described in a program. The sequence control unit 1 is connected to an address pattern generation unit 2, a data pattern generation unit 3, and an address storage unit 4, which will be described later, via control lines C2, C3, and C4.
[0025]
Here, a calculation command (address pattern generation command) for causing the address pattern generation unit 2 to perform a calculation for generating an address pattern is output to the control line C2, and a data pattern is generated to the control line C3. An operation instruction (data pattern generation instruction) for causing the data pattern generation unit 3 to perform an operation for generating the data pattern is output. For the control line C4, an instruction (pattern storage instruction) for storing the address signal calculated by the address pattern generation unit 2 in the address storage unit 4 and an address signal stored in the address storage unit 4 are selected. Command (pattern selection command) is output.
[0026]
The address pattern generation unit 2 and the data pattern generation unit 3 are input with the operation instructions of the address pattern generation command and the data pattern generation command output from the sequence control unit 1 via the control lines C2 and C3. These address pattern generator 2 and data pattern generator 3 have a circuit for performing four basic arithmetic operations for generating a test pattern, and execute an operation specified by an input operation instruction to be a measurement target. It is configured to output a test pattern consisting of a suitable address and data.
[0027]
The address storage unit 4 is connected to the address pattern generation unit 2 through the signal line A2, and the addresses calculated by the address pattern generation unit 2 are sequentially input. The address storage unit 4 includes a plurality of storage registers, and sequentially stores address signals in the respective storage registers in accordance with a pattern storage command input via the control line C4. The address storage unit 4 includes a selection circuit that selects one of the plurality of storage registers, selects a storage register according to a pattern selection signal input via the control line C4, and is stored in the storage register. Configured to output the specified address.
[0028]
The data scramble unit 5 is connected to the address storage unit 4 through a signal line A4, and is connected to the data pattern generation unit 3 through a signal line D3. The data scramble unit 5 receives the address stored in the storage register selected by the address storage unit 4 via the signal line A4, and the data pattern data calculated by the data pattern generation unit 3 It is input via the signal line D3. The data scrambler 5 is configured to convert the data output from the data pattern generator 3 into physical data suitable for the object to be measured and output it in correspondence with the address input from the address storage unit 4. .
[0029]
The phase adjustment unit 6 is connected to the address pattern generation unit 2 through the signal line A2, and receives an address signal calculated by the address pattern generation unit 2. The phase adjusting unit 6 has a role of adjusting the phase of the address signal to the phase of the output data signal of the data scramble circuit 5 by advancing or delaying the phase of the address signal.
[0030]
Next, the operation of the pattern generation circuit according to this embodiment will be described.
FIG. 2 is a time chart when programming is performed so that the phase of data is delayed by three stages (three addresses) with respect to the address. , A1, a2,... Are address signals, d1, d2,... Are data signals, and ds1, ds2,. For example, the data for the address a1 is d1, and the converted data of the data d1 is ds1.
[0031]
Sequence control unit 1 outputs an address pattern generation command and a data pattern generation command to address pattern generation unit 2 and data pattern generation unit 3 in accordance with a preset test program. Further, a pattern storage command and a pattern selection command are output to the address storage unit 4.
[0032]
When the address pattern generation unit 2 receives an address pattern generation command from the sequence control unit 1, the address pattern generation unit 2 performs an operation according to the command, and sends the address signal shown in FIG. 2 (the uppermost waveform) to the address storage unit 4 and the phase adjustment unit. 6 is output.
When the data pattern generation unit 3 receives a data pattern generation command from the sequence control unit 1, it performs an operation according to this command, and as shown in FIG. 2 (second waveform from the top), for the corresponding address The data signal is output to the data scramble unit 5 with a delay of three addresses.
[0033]
When the address storage unit 4 receives an address signal from the address pattern generation unit 2, the address storage unit 4 sequentially stores the address signal in accordance with a pattern storage command input from the sequence control unit 1. Then, as shown in FIG. 2 (third waveform from the top), the address storage unit 4 delays and outputs the address signal generated by the address pattern generation unit 2 by three addresses. Here, in the address storage unit 4, in accordance with the pattern selection command received from the sequence control unit 1, the storage register that has taken in the address signal three addresses before is selected by the selection circuit, and the address signal stored in this storage register Is output. As a result, the addresses and data corresponding to each other are input to the data scramble unit 5 with substantially the same phase.
[0034]
When the data scramble unit 5 receives the address signals a1, a2,... From the address storage unit 4 and the data signals d1, d2,... From the data pattern generation unit 3, the data scramble unit 5 converts the data signals into physical data ds1 corresponding to the address signals. , Ds2,. At this time, since the input address and the data are in phase, the data corresponding to each address is correctly physically converted. Then, as shown in FIG. 2 (the fourth waveform from the top), physical data ds1, ds2,... Are transferred from the data scramble unit 5 with a delay of one address with respect to the address signal output from the address storage unit 4. Is output. This physical data is data supplied to the object to be measured.
[0035]
When the phase adjustment unit 6 receives the address signal from the address pattern generation unit 2, the phase adjustment unit 6 adjusts the phase of the address signal so as to match the phase of the output data of the data scramble unit 5, and outputs the address signal whose phase is adjusted. This address signal is an address supplied to the device under test. In this example, the phase adjustment unit 6 sends the address output from the address pattern generation unit 2 by one address, so that the address supplied from the phase adjustment unit 6 to the measurement target is The physical data supplied from the data scramble unit 5 to the object to be measured is delayed by 3 addresses, and a delay relationship between the address and the data according to the test program is set.
[0036]
The sequence control unit 1 sequentially outputs operation instructions such as an address pattern generation instruction and a data pattern generation instruction at predetermined time intervals according to the test program. Thereby, the series of operations described above are repeatedly executed, and test patterns (address patterns and data patterns) are output one after another.
[0037]
As mentioned above, although one embodiment of the present invention has been described, the present invention is not limited to this embodiment, and design changes and the like within a scope not departing from the gist of the present invention are included in the present invention. For example, in the above-described embodiment, the address storage unit 4 includes a plurality of storage registers and a selection circuit. However, for example, the address storage unit 4 may include a delay circuit that outputs an input address with a predetermined delay.
[0038]
【The invention's effect】
According to the first aspect of the present invention, an address pattern generation instruction and a data pattern generation instruction are output according to a sequence described in a program, and an address pattern is sequentially output based on the address pattern generation instruction, and the data pattern generation instruction the corresponding data pattern sequentially outputs to the address pattern, it stores the address thus sequentially outputted to the pattern storage instruction output from the sequence control unit in the storage register based on, is output from the sequence control unit The address stored in the storage register selected by the selection circuit according to the pattern selection command is sequentially output, and based on this address, the data is converted into physical data suitable for the object to be measured, and the physical data is converted to the address. To adjust the phase of Because, even if the address and data phases do not match, it is possible to properly convert the data into physical data. In other words, data can be physically converted for addresses having different phases. It is also possible to input corresponding addresses and data to the data scramble means.
[0039]
According to the second aspect of the present invention, since the pattern selection command is output so that the phase of the address output from the address storage means matches the phase of the corresponding data, the data scramble means corresponds to the address. It becomes possible to generate physical data correctly .
[0040]
According to the third aspect of the present invention, the physical data is generated by inverting the data in accordance with the address. Therefore, it is possible to generate the physical data of the data having dependency on the address.
According to the invention of claim 4 , since the phase of the address is delayed in accordance with the pattern storage command and the pattern selection command, even if it takes time for data scrambling, the phases of the corresponding address and data are matched. Can be output.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a pattern generation circuit according to the present invention.
FIG. 2 is a time chart for explaining the operation of the pattern generation circuit according to the present invention;
FIG. 3 is a block diagram showing a configuration of a conventional pattern generation circuit.
FIG. 4 is a time chart for explaining the operation of a conventional pattern generation circuit.
[Explanation of symbols]
1: Sequence control unit 2: Address pattern generation unit 3: Data pattern generation unit 4: Address storage unit 5: Data scramble unit 6: Phase adjustment unit

Claims (4)

Sequence control means for outputting an address pattern generation instruction and a data pattern generation instruction in accordance with a sequence described in the program;
Address pattern generation means for generating an address pattern based on an address pattern generation instruction output from the sequence control means and sequentially outputting addresses forming the address pattern;
Data pattern generation means for generating a data pattern corresponding to the address pattern based on a data pattern generation command output from the sequence controller and sequentially outputting data forming the data pattern;
A plurality of storage registers for storing addresses sequentially output from the address pattern generation means according to a pattern storage instruction output from the sequence control means, and a pattern selection instruction output from the sequence control means from among the storage registers An address storage means for sequentially outputting the addresses stored in the storage registers selected by the selection circuit ;
Data scrambling means for converting data output from the data pattern generation means into physical data suitable for the measurement target based on the address output from the address storage means;
Phase adjusting means for adjusting the phase of the address output from the address pattern generating means with respect to the data output from the data scramble means;
A pattern generation circuit comprising: The sequence control means includes
2. The pattern generation circuit according to claim 1, wherein the pattern selection instruction is output so that a phase of an address output from the address storage unit matches a phase of corresponding data. The data scramble means includes
  2. The pattern generation circuit according to claim 1, wherein the data output from the data pattern generation means is inverted in accordance with an address output from the address storage means. The phase adjusting means is
  2. The pattern generation circuit according to claim 1, wherein a phase of an address output from the address pattern generation means is delayed according to the pattern storage instruction and the pattern selection instruction.

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