JP4192616B2 - Ferroelectric memory and initialization method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric memory (FeRAM) using a ferroelectric capacitor as a storage medium and an initialization method thereof.
[0002]
[Prior art]
FIG. 4 is a circuit diagram showing a main part of an example of a conventional ferroelectric memory in which a 1-transistor / 1-capacitor type memory cell and a reference cell are arranged (see, for example, Patent Document 1). In FIG. 4, 1 is a memory cell region, 2 is a memory cell, WL is a word line, PL is a plate line, and BL and / BL are bit lines. 3 is a reference cell region, 4 is a reference cell, RWL is a reference word line, and RPL is a reference plate line. Reference numeral 5 denotes a sense amplifier.
[0003]
FIG. 5 is a circuit diagram showing the configuration of the memory cell 2 and the reference cell 4. In FIG. 5, in the memory cell 2, 6 is a ferroelectric capacitor, 7 is an nMOS transistor that forms a transfer gate, 8 in the reference cell 4, 8 is a ferroelectric capacitor, and 9 is an nMOS transistor that forms a transfer gate. The size of the ferroelectric capacitor 8 is smaller than that of the ferroelectric capacitor 6.
[0004]
For example, when the ferroelectric memory shown in FIG. 4 is used as a security chip, the device manufacturer is security related to a specific or all memory cell area under the wafer state, for example, the memory cell 2 in the memory cell area 1. Data is written, logic 0 is written in the reference cell 4 in the reference cell area 3 and packaged before shipment. The customer uses the memory cell area 1 as a ROM (Read Only Memory).
[0005]
[Patent Document 1]
Japanese Patent Laid-Open No. 2000-67597 [0006]
[Problems to be solved by the invention]
Generally, a ferroelectric memory receives a thermal history of 200 ° C. to 250 ° C. in a packaging process. For this reason, the ferroelectric memory in which the memory cell region 1 and the reference cell region 3 are written under the wafer state for use as a security chip has the polarization of the ferroelectric capacitors 6 and 8 in the packaging process. You will receive thermal depolarization due to thermal history.
[0007]
FIG. 6 is a diagram showing hysteresis characteristics of the ferroelectric capacitor 6. The vertical axis represents the charge amount Q, and the horizontal axis represents the voltage V of the plate line PL with respect to the bit line BL. The remanent polarization point a is in a state storing a logic 0 before undergoing depolarization, and the remanent polarization point b is in a state storing a logic 1 before undergoing depolarization. For example, the remanent polarization point a moves to c, and the remanent polarization point b moves to d.
[0008]
Here, FIG. 7 is a diagram for explaining a problem when the conventional ferroelectric memory shown in FIG. 4 is used as a security chip. For example, when a thermal history of 250 ° C. is received in the packaging process. The change of the output charge amount to the bit line of the memory cell 2 and the reference cell 4 is shown.
[0009]
In FIG. 7, the vertical axis represents the output charge amount to the bit line, the curve 10 represents the change in the output charge amount to the bit line of the memory cell 2 storing logic 1, and the curve 11 represents the memory storing logic 0. The change in the output charge amount to the bit line of the cell 2, the curve 12 shows the change in the output charge amount to the bit line of the reference cell 4, P0 is a point before the thermal history in the packaging process, and P1 is in the packaging process After the heat history, the first cycle is read, and P2 to P8 are the second cycle to the eighth cycle.
[0010]
As described above, when the conventional ferroelectric capacitor shown in FIG. 4 is used as a security chip, the output charge amount from the reference cell 4 to the bit line becomes large at the time of reading in the first cycle after packaging, and the logic 1 Approaches the amount of output charge from the memory cell 2 storing the data to the bit line. Even in such a case, when the design rule is large and the driving voltage is high, there is no problem in reading the logic 1 data without taking a special reading method.
[0011]
However, when the design rule is reduced and the drive voltage is designed to be low, for example, 2.7 V or less as the capacity and the voltage are reduced, the data read margin is reduced. When the output charge amount from the memory cell 2 increases and approaches the output charge amount from the memory cell 2 storing the logic 1, there is a problem that the data of the logic 1 cannot be guaranteed.
[0012]
In view of this point, the present invention, for example, causes a device manufacturer to write in a specific or all memory cell region and reference cell region under a wafer state, and the polarization of the ferroelectric capacitor is caused by the thermal history at the time of packaging. An object of the present invention is to provide a ferroelectric memory capable of guaranteeing reading after packaging even in the case of depolarization.
[0013]
[Means for Solving the Problems]
The ferroelectric memory of the present invention, upon initial power-up after writing to the reference cell, without driving the plate line, the reference plate line driving circuit for one cycle drives certain or all of the reference plate line It is to have.
[0014]
According to the ferroelectric memory of the present invention, upon initial power-up after writing to the reference cell, without driving the plate line, the reference plate line to one cycle drives certain or all of the reference plate line Since the device is equipped with a drive circuit, for example, the device manufacturer writes to a specific or all memory cell region and reference cell region under the wafer state, and the polarization of the ferroelectric capacitor is reduced by the thermal history at the time of packaging. Even in such a case, the polarization state of the ferroelectric capacitor of the specific or all reference cells can be brought close to the state before the thermal history before the read cycle is started.
[0015]
According to the ferroelectric memory initialization method of the present invention, a reference cell is driven by driving a specific or all reference plate lines for one cycle without driving a plate line at the first power-on after writing to the reference cell. It has the process of initializing.
[0016]
According to the ferroelectric memory initialization method of the present invention, at the first power-on after writing to the reference cell, the specified or all reference plate lines are driven for one cycle without driving the plate lines. Since it has a process of initializing the reference cell, for example, a device manufacturer writes data to a specific or all memory cell area and reference cell area under a wafer state, and a ferroelectric material is formed by a thermal history at the time of packaging. Even in the case where the polarization of the capacitor is depolarized, the polarization state of the ferroelectric capacitor of a specific or all reference cells can be brought close to the state before the thermal history before the read cycle is started. it can.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
1 to 3, a ferroelectric memory and an initialization method thereof according to an embodiment of the present invention will be described with reference to a one-transistor / one-capacitor type ferroelectric memory and an initialization method thereof. A case where the present invention is applied to a ferroelectric memory formed by arranging memory cells and reference cells and an initialization method thereof will be described as an example.
[0018]
FIG. 1 is a circuit diagram showing a main part of one embodiment of a ferroelectric memory according to the present invention. In one embodiment of the ferroelectric memory according to the present invention, a reference plate line driving circuit 13 for driving the reference plate line RPL for one cycle is provided only at the first power-on after the package, and the others are shown in FIG. The same configuration as that of the ferroelectric memory. The reference plate line drive circuit used in the read cycle is provided as is well known in the art, but is not shown.
[0019]
FIG. 2 is a circuit diagram showing a configuration of the reference plate line driving circuit 13. In FIG. 2, 14 is a power supply voltage input terminal for inputting the power supply voltage VCC, 15 is a voltage pulse generation circuit (first voltage pulse generation circuit), 16 is an NPN transistor, 17 to 19 are resistors, and 20 is a resistor. It is a capacitor. The voltage pulse generation circuit 15 generates one positive voltage pulse in response to the power supply being supplied and the power supply voltage VCC being input.
[0020]
Further, 21 is an AND circuit (third voltage pulse generation circuit), and 22 is a counter (voltage pulse generation control circuit). The AND circuit 21 AND-processes the output of the voltage pulse generation circuit 15 and the output of the counter 22 to generate a voltage pulse for driving the reference plate line RPL whose voltage is the power supply voltage VCC.
[0021]
The counter 22 sets the initial value of the output to logic 1, counts the voltage pulse output from the AND circuit 21, and when one voltage pulse is output from the AND circuit 21 after packaging, the count value “ 1 "is stored in a nonvolatile manner, and thereafter, logic 0 is output.
[0022]
In the reference plate line drive circuit 13 configured as described above, for example, when a device manufacturer ships an embodiment of the ferroelectric memory of the present invention and then the customer first turns on the power, the voltage pulse generation circuit 13 15 generates a voltage pulse. In response to this, the AND circuit 21 supplied with logic 1 from the counter 22 generates a voltage pulse corresponding to the voltage pulse generated by the voltage pulse generation circuit 15 to drive the reference plate line RPL.
[0023]
The counter 22 counts the voltage pulse output from the AND circuit 21, stores the count value “1” of the voltage pulse in a non-volatile manner, and thereafter outputs logic 0. As a result, every time the power is turned on, the voltage pulse generation circuit 15 generates a voltage pulse, but the AND circuit 21 generates a voltage pulse corresponding to the voltage pulse generated by the voltage pulse generation circuit 15. There is no.
[0024]
As described above, in one embodiment of the ferroelectric memory according to the present invention, the AND circuit 21 and the counter 22 use the voltage corresponding to the voltage pulse generated by the voltage pulse generation circuit 15 only at the first power-on after the package. A second voltage pulse generating circuit that generates a pulse to drive the reference plate line RPL is configured.
[0025]
When one embodiment of the ferroelectric memory according to the present invention configured as described above is used as, for example, a security chip, a device manufacturer relates to a security cell in a memory cell 2 in the memory cell region 1 under a wafer state. In addition to writing data, logic 0 is written to the reference cell 4 in the reference cell area 3 and packaged before shipment. The customer uses the memory cell area 1 as a ROM.
[0026]
FIG. 3 is a timing chart showing the operation of one embodiment of the ferroelectric memory of the present invention (one embodiment of the initialization method of the ferroelectric memory of the present invention). FIG. 3A is a power supply voltage VCC, and FIG. The voltage of the reference plate line RPL, FIG. 3C shows the voltage of the plate line PL, and FIG. 3D shows the voltages of the bit lines BL and / BL.
[0027]
That is, when an embodiment of the ferroelectric memory according to the present invention is shipped by a device manufacturer, for example, when the customer first turns on the power, a read preparation cycle is started, and the reference plate line driving circuit 13 starts the reference. A voltage pulse whose voltage is the power supply voltage VCC is supplied to the plate line RPL. As a result, the polarization state of the ferroelectric capacitor 8 of the reference cell 4 can be brought close to the state before receiving the thermal history. Therefore, when a read cycle is subsequently started, normal reading can be performed by a conventionally known method.
[0028]
According to one embodiment of the ferroelectric memory of the present invention, for example, in order to design a drive voltage as a low voltage of 2.7 V or less and use it as a security chip, a device manufacturer can Even after writing to the memory cell region 1 and the reference cell region 3 and the polarization of the ferroelectric capacitor 8 of the reference cell 4 is depolarized due to the thermal history during the packaging, reading after the packaging is performed. Can be guaranteed.
[0029]
In the embodiment of the ferroelectric memory of the present invention, the case where the ferroelectric memory of the present invention is used as a security chip has been described as an example. However, the ferroelectric memory of the present invention has one transistor / A ferroelectric memory in which a one-capacitor type memory cell and a reference cell are arranged, and is widely applied to a ferroelectric memory in which a device manufacturer writes data in a memory cell region and a reference cell region under a wafer state. be able to.
[0030]
In addition, since a memory cell miniaturized to perform a low voltage operation has a small data read margin, the ferroelectric memory of the present invention has a miniaturized 2-transistor / 2-capacitor type memory cell. The present invention can be applied to a ferroelectric memory having an MFS (Metal Ferroelectric Semiconductor) FET, and the like to obtain an effect.
[0031]
【The invention's effect】
As described above, according to the ferroelectric memory of the present invention, upon initial power-up after writing to the reference cell, without driving the plate line, identified or one cycle every reference plate line By providing a reference plate line drive circuit for driving, for example, a device manufacturer writes data to a specific or all memory cell area and reference cell area under a wafer state, and ferroelectrics are generated by a thermal history at the time of packaging. Even if the polarization of the body capacitor is depolarized, the polarization state of the ferroelectric capacitor of a specific or all reference cells is brought close to the state before the thermal history before the read cycle is started. Therefore, reading after packaging can be guaranteed.
[0032]
Further, according to the initialization method of the ferroelectric memory of the present invention, at the first power-on after writing to the reference cell, the specified or all reference plate lines are driven for one cycle without driving the plate lines. In this case, for example, the device manufacturer writes data to a specific or all memory cell area and reference cell area under the wafer state, and the thermal history at the time of packaging. Even in the case where the polarization of the ferroelectric capacitor is depolarized, the polarization state of the ferroelectric capacitor in a specific or all reference cells is set to the state before the thermal history before the read cycle is started. Since they can be close to each other, reading after packaging can be guaranteed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a main part of an embodiment of a ferroelectric memory of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a reference plate line driving circuit provided in an embodiment of a ferroelectric memory of the present invention.
FIG. 3 is a timing chart showing the operation of one embodiment of the ferroelectric memory of the present invention (one embodiment of the ferroelectric memory initialization method of the present invention);
FIG. 4 is a circuit diagram showing a main part of an example of a conventional ferroelectric memory.
5 is a circuit diagram showing a configuration of a memory cell and a reference cell included in the conventional ferroelectric memory shown in FIG. 4. FIG.
6 is a diagram showing hysteresis characteristics of a ferroelectric capacitor of a memory cell included in the conventional ferroelectric memory shown in FIG. 4; FIG.
FIG. 7 is a diagram for explaining a problem when the conventional ferroelectric memory shown in FIG. 4 is used as a security chip.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell area 2 ... Memory cell 3 ... Reference cell area 4 ... Reference cell 5 ... Sense amplifier 13 ... Reference plate line drive circuit WL ... Word line PL ... Plate line RWL ... Reference word line RPL ... Reference plate line BL, / BL ... Bit line

Claims (5)

Upon initial power-up after writing to the reference cell, without driving the plate line, a ferroelectric, characterized in that it comprises a reference plate line driving circuit for one cycle drives certain or all of the reference plate line Body memory.   2. The ferroelectric memory according to claim 1, wherein the memory cell and the reference cell have a one-transistor / one-capacitor structure. The reference plate line drive circuit includes a voltage pulse generation circuit that generates a voltage pulse in response to power-on, and a voltage pulse transmission control circuit that controls the interruption and passage of the voltage pulse generated from the voltage pulse generation circuit. 2. The ferroelectric memory according to claim 1, further comprising: The reference plate line driving circuit further first when the voltage pulse generation circuit is outputting the voltage pulse after the writing to the reference cell, passed through the voltage pulse to the voltage pulse transfer control circuit, and wherein the voltage pulse transfer control circuit and nonvolatile manner that passed through the voltage pulse, thereafter, controlling said voltage pulse transfer control circuit so as to cut off the voltage pulse the voltage pulse generating circuit generates 4. The ferroelectric memory according to claim 3, further comprising a control circuit for performing the operation .   Strongly characterized by having a step of initializing a reference cell by driving a specific or all reference plate lines for one cycle without driving a plate line at the first power-on after writing to the reference cell A method for initializing a dielectric memory.

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