JP4192772B2 - Semiconductor chip mounting substrate, manufacturing method thereof, and manufacturing method of semiconductor package - Google Patents

Description

  The present invention relates to a semiconductor chip mounting substrate, a semiconductor package, and manufacturing methods thereof.

  In the field of semiconductor packages, demands for higher integration and higher speed are increasing in recent years. As a semiconductor package corresponding to these, a semiconductor chip mounted on a semiconductor chip mounting substrate in which a build-up layer is formed in a multilayer on a glass epoxy core substrate has been proposed. Such a semiconductor package is mounted on a larger substrate called a mother board by external connection terminals of the semiconductor chip mounting substrate, and is connected to each other by wiring in the mother board. By adopting such a mounting form, 0.1 to 0.25 mm, which is the electrode interval of the semiconductor chip, can be expanded to 0.5 to 1.0 mm and mounted on the board.

Many technologies related to a semiconductor chip mounting substrate using a build-up substrate have been proposed so far for the purpose of thinning, fine wiring, high reliability, and the like. For example, as a technology related to downsizing, a plurality of input / output pins for external connection that include an electronic component mounting portion on the surface side of a base material having a conductor circuit and are electrically connected to the electronic component side on the back side of the base material In the electronic component mounting substrate comprising: the interlayer insulating layer and the outer layer conductor circuit are formed on both front and back surfaces of the base material by a build-up method, and includes at least a region corresponding to at least the back side of the electronic component mounting portion of the substrate A semiconductor chip mounting substrate has been proposed in which a plurality of via holes are provided in almost the entire region of the interlayer insulating layer, and the input / output pins are erected in the via holes (see Patent Document 1).
Also in the formation of fine wiring, the wiring that can be formed with high yield by the subtracting method of forming wiring by etching is circuit conductor width / circuit conductor interval (hereinafter referred to as L / S) = about 50 μm / 50 μm. For finer L / S = 35 μm / 35 μm wiring, a relatively thin plating layer is formed on the substrate surface, a plating resist is formed thereon, and the conductor is formed to the required thickness by electroplating. A semi-additive process is being used which is formed and then the relatively thin plating is removed by soft etching.

Japanese Patent No. 3091051

However, the semiconductor chip mounting substrate as in Patent Document 1 has a core substrate thickness of about 100 to 400 μm, and the multilayer semiconductor chip mounting substrate having a build-up layer formed on the surface thereof has a substrate thickness of 200 μm or less. It was difficult. On the other hand, if the thickness is made too thin, the rigidity of the substrate is lowered, and there is a problem that it becomes difficult to carry in the substrate manufacturing process or the semiconductor package assembly process. On the other hand, the inventors have provided a semiconductor chip mounting substrate in which a plurality of build-up layers are formed on a conductive temporary substrate as a semiconductor chip mounting substrate capable of efficiently producing a thin semiconductor package, and at least the conductive temporary mounting substrate. A first insulating layer formed on one surface of the substrate; a first wiring formed on the first insulating layer; and a first wiring electrically connecting the conductive temporary substrate and the first wiring. 1 connection conductor, a second insulating layer formed on the first wiring, a second wiring formed on the second insulating layer, the first wiring, and the second wiring A semiconductor chip mounting board is provided, comprising: a second connection conductor that electrically connects the wiring. In such a semiconductor chip mounting substrate, after sealing the semiconductor chip, it is necessary to process the conductive temporary substrate into an external connection terminal by etching or the like, and then apply nickel and gold plating on the surface, which is complicated. There was a problem that.
On the other hand, the bonding between the wiring and the insulating layer according to the prior art has formed an unevenness exceeding 1 μm on the wiring surface and secured the bonding strength by the anchor effect. However, when a high-speed electrical signal is applied to the uneven wiring having a surface exceeding 1 μm in this way, the electrical signal is concentrated and flows near the surface of the wiring due to the skin effect, which increases transmission loss. There is. Further, when the wiring becomes smaller than L / S = 25 μm / 25 μm, when the wiring surface is roughened by the conventional method, the wiring becomes thin or the variation in the wiring width becomes large. is there.

The object of the present invention is to improve the above-mentioned problems of the prior art, and the object is to provide a thin and highly reliable semiconductor package capable of high-density mounting, and a semiconductor chip mounting substrate used therefor, And it is providing the manufacturing method which can manufacture them efficiently.
Another object of the present invention is to provide a semiconductor chip mounting substrate, a semiconductor package, and a manufacturing method capable of efficiently manufacturing the same, which can form fine wiring with high accuracy and efficiently transmit high-speed electrical signals. And

  In order to achieve the above object, the present invention provides a semiconductor chip mounting substrate in which a plurality of buildup layers are formed on one surface of a carrier layer, and an opening is formed in an external connection terminal portion of the carrier layer, and the semiconductor Provided are a semiconductor package in which a semiconductor chip is mounted on a chip mounting substrate, the carrier layer is removed after resin sealing, and a manufacturing method thereof. The present invention is configured as follows.

The invention according to claim 1 is a semiconductor chip mounting substrate on which a large number of semiconductor chips are mounted on one surface, and a carrier layer and two or more insulating layers formed on one surface of the carrier layer A plurality of wirings formed on each interlayer and on the outermost insulating layer, and a connection conductor for electrically connecting the wirings formed on different layers, and the wiring on the outermost layer includes a semiconductor. Chip connection terminals, external connection terminals are formed on the wiring formed in a layer closest to the carrier layer, and the external connection terminals are formed on the carrier layer or the carrier layer and the insulating layer of the external connection terminal portion. An opening is formed, and the carrier layer is removable at least after the semiconductor chip is mounted.
A second aspect of the present invention is the semiconductor chip mounting substrate according to the first aspect, wherein the carrier layer can be removed mechanically.
A third aspect of the present invention is the semiconductor chip mounting substrate according to the second aspect, wherein an adhesive force between the insulating layer and the carrier layer is 10 to 500 N / m.
A fourth aspect of the present invention is the semiconductor chip mounting substrate according to any one of the first to third aspects, wherein the insulating layer has a thickness of 1 to 50 μm.
A fifth aspect of the present invention is the semiconductor chip mounting substrate according to any one of the first to fourth aspects, wherein the carrier layer has a thickness of 30 to 500 μm.
A sixth aspect of the present invention is the semiconductor chip mounting substrate according to any one of the first to fifth aspects, wherein the carrier layer is an insulating film.
In the invention according to claim 7, the material of the carrier layer is at least one or more of imide group, amide group, phenol group, phenylene group, ester group, ether group, sulfone group, carbonate group, carbonyl group, and silicone bond. The semiconductor chip mounting substrate according to any one of claims 1 to 6, wherein the semiconductor chip mounting substrate is any one of a resin, a liquid crystal polymer, a fluorine-containing resin and an epoxy resin.

The invention according to claim 8 is a method of manufacturing a semiconductor chip mounting substrate comprising a carrier layer and a plurality of insulating layers formed on one surface thereof, and a plurality of semiconductor chips mounted on the surface on which the insulating layer is formed. A step of forming a first insulating layer on one surface of the carrier layer, a step of forming an opening in the carrier layer and the first insulating layer at a location to be an external connection terminal, Forming a first wiring including the external connection terminal on one insulating layer, forming a second insulating layer on the first insulating layer and the first wiring, and the second Forming a second wiring on the insulating layer, forming a connection conductor for electrically connecting the first wiring and the second wiring, and providing a semiconductor chip connection terminal on the outermost wiring And forming the external connection terminals and the outermost layer wiring. Consists step of applying at least nickel and gold plating part, the carrier layer is a method for producing a semiconductor chip mounting board comprising a step of removing at least the semiconductor chip after mounting.
The invention according to claim 9 is a method of manufacturing a semiconductor chip mounting substrate comprising a carrier layer and a plurality of insulating layers formed on one surface thereof, and a plurality of semiconductor chips mounted on the surface on which the insulating layer is formed. A step of forming an external connection terminal on one surface of the carrier layer, a step of forming an opening reaching the external connection terminal in the carrier layer, and a surface of the carrier layer on which the external connection end is formed. Forming a first insulating layer on the first insulating layer; forming a first wiring on the first insulating layer; and a first connection for electrically connecting the external connection terminal and the first wiring. Forming a conductor; forming a second insulating layer on the first insulating layer and the first wiring; forming a second wiring on the second insulating layer; A second electrically connecting the first wiring and the second wiring; A step of forming a connection conductor, a step of forming a semiconductor chip connection terminal in the outermost layer wiring, and a step of applying at least nickel and gold plating to the exposed portion of the external connection terminal and the outermost layer wiring, The carrier layer is a method for manufacturing a semiconductor chip mounting substrate having a step of removing at least after the semiconductor chip is mounted.
According to a tenth aspect of the present invention, there is provided the semiconductor chip mounting substrate according to any one of the first to seventh aspects, or the semiconductor chip mounting substrate obtained by the manufacturing method according to the eighth or ninth aspect. A step of mounting a chip, a step of electrically connecting the semiconductor chip connection terminal of the semiconductor chip mounting substrate and the semiconductor chip, a step of sealing at least a necessary portion of the semiconductor chip with a sealing resin, A method of manufacturing a semiconductor package, comprising: removing the carrier layer of the semiconductor chip mounting substrate; and forming external connection bumps on the external connection terminals of the semiconductor chip mounting substrate.

The invention according to claim 11 is the method for manufacturing a semiconductor package according to claim 10, further comprising a step of removing the carrier layer by mechanical peeling.
The invention according to claim 12 is the method of manufacturing a semiconductor package according to claim 11, further comprising a step of performing means for reducing an adhesive force between the carrier layer and the insulating layer before performing the mechanical peeling. is there.
A thirteenth aspect of the present invention is the method according to any one of the tenth to thirteenth aspects, wherein the semiconductor chip is mounted using a die bond film, and the resin sealing is performed while the die bond film is semi-cured. It is a manufacturing method of the semiconductor package of description.
The invention described in claim 14 includes the step of performing an electrical connection between the semiconductor chip connection terminal of the semiconductor chip mounting substrate and the semiconductor chip by wire bonding. A method for manufacturing a semiconductor package.
The invention according to claim 15 is the step of simultaneously sealing a plurality of the semiconductor chips with the sealing resin integrally connected, and the integrated sealing resin and the insulating layer of the semiconductor chip mounting substrate. 15. The method of manufacturing a semiconductor package according to claim 10, further comprising a step of simultaneously cutting with a dicer.
The invention according to claim 16 is the method of manufacturing a semiconductor package according to claim 15, further comprising a step of cutting the insulating resin and the insulating layer of the semiconductor chip mounting substrate after the formation of the external connection bumps. .
A seventeenth aspect of the present invention is a semiconductor package manufactured by the manufacturing method according to any one of the tenth to sixteenth aspects.

According to the present invention, it is possible to efficiently manufacture a semiconductor chip mounting substrate, a semiconductor package, and a semiconductor package that can be mounted at high density and that are thin and excellent in reliability.
At the same time, it is possible to efficiently form a fine wiring and to efficiently manufacture a semiconductor chip mounting substrate, a semiconductor package, and a semiconductor package capable of efficiently transmitting high-speed electrical signals.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Semiconductor chip mounting substrate)
In FIG. 1, the cross-sectional schematic diagram of one Embodiment (two buildup layers) of the semiconductor chip mounting substrate of this invention was shown. In the semiconductor chip mounting substrate of the present invention, as shown in FIG. 1, the first insulating layer 100 is formed on one surface of the carrier layer 110, and the first wiring including the external connection terminal 103 is further formed thereon. 101 is formed. An opening 107 is formed in the carrier layer 110 and the first insulating layer 100 in the external connection terminal portion. A second insulating layer 102 is formed over the first insulating layer 100 and the first wiring 101, and a second wiring 104 is formed thereover. The first wiring 101 and the second wiring 104 are electrically connected by a connection conductor 105 (blind via). Although only two insulating layers are shown in FIG. 1, a plurality of insulating layers and wirings may be formed as necessary. A wiring (second wiring 104 in FIG. 1) including the semiconductor chip connection terminal is formed on the outermost insulating layer. Further, on the outermost insulating layer (the second insulating layer 102 in FIG. 1) and the outermost layer wiring (the second wiring 104 in FIG. 1), a solder resist except for the semiconductor chip connection terminals is necessary. An insulating coating 106 like this may be formed. In FIG. 2, a semiconductor chip in which external connection terminals 103 are formed on the carrier layer separately from the first wiring, and the first connection terminals 108 (metal bumps) and the second connection terminals 109 (metal bumps) are used. The cross-sectional schematic diagram of one Embodiment (2 buildup layers) of the mounting substrate was shown.
The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed for manufacturing a semiconductor chip to be mounted and a target semiconductor package.

(Carrier layer)
In the conventional semiconductor chip mounting substrate, the insulating base material used is such as heat resistance, rigidity, dimensional stability, chemical resistance, etc. in the substrate manufacturing process and semiconductor package assembly process, and reflow resistance as a semiconductor package, All reliability tests such as PCT property (pressure cooker test), THB property (high temperature and high humidity bias), and TCT property (temperature cycle test) had to be satisfied. As a base material that can satisfy all of these characteristics, a polyimide film or a glass epoxy base material is generally used, but a polyimide film is very expensive or a thin glass epoxy base material is difficult to obtain. There was a problem such as that.
The semiconductor chip mounting substrate of the present invention is composed of at least an insulating layer and a carrier layer, and each layer may be composed of a plurality of layers as necessary. For this reason, characteristics such as rigidity and dimensional stability as a semiconductor mounting substrate are not necessarily required for the insulating layer, and the carrier layer is removed after sealing, so that it is not necessary to satisfy the reliability of the semiconductor package. Inexpensive materials that could not be used conventionally can be used.
The carrier layer is preferably a material containing a heat-resistant engineering plastic film or a resin thereof. For example, an imide group, an amide group, a phenol group, a phenylene group, an ester group, an ether group, a sulfone group, a carbonate group, a carbonyl group, a resin containing at least one silicone bond, or a liquid crystal polymer, a fluorine-containing resin, an epoxy resin It is preferable to use either one. More specifically, the resin containing at least one imide group includes a polyimide resin and a polyamide-imide resin, and the resin including at least one amide group includes a polyamide resin and an aramid resin, and includes a phenol group. As the resin containing at least one or more, there is a phenol resin. As the resin containing at least one phenylene group, there is a polyphenylene sulfide resin. As the resin containing at least one ester group, there are polyethylene terephthalate resin, polyethylene naphthalate. There are phthalate resins and polyarylate resins. Examples of resins containing at least one ether group include polyether ether ketone resins and polyetherimide resins. Examples of resins containing at least one sulfone group include polysulfone resins and polyaryl resins. There is Terusaruhon resin, as the at least one containing resins carbonate groups, there is a polycarbonate resin, as the at least one including resin silicone bond, there is a siloxane-modified polyamideimide resin.
Further, the material of the carrier layer is not particularly limited as long as the characteristics of the manufacturing process of the semiconductor chip mounting substrate and the semiconductor package assembling process can be satisfied, and it is preferable to select a material that is easy to remove because it is removed after resin sealing. . For example, in addition to the above-mentioned engineering plastic film, metals such as copper, aluminum, iron, nickel, or alloys containing them, paper, cloth, glass cloth, or combinations thereof can also be used. However, when using a metal, in order to prevent gold plating from depositing on the carrier layer in the gold plating step of the wiring, it is preferable to cover the surface with a resist or other material that does not deposit plating. Further, since the material of the carrier layer becomes unnecessary after the removal, it is preferable that the material is recyclable in order to reduce the environmental load. For example, metals such as copper and aluminum, engineering plastic films using thermoplastic resins, paper, and the like are preferable because they are easy to recycle.
It is preferable to use a material having a high water vapor transmission rate as the material for the carrier layer. It is preferable to use a material having a water vapor transmission rate of 1 (g / m ² · 24h) or more, and 10 (g / m ² · 24 h). The above is more preferable. In addition, from the viewpoint of difficulty in obtaining the material, 1000 (g / m ² · 24 h) or less is preferable.
Since the moisture permeability is inversely proportional to the thickness of the carrier layer, the moisture permeability increases by reducing the thickness. The thickness of the carrier layer is preferably 30 to 500 μm, more preferably 50 to 200 μm, in order to ensure the rigidity and dimensional stability of the semiconductor chip mounting substrate. However, it is preferable to experimentally obtain the optimum thickness in consideration of the thermal expansion coefficient, humidity expansion coefficient, elastic modulus, transportability, etc. of the material used.
Further, the carrier layer preferably has a low water absorption, and the water absorption rate according to JIS K7209 is preferably less than 1.5% by weight, and more preferably less than 1.0% by weight. When the water absorption rate exceeds 1.5% by weight, moisture evaporates in the manufacturing process of the semiconductor chip mounting substrate or the semiconductor package, and defects such as peeling, blistering or foaming are likely to occur due to the pressure.

(Insulating layer)
The first insulating layer 100 and the second insulating layer 102 in the present invention are preferably made of an insulating material. As the insulating material, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used. In particular, a thermosetting organic insulating material is more preferably a main component. Thermosetting resins include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, tris (2-hydroxyethyl) ) Resin containing isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, xylene resin, thermosetting containing condensed polycyclic aromatic Resin, benzocyclobutene resin, etc. can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.
A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.
As a method for forming the insulating layer, a varnish-like insulating material can be formed by a spin coater, a comma coater, printing, or the like, and then dried and cured. Alternatively, it can be formed in advance in a film shape and adhered to the substrate by pressing or laminating. Depending on the insulating material, it can be formed by impregnating a glass cloth or non-woven fabric with the material, forming a prepreg, and then bonding. Furthermore, varnish can also be apply | coated to metal foil and it can also adhere | attach on a board | substrate after drying. The thickness of the insulating layer is not particularly limited, but is preferably 5 to 30 μm, more preferably 5 to 15 μm, taking into account the insulation reliability and the thickness of the entire substrate. Moreover, it is preferable that the thermal expansion coefficient of an insulating layer is 10-40 ppm / degrees C, More preferably, it is 10-20 ppm / degrees C.

(Young's modulus)
The Young's modulus of the first insulating layer 100 and the second insulating layer 102 is preferably 1 to 5 GPa from the viewpoint of stress relaxation against thermal stress. The filler in the insulating layer is preferably added by appropriately adjusting the addition amount so that the thermal expansion coefficient of the insulating layer is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Flatness)
The flatness of the surfaces of the first insulating layer 100 and the second insulating layer 102 has an average roughness (Ra) of 1.0 μm or less, particularly 0.01 to 1.0 μm from the aspect of high-speed electrical signal transmission characteristics. More preferably, it is more preferably 0.01 to 0.4 μm. When the thickness exceeds 1.0 μm, the width variation of the formed wiring is large, and the attenuation of the high-speed electrical signal tends to be large. If it is less than 0.01 μm, the peel strength tends to be insufficient.
Similarly, the flatness of the wiring surface is preferably 1.0 μm or less in terms of Ra. That is, the interface between the first insulating layer 100 and the first wiring 101, the interface between the first wiring 101 and the second insulating layer 102, and the interface between the second insulating layer 102 and the second wiring 104 are The flatness of at least one of the interfaces is preferably 1.0 μm or less in terms of Ra. In particular, 0.01 to 1.0 μm is preferable, and 0.01 to 0.4 μm is more preferable.
In the present invention, Ra is an average roughness as described above, and can be measured using a stylus type surface roughness meter or the like (see JIS C 6481). Ra can be measured using a stylus type surface roughness meter or the like.

(Removal method of carrier layer)
As a method for removing the carrier layer, there are a method of peeling by mechanical force, a method by mechanical polishing, a wet etching by chemical solution, a method by dry etching by plasma, a method by laser, etc., depending on the combination of materials used They can be selected and combined as necessary. In these, the method of peeling with a mechanical force is preferable.

(Method of peeling with mechanical force)
In order to mechanically peel, the adhesive force between the insulating layer and the carrier layer is preferably 10 to 500 N / m, and more preferably 50 to 200 N / m. If the adhesive force is less than 10 N / m, there is a risk of peeling in the manufacturing process of the semiconductor chip mounting substrate or the semiconductor package, and if it is greater than 500 N / m, peeling becomes difficult in the carrier layer removing step. It is not preferable. However, when the adhesive force can be reduced to 500 N / m or less, more preferably 200 N / m or less by using the adhesive strength lowering means described below in the carrier layer removing step, the initial value of the adhesive force is greater than 500 N / m. May be.

(Adhesive strength reduction means)
The adhesive force can be lowered by any one or combination of temperature treatment, light irradiation, moisture absorption, and liquid treatment, and it is preferable to select an efficient method depending on the insulating layer and carrier layer materials. Further, the adhesive strength reducing means can be performed before or simultaneously with the peeling of the carrier layer. Furthermore, the adhesive force between the carrier layer and the insulating layer can be adjusted by previously performing a release treatment on the insulating layer forming side of the carrier layer. The method for the release treatment is not particularly limited, and surface treatment with a general silicone-based or non-silicone-based material can be used. Conversely, when the adhesive strength is weak, plasma treatment or corona discharge treatment can be performed to adjust the adhesive strength to a preferable level.

(Decrease in adhesive strength due to temperature treatment)
The temperature treatment is roughly divided into a constant temperature standing before the peeling step and a heat treatment and a cooling treatment performed simultaneously with the peeling step. As the temperature for the constant temperature standing, it is necessary that the adhesive force is sufficiently lowered so that the carrier layer does not remain and the insulating layer or the semiconductor package is not damaged by heat, preferably 50 to 250 ° C., and 80 to 150 ° C. More preferred. Such constant temperature standing is efficient and preferable to be performed simultaneously with heating and curing of the sealing resin. In addition, it is more preferable to use a material that rapidly shrinks at a certain temperature or more for the carrier layer because it may be easily peeled off only by heat treatment. The temperature is preferably 180 ° C. to 250 ° C., and polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, or the like can be used as the material to be used.
The heat treatment performed at the same time as the peeling step needs to be a temperature at which the adhesive force is sufficiently reduced so that no contaminants remain on the surface of the insulating layer and the semiconductor package is not damaged by heat. ° C is preferred, and 40 to 100 ° C is more preferred. Moreover, as a cooling process, it is necessary to do not damage a semiconductor package, -20-30 degreeC is preferable and 0-30 degreeC is more preferable.

(Decrease in adhesive strength due to light irradiation)
The adhesive force can be reduced by irradiating light before peeling off the carrier layer. As such light, ultraviolet rays are preferably used, and an ultraviolet exposure machine used in a general wiring board manufacturing process can be used. It is preferable to experimentally obtain an appropriate exposure amount based on the light transmission amount, type, and thickness of the carrier layer. What is necessary is just to select the optimal wavelength with the wavelength to use according to material.

(Decrease in adhesive strength due to moisture absorption)
Adhesion can be reduced by performing a moisture absorption treatment before the carrier layer is peeled off. The condition is preferably, for example, 60% RH or more, and can be heated simultaneously if necessary. As an atmosphere for absorbing moisture, pure water is preferable for preventing contamination and the like, but an organic solvent can be used as necessary.

(Decrease in adhesive strength due to liquid treatment)
Adhesive strength can be reduced by performing a liquid treatment before peeling off the carrier layer. As such a liquid, water, alcohol, an organic solvent, an alkaline aqueous solution, or the like can be used, and an effective one can be selected depending on the type and thickness of the carrier layer, and can also be combined. For example, the alcohol includes methanol, ethanol, and propanol, and the organic solvent includes acetone, tetrahydrofuran, dimethylformamide, dimethoxyethane, toluene, and the like. Furthermore, examples of the alkali component of the aqueous alkali solution include amine materials such as monoethanolamine and ethylenediamine, potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide. Moreover, as a liquid processing method, there exist immersion in a liquid and spray spraying, and when long-time processing is required, immersion in a liquid is preferable. Spray atomization is more efficient and more preferable when the carrier layer can be peeled off by spray pressure.

(Manufacturing method of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate can be manufactured by a combination of the following manufacturing methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Wiring formation method)
As a wiring formation method, a metal foil is formed on an insulating layer, an unnecessary portion of the metal foil is removed by etching (subtract method), and a method of forming a wiring by plating only at a necessary portion on the insulating layer ( There is a method (a semi-additive method) in which a thin metal layer (seed layer) is formed on an insulating layer, a necessary wiring is formed by electrolytic plating, and then the thin metal layer is removed by etching.

(Wiring formation by etching)
An etching resist is formed in a portion that becomes a wiring of the metal foil, and a chemical etching solution is sprayed and sprayed on a portion exposed from the etching resist, and unnecessary metal foil is removed by etching to form a wiring. For example, when a copper foil is used as the metal foil, an etching resist material that can be used for an ordinary wiring board can be used as the etching resist, and a resist ink can be formed by silk-screen printing or photosensitivity for etching resist. A dry film is laminated on a copper foil, and a photomask that transmits light is overlapped on the wiring shape thereon, exposed to ultraviolet rays, and unexposed portions are removed with a developer to form. As the chemical etching solution, a chemical etching solution used for a normal wiring board, such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used.

(Wiring formation by plating)
Further, the wiring can be formed by plating only a necessary portion on the insulating layer, and a wiring forming technique by normal plating can be used.
For example, after depositing an electroless plating catalyst on the surface of the insulating layer, a plating resist is formed on the surface where plating is not performed, and immersed in an electroless plating solution. Perform electroless plating. Thereafter, if necessary, the plating resist can be removed. Furthermore, a wiring having a height of 5 to 50 μm can be formed by electrolytic plating.

(Semi-additive seed layer formation)
There are two methods for forming the seed layer by the semi-additive method, such as vapor deposition or plating, and a method of bonding a metal foil. A subtractive metal foil can be formed in the same manner.

(Formation of seed layer by vapor deposition or plating)
A seed layer can be formed on the insulating layer by vapor deposition or plating. For example, when a base metal and a thin film copper layer are formed by sputtering as a seed layer, the sputtering apparatus used to form the thin film copper layer is a bipolar sputtering, a three-pole sputtering, a four-pole sputtering, a magnetron sputtering, a mirror. Tron sputtering or the like can be used. A target used for sputtering is sputtered 5 to 50 nm using, for example, a metal such as Cr, Ni, Co, Pd, Zr, Ni / Cr, or Ni / Cu as a base metal in order to ensure adhesion. Thereafter, a thin film copper layer can be formed by sputtering 100 to 500 nm using copper as a target.
Alternatively, copper can be formed by electroless plating of 0.5 to 3 μm on the insulating layer.

(Method of bonding metal foil)
In the case where the insulating layer has an adhesive function, the seed layer can be formed by bonding metal foils together by pressing or laminating. However, since it is very difficult to directly bond a thin seed layer, there are a method of thinning a thick metal foil and then thinning it by etching or a method of removing a carrier layer after bonding a metal foil with a carrier. is there. A copper / nickel / copper three-layer copper foil can be used as the former, and a peelable copper foil can be used as the latter. A seed layer of 5 μm or less can be formed.

(Wiring formation by semi-additive method)
A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form a wiring.

(Wiring shape)
The shape of the wiring is not particularly limited, but at least the outermost layer wiring on which the semiconductor chip is mounted is formed with a semiconductor chip connection terminal 16 (wire bond terminal or the like), and a developed wiring 20 connecting the external connection terminal 19 and interlayer connection It consists of terminals. The wiring arrangement is not particularly limited, but as shown in FIG. 3 (inner layer wiring, interlayer connection terminals, etc. are omitted), a fan-in type in which external connection terminals 19 are formed inside the semiconductor chip connection terminals 16. Alternatively, a fan-out type in which the external connection terminals 19 are formed outside the semiconductor chip connection terminals 16 as shown in FIG. 4 or a combination of these may be used.

FIG. 3 is a plan view of a fan-in type semiconductor chip mounting substrate according to an embodiment of the present invention. FIG. 4 is a plan view of a fan-out type semiconductor chip mounting substrate according to another embodiment of the present invention.
In the figure, reference numeral 13 denotes a semiconductor package region.
In the case of the flip chip type, 14 is a die bond film adhesion region, and 15 is a semiconductor chip mounting region. Reference numeral 16 denotes a semiconductor chip connection terminal.
In the case of the wire bond type, 17 is a die bond film adhesion region, and 18 is a semiconductor chip mounting region.
Reference numeral 19 is an external connection terminal, and 20 is a developed wiring.
Further, if necessary, a dummy pattern 21 that is not electrically connected to the semiconductor chip can be formed. The shape and arrangement of the dummy pattern are not particularly limited, but it is preferable to arrange the dummy pattern uniformly in the semiconductor chip mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Treatment of wiring surface)
When an insulating layer is formed on the wiring, it is preferable to form a film (not shown) containing a coupling agent such as a silane coupling agent on the surface of the wiring. The film containing this coupling agent can improve the adhesion reliability between the wiring and the insulating layer.
The coupling agent used is preferably a silane coupling agent, for example, the silane coupling agent has a functional group such as an epoxy group, amino group, mercapto group, imidazole group, vinyl group, or methacryl group in the molecule, A solution containing one or a mixture of two or more of these silane coupling agents can be used. As the solvent used for the preparation of the silane coupling agent solution, water, alcohol, ketones or the like can be used. A small amount of acid such as acetic acid or hydrochloric acid can be added to promote hydrolysis of the coupling agent. The content of the coupling agent is 0.01 wt% to 5 wt%, preferably 0.1 wt% to 0.5 wt%, based on the entire solution. The film formation treatment with the coupling agent can be performed by a method of immersing in the coupling agent solution adjusted as described above, spraying the solution, applying, or the like.
The substrate treated with the silane coupling agent is dried by natural drying, heat drying, or vacuum drying. Depending on the type of coupling agent used, it may be washed with water or ultrasonically before drying. is there. Furthermore, it is preferable to clean the surface of the wiring surface before the silane coupling agent treatment by appropriately combining degreasing treatment, alkali treatment, acid treatment, water washing, and the like as necessary.

(Connection conductor)
Since the semiconductor chip mounting substrate of the present invention has a plurality of wiring layers, a connection conductor for electrically connecting the wirings of each layer is provided. The connection conductor can be formed by providing a hole for connection in the insulating layer and filling the hole with a conductive paste or plating. Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching using plasma. The hole diameter is not particularly limited, but is preferably 20 to 300 μm and more preferably 50 to 150 μm.
Moreover, a metal bump can also be used as a connection conductor. For example, a metal bump is formed on the external connection terminal 103 or the first wiring 101, an insulating layer is formed thereon, and then the metal bump is exposed on the surface of the insulating layer by polishing or the like.
The diameter of the metal bump is not particularly limited, but is preferably 10 to 150 μm and more preferably 20 to 100 μm.
The material of the connecting conductor is not particularly limited, but copper, nickel, gold, silver, tin, aluminum, iron and alloys containing these can be used. Further, the metal bumps can be formed from a plurality of metal layers as required.

(Desmear treatment)
As the smear removal of the holes formed by the above-described method, dry treatment or wet treatment can be used. As the dry treatment, plasma treatment, reverse sputtering treatment, ion gun treatment, or RIE treatment can be used. Furthermore, plasma processing includes atmospheric pressure plasma processing and vacuum plasma processing, which can be selected as necessary. As a gas used for these treatments, nitrogen, oxygen, argon, freon (CF ₄ ), or a mixed gas thereof is preferable. An oxidizing agent such as chromate or permanganate can be used for the wet treatment.

(External connection terminal opening)
An opening for exposing the external connection terminal is provided in the carrier layer of the external connection terminal portion or in the carrier layer and the insulating layer. Examples of the processing method for the opening include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching using plasma. The opening diameter is not particularly limited, but is preferably 100 to 800 μm and more preferably 200 to 500 μm. Further, the order of forming the openings may be before or after forming the first wiring, as necessary.

(Formation of insulation coating)
An insulating coating 106 can be formed on the outermost layer wiring of the semiconductor chip mounting substrate except for the semiconductor chip connection terminals. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used. The thickness of the insulating coating is preferably 5 to 50 μm, more preferably 10 to 30 μm. If the thickness is 50 μm or more, the entire thickness of the semiconductor chip mounting substrate becomes thick, and if it is 5 μm or less, there may be a problem in insulation.

(Plating of wiring)
Nickel and gold plating can be sequentially applied to necessary portions of the wiring. Furthermore, nickel, palladium, or gold plating may be used as necessary. These platings are preferably performed on the semiconductor chip connection terminals and the external connection terminals of the wiring. For this plating, either electroless plating or electrolytic plating may be used. Further, if necessary, it can be simultaneously applied to the surface of the metal pattern such as an exposed wiring, a dummy pattern, or a reinforcing pattern. When a metal is used for the carrier layer, plating may be performed after the surface of the carrier layer is covered with a plating resist or the like.

(Manufacturing process of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate of the present invention can be manufactured by the following processes. FIGS. 5A to 5D are schematic cross-sectional views showing an example of an embodiment of the method for manufacturing a semiconductor chip mounting substrate of the present invention. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
In step (a), the first insulating layer 100 is formed on one surface of the carrier layer 110 as shown in FIG. 5A, and the carrier layer 110 and the first portion where the external connection terminals 103 are formed. In this step, the opening 107 is formed in the insulating layer 100.

(Process b)
(Step b) is a step of forming the first wiring 101 on the first insulating layer 100 as shown in FIG. The first wiring 101 can be formed by bonding a metal foil on the first insulating layer 100 and then processing it into a necessary pattern by etching. Alternatively, after the thin metal foil is bonded to the first insulating layer 100, the first wiring 101 may be formed in a semi-additive manner.

(Process c)
(Step c) is a step of forming the second insulating layer 102, the second wiring 104, and the connection conductor 105 as shown in FIG. A second insulating layer is formed over the first wiring 101 and the first insulating layer 100. Next, a hole reaching the first wiring 101 is formed in the second insulating layer 102 with a laser or the like, and after the inside of the hole is desmeared, a blind via serving as the second wiring 104 and the connection conductor 105 is formed. When an additive method or a semi-additive method is used as a wiring formation method, wiring and blind vias can be formed simultaneously, which is efficient and preferable. In FIG. 5, an example of two wiring layers is described. However, if necessary, (Step c) can be repeated to form more insulating layers and wiring layers.

(Process d)
(Step d) is a step of forming the insulating coating 106 on the outermost layer wiring except for the semiconductor chip connection terminals as shown in FIG. 5D. This step is not always necessary and can be omitted.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate in this way, it is possible to efficiently assemble the semiconductor package. Hereinafter, a preferable frame shape will be described in detail.
FIG. 7A is an overall plan view showing an example of a frame shape of the semiconductor chip mounting substrate of the present invention, and FIG. 7B is an enlarged view of a broken line part of FIG. As shown in FIG. 7, a block 23 is formed in which a plurality of semiconductor package regions 13 (portions to be a single semiconductor package) are arranged in rows and columns at regular intervals. Further, such a block is formed in a plurality of rows and columns. Although only two blocks are shown in FIG. 7, the blocks may be arranged in a lattice shape as necessary. The space width between the blocks is not particularly limited, but 0.5 to 10 mm is preferable in consideration of effective use of the semiconductor chip mounting substrate.

Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same. By arranging the semiconductor package region in this way, the semiconductor chip mounting substrate 22 can be effectively used.
In addition, a positioning mark such as the alignment guide hole 11 is preferably formed at the end of the semiconductor chip mounting substrate 22, and a pin hole by a through hole is more preferable. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.
Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions or outside the block. By forming the reinforcing pattern, the rigidity of the semiconductor chip mounting substrate is improved, and the assembly of the semiconductor package is facilitated. In addition, the reinforcing pattern can prevent warping and twisting of the semiconductor chip mounting substrate, and can be formed on both sides of the substrate and further on the inner buildup layer as necessary. The reinforcing pattern may be separately manufactured and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region, and the surface thereof is similar to the wiring. More preferably, nickel or gold is plated or an insulating coating is applied. When the reinforcing pattern is such a metal, it can also be used as a plating lead for electrolytic plating. Moreover, it is preferable to form the cutting position alignment mark 25 at the time of cutting with a dicer outside the block.
In this way, a semiconductor chip mounting substrate can be manufactured. In the above description, the external connection terminal 103 is formed on the first insulating layer 100. However, as shown in FIG. 6A, the external connection terminal 103 is formed on the carrier layer, and thereafter the same. It is also possible to form the first insulating layer 100.

(Semiconductor package manufacturing process)
A semiconductor package includes the semiconductor chip mounting substrate, a semiconductor chip mounted on the semiconductor chip mounting substrate, and a resin that seals at least a face surface (surface on which a semiconductor element is formed) of the semiconductor chip. Is done.
The semiconductor package of the present invention can be manufactured by the following process. An example of an embodiment of the method for manufacturing a semiconductor package of the present invention is shown in a schematic cross-sectional view in FIGS. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process e)
(Step e) is a step of mounting the semiconductor chip 111 on the semiconductor chip mounting substrate of the present invention and sealing the face surface of the semiconductor chip as shown in FIG. The semiconductor chip 111 and the semiconductor chip connection terminal are electrically connected by flip-chip connection using the connection bump 112. Further, in these semiconductor packages, it is preferable to seal between the semiconductor chip and the semiconductor chip mounting substrate with an underfill material 113 such as a thermosetting resin, as illustrated.
Furthermore, the semiconductor chip can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, there is no need for a step of sealing with an underfill material, which is efficient. Furthermore, it is more preferable to use ultrasonic waves in combination when mounting the semiconductor chip because electrical connection can be performed at a low temperature and in a short time.

(Process f)
(Step f) is a step of removing the carrier layer as shown in FIG. Although the above-mentioned method can be used as a removal method, it is preferable to further perform an adhesive strength reduction means.

(Process g)
(Step g) is a step of mounting the solder balls 114 on the external connection terminals 103 as shown in FIG. Tin-lead eutectic solder or lead-free solder is used for the solder balls. As a method for fixing the solder balls to the external connection terminals, an N ₂ reflow apparatus can be used.

Further, FIG. 6H shows a cross-sectional view of an embodiment of a wire bond type semiconductor package. A general die bond paste can be used for mounting the semiconductor chip, but it is more preferable to use a die bond film 117 as shown in FIG. The electrical connection between the semiconductor chip and the semiconductor chip connection terminal is preferably performed by wire bonding using a gold wire 115. The semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116. The sealing region may seal only a necessary portion of the semiconductor chip, but may seal the entire semiconductor package region as shown in FIG. This is a particularly effective method in the case where a semiconductor chip mounting substrate as shown in FIG. 7 in which a plurality of semiconductor package regions are arranged in rows and columns is cut simultaneously with a dicer or the like.
Finally, each semiconductor package is cut using a dicer or the like.

EXAMPLES Next, although an Example is given and this invention is demonstrated concretely, this invention is not restrict | limited to these Examples.
Example 1
(Process a)
As shown in FIG. 5 (a), a 75 μm thick polyethylene naphthalate film is prepared as the carrier layer 110, and after silicone release treatment is performed on one surface thereof, an adhesive is applied to the release treatment surface side. A polyimide adhesive N4 (manufactured by Hitachi Chemical Co., Ltd., trade name) was applied to a thickness of 10 μm as a certain first insulating layer 100, and heated and dried at 120 ° C. for 10 minutes to make it semi-cured. The surface roughness of the insulating layer was Ra = 0.1 μm.
Next, a direct 0.35 mm opening 107 was formed using a drill at a position where the carrier layer 110 and the external connection terminal of the first insulating layer were formed.

(Process b)
As shown in FIG. 5 (b), a copper foil having a thickness of 18 μm is layered on the first insulating layer, heated and pressurized at 250 ° C. under the condition of 2 MPa, and held for 60 minutes so that lamination is integrated and unnecessary. A portion of the copper foil was removed by etching to form the first wiring 101.

(Process c)
As shown in FIG. 5C, the first wiring surface was treated with a silane coupling agent to form a film (not shown) containing the silane coupling agent on the wiring surface. At this time, the roughness of the wiring surface was Ra = 0.15 μm. After that, the second insulating layer 102 was formed in the same manner as in (Step a), and heat treatment was performed at 250 ° C. for 60 minutes to completely cure N4. Next, a hole having a diameter of 50 μm was formed with a laser until the first wiring 101 was reached from the surface of the second insulating layer. YAG laser LAVIA-UV2000 (trade name, manufactured by Sumitomo Heavy Industries, Ltd.) is used as the laser, under the conditions of frequency 4 KHz, number of shots 20, mask diameter 0.4 mm, and vacuum plasma treatment as desmear treatment inside the aperture. Went. The gas used is a mixed gas of oxygen and freon.
Next, in order to form the second wiring 104 and the connection conductor 105 (blind via), a base metal Ni layer 20 nm and a thin film copper layer 200 nm, which become a power feeding layer, were formed by sputtering. Sputtering was performed under the conditions shown below using MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.
〔conditions〕
(nickel)
Current: 5.0A
Current: 350V
Voltage argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 0.3 nm / second (copper)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

Next, a 20 μm-thick resist layer was formed by a spin coating method using a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Exposure was performed at 1000 mJ / cm ² , and immersion rocking was performed at 23 ° C. for 6 minutes using PMER developer P-7G to form a resist pattern of L / S = 10 μm / 10 μm. Then, pattern copper plating was performed about 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. For quick etching of the copper sputtered film (seed layer), a 5-fold diluted solution of CPE-700 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.) is used to remove it by immersing and shaking at 30 ° C. for 30 seconds. Then, the second wiring 104 and the connection conductor 105 were formed.

(Process d)
As shown in FIG. 5D, a solder resist is formed as an insulation coating 106 on the second insulating layer 102 and the second wiring 104, excluding the semiconductor chip connection terminals, and FIG. A fan-in type BGA semiconductor chip mounting substrate as shown in FIG. 3 (plan view of one package) and FIG. 7 (overall view of the semiconductor chip mounting substrate) was produced.

(Process e)
As shown in FIG. 5E, the semiconductor chip 111 having the connection bumps 112 formed in the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above-described (steps a) to (d) is flip-chiped. A required number of ultrasonic waves were applied using a bonder. Further, an underfill material 113 is injected from the end of the semiconductor chip into the gap between the semiconductor chip mounting substrate and the semiconductor chip, and primary curing is performed at 80 ° C. for 1 hour and secondary curing at 150 ° C. for 4 hours using an oven. Went.

(Process f)
As shown in FIG. 5 (f), the moisture absorption treatment at 85 ° C./85% RH was performed for 24 hours as a means for reducing the adhesive strength, and then the carrier layer 110 was mechanically peeled off. The adhesive force between the carrier layer and the first insulating layer after the moisture absorption treatment was 100 N / m.

(Process g)
As shown in FIG. 5G, a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm was fused to the external connection terminal 103 with an N ₂ reflow apparatus. Finally, the semiconductor chip mounting substrate was cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG. The thickness of the semiconductor package was 0.8 mm.

Example 2
(Process a)
As shown in FIG. 6A, a glass cloth-containing polyphenylene sulfide film having a thickness of 100 μm was prepared as the carrier layer 110, and a copper foil was formed on one side. Next, unnecessary portions of the copper foil were etched to form an external connection terminal 103 having a diameter of 0.35 mm. Further, an opening 107 reaching the external connection terminal was formed in the carrier layer 110 using a laser.

(Process b)
As shown in FIG. 6B, a copper bump having a height of 12 μm was formed as the first connection conductor 108 on the external connection terminal 103. Next, the first insulating layer 100 was formed on the carrier layer 110 on the side where the external connection terminals were formed as follows. That is, using an insulating resin material FTF (trade name, manufactured by Hitachi Chemical Co., Ltd.), an insulating layer having a thickness of 15 μm is formed by spin coating at 1700 rpm, and 50 ° C., 15 minutes, 100 ° C., 15 minutes. The first insulating layer 100 was formed by sequentially heating and curing at 150 ° C. for 15 minutes, 200 ° C. for 60 minutes. Then, it grind | polished until the 1st insulating layer 100 became about 10 micrometers, and exposed the 1st copper bump on the surface. At this time, the surface roughness of the first insulating layer 100 was Ra = 0.08 μm.

(Process c)
As shown in FIG. 6C, in order to form the first wiring 101, a nickel layer 20 nm and a thin film copper layer 200 nm were formed by sputtering as an adhesive metal to be a power feeding layer. Sputtering was performed under the conditions shown below using MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.
〔conditions〕
(nickel)
Current: 5.0A
Current: 350V
Voltage argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 0.3 nm / second (copper)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

Next, a 20 μm-thick resist layer was formed by a spin coating method using a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Exposure was performed at 1000 mJ / cm ² , and immersion rocking was performed at 23 ° C. for 6 minutes using PMER developer P-7G to form a resist pattern of L / S = 10 μm / 10 μm. Then, pattern copper plating was performed about 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. For quick etching of the copper sputtered film (seed layer), a 5-fold diluted solution of CPE-700 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.) is used to remove it by immersing and shaking at 30 ° C. for 30 seconds. A first wiring was formed.

(Process d)
As shown in FIG. 6D, after the second copper bump 109 having a diameter of 50 μm and a height of 12 μm is formed by plating as the second connection conductor in the same manner as in (Step b), the first wiring 101 is formed. The surface was treated with a silane coupling agent to form a film (not shown) containing the silane coupling agent on the wiring surface. Next, approximately 10 μm of the second insulating layer 102 was formed in the same manner as in (Step b), and the second copper bumps were exposed on the surface. Further, the second wiring 104 was formed in the same manner as in (Step c).

(Process e)
As shown in FIG. 6E, a solder resist 106 is formed as an insulating coating on the second insulating layer 102 and the second wiring 104, excluding the semiconductor chip connection terminals, and FIG. A fan-in type BGA semiconductor chip mounting substrate as shown in FIG. 3 (plan view of one package) and FIG. 7 (overall view of the semiconductor chip mounting substrate) was produced.

(Process f)
As shown in FIG. 6 (f), a die bond film DF-100 (manufactured by Hitachi Chemical Co., Ltd., a product) is formed on the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above (steps a) to (step e). Name) A required number of semiconductor chips 111 temporarily bonded with 117 were mounted. At this time, the die bond film 117 was still kept in a semi-cured state. Next, using a wire bonder UTC230 (trade name, manufactured by Shinkawa Co., Ltd.), a terminal on the semiconductor chip and a semiconductor chip connection terminal of the semiconductor chip mounting substrate were electrically connected by a gold wire 115 having a diameter of 25 μm. Furthermore, using CEL9200 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a sealing resin 116, the semiconductor chip is integrated into one block 23 shown in FIG. 7 at a pressure of 10 MPa, a temperature of 180 ° C., and a time of 90 seconds. Transfer molded. Next, heat treatment was performed in an oven at a temperature of 180 ° C. for 5 hours to completely cure the sealing resin 116 and the die bond film 117.

(Process g)
As shown in FIG. 6G, after the moisture absorption treatment at 85 ° C./85% RH was performed for 24 hours as a means for reducing the adhesive strength, the carrier layer 110 was mechanically peeled off. The adhesive force between the carrier layer after the moisture absorption treatment and the first adhesive was 200 N / m.

(Process h)
As shown in FIG. 6 (h), a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm was fused to the external connection terminal 103 with an N ₂ reflow apparatus. Finally, the sealing resin and the semiconductor chip mounting substrate were simultaneously cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG. The thickness of the semiconductor package was 1.2 mm.

Comparative Example As shown in FIG. 8, a glass cloth epoxy resin substrate having a thickness of 0.4 mm is used as the core substrate 130, and two insulating layers and wirings are provided on the surface opposite to the semiconductor chip mounting surface of the glass cloth epoxy resin substrate. A semiconductor chip mounting substrate provided with a layer was produced. Thereafter, a fan-in type BGA semiconductor package was produced in the same manner as in (Step e) and (Step g) of Example 1. The thickness of the semiconductor package was 1.5 mm.

The following tests were performed on each semiconductor package manufactured as described above.
Semiconductor package reliability test:
After each semiconductor package sample was subjected to moisture absorption treatment, 22 samples were reflowed in a reflow oven with an ultimate temperature of 240 ° C. and a length of 2 m at a rate of 0.5 m / min, and the occurrence of cracks was examined. . The number of cracks that occurred after reflow was taken as the NG number, and the results are shown in Table 1. Similarly, several 22 semiconductor packages were mounted on a 0.8 mm thick mother board, and a temperature cycle test was performed at −55 to 125 ° C. for 30 minutes each to examine the connection reliability of the solder balls. The number of connection failures after the temperature cycle test was defined as the number of NG after the temperature cycle test, and the results are shown in Table 2.

Examples 1 and 2 using the semiconductor chip mounting substrate manufactured by the manufacturing method of the semiconductor chip mounting substrate of the present invention are excellent in connection reliability by the reflow test and the temperature cycle test. On the other hand, the comparative example which does not depend on the manufacturing method of this invention is inferior to connection reliability. As described above, according to the present invention, it is possible to provide a thin semiconductor package that can be mounted at a high density and has excellent reliability such as temperature cycleability, a semiconductor chip mounting substrate used therefor, and a manufacturing method thereof.
Further, it is possible to provide a semiconductor chip mounting substrate and a semiconductor package that can form fine wiring with high accuracy and efficiently transmit high-speed electrical signals.

1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. Sectional drawing of the semiconductor chip mounting substrate to which another embodiment of this invention is applied. The top view of the fan-in type semiconductor chip mounting substrate which is one Embodiment of this invention. The top view of the fan-out type semiconductor chip mounting substrate which is another embodiment of this invention. (A)-(g) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention, and a semiconductor package. (A)-(h) is process drawing which shows another embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention, and a semiconductor package. (A) is the whole top view showing an example of the frame-shaped semiconductor chip mounting board | substrate of this invention, (b) is an enlarged view of the broken-line part of (a). Sectional drawing of the flip chip type semiconductor package using the conventional semiconductor chip mounting substrate.

Explanation of symbols

11 Guide hole for alignment 13 Semiconductor package area 14 Die bond film adhesion area (flip chip type)
15 Semiconductor chip mounting area (flip chip type)
16 Semiconductor chip connection terminal 17 Die bond film adhesion area (wire bond type)
18 Semiconductor chip mounting area (wire bond type)
DESCRIPTION OF SYMBOLS 19 External connection terminal 20 Expanded wiring 21 Dummy pattern 22 Semiconductor chip mounting substrate 23 Block 24 Reinforcement pattern 25 Cutting alignment mark 100 1st insulating layer 101 1st wiring 102 2nd insulating layer 103 External connection terminal 104 2nd Wiring 105 Connection conductor (blind via)
106 Insulation coating (solder resist)
107 opening 108 first connecting conductor (metal bump)
109 Second connection conductor (metal bump)
110 Carrier layer 111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Sealing resin 117 Die bond film 130 Core substrate

Claims (18)

A semiconductor chip mounting substrate which many semiconductor chips are mounted on one surface, and the carrier layer, and two or more layers Ru formed on one surface of the insulating layer of the carrier layer, is formed on the insulating layer a plurality of wirings that are composed of connecting conductors for electrically connecting said that Ru formed in different layers wiring, wherein the outermost layer of the wiring Ru is formed in a layer closer to the semiconductor chip connection terminals, most carrier layer An external connection terminal is formed in the wiring, and an opening reaching the external connection terminal is formed in the carrier layer where the external connection terminal is formed and an insulating layer immediately above the carrier layer. A semiconductor chip mounting substrate, which is removed at least after the semiconductor chip is mounted.   A semiconductor chip mounting substrate on which a large number of semiconductor chips are mounted on one surface, a carrier layer, two or more insulating layers formed on one surface of the carrier layer, and the insulating layer of the carrier layer Between the plurality of external connection terminals formed on the surface on the side of forming the wiring, the plurality of wirings formed on the insulating layer, and between the external connection terminals and the wirings or between the wirings formed in different layers. A semiconductor chip connection terminal is formed in the wiring on the outermost layer, and an opening reaching the external connection terminal is formed in the carrier layer where the external connection terminal is formed. The carrier layer is removed at least after the semiconductor chip is mounted. Semiconductor chip mounting board according to claim 1 or claim 2 removal of the carrier layer is mechanically peeled. The semiconductor chip mounting substrate according to claim 3 , wherein an adhesive force between the insulating layer and the carrier layer is 10 to 500 N / m. Semiconductor chip mounting board according to any one of claims 1 to 4 further thickness of the insulating layer is 1 to 50 [mu] m. Semiconductor chip mounting board according to any one of claims 1 to 5 the thickness of the carrier layer is 30 to 500 m. Semiconductor chip mounting board according to any one of claims 1 to 6 wherein the carrier layer is an insulating film. A material of the carrier layer is a resin containing at least one or more of an imide group, an amide group, a phenol group, a phenylene group, an ester group, an ether group, a sulfone group, a carbonate group, a carbonyl group, or a silicone bond, or a liquid crystal polymer or a fluorine-containing material resin, the semiconductor chip mounting board according to any one of claims 1 to 7 is any one of epoxy resin.   The semiconductor chip mounting substrate according to claim 1, wherein a material of the carrier layer is a metal. A plurality of insulating layers and a carrier layer Ru are formed on one surface of a method for manufacturing a semiconductor chip mounting substrate which many semiconductor chips are mounted on the surface to form the insulating layer, one of said carrier layer Forming a first insulating layer on the surface, forming an opening in the carrier layer and the first insulating layer at a location to be an external connection terminal, and the external connection on the first insulating layer Forming a first wiring including a terminal; forming a second insulating layer on the first insulating layer and the first wiring; and a second wiring on the second insulating layer. Forming a connection conductor that electrically connects the first wiring and the second wiring, forming a semiconductor chip connection terminal on the outermost layer wiring, and the external connection terminal At least Knitting wherein the exposed portion of the outermost layer of wiring and Le and consists step of performing gold plating, wherein the carrier layer manufacturing method of the semiconductor chip mounting board comprising a step of removing at least the semiconductor chip after mounting. A plurality of insulating layers and a carrier layer Ru are formed on one surface of a method for manufacturing a semiconductor chip mounting substrate which many semiconductor chips are mounted on the surface to form the insulating layer, one of said carrier layer forming a step of forming external connection terminals on the surface, forming an opening reaching the external connection terminal to the carrier layer, a first insulating layer on the surface forming the external connection pin of the carrier layer of A step of forming a first wiring on the first insulating layer, a step of forming a first connection conductor for electrically connecting the external connection terminal and the first wiring, A step of forming a second insulating layer on the first insulating layer and the first wiring; a step of forming a second wiring on the second insulating layer; the first wiring and the first wiring; A process for forming a second connection conductor for electrically connecting the two wires If, consists step of applying and forming a semiconductor chip connection terminals outermost wiring, at least nickel and gold plating on the exposed portion of the external connection terminal and the outermost layer of wires, the carrier layer is at least the A method for manufacturing a semiconductor chip mounting substrate, comprising a step of removing the semiconductor chip after mounting. A step of mounting the semiconductor chip on the semiconductor chip mounting substrate obtained by the process according to the semiconductor chip mounting substrate or claim 10 or claim 11, according to any one of claims 1 to 9, wherein the semiconductor A step of electrically connecting the semiconductor chip connection terminal of the chip mounting substrate and the semiconductor chip, a step of sealing at least a necessary portion of the semiconductor chip with a sealing resin, and the carrier layer of the semiconductor chip mounting substrate And a step of forming an external connection bump on the external connection terminal of the semiconductor chip mounting substrate. The removal of the carrier layer, a method of manufacturing a semiconductor package according to claim 1 2, comprising a step of performing a mechanical peeling. Before performing the mechanical peeling method of manufacturing a semiconductor package according to claim 1 3, comprising a step of performing a means of reducing the adhesive strength of the insulating layer and the carrier layer. The semiconductor chip is mounted using die-bonding film, a manufacturing method of a semiconductor package according to any one of claims 1 2 to claims 1 to 4, wherein the die-bonding film has a step of performing the resin sealing in a semi-cured state . The semiconductor chip connecting terminal and the method for manufacturing a semiconductor package according to any one of claims 1 2 to claims 1 to 5, comprising the step to be done by wire bonding the electrical connections of the semiconductor chip of the semiconductor chip mounting substrate. A step of simultaneously sealing a large number of the semiconductor chips with the sealing resin integrally connected; and a step of simultaneously cutting the integrated sealing resin and the insulating layer of the semiconductor chip mounting substrate with a dicer. the method of manufacturing a semiconductor package according to any one of claims 1 2 to claims 1 to 6. The method for manufacturing a semiconductor package according to claim 17 , further comprising a step of cutting the insulating resin and the insulating layer of the semiconductor chip mounting substrate after forming the external connection bumps.

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