JP4194473B2 - Memory controller and flash memory system including the memory controller - Google Patents

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  In recent years, a flash memory is often used as a semiconductor memory used in a memory system such as a memory card or a silicon disk. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.

  By the way, the NAND flash memory that is often used in the above-described devices is used when a memory cell is changed from an erased state (logical value “1”) to a written state (logical value “0”). Can be performed in units of memory cells. However, when a memory cell is changed from a written state (logical value “0”) to an erased state (logical value “1”), it must be performed in memory cells. This can only be done with a predetermined erase unit (block) consisting of a plurality of memory cells. Such a batch erase operation is generally called block erase.

  Therefore, when data is rewritten in the NAND flash memory, new data (data after rewriting) is written to the erased block which has been erased, and old data (data before rewriting) is written. The process of erasing the written block must be performed. When rewriting data in this way, the data after rewriting is written in a different block from before rewriting, so the logical block address given from the host system side and the physical block address that is the block address in the flash memory The correspondence between and changes dynamically every time data is rewritten. For this reason, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required.

  If this address conversion table is created for all blocks in the flash memory, the size of the address conversion table increases with the increase in the capacity of the flash memory. The time burden increases. In order to solve this problem, in Patent Document 1 (Japanese Patent Laid-Open No. 2000-284996), the flash memory is divided into a plurality of zones, and an address conversion table is created for the blocks allocated to each zone.

In addition, in the flash memory system adopting the above-described zone, in consideration of the occurrence of a defective block, the block constituting the zone is extra for the host system side data area (data area corresponding to the logical block address in a specific range). Assigned.
JP 2000-284996 A

When a zone is configured with a plurality of blocks in the flash memory as described above, if the number of spare blocks (an extra allocated block in consideration of the occurrence of a bad block) allocated to each zone is increased, The ratio of spare blocks increases and the data area on the host system side that can be covered by the flash memory of the same capacity becomes narrower (hereinafter, the width of the data area on the host system side that can be covered by the flash memory of the same capacity is called usage efficiency). ). On the other hand, if the number of spare blocks allocated to each zone is reduced, the use efficiency of the flash memory is improved, but the allowable amount for the generation of defective blocks (the allowable number of defective blocks generated) decreases.

  Accordingly, an object of the present invention is to provide a memory controller and a flash memory system including the memory controller that can improve the tolerance for the occurrence of a defective block without reducing the use efficiency of the flash memory.

An object of the present invention is to provide an allocation management function for managing the correspondence between a zone composed of a plurality of blocks in a flash memory and a logical block address space on the host system side allocated to the zone, and to control access to the zone. Access control function to
This is achieved by a memory controller comprising a zone configuration function that configures the zone such that a plurality of blocks belonging to the zone exist.

  The object of the present invention is also achieved by a flash memory system comprising the memory controller and a flash memory.

  Here, “there are blocks belonging to a plurality of zones” means that there are blocks belonging to two or more zones, and the blocks are shared blocks shared by two or more zones. Means.

  According to the present invention, it is preferable that the zone configuration function configures the zone such that there are blocks belonging to two zones.

  Here, “there are blocks belonging to two zones” means that there are shared blocks shared by the two zones.

  According to the present invention, it is preferable that the zone configuration function configures the zone such that a block belonging to any one of the zones and the other two zones exists.

  Here, “a block belonging to any one of the zones and the other two zones exists” means that the first zone, the second zone, and the third zone This means that there is a block shared by the second zone and the second zone, and a block shared by the first zone and the third zone. That is, it means that the first zone includes a block shared with the second zone and a block shared with the third zone.

  In addition, according to the present invention, it is preferable to provide a conversion table creating means for creating an address conversion table for each zone.

  In addition, according to the present invention, it is preferable that a candidate table creating means for creating a candidate table for each zone is provided.

  According to the present invention, since a shared block (a block shared by a plurality of zones) exists in a zone configured by a plurality of blocks of the flash memory, this shared block is a zone where a large number of bad blocks are generated. However, if it is used preferentially, it is possible to improve the tolerance for the occurrence of defective blocks while suppressing a decrease in the usage efficiency of the flash memory.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2. The flash memory system 1 is normally used by being detachably attached to the host system 4, and is used as a kind of external storage device for the host system 4.

  Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block is composed of 32 pages, and one page is a 512-byte user area and a 16-byte redundant area. It is configured.

  The controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, And a flash memory sequencer block 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.

  The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

  The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in this state, the host system 4 connects to the flash memory system 1. The supplied data is taken into the controller 3 through the host interface block 7 as an entrance, and the data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit. Is done.

  Further, the host interface block 7 includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host system 4 and an error register (not shown) set when an error occurs. ) Etc.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block configured by a plurality of SRAM (Static Random Access Memory) cells.

The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 becomes writable. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, and internal command information with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code added to the data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data. It is a block.

[Description of memory cell]
Next, a specific structure of the memory cell 16 constituting the flash memory 2 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed over type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed. A plurality of memory cells 16 having such a configuration are connected in series in the flash memory.

  The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.

  In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 In the meantime, no channel is formed on the surface of the P-type semiconductor substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage (high level voltage) is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. The source diffusion region 18 and the drain diffusion region 19 are electrically connected by this channel.

That is, in the “erased state”, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the control gate electrode 23 In the state where the read voltage (high level voltage) is applied, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.

  FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23, A channel 24 is formed on the surface of the P-type semiconductor substrate 17 between the drain diffusion region 19. Therefore, in the “written state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23. Will be connected.

  Whether the memory cell 16 is in an erased state or a written state can be read as follows. A plurality of memory cells 16 are connected in series in the flash memory. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if the serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.

  When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when changing the flash memory cell 16 in the written state to the erased state, a high voltage is applied to the control gate electrode 23 on the low potential side, and the voltage is stored in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.

[Description of flash memory structure]
Next, the memory structure of the flash memory will be described. FIG. 4 schematically shows a memory structure of the flash memory. As shown in FIG. 4, the flash memory is composed of pages, which are processing units for reading and writing data, and blocks, which are data erasing units.

  The page is composed of, for example, a user area 25 of 512 bytes and a redundant area 26 of 16 bytes. The user area 25 is an area for mainly storing data supplied from the host system 4, and the redundant area 26 is an area for storing additional information such as an error collection code, a corresponding logical block address and a block status. is there.

  The error collection code is additional information for correcting an error included in the data stored in the user area 25, and is generated by an ECC block. Based on the error collection code, if the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined number, the error is corrected.

The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. Judgment can be made. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block.

  The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

[Description of logical block address and physical block address]
Since data cannot be overwritten in the flash memory, when rewriting data, new data (data after rewriting) is written to the erased block that has been erased, and old data (data before rewriting). The process of erasing the block in which "." Has been written must be performed. At this time, since erasure is processed in units of blocks, data of all pages of a block including a page in which old data (data before rewriting) is written is erased. Therefore, when data is rewritten, it is necessary to perform processing for moving the data of other pages of the block including the page to be rewritten to the erased block.

  When rewriting data as described above, since the data after rewriting is written in a different block from before rewriting, the logical block address given from the host system side and the physical block which is the block address in the flash memory The correspondence with the address changes dynamically every time data is rewritten. For this reason, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required. This address conversion table is created based on the corresponding logical block address written in the redundant area of the flash memory, and each time the data is rewritten, the correspondence relationship of the part involved in the rewriting is updated.

[Description of zone configuration]
Next, zone management for assigning a zone composed of a plurality of blocks in the flash memory to a logical block address space will be described with reference to the drawings. FIG. 5 shows an example in which a zone is composed of 512 blocks. In the example shown in FIG. 5, the zone is composed of 512 blocks B0000 to B0511 (physical block addresses 0000 to 0511), and each block is composed of 32 pages P00 to P31 which are units of read and write processing. Has been. Here, the block is a unit of erasing processing, and the page is a unit of reading and writing processing.

  When this zone is assigned to a logical block address space, it is assigned to a logical block address space having a smaller number of blocks than the number of blocks constituting the zone in consideration of the occurrence of a defective block. This allocation is normally performed according to the specifications of the flash memory. For example, a zone composed of 512 blocks is allocated to a logical block address space of 500 blocks, or a logical block address of 490 blocks is allocated. Can be assigned to space. At this time, if the number of blocks allocated to the space of the logical block address is increased, the use efficiency of the flash memory is improved, but the allowable amount for the generation of defective blocks (the allowable number of defective blocks generated) is reduced. For example, when a zone composed of 512 blocks is allocated to a space of logical block addresses for 500 blocks and a case of allocation to a space of logical block addresses for 490 blocks, the usage efficiency of flash memory is However, the allocation to the space of the logical block address for 500 blocks is better, but the tolerance for the occurrence of the defective block is larger in the case of the allocation to the space of the logical block address for 490 blocks.

In the flash memory system according to the present invention, the blocks constituting the zone are shared by two zones (hereinafter, the blocks shared by a plurality of zones are referred to as shared blocks). The block sharing between the zones will be described with reference to the drawings. FIG. 6 shows an example of a zone configuration in the flash memory system according to the present invention. Here, each zone is composed of 512 blocks, and these zones are assigned to a logical block address space of 496 blocks. Each zone shares 16 blocks with other zones.

  For example, in zone 0, blocks B0000 to B0007 (physical block addresses 0000 to 0007) are shared with zone N, and blocks B0504 to B0511 (physical block addresses 0504 to 0511) are shared with zone 1. In zone 1, blocks B0504 to B0511 (physical block addresses 0504 to 0511) are shared with zone 0, and blocks B1008 to B1015 (physical block addresses 1008 to 1015) are shared with zone 2. In zone 2, blocks B1008 to B1015 (physical block addresses 1008 to 1015) are shared with zone 1, and blocks B1512 to B1519 (physical block addresses 1512 to 1519) are shared with zone 3. In zone 3, blocks B1512 to B1519 (physical block addresses 1512 to 1519) are shared with zone 2, and blocks B2016 to B2023 (physical block addresses 2016 to 2023) are shared with zone 4. Similarly for the subsequent zones, each zone shares eight blocks with the other two zones.

  When a zone is configured in this way, the generation of a maximum of 16 defective blocks can be allowed for a zone that occupies all shared blocks. However, if new data is once written in another block at the time of data rewriting and then the block where the old data has been written is erased, a spare block for writing new data is necessary. Up to 15 blocks can be made. Further, the usage efficiency of the flash memory is the same as when a zone composed of 504 blocks is allocated to a logical block address space of 496 blocks. Therefore, it is possible to improve the tolerance for the occurrence of defective blocks while suppressing a decrease in the usage efficiency of the flash memory.

  Note that the number (or ratio) of blocks to be used as shared blocks is preferably set as appropriate according to the specifications of the flash memory and the number of blocks constituting the zone. Further, the number of blocks in each zone and the number of shared blocks included in each zone may be different for each zone. Further, the number of shared blocks may be increased or decreased according to the number of defective blocks generated.

[Description of address translation table]
Next, the address conversion table will be described with reference to the drawings. FIG. 7 shows an example of the address conversion table for zone 0 shown in FIG. 6, and the physical block address in the flash memory in which data corresponding to each logical block address is stored is the logical block address. It is described in order. That is, the correspondence between the logical block address and physical block address assigned to each subzone is described in the order of logical block addresses. For a logical block address in which no data is stored in the flash memory, a flag indicating that no data is stored in the portion corresponding to the logical block address of the address conversion table (not a physical block address) A flag indicating that the corresponding data is not stored is referred to as an unstored flag).

For example, when the address conversion table for zone 0 shown in FIG. 6 is created, an area in which physical block addresses for 496 blocks can be described is secured on the SRAM, and the initial setting is not stored in the area for describing the physical block addresses. Set the flag. Thereafter, the redundant areas of the blocks constituting the zone 0 are sequentially read out, and when the logical block address (the logical block address described as the corresponding logical block address) is described in the redundant area, the address conversion table In the portion corresponding to the logical block address, the physical block address of the block in which the logical block address is described is described.

  Here, since zone 0 shares blocks B0000 to B0007 (physical block addresses 0000 to 0007) with zone N and blocks B0504 to B0511 (physical block addresses 0504 to 0511) with zone 1, A block shared with zone N may store data of a logical block address assigned to zone N, and a block shared with zone 1 is assigned to zone 1 In some cases, data of a logical block address is stored. Accordingly, when the logical block address described in the redundant area is a logical block address assigned to zone N or zone 1, the physical block address is not described in the zone 0 address conversion table. In other words, when the logical block address described in the redundant area is the logical block address assigned to zone 0, the logical block address in the portion corresponding to the logical block address in the zone 0 address conversion table Describes the physical block address of the block in which is described.

  Note that the unstored flag described in the initial setting remains as it is in the portion where the physical block address is not described in the address conversion table creation processing.

[Description of erased block search table and candidate table]
Next, the erased block search table and candidate table will be described with reference to the drawings. The candidate table is a table in which erased blocks prepared as data write destinations (hereinafter, erased blocks prepared as data write destinations are referred to as write candidate blocks) are set in each zone. Created every time. The erased block search table is a table for searching for erased blocks set as candidate write blocks in the candidate table.

  First, a method for searching for an erased block using the erased block search table will be described. For example, when searching the erased block in the zone shown in FIG. 6, a 512-bit area is secured on the SRAM, and an erased block search table in which each block constituting the zone is assigned to each bit of the area is stored. create. However, when the blocks are shared among the zones as in the zone shown in FIG. 6, it is preferable to share the bits corresponding to the shared blocks on the erased block search table.

  FIG. 8 is a conceptual diagram conceptually showing the erased block search table for zones 0 to 2 shown in FIG. Here, the bits on the erased block search table for zone 0 correspond to blocks B0000 to B0511 (physical block addresses 0000 to 0511), and the bits on the erased block search table for zone 1 correspond to block B0504. Correspond to .about.B1015 (physical block addresses 0504 to 1015), and the bits on the erased block search table for zone 2 correspond to blocks B1008 to B1519 (physical block addresses 1008 to 1519). Therefore, the bits corresponding to the blocks B0000 to B0007 (physical block addresses 0000 to 0007) on the erased block search table are shared by the zone 0 and the zone N erased block search tables, and the blocks B0504 to B0511 ( Bits corresponding to physical block addresses 0504 to 0511) are shared by the zone 0 and zone 1 erased block search tables, and bits corresponding to blocks B1008 to B1015 (physical block addresses 1008 to 1015) are 1 and zone 2 erased block search tables are shared, and bits corresponding to blocks B1512 to B1519 (physical block addresses 1512 to 1519) are shared by zone 2 and zone 3 erased block search tables.

For the correspondence between the bits on the erased block search table and the blocks constituting the zone, the bits on the erased block search table shown in FIG. 8 are changed from the upper row to the lower row. Each row is associated from left to right in the order of physical block addresses. Therefore, in the erased block search table for zone 0, the upper left bit corresponds to the block B0000 (physical block address 0000) and the lower right bit corresponds to the block B0511 (physical block address 0511). To do.

  The bits on the erased block search table indicate whether the block is an erased block by “0” and “1”. For example, when data is written (or a defective block) Is set to “0” in the bit, and “1” is set in the bit when data is not written (in the case of an erased block). The erased block search table can be created together with the address conversion table. For example, “0” is set in the SRAM area for creating the erased block search table, and the corresponding logical block address is not described in the redundant area of each block and the block status indicating that it is a bad block is not described. Sometimes, if the bit corresponding to the block is set to “1”, the address conversion table can be created together. In other words, if this process is performed when the data described in the redundant area of the blocks constituting the zone is read out, only “1” is set to the bit corresponding to the erased block, and this corresponds to the block that is not the erased block. The bit to be maintained remains “0” set in advance.

  For updating the erased block search table, when data is written to the erased block, the bit corresponding to the block is changed from “1” to “0” and the data is written. When a block is erased, the bit corresponding to that block is changed from “0” to “1”.

  Next, a case where an erased block is searched using this erased block search table will be described with reference to FIG. FIG. 9 shows the erased block search table for zone 0, with each bit in the top row corresponding to blocks B0000 to B0007 (physical block addresses 0000 to 0007) shared with zone N. The bottom row corresponds to blocks B 0504 to B 0511 (physical block addresses 0504 to 0511) shared with zone 1. Each bit in the portion excluding the top row and the bottom row corresponds to blocks B0008 to B0503 (physical block addresses 0008 to 0503) used only by zone 0.

  For example, if you want to preferentially use blocks B0008 to B0503 (physical block addresses 0008 to 0503) used only by zone 0, erased data using the portion excluding the top row and the bottom row. Search for a block. That is, from the bit corresponding to the block B0008 (physical block address 0008) (the leftmost bit in the second row from the top) to the bit corresponding to the block B0503 (physical block address 0503) (the second from the bottom) To the rightmost bit in the row) and search for a bit of “1” corresponding to the erased block. The scanning is performed from the upper row to the lower row and from the left to the right in each row.

In the erased block search table shown in FIG. 9, when scanning is started from the leftmost bit in the second row from the top, the third bit from the left in the second row from the top is “1”. Therefore, the search ends here, and the block B0010 (physical block address 0010) corresponding to this bit is set in the candidate table as a write candidate block. In the next search, scanning starts from the fourth bit from the left in the second row from the top, and the fifth bit from the left in the fourth row from the top is “1”. And block B0028 (physical block address 0028) corresponding to this bit is set in the candidate table as a write candidate block. Thereafter, such a search is continued, and when the scanning proceeds to the rightmost bit in the second row from the bottom, the processing returns to the leftmost bit in the second row from the top. When all the bits except for the top row and the bottom row are all “0”, that is, in blocks B0008 to B0503 (physical block addresses 0008 to 0503) used only by zone 0. If there is no erased block, the top or bottom row, which is a bit corresponding to a block shared with zone N or zone 1, is scanned.

  In the above description, blocks that are not shared with other zones are used preferentially, but all zones are used in the same way regardless of whether they are shared blocks or not. Also good. In addition, it is preferable to use the shared block preferentially in a zone where a large number of bad blocks are generated.

  Next, a candidate table for setting erased blocks detected by the above search as write candidate blocks will be described. FIG. 10 is a diagram showing data items in the candidate table. In this candidate table, a block number, a check request flag, an error detection flag, and a check start page are set as data items.

  Here, the physical block address of the erased block detected by the search is set in the block number setting unit. In addition, when data is written to the write candidate block set in the candidate table, the block number setting part displays “unset flag (for example, whether the block address is valid or invalid in the block number setting part). If the bit indicates invalid, this bit is set as an unset flag, and when a block address is set in the block number setting part, this bit is set valid.) Set. In the check request flag setting section, the presence / absence of a check request is set, that is, the “present flag” is set before the check is completed, and the “absence flag” is set after the check is completed. In the error detection flag setting section, an “OK flag” is set when no error is detected in an erase state check described later, and an “NG flag” is set when an error is detected. In the check start page setting section, a page for continuing the processing after canceling the interruption when an erase state check to be described later is interrupted is set. In addition, when data is written in the write candidate block set in the candidate table, the “unset flag” is set in the setting part of the block number, check request flag and error detection flag, and the check start page setting part Set “0” to.

  In the write candidate block set in this candidate table, the erase state is checked before data is written. In this erasure check, it is checked whether all the data of each page of the block set in the block number setting part of the candidate table is in the erasure state (logical value “1”), and all the bits are erased. If it is in the state (logical value “1”), if the “OK flag” is in the error detection flag setting part and the bit is in the write state (logical value “0”), the error detection flag setting part "NG flag" is set in

  For example, as shown in FIG. 10A during initialization, “unset flag” is set in the setting part of the block number, check request flag and error detection flag, and “0” is set in the setting part of the check start page. . Next, an erased block is searched, and if the block address is B0010, B0010 is set in the block number setting section, and “present flag” is set in the check request flag setting section (FIG. 10B). ).

Thereafter, the check of the erased state is executed, and when the processing is interrupted when the check is finished up to the 14th page, “15” is set in the check start page (FIG. 10C). Thereafter, the check of the erasure state is resumed, and when all the 32 pages have been normally erased when the processing is completed, as shown in FIG. “None flag” and “OK flag” in the error detection flag setting section. On the other hand, when a page that has not been normally erased is detected, as shown in FIG. 10E, the “none flag” is set in the check request flag setting section and “NG” is set in the error detection flag setting section. Set the flag.

[Description of read processing and write processing]
When reading data stored in the flash memory in response to a request from the host system side, the logical block address given from the host system side is based on the physical block address (logical block address) based on the address conversion table shown in FIG. To the physical block address of the block in which the data corresponding to is stored. Subsequently, the following read processing is set in the register of the flash memory sequencer block.
1) An internal read command is set in a predetermined register in the flash memory sequencer block as an internal command.
2) The address of the page in the block in which the data corresponding to the logical block address given from the host system side is stored is set in a predetermined register in the flash memory sequencer block. Here, the address of the page is given by adding 5 bits (bits for identifying 32 pages) corresponding to the page number to the physical block address.

  Thereafter, the flash memory sequencer block executes the process based on the setting of the read process. When this process is executed, command information, address information, and the like for executing an internal read command are supplied from the flash memory interface block to the flash memory via the internal bus. Based on these pieces of information, data stored in a page in a block in which data corresponding to a logical block address given from the host system side is stored is read out to a buffer via the internal bus.

Further, when data is written to the flash memory in response to a request from the host system side, data writing processing is performed on the write candidate block set in the candidate table shown in FIG. In this write process, the following write process is set in the register of the flash memory sequencer block.
1) An internal write command is set in a predetermined register in the flash memory sequencer block as an internal command.
2) The address of the page in the write candidate block set in the candidate table is set in a predetermined register in the flash memory sequencer block.

  Thereafter, the flash memory sequencer block executes processing based on the setting of the write processing. When this process is executed, command information and address information for executing an internal write command are supplied from the flash memory interface block to the flash memory via the internal bus. The write data held in the buffer is also supplied to the flash memory via the internal bus, and is written to the page in the write candidate block set in the candidate table.

If there is old data corresponding to the logical block address supplied from the host system side in the write process, the old data is erased after the new data write process. The physical block address of the block storing the old data to be erased can be obtained based on the address conversion table shown in FIG. In this erasing process, the following erasing process is set in the register of the flash memory sequencer block.
1) An internal erase command is set as an internal command in a predetermined register in the flash memory sequencer block.
2) The physical block address of the block in which the old data is stored is set in a predetermined register in the flash memory sequencer block.

  Thereafter, the flash memory sequencer block executes the process based on the setting of the erase process. When this processing is executed, command information and address information for executing an internal erase command are supplied from the flash memory interface block to the flash memory via the internal bus, and the data of the block in which the old data is stored Is erased.

FIG. 1 is a block diagram schematically showing a flash memory system according to the present invention. FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell constituting the flash memory. FIG. 3 is a cross-sectional view schematically showing a memory cell in a written state. FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory. FIG. 5 is a diagram illustrating an example in which a zone is configured by 512 blocks. FIG. 6 is a diagram illustrating a configuration example of a zone including a shared block. FIG. 7 is a diagram illustrating an example of an address conversion table. FIG. 8 is a conceptual diagram illustrating an example of an erased block search table. FIG. 9 is a diagram for explaining an erased block search method using an erased block search table. FIG. 10 is a diagram for explaining the candidate table.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Controller 4 Host system 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus 16 Memory Cell 17 P-type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 25 User region 26 Redundant region

Claims (6)

An allocation management function for managing a correspondence relationship between a zone composed of a plurality of blocks in the flash memory and a logical block address space on the host system side allocated to the zone;
An access control function for controlling access to the zone;
A memory controller comprising: a zone configuration function for configuring the zone such that a plurality of blocks belonging to the zone exist. The memory controller according to claim 1, wherein the zone configuration function configures the zone such that there are blocks belonging to two of the zones. 3. The zone according to claim 1, wherein the zone configuration function configures the zone such that a block belonging to any one of the zones and the other two zones exists. Memory controller. 4. The memory controller according to claim 1, further comprising a conversion table creating unit that creates an address conversion table for each zone. The memory controller according to claim 1, further comprising candidate table creation means for creating a candidate table for each zone. A flash memory system comprising: the memory controller according to claim 1; and a flash memory.

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