JP4196982B2 - Processor and program execution method - Google Patents

Description

  The present invention relates to a processor, and more particularly to a technique for efficiently executing a program.

  Conventionally, there is an OS (Operating System) for processing a plurality of tasks in a pseudo-parallel manner by a single processor. This OS causes the processor to execute the following processing. That is, the processor stores control information (hereinafter referred to as “context”) indicating the execution position of the program corresponding to each task, the data storage position, and the like in a register group inside the processor, and based on the stored context. The process of acquiring a program and data, executing a task, updating the context as the task is executed, and writing the context to the memory is repeated.

  Here, for convenience, writing the context stored in the external memory to the register group is referred to as restoration, and writing the context stored in the register group to the memory is referred to as saving. FIG. 32 is a functional block diagram of a conventional processor 1001 that executes a task under the control of such an OS, and also shows a context memory 1010 that stores the above-described context.

The processor 1001 includes a process execution unit 1002 that executes a task, a control unit 1003 that performs control related to processing in the process execution unit 1002, and a register group 1004 that stores the context of the task to be executed. The register group 1004 is a collection of registers for storing a context corresponding to one task, that is, a register value group.
Each time a new context is stored in the register group 1004, the process execution unit 1002 acquires a program or data based on this context and executes a task. The control unit 1003 saves the context already stored in the register group 1004 by overwriting the context memory 1010, determines which context is to be stored in the register group 1004, and based on this determination. The context to be stored is restored by reading it from the context memory 1010 and writing it to the register group 1004.

  Therefore, the processing execution unit 1002 has to interrupt the execution of the program because the context as the contents of the register group 1004 is being updated during the saving, determination, and restoration described above. FIG. 33 is a diagram illustrating a task execution flow in the processor 1001 and a context input / output state between the register group 1004 and the context memory 1010.

It is assumed that time elapses from left to right in this figure. Here, for example, it is assumed that there are four tasks, task A, task B, task C, and task D, and the execution order of the tasks is task A, task B, task C, and so that each task is processed equally. It is assumed that task D is in order, and task D is executed from task A next.
Conventionally, when executing each task, the above-described saving, determination, and return are performed in advance. That is, in executing each task, the above-described saving, determining, and returning are overhead. Here, if the processing from task A to task D is defined as one-cycle processing, the OS described above specifies the execution order of each task and the execution time of each task, that is, the task schedule in this one cycle. ing.

Based on this schedule, the control unit 1003 determines the context described above, that is, the context to be stored in the register group 1004. By executing the processing as described above, a plurality of tasks can be processed in a pseudo-parallel manner by one processor. There is also a processor that executes the above-described saving, determination, and restoration by hardware and processes a plurality of tasks in a pseudo-parallel manner. (For example, Patent Document 1)
JP-A-10-111301

However, when a plurality of tasks are processed in a pseudo-parallel manner by one processor in this way, the overhead of the above-described saving, judgment and restoration is executed before the task is executed, compared to the case where only one task is continuously executed. As a result, there is a problem that it takes time from the start of execution of a task to the start of execution of the next task, and the task cannot be executed efficiently.
Especially in communication devices such as mobile phones and broadcasting devices such as TV receivers, it is necessary to execute data processing in a state close to real time. In the case of processing, with the conventional task execution method having the overhead described above, it becomes difficult to perform data processing in a state close to real time as described above.

  Accordingly, the present invention has been made in view of the above problems, and a processor capable of efficiently executing a task and a program execution when a plurality of tasks, that is, a program is executed in a pseudo-parallel manner by one processor. It aims to provide a method.

  To achieve the above object, a processor according to the present invention uses a plurality of register value groups stored in a memory, and sequentially executes a program corresponding to each of these register value groups. A selection destination switching unit that selects any one of the plurality of register groups and the plurality of register groups as an execution target register group that is a basis for program execution, and switches the selection destination at predetermined time intervals; Each time it is made, a return means for returning the register value group to one register group that has not been selected from among the plurality of register groups, and before each return, By overwriting each register value in the register group to be restored to the register value group in the memory corresponding to these register values. Saving means for saving and program execution means for specifying a program by a register value group including a program counter value in the execution target register group each time the switching is performed, and executing the specified program, The predetermined time is a time specified by the count value based on table information in which a plurality of count values are stored in association with each program, and a plurality of register value groups are used. A processor for sequentially executing a program corresponding to each of these register value groups, wherein a plurality of register groups storing each of the register value groups and any one of the plurality of register groups are program-executed Selected as the execution target register group that is the basis of the target, and the selection destination is switched every predetermined time A selection destination switching means; and a program execution means for specifying a program by a register value group including a program counter value in the execution target register group each time the switching is performed, and executing the specified program, The predetermined time is a time specified by the count value based on table information in which a plurality of count values are stored in association with each program.

  In addition, a program execution method according to the present invention includes a plurality of register groups, and uses a plurality of register value groups stored in a memory to sequentially execute a program corresponding to each of these register value groups. And a selection destination switching step of selecting any one of the plurality of register groups as an execution target register group as a basis for program execution and switching the selection destination at predetermined time intervals. And a return step of returning the register value group to one register group that has not been selected among the plurality of register groups each time the switching is performed, and to the return each time the switching is performed. Prior to this, each register value in the register group to be restored corresponds to these register values. A save step for saving by overwriting the register value group in the memory, and each time the switching is performed, a program is specified by a register value group including a program counter value in the execution target register group, and the specified A program execution step of executing a program, wherein the predetermined time is a time specified by the count value based on table information in which a plurality of count values are stored in association with each program. A program execution method for executing a program in a processor comprising a plurality of register groups and using a plurality of register value groups to sequentially execute a program corresponding to each register value group. One of the register groups of A selection destination switching step for selecting the execution target register group to be performed and switching the selection destination at predetermined time intervals, and each time the switching is performed, a program is executed by a register value group including a program counter value in the execution target register group. And a program execution step for executing the specified program, wherein the predetermined time is specified by the count value based on table information in which a plurality of count values are stored in association with each program. It is characterized by a long time.

  With the above configuration, since the predetermined time is specified based on a plurality of count values, and the predetermined time can be set to a non-fixed time, the switching interval, that is, the program execution time is set non-fixed. can do. In addition, since the register value group is restored in advance to a register group other than the execution target register group without affecting the execution of the program, when the program is to be executed based on the register value, the restoration and saving are performed. Therefore, the program can be executed quickly, and the program is executed at higher speed.

Further, by eliminating the overhead described above, even if the switching is frequently performed, the execution time of the program is not affected, and it is effective for parallel execution of pseudo real-time processing.
Further, the program execution means may start the execution when the switching is performed.
As a result, when the program is to be executed, the program is quickly executed, and the overhead is almost eliminated.

The processor further includes order information acquisition means for acquiring order information indicating the order of register value groups corresponding to each program, and the return means is a register value group to be returned based on the order information. And the return may be performed.
Thereby, the execution order of the program is determined by the order information.
In addition, the predetermined time is the total of the time when each of the register groups that have been restored is selected as the execution target register group when the restoration can be performed in all the register value groups corresponding to the order of the order information. May be determined to be within a predetermined period.

As a result, a plurality of processes are simulated and executed in parallel within a limited time. In other words, it is effective for pseudo-parallel real-time processing with a limited processing time.
The order information may be a table in which identification information unique to each register value group is arranged in a predetermined order, and the order may be indicated by the order of the arrangement of the identification information.
Thereby, the return order of the register value group is indicated by the order of the arrangement of the identification information, and the return order of the register value group is changed by changing the order of the array.

The order information includes one or more pieces of the same identification information in the array, and is arranged so that the same identification information is not biased in position. The number of the same identification information in the array It may be unique to each program corresponding to the register value group specified by.
Thereby, the execution timing of each program is equalized.

The plurality of programs includes a management program for determining whether or not the table needs to be changed and changing the table, and specifies a location of a register value group corresponding to the management program in the array. The number of identification information may be only one.
This gives an opportunity to change the table each time it is executed in parallel in a pseudo manner.
The predetermined time is a time unique to each of the plurality of programs, and each identification information includes time information indicating the unique time of the program corresponding to the register value group specified by the identification information. The management program may perform the change so that the total of the specific times indicated by the time information added to each identification information is within the predetermined period.

Thereby, the specific time is updated by the management program so that a plurality of processes are executed in parallel in a pseudo manner within a limited time.
In addition, when the program execution unit determines that the table needs to be changed during the execution of the management program, the program execution unit generates a dummy table in which the change has been made with respect to the table, The change may be performed by replacing the table.

Thereby, the table can be changed without affecting the execution of the program.
The plurality of programs includes a video processing program for executing video processing, and the number of pieces of identification information for specifying the location of the register value group corresponding to the video processing program in the array is different from the other programs. It may be more.

As a result, a video processing program with a large amount of information is assigned a long processing time when viewed comprehensively.
Further, the identification information is an address value indicating an area in which the register value group is stored, and the return means specifies the location of the register value group to be returned by the address value and performs the return Also good.

Thereby, the return order of the register value group can be indicated by the magnitude relationship of the address values.
The order information is a table in which each identification information unique to each register value group is attached with a pointer pointing to other identification information, and the order is indicated by tracing the pointer. It is good.

Thereby, the return order of the register value group is indicated by the pointer, and the return order of the register value group is changed by changing the destination indicated by the pointer.
Further, the program execution includes: an interruption reason occurrence detecting means for detecting that an interruption reason for interrupting execution of the program has occurred; and an interruption reason elimination detecting means for detecting that the interruption reason has been resolved. The means may abandon an execution period to be allocated for the execution of the program until the interruption cause is resolved when the occurrence of the interruption cause for the program is detected.

This avoids execution of meaningless programs.
Also, there are a plurality of interruption reasons, the interruption reasons effective as a trigger for abandonment are specific to each program, and the program execution means is provided when an effective interruption reason occurs in the program being executed. As long as the above abandonment may be implemented.
As a result, it is determined for each program whether or not the program can be abandoned when an interruption event occurs.

  The register further includes acquisition means for acquiring interruption information in which information specifying one of the plurality of interruption reasons is associated with information indicating whether or not the specified interruption cause has occurred. The value group includes setting information in which information specifying one of the plurality of interruption reasons is associated with information indicating validity or invalidity of the specified interruption reason, and the program execution unit includes It may be determined whether the abandonment is performed by comparing and referring to the interruption information and the setting information.

Thereby, even if there are a plurality of the above-mentioned interruption reasons, an effective interruption reason is specified.
The setting information includes bit string data in which a unique bit position is determined for each interruption reason, and each bit position indicates a value indicating whether the interruption cause corresponding to the bit position is valid or invalid. A unique bit position is defined for each interruption reason, and each bit position has bit string data indicating a value indicating the presence or absence of the interruption cause corresponding to the bit position, and the program execution means includes the setting information The determination may be performed with reference to only the bit position in the interruption information indicating the interruption reason corresponding to the bit position where the value indicating validity exists.

As a result, even if there are a plurality of interruption reasons, the reference range is limited, so that an effective interruption reason can be quickly identified.
Further, when the program execution unit performs the abandonment, the program execution unit notifies the return unit to that effect, and the return unit stores a register value group corresponding to the program that has performed the abandonment until the reason for the interruption is resolved. The return may be performed by ignoring the order of the register value group so that the target is not the return target.

Thereby, the return of the useless register value group is avoided.
Further, when the notification is made, the return means exceptionally sets the register value group that is going to be ignored as the highest priority return target candidate for the return to be executed for the second time after the notification. If the reason for the interruption has been resolved before the start of the second return, the register value group is determined as the return target, and if the reason for the interruption has not been resolved, The ignore may be continued for the register value group.

Thus, another effective program can be executed at the time when the abandonment is made.
The return means has a plurality of neglected register value groups, and when two or more register value groups are out of the interruption reason, one of the two or more register value groups is ignored. When the return time comes, the register value group that was ignored lastly among the two or more register value groups may be set as the return target at the time.

As a result, after the reason for the interruption is resolved, it is possible to avoid the return of the register value that has been ignored at an unbalanced time.
The program execution unit may notify the selection destination switching unit when the abandonment is performed, and the selection destination switching unit may perform the switching when the notification is received.

Thereby, when the abandonment is made, the next program can be executed promptly.
The reason for the interruption may be that a cache miss has occurred during execution of the program. Thereby, when a cache miss occurs, the next program is promptly executed.

Further, the reason for the interruption may be a state in which processing is requested to an external device and a processing result from the external device is waited for when executing the program. Thereby, when it will be in the said state, the following program will be implemented rapidly.
In addition, the reason for the interruption may be a state in which a shared resource is used to wait for the shared resource to be released when the program is executed.

Thereby, when it will be in the said state, the following program will be implemented rapidly.
The program execution means may include a CPU for executing a program and stop the CPU during the execution period when the abandonment is performed. Thereby, useless power consumption is avoided.
The program execution means may include a CPU for executing a program and reduce the drive frequency of the CPU during the abandoned execution period.

Thereby, useless power consumption is reduced.
Further, the program execution means has a CPU for program execution, and when executing the plurality of programs, the processing capacity of the CPU is too high for the execution load of these programs, so that the processing free time The CPU drive frequency may be adjusted according to the execution load of the program so as not to occur.

Thereby, useless power consumption is reduced.
The plurality of register groups may be two, and the selection destination switching unit may alternately perform the switching for the two register groups. As a result, only two register groups allow a plurality of programs to be executed in parallel in a pseudo manner while eliminating overhead.

In other words, two register groups are sufficient regardless of the number of pseudo-parallel programs.
The program execution means may execute N stages of pipeline processing, and the save means may execute the save after (N-1) clocks from the time when the selection destination is switched. .

Thereby, even when pipeline processing is executed, a plurality of programs are executed in parallel in a pseudo manner while eliminating overhead.
Further, the selection destination switching means determines the selection destination in a predetermined order from the plurality of register groups, performs the switching, and the return means stores register value groups in a predetermined order from the plurality of register groups. The return destination may be determined and the return may be performed.

As a result, the overhead such as return and saving is eliminated, so the program is executed quickly and the program is executed at high speed.


The return means performs the return by copying the register value group stored in the memory, and the program execution means registers the register values in the execution target register group as the program is executed. The saving unit may execute the saving only when the change is made by the program execution unit.

As a result, only the changed register value is saved, so that the save time is shortened.
Further, each register of the plurality of register groups is attached with change information indicating whether or not the register value returned to the respective register has been changed, and the saving means is based on the change information, The saving may be performed by writing only the changed register values to the locations in the memory where the values before the register values are changed are stored.

As a result, whether or not there is a change is easily recognized, and only the changed register value is saved, so that the save time is further shortened.
The change information may be a 1-bit flag.
Thereby, the change is indicated by the flag.
Further, in the table information, specific information that specifies any one of the plurality of register value groups is associated with each count value, and the return target is a register value group that is returned by the specific information. Based on the order, the register value specified by the count value in the order is selected each time the selection is performed, and the register group including the register value group restored by the specifying information is selected as an execution target register group, and then another register is selected. The predetermined time until the group is selected as the execution target register group may be a time indicated by the count value associated with the specific information used for the return.

Thus, the switching interval can be freely set, and specific information specifying the same register value group can be associated with each of the different count values. Can be set to
The predetermined time may be unique for each of the plurality of programs.
Thereby, program execution time suitable for execution of each program can be allocated.

  Further, a plurality of caches for storing execution data necessary for program execution, and the register value group that has been restored in association with the restoration by the restoration means, are referred to as the register value group. Execution data specifying means for specifying execution data of a corresponding program; and cache writing means for writing the specified execution data into any one of the plurality of caches that are not used for program execution. It may be provided.

Thereby, occurrence of a cache miss is avoided.
The processor according to the present invention is a processor that sequentially executes a program corresponding to each register value group using a plurality of register value groups, and a plurality of register groups storing each of the register value groups; Selecting any one of the plurality of register groups as an execution target register group that is a basis for program execution, and a selection destination switching unit that switches the selection destination at predetermined time intervals, and each time the switching is performed. A program execution means for specifying a program by a register value group including a program counter value in the execution target register group and executing the specified program, and a plurality of count values are assigned to each program for the predetermined time. Based on the table information stored in association with each other, it is specified by the count value. The program execution method according to the present invention includes a plurality of register groups, and uses a plurality of register value groups to sequentially execute a program corresponding to each of these register value groups. A program execution method for executing a program, wherein one of the plurality of register groups is selected as an execution target register group as a basis for program execution, and a selection destination for switching the selection destination every predetermined time A switching step; and a program execution step of specifying a program by a register value group including a program counter value in the execution target register group each time the switching is performed, and executing the specified program, the predetermined time Stores multiple count values associated with each program Based on the table information, characterized in that it is a time specified by the count value.

  As a result, the program can be executed quickly without affecting the execution time of each program, and a plurality of programs are executed at high speed while being frequently switched every predetermined time. This is effective for parallel real-time processing.

<First Embodiment>
(1. Configuration)
A first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a functional block diagram of the virtual multiprocessor 100 according to the first embodiment of the present invention.
The virtual multiprocessor 100 is a processor that performs sequential switching of plates. Here, the plate is a collection of one or more tasks that are conventional tasks or OS scheduling units, and is an execution target viewed from the processor side. One plate has one execution position, that is, an instruction position in the program.

  FIG. 1 also shows control information such as the value of the program counter indicating the execution position of the program corresponding to the plate prepared for each plate described above, the address indicating the storage location of the program and data, that is, the context. A stored context memory 200 is also shown. Here, executing the program corresponding to the above plate is referred to as execution of the plate.

  The above-described context memory 200 includes an SRAM, and includes a context storage area 201 in which each context of a plurality of plates is stored, and an execution order table storage area 202 in which an execution order table 300 indicating the execution order of each plate is stored. Have The execution order table 300 is a table that defines an execution schedule of plates generated by a management application program (hereinafter referred to as “management application”) included in one plate, and includes a plurality of memories in the context storage area 201. It is an array of values of addresses (hereinafter referred to as “context addresses”), and in each location indicated by these context address values, there is a context necessary to execute each plate.

  In the execution order table storage area 202, an address indicating a physical location where the value of each context address is stored is hereinafter referred to as a table address. The above table address is indicated by a numerical value, and the magnitude relation of this numerical value corresponds to the order of the context addresses stored at the position specified by this table address in the above arrangement.

  That is, in one scheduling cycle, plates corresponding to the context address specified by the context address value stored in the physical location indicated by the table address value are executed in ascending order of the table address value. It becomes. In this way, when the execution order table 300 indicates that the execution order of the plates is A → B → C → A → D → C, the execution of each plate for one cycle is completed in this order. This cycle is repeated a plurality of times.

The processing time for one time of each plate is the same time, and a plate that takes a long time for processing has a larger number of executions in one cycle like the plate A described above.
FIG. 34 is a diagram illustrating a connection relationship between the virtual multiprocessor 100 and the external processor 30.

  In addition to the functional units described above, the following functional units are associated with the virtual multiprocessor 100. That is, a program and data are stored, and a main memory 10 composed of DRAM and a program (not shown) connected between the main memory 10 and the virtual multiprocessor 100, and the above-described program and data composed of SRAM are stored. There is a cache memory for storing, and these are connected to the virtual multiprocessor 100 via the bus 700.

  The virtual multiprocessor 100 executes a plurality of plates in a pseudo-parallel manner, but one of the plurality of plates may request an external processor for processing. Similarly to the above, it is connected to the virtual multiprocessor 100 via a bus. That is, as shown in FIG. 34, the external processor 30 and the main memory 10 are connected by a bus 700, and the virtual multiprocessor 100 and the external processor 30 are connected via the main memory 10.

The virtual multiprocessor 100 writes the input data of the process executed by the external processor 30 to the main memory 10 via the bus 700 described above, and reads the data that is the result of the process executed by the external processor 30 from the main memory 10. To do.
The external processor 30 reads processing input data from the main memory 10 and writes processing result data to the main memory 10.

  The external processor processing request signal line 701 and the external processor processing completion signal line 702 are provided independently of the above-described bus 700, and are connected to the virtual multiprocessor 100 and the external processor 30, respectively. More specifically, the external processor processing request signal line 701 is a signal system for transmitting a processing request signal from the virtual multiprocessor 100 to the external processor 30, and the external processor processing completion signal line 702 is This is a signal system for transmitting a processing completion signal from the external processor 30 to the virtual multiprocessor 100.

  By transmitting these signals, a request for processing from the virtual multiprocessor 100 to the external processor and a notification of processing completion from the external processor to the virtual multiprocessor 100 are made. The virtual multiprocessor 100 is a SIMD (Single Instruction / MultipleData) type processor, and includes a processing execution unit 110, a processing control unit 111, a register switching unit 112, a switching replacement control unit 113, and a first register group 114. A second register group 115, a cycle counter 116, an external I / F 117, a DMA management unit 118, a completion notification register 119, a control register 120, and a setting flag register 121.

The first register group 114 and the second register group 115 are a collection of registers for storing register values such as program counter values, addresses indicating program and data storage locations, which are context contents.
Each register has a 1-bit storage area for storing a value of an update flag indicating whether a value of a program counter or the like stored in the register is updated when the plate is executed.

  When the above-mentioned value is updated, the value of the update flag indicates 1, and when the update is not performed, the value of the update flag indicates 0. In the default state, the value of the update flag of each register of the first register group 114 and the second register group 115 is 0. In accordance with an instruction from the switching replacement control unit 113, the register switching unit 112 uses one of the first register group 114 and the second register group 115 for register execution (hereinafter, “ Current register group)).

  Here, for convenience, the register group that is not selected as the current register group is referred to as a standby register group, and switching the above-described selection target from the currently selected register to the other register is referred to as register switching. I will do it. When the above-described register switching, that is, selection of the current register group is made, the process execution unit 110 executes a program to be executed and data necessary for executing the program based on the context stored in the current register group. The location is specified, and the DMA management unit 118 is instructed to acquire these programs and data.

  The acquisition of these programs and data is premised on the acquisition from the cache memory, and when the target data exists in the cache memory (hereinafter referred to as “cache hit”), or as an exception, an external storage device described later When the program and data are acquired from the program, the process execution unit 110 acquires these programs and data, and executes the plates according to instructions from the process control unit 111 using these programs and data.

  However, the process execution unit 110 may exceptionally instruct the DMA management unit 118 to acquire a program and data from an external storage device (not shown). This external storage device can also be accessed (for example, read and written) by other input / output devices not shown. The access time differs between when accessing from a plurality of devices and when accessing from one device (access times from a plurality of devices are longer).

  On the other hand, when the target data does not exist in the cache memory, that is, when a cache miss occurs or when it is determined that it takes time to access the external storage device, the process execution unit 110 notifies the fact. The processing control unit 111 is notified, and subsequent processing is performed in accordance with an instruction from the processing control unit 111. Along with the execution of this plate, the process execution unit 110 updates the value to be updated such as the program counter with the value stored in the context, and sets the value of the update flag included in the register whose value has been updated to 1.

In addition, when a waiting factor described later occurs during execution of the plate, the process execution unit 110 outputs a notification indicating that the plate has been put to sleep to the switching replacement control unit 113 via the process control unit 111, and The value of a setting flag, which will be described later, corresponding to the type of waiting factor that has occurred in the setting flag register 121 is changed to 1.
Further, the processing execution unit 110 requests the external processor 30 to perform processing when a previous waiting factor occurs.

  Further, when the reason for eliminating the waiting factor is to receive the processing result from the external processor 30, the processing execution unit 110 requests the processing to the external processor 30 to notify that the plate has been put to sleep. Then, the data is output to the switching replacement control unit 113 via the processing control unit 111. At this time, the switching replacement control unit 113 outputs a processing request signal to an external I / F 117 described later.

  FIG. 1 is a diagram showing a state at a certain moment. The processing execution unit 110 (plate B execution) is that the context corresponding to the plate B is stored in the first register group 114. This shows the state at the time when one register group 114 is selected as the current register. Data input / output in the virtual multiprocessor 100 and data input / output to / from the context memory 200, the main memory 10, the cache memory, and the external processor are performed by DMA transfer, and the DMA management unit 118 performs this DMA transfer. Control.

  Also, the DMA management unit 118 performs switching switching control for a signal indicating the fact (hereinafter referred to as “transfer completion signal”) when the DMA transfer is completed based on a request from each functional unit and the transfer is completed. When a cache miss occurs while trying to obtain a program and data from the cache memory, a signal indicating that a cache miss has occurred (hereinafter referred to as a “cache miss signal”) is switched control. Output to the unit 113.

Furthermore, the DMA management unit 118 indicates that the memory latency is large when it is determined that it takes time (high latency) to access the external storage device in order to acquire a program and data from an external storage device (not shown). A signal (hereinafter referred to as “memory access delay signal”) is output to the switching replacement control unit 113.
The external I / F 117 is an interface connected to an external device such as an external processor. For example, the external I / F 117 switches an external signal such as an external processor processing completion signal indicating that processing requested to the external processor is completed. 113 is notified.

Also, the external I / F 117 notifies the external processor 30 of a processing request signal indicating that the external processor 30 is requested to perform processing, for example.
That is, as described above, the external I / F 117 outputs the processing request signal to the external processor 30 when the processing request signal is notified from the switching replacement control unit 113 to the external I / F 117. The process control unit 111 controls the process execution unit 110 to continuously execute the plate from the start to the end of the plate execution.

The cycle counter 116 has a clock counter, and counts the value determined by the execution of the plate including the management application in the process execution unit 110 via the switching replacement control unit 113 and the process control unit 111. Register the value as the initial value.
Further, the cycle counter 116 counts down by decrementing one by one from the initial value described above, and when the value becomes 0, a signal (hereinafter, “ "Count value 0 signal") is output and the initial value is set again to start counting down.

  The initial value of the count value is a value common to each plate. The control register 120 is a register for storing information for specifying the current plate being executed and the plate to be executed next. More specifically, the control register 120 stores the value of the table address (hereinafter referred to as “current address”) of the physical location in which the value of the context address corresponding to the current plate being executed is stored, and the next. Stores the value of the table address of the physical location where the context address corresponding to the plate to be executed (hereinafter referred to as “next address”) is stored, and is the smallest in the execution order table storage area 202. A table address (hereinafter referred to as “table head address”) value and a maximum table address (hereinafter referred to as “table end address”) value are stored.

  By the way, shared resources used at the time of task execution are used by other devices and are currently being executed non-steadily by software triggered by the occurrence of waiting and so-called interrupts due to the fact that they cannot be used immediately. Suspend the task and remove it from the task execution schedule, give the execution time assigned to this task to other tasks, and execute the task execution order when the factor that triggered the task suspension is resolved It is a well-known technique to execute the scheduling again.

  Further, according to the present invention, when a predetermined factor (hereinafter referred to as a “waiting factor”) that can trigger a plate execution interruption occurs by hardware, register switching, that is, plate switching is performed. The sleep which excludes the made plate from the execution order is executed, and when this waiting factor is resolved, the wakeup which tries to execute this plate is executed.

When performing such sleep and wakeup, it is necessary to know what wait factor causes the sleep for each plate in order to identify the wait factor that triggers the wakeup.
In addition, when an external interrupt request or the like arrives, it is necessary to know in advance whether or not to respond to the external request.

For this reason, the context of each plate has an area for storing the value of a setting flag indicating the type of the waiting factor that triggered the occurrence of sleep, whether or not to accept an interrupt request, and the like. Thus, there are a plurality of types of waiting factors, and there is a setting flag, that is, a set flag group for each type.
This set flag group is included in each context stored in the context storage area 201. The setting flag register 121 is a register for storing setting flag groups included in the two plates. When executing a plate, the executed plate itself requests that the execution of the plate be interrupted, or a request to stop the execution of the plate comes from the outside. Of the plurality of setting flags of the context corresponding to the plate, the value of the setting flag corresponding to the type of the waiting factor that has occurred is changed from 0 to 1 by the process execution unit 110.

  Here, the above-described request for interrupting the execution of the plate includes a so-called interrupt request. When such an interrupt occurs, it is not always necessary to interrupt the plate being executed. Is determined for each plate. Therefore, in the plate that allows interruption, 1 is set as a value indicating that interruption is possible in the value of a setting flag that indicates whether or not an interruption request is accepted by the program designer.

  The completion notification register 119 is a register for storing a flag (hereinafter referred to as “completion notification flag”) indicating whether or not the above-described wait factor is currently resolved, whether an interrupt request has occurred, or the like. is there. There are as many completion notification flags as the number of setting flags included in one context, and each completion notification flag has a one-to-one correspondence with each setting flag existing for each type of waiting factor. .

  In other words, the bit string length of the completion notification flag group that constitutes the collection of completion notification flags is the same as the bit string length of the setting flag group that constitutes the collection of setting flags, and if the bit position from the head is the same, the same wait factor Stores a value for. When the switching replacement control unit 113 receives a count value 0 signal from the cycle counter 116, receives a notification indicating that the plate has been put to sleep from the processing execution unit 110, and receives a cache miss signal from the DMA management unit 118. When it is received, or when a memory access delay signal is received, the flag determination process described later is performed and the current next address value is left as it is, or another table address value is set as a new next address. The next address value stored in the control register 120 is re-stored as a new current address value while the next address value is reviewed and the next address value is reviewed. The value of the next table address after the value is set to the new next address. Stored as a value, it instructs the register switching unit 112 to perform the register switching described above.

  Further, as a result of this register switching, the switching replacement control unit 113 refers to the update flag of each register of the register group that becomes the standby register group, and is stored in the register whose update flag value is 1. DMA so as to save the stored register value by overwriting the storage area corresponding to this register value in the context storage area 201, that is, the location where the register value before being changed when stored in the register group is read. In addition to instructing the management unit 118, a flag determination process described later is performed.

Further, the switching replacement control unit 113 reads the setting flag of the context to be saved from the setting flag register 121 in association with the saving, and a storage area corresponding to the setting flag in the context storage area 201, that is, The value of the setting flag is saved by overwriting the location where the setting flag is read when stored in the setting flag register 121.
When the above-described saving and flag determination processing described later are completed, the switching replacement control unit 113 stores the plate context specified by the value of the next address in the control register 120 in each register of the standby register group, that is, returns. . At this time, the switching replacement control unit 113 clears the value of the update flag of each register to 0.

  The switching replacement control unit 113 performs the above-described saving, flag determination processing, and return in parallel with the execution of the plate by the processing execution unit 110 using the context stored in the current register group. The register switching time span is determined by a management application or the like so that the time required for the save, flag determination process, and return is shorter than the plate execution time.

  Hereinafter, the details of the flag determination process in the switching replacement control unit 113 will be described. The switching / replacement control unit 113 exists in the context storage area 201, and is a bit in which one value is stored in the bit string of the setting flag group included in the context specified by the value of the next address of the control register 120 ( Hereinafter, the position of “effective bit” is grasped.

Such processing for grasping the position of the effective bit is referred to as effective bit position search processing. At this time, if there is no valid bit in the bit string of the set flag group, the switching / replacement control unit 113 ends the flag determination process while leaving the next address value as it is.
When there is a valid bit in the bit string of the setting flag group, the switching replacement control unit 113 refers to only the position corresponding to the position of the valid bit in the bit string of the completion notification flag group in the completion notification register 119. If a value of 1 is stored in all the positions corresponding to the positions of the valid bits, the flag determination process ends with the next address value unchanged.

  The position corresponding to the position of the valid bit is a position separated from the head position of the bit string of the completion notification flag group by the same number of bits as the number of bits from the head position of the bit string of the setting flag group to the valid bit (hereinafter, "Position corresponding to valid bit"). On the other hand, when a value of 0 is stored in any of the valid bit corresponding positions of the completion notification flag group, the switching / replacement control unit 113 sets the next address value at the current time indicated in the execution order table storage area 202. Subsequently, the next largest table address value is provisionally set as a new next address value.

Then, the switching replacement control unit 113 performs the above-described effective bit position search processing for the setting flag included in the context specified by the provisional next address value, and then, the effective bit of the completion notification flag group. The above-described process for reviewing the next address according to the value of the corresponding position is repeatedly performed until the flag determination process is completed.
When the current next address value is the table end address value, the next largest table address value is the table top address value following the next address value.
(2. Data)
Hereinafter, data used in the virtual multiprocessor 100 will be described.

  FIG. 2 is a diagram showing an execution order table 300 stored in the context memory 200 and the data structure of the context. The execution order table 300 shows a plurality of context address values in the context storage area 201 in which contexts are stored, and the physical storage position of these context address values, that is, the table address depends on each context address. The execution order of the identified plates is determined.

  That is, the execution order of the plate corresponding to the context address is higher in the context address stored in the place where the table address having a smaller value is assigned. Although the execution order of the plates may be skipped by the flag determination process described above, the plates are basically executed according to the physical storage position of the context address values, that is, the order indicated by the array, and the table final address is set. After the plate specified by the current address is executed in the case of the current address, the plate specified by using the table head address as the current address is executed.

That is, the physical storage position of the context address, that is, the table address indicates the execution order of the plates in one cycle. In FIG. 2, the table address has a value from 2000 to 2005. In this case, the value of the table head address is 2000 and the value of the table end address is 2005.
The execution order of the plate of the context address stored in the smaller table address is first. FIG. 3 is a diagram illustrating each flag of the completion notification flag group and the setting flag group. The completion notification flag group includes a forced wait flag, a queue empty notification flag, an interrupt notification flag, a software wait instruction flag, an external processor processing completion notification flag, a transfer notification flag, and the like.

  The forced waiting flag is a flag in which a value of 0 is fixedly stored. Queue availability notification flag indicates that there is no vacancy in the queue from an external device that manages the queue, such as when trying to queue an instruction in a queue with less capacity while the plate is running It is a flag indicating whether or not there is a vacancy in the queue, takes a value of 0, and takes a value of 1 if the queue has a vacancy.

  The interrupt notification flag is a flag indicating whether or not an interrupt request has arrived from an external device. When the interrupt request has not arrived, the interrupt notification flag takes a default value of 1, and when an interrupt request has arrived, The switching replacement control unit 113 sets the value to 0. The software wait instruction flag is a flag indicating whether or not an instruction for waiting for execution of a plate has arrived from application software or the like, and when the above instruction has not arrived, a value of 1 which is a default value When the above instruction arrives, the switching replacement control unit 113 sets the value to 0.

  The external processor processing completion notification flag is a flag indicating whether or not a notification indicating that the requested processing has been completed has been received when processing is requested to an external processor during execution of the plate, that is, a cache miss signal or This flag indicates completion of DMA transfer that has caused a memory access delay signal, DMA transfer requested by a program, etc. If this notification has not arrived, it takes a default value of 0, Further, when a notification indicating that the requested process has been completed has arrived, the switching replacement control unit 113 sets the value to 1.

  The transfer notification flag is a flag indicating whether or not a notification indicating that the DMA transfer has been completed has arrived. When this notification has not arrived, the transfer notification flag takes a default value of 0, and the DMA transfer is not performed. When a notification indicating completion is received, the switching replacement control unit 113 sets the value to 1. Each of the above-described flags, when a new plate is executed with the flag as a trigger, the value of the flag is reset to the default value by the switching / replacement control unit 113 by the execution of the plate. It will be.

Each flag constituting the setting flag group is a flag corresponding to each flag of the completion notification flag group, and indicates whether or not to ignore the corresponding flag. When the value of the setting flag constituting the setting flag group included in the context is 0, the plate is executed based on this context without being affected by the value of the corresponding completion notification flag.
When the value of the setting flag is 1, the switching replacement control unit 113 determines whether or not the plate corresponding to the context including the setting flag is to be executed based on the value of the corresponding completion notification flag. As an example in which 1 is stored as the value of the setting flag, a waiting factor has occurred when the plate corresponding to the context including the setting flag has been executed before, and execution of the plate is interrupted. Such a plate is in a sleep state until the holding factor is eliminated.

More specifically, when the value of the completion notification flag and the setting flag of the corresponding items are 1, the plate corresponding to the context including the setting flag is set as the execution target, and the completion notification flag of the corresponding items is set. When the value of is 0 and the value of the setting flag is 1, the plate corresponding to this context is set as a non-execution target, that is, excluded from the execution order of the plates.
That is, when the value of the corresponding completion notification flag and the value of the setting flag are 1, the plate corresponding to the context including the setting flag is waked up by the switching replacement control unit 113, and the value of the corresponding completion notification flag is 0. If the value of the setting flag is 1, this plate enters the sleep state.

If the value of the setting flag is 0, the switching replacement control unit 113 ignores the waiting factor of the type corresponding to the place where the value of 0 is stored, and the completion notification flag corresponding to the waiting factor is also set. Not referenced.
FIG. 4 is a diagram illustrating the relationship between tasks and plates. There are a plurality of tasks on the software side, and among these tasks, tasks to be processed in real time are directly under the management of the management application without going through the OS. Note that a management application for updating the contents of the execution order table 300 is included in the task to be processed in real time, and when this task, that is, a plate is executed, for example, a new process is executed. If it is in the power state, the processing execution unit 110 updates the contents of the execution order table 300.

  As a result, every time the plate for one cycle is executed, an opportunity to review the task scheduling at least once occurs. More specifically, each time a plate corresponding to the management application is executed, the presence / absence of the condition is determined, and when this condition occurs, a dummy table that is an execution order table of new contents is executed. The execution order table generated in the order table storage area 202 and updated as a basis for plate execution is switched from the current execution order table 300 to the dummy table.

On the other hand, tasks that do not need to be processed in real time are first placed under the management of the OS and further under the management of the management application. The plate is one execution unit in the hardware side, that is, the processing execution unit 110, and may be one task itself or may be a group of a plurality of tasks. It can be determined freely by programming.
(3. Operation)
Hereinafter, a process for realizing efficient plate execution when the virtual multiprocessor 100 executes plates in a pseudo-parallel manner by one processor will be described.

FIG. 5 is a flowchart showing processing executed in the virtual multiprocessor 100. The switching replacement control unit 113 refers to the execution order table 300 in the context memory 200 and registers the table start address, current address, next address, and table end address in the control register 120 (step S500).
All values in the first register group 114 and the second register group 115 are cleared (step S501). The switching replacement control unit 113 selects a current register group and a standby register group from the first register group 114 and the second register group 115 (step S502).

  Then, the switching replacement control unit 113 stores the context specified by the current address in the current register group (step S503). Subsequently, the switching replacement control unit 113 gives a plate execution instruction to the process execution unit 110 via the process control unit 111. As a result, the process execution unit 110 is based on the context stored in the current register group. Then, execution of the plate is started (step S504).

The cycle counter 116 starts counting down from the initial value set by the execution of the plate when the plate execution starts (step S505). The switching replacement control unit 113 receives signal inputs from the external I / F 117 and the DMA management unit 118, and updates the value of the completion notification flag in the completion notification register 119 according to the input signal (step S506).
Then, the switching / replacement control unit 113 performs flag determination processing to determine the value of the next address in the control register 120 (step S507). Subsequently, the switching replacement control unit 113 saves only the context part in which the update flag value of each register constituting the standby register group is 1 in the context storage area 201 (step S508), and stores it in the standby register group. All the values that have been set are cleared (step S509).

  Further, the switching replacement control unit 113 stores the context specified by the next address in the control register 120 in the standby register group (step S510). Then, the switching replacement control unit 113 re-registers the next address in the control register 120 as the current address, and re-registers the next address after the next address as a new next address (step S511).

  Whether the switching / replacement control unit 113 has received a count value 0 signal from the cycle counter 116, that is, whether the end of plate execution has been instructed or the processing execution unit 110 has notified that the plate being executed has been put to sleep. Further, it is determined whether the notification is a notification indicating that the plate has been put to sleep after requesting the processing to the external processor 30 (step S512). If these signals are input or notified, the processing is executed. When the plate 110 is made to finish executing the plate and the processing is requested from the external processor 30 and the plate is put to sleep, the switching replacement control unit 113 notifies the external I / F 117 of a processing request signal, and the external I / O 117 / F117 causes the external processor 30 to output a processing request signal (step S513), and the register To implement register switching the replacement unit 112 (step S514), the flow returns to step S504 to start the execution of the plate.

  On the other hand, if these signals are not input or notified, the execution of the current plate is continued, and the process returns to step S512 for determining whether there is a notification indicating that the plate is ended or put to sleep. FIG. 6 is a flowchart showing the flag determination process. The switching / replacement control unit 113 exists in the context storage area 201, and the position of the effective bit in which the value 1 is stored in the bit string of the setting flag group included in the context specified by the next address of the control register 120 The effective bit position search process is performed to grasp (step S600).

  Then, the switching / replacement control unit 113 determines whether there is no valid bit (step S601). If there is no valid bit, the flag determination process is performed with the next address value in the control register 120 as it is. Exit. On the other hand, when there are one or more valid bits, the switching replacement control unit 113 refers to only the positions of the valid bits in the bit string of the completion notification flag group in the completion notification register 119 (step S602), and all the valid bits are referred to. Whether a value of 1 is stored is determined (step S603).

  When a value of 1 is stored in all the valid bits of the completion notification flag group, the switching replacement control unit 113 ends the flag determination process while leaving the next address value as it is (step S604). On the other hand, when a value of 0 is stored in any of the valid bits in the bit string of the completion notification flag group, the switching / replacement control unit 113 follows the next address at the current time indicated in the execution order table storage area 202. Is temporarily set as a new next address (step S604), and the process returns to step S600 where the effective bit position search process is performed.

  By performing the above processing, the virtual multiprocessor 100 can execute the plate without interposing the time required for saving, judging and returning the context between the end of the plate and the start of the next plate. it can. FIG. 7 is a diagram for explaining such a state in time series. Context saving, determination, and restoration are performed in parallel with the execution of the plate.

  For this reason, it is avoided that the time required for context evacuation, determination and return is interposed between the end of the plate and the start of the next plate. As described above, according to the present embodiment, even if a plurality of plates are executed in a pseudo-parallel manner in one virtual multiprocessor 100, context saving, determination, and restoration are performed in parallel with the execution of the plates. Therefore, the time required for saving, judging and returning the context does not intervene in the execution time of the plate, so that the task can be executed efficiently.

  In this embodiment, the execution order table 300 indicates the execution order of the plates, and the physical storage position of the value of the context address in the execution order table 300, that is, the basic execution order of the plates according to the arrangement. However, the present invention is not limited to this method. For example, a set of a context address value and a table address value is stored in the execution order table 300, and the table address value corresponds to the next execution order. The plate execution order may be determined by indicating the physical storage position of the context address, that is, by using the value of this table address as a pointer.

  In this case, the execution order is not affected by the physical storage position of the stored context address value, and the execution order can be easily changed by changing this pointer. FIG. 8 is a diagram showing the data structure of a table indicating the execution order when such pointers are used, and also shows the data structure in the context storage area 201 in order to show the correspondence with the storage position of the context. ing.

This execution order table stores a set of the above-described context address and a table address as a pointer indicating the next execution order.
In the present embodiment, the switching replacement control unit 113 performs the flag determination process based on the execution order indicated by the execution order table 300, so that the timing when the sleeped plate wakes up is When the execution order of the plate specified in the execution order table 300 is reached, flag determination is performed by preferentially referring to the set flag group in the context of the sleeping plate in the flag determination process. If the process is executed and the wake-up conditions are met, the process may be executed without waiting for the execution order of the sleeping plates.

FIG. 9 is a diagram showing the plate execution status in such a case in time series. At t0, the plate A requests the external processor 30 to perform processing, and performs so-called extrude to enter sleep until a processing result is received from the external processor 30.
Here, this protrusion will be described. First, the virtual multiprocessor writes input data of processing executed by the external processor 30 to the main memory 10, then outputs a processing request signal to request processing from the external processor 30 and sleeps the plate. The external processor 30 operates by executing an instruction from the main memory 10, reads the input data of the process from the main memory, performs the requested process, and writes the data that is the process result to the main memory.

  Thereafter, the external processor 30 outputs a processing completion signal to notify the virtual multiprocessor 100 that the processing has been completed. When the completion of the process is notified, the virtual multiprocessor 100 executes the sleeped plate again by the flag determination process described above with reference to FIGS. 5 and 6 and the external processor 30 processes from the main memory 10. Read data.

As described above, by executing the plate, the virtual multiprocessor 100 requests processing from an external processor and sleeps until a processing result is received from the external processor. The operation will be specifically described below. First, at t0, the value of the external processor processing completion notification flag in the setting flag group is changed to 1.
From t2 to t4, the flag determination process is preferentially performed for the plate A. However, the valid bit in the completion notification register 119, that is, the value of the external processor processing completion notification flag is 0, so that the wakeup is not performed. At t5 during the execution period of the plate D, the value of the external processor processing completion notification flag is 1, so the wakeup is performed.

  With this wake-up, the switching replacement control unit 113 stores the wake-up plate context in the standby register group. At t6, the switching replacement control unit 113 causes the register switching unit 112 to perform register switching. Then, the process execution unit 110 executes the plate A based on the context corresponding to the plate A stored in the current register.

After that, the plate A is executed again when the regular execution order of the plate A comes around.
Further, FIG. 9 shows the case where there is one sleeping plate, but there may be a case where a plurality of plates are sleeping. In such a case, priority is given to the context of the plate that has been sleeping early. Alternatively, the flag determination process may be performed on the contrary, and conversely, the flag determination process may be performed preferentially on the context of the plate that has slept late.

  FIG. 10 is a diagram illustrating an example in which the flag determination process is preferentially performed on the context of a plate that has been slept late. The plate D following the plate B is in the sleep state, and in the fifth determination in the figure, it is determined that the plate B and the plate D are executable, and the plate D having the shortest sleep time at this time point is determined. Is preferentially waked up, and then plate B is waked up.

  This is because the execution order of the previously sleeping plate is closer to that of the later sleeping plate, so if you wake up and run the previously sleeping plate, it will immediately reappear. This is because if the time point is captured, the plate execution start interval becomes extremely narrow, and the plate execution time may not be equalized.

Further, in the above-described flag determination processing described with reference to FIGS. 9 and 10, when the sleep time of the plate exceeds a predetermined time, the above-described priority may be canceled.
In this embodiment, the completion notification flag group and the setting flag group include a forced wait flag, a queue empty notification flag, an interrupt notification flag, a software wait instruction flag, an external processor processing completion notification flag, a transfer notification flag, and the like. However, other flags may be provided.

  For example, when a plurality of plates are sleeping, it is impossible to determine which plate the various completion notification flags correspond to. Therefore, a flag associated with a number for identifying a plate is provided in the completion notification flag group and the setting flag group, and when the sleep occurs, the processing execution unit 110 identifies a plate being executed. A new number is generated, and this number is registered in a flag newly provided in the set flag group, and this number is notified to the external device that has triggered the occurrence of sleep.

When the wait factor is resolved, for example, the external processor processing completion notification flag is set to 1 by notifying the external processor processing management signal and the like together with the above-mentioned number from an external device such as an external processor. In addition, since the flag indicating this number is set to 1, it is possible to determine which plate it corresponds to.
In this embodiment, when a wait factor occurs, an example in which the execution time assigned to the plate being executed is abandoned and transferred to another plate has been shown. Instead of surrendering to other plates, the processor drive frequency may be lowered and the power consumption may be reduced by the time for which the above-mentioned abandonment has been made.

  In that case, in order to prevent the absolute time allocated to the execution of the plate from changing, for example, when the drive frequency of the processor, that is, the clock frequency is reduced by a factor of two, the cycle counter 116 is 1 per clock. What was decremented one by one is decremented by two per clock. In this embodiment, it is assumed that the time period for register switching is determined by a management application or the like so that the time required for saving, flag determination processing, and restoration is shorter than the execution time of the plate. However, this is a constraint that determines the lower limit of this time span.

  On the other hand, the constraint condition for determining the upper limit value of the time span is not particularly mentioned in the present embodiment, but this time span is a limit time during which the plate can be executed. If the processing is performed in an extremely short time with respect to this limit time, there will be wasted time during which each plate is not being processed. To avoid this, the management application should ensure that the time span of the plate is such that the actual execution time of the plate is approximately the same as the time span described above, and that the time span described above is greater than or equal to the actual execution time of each plate. An upper limit value may be determined.

  By the way, in real-time processing such as communication processing, the period of arrival of data to be processed by the execution of the plate is almost determined. That is, the processing load of each plate in one cycle is determined, and even if each plate for one cycle is executed using the time span having the upper limit value and the lower limit value determined as described above, It is meaningless if the data to be processed in the cycle has not arrived.

Therefore, when the processing capacity of the processing execution unit 110 exceeds the processing load of the plate to be processed in one cycle, and there is a margin in processing time, the processor in the processing execution unit 110 is such that such a margin does not occur. The drive frequency, i.e., processing capability, may be reduced and the substantial execution time of each plate may be increased.
In that case, when each plate is executed, useless time during which processing is not performed is reduced, and power consumption is also reduced by lowering the drive frequency of the processor.

Further, a plate to be executed next to a plate currently being executed, that is, data necessary for execution of a plate corresponding to a context stored in the standby register group may be stored in a cache in advance.
In this case, a function unit is required that refers to the context stored in the standby register group in advance, grasps data necessary for execution of the next plate, and stores this data in the cache.

Also, in order to make the main memory capacity virtually larger than the physical capacity, the correspondence (mapping) between the “logical address specified by the program” and the “physical address physically accessed by the processor” is set. A “virtual memory function unit” to be managed may be added to the present embodiment.
This virtual memory function is a known technique. In this case, the cache includes an “address conversion table cache” that stores an “address conversion table” indicating a correspondence relationship (mapping) between a logical address and a physical address. An “address conversion table” that can convert a logical address indicating data required for a plate to be executed into a physical address may be stored.

  In that case, refer to the plate to be executed next to the currently executed plate, that is, the context stored in the standby register group in advance, and grasp the data necessary for the execution of the next plate. It is necessary to have a functional unit that grasps the value of the address conversion table that can convert the logical address to the physical address and stores it in the address conversion table cache.

  In addition, although the initial value of the count value in the cycle counter 116 is a value common to each plate, it may be different for each plate. That is, this initial value indicates the time prepared for the execution of the plate, and an execution time unique to the plate may be assigned according to the content of the plate processing. In that case, as shown in FIG. 11, the initial value of the count value is stored in the execution order table storage area 202 in association with the context address.

Then, the switching / replacement control unit 113 stores the initial value of the count value in association with each of the current address and the next address in the control register 120.
Accordingly, it is desirable to provide two cycle counters 116 in order to count down based on different initial values as needed while eliminating overhead.
Further, the cycle counter 116 may be configured as a functional unit shown in FIG. In this figure, the cycle counter 116 includes an input / output unit 301, a first memory 302, a second memory 303, and a countdown unit 304. The input / output unit 301 has a function of receiving the initial value of the count value from the switching replacement control unit 113 and storing the received initial value in the first memory 301 and the second memory 303 alternately.

  Further, when the input / output unit 301 receives a signal from the countdown unit 304, the input / output unit 301 outputs a count value 0 signal to the switching replacement control unit 113. The first memory 302 and the second memory 303 are FIFO memories. The countdown unit 304 alternately reads initial values from the first memory 302 and the second memory 303 and performs countdown based on the initial values.

With the configuration as described above, an execution time unique to the plate can be assigned according to the content of the plate processing.
Further, the process execution unit 110 may execute the plate by N-stage pipeline processing. FIG. 13 shows an example in which four-stage pipeline processing is performed.
In this case, even if execution of the processing of the plate A is completed at the first stage, the plate A is still being executed from the second stage to the fourth stage. That is, in this state, the register value of the plate A cannot be saved because the register value of the current register group is necessary. When three clocks have elapsed since the execution of the processing of the first-stage plate A has been completed, the execution of the fourth-stage plate A is completed, so that the register value of the plate A can be saved here.

Therefore, for example, when the plate is executed by N-stage pipeline processing, the register value, that is, the context is set unless at least (N−1) clocks after the execution of the first-stage plate is completed. It cannot be evacuated.
Further, in the present embodiment, once the plate sleeps, the opportunity to wake up is only the next execution order shown in the execution order table 300. In some cases, this waiting factor may be resolved instantaneously. Considering this, the sleep plate execution order is the earliest order from immediately after going to sleep until the first plate execution. A sleep plate may be preferentially executed. FIG. 14 is a diagram for explaining the state of plate execution when such plate execution is performed.

  In this figure, the waiting factor that caused the sleep immediately after the plate C sleeps has been eliminated, and the execution order of the plate C is the earliest during the execution of the plate D. After execution, plate C is executed. However, in this case, when the timing for eliminating the waiting factor is just before the end of the execution of the plate D, in this embodiment, since the number of standby registers is only one, it is originally executed after the plate D. The margin for the return time of plate A, which should be expected, must be taken into account.

  Therefore, the time in which the execution order of the sleeping plates is given the highest priority (hereinafter referred to as “priority period”) is shorter than the execution time of the plate D in this figure. In order to eliminate such an inconvenience, at least three register groups are provided, one of which is a current register group and the other two are standby register groups. By storing the context of the plate A in the two standby register groups at the same time, the above-described priority period becomes longer until the end of the execution of the plate D.

In the first embodiment, the description has been made on the assumption that the number of plates exceeds the number of register groups. However, the present invention is not limited to this, and the number of plates may be equal to or less than the number of register groups. Good. In this case, it is not necessary to provide a context storage area in the context memory, and the saving and restoring steps are not necessary.
Specifically, S508 (save) and S509 (clear standby register group) in FIG. 5 are not necessary, and the processing of S510 and S514 is changed. In other words, in the first embodiment, S510 (storage in the standby register group) is a process of storing in the standby register group the context specified by the next address in the control register 120 determined in the flag determination process in S507. If there is no context storage area, the switch replacement control unit sets S510 as "the next current register group" as "the register group previously associated with the context specified by the next address determined in S507" The process may be selected and stored in 113.

  In step S514, the register switching unit 112 may perform register switching so that the register group previously selected as the “next current register group” by the switching replacement control unit 113 becomes the current register group. In this case, the switch replacement control unit 113 has a function of grasping and storing which register group is associated with the context specified by the next address. The control unit 113 has a function of switching the current register group to the register group stored.

Here, when the number of plates and register groups is two, more specifically, it is assumed that plate A is associated with the first register group and plate B is associated with the second register group. For example, when executing the plate A, the switching replacement control unit 113 selects the first register group as the current register group without performing the operation of restoring the register value group from the context memory.
Even if the number of register groups and plates (there are plates A, B, and C, and plate C is associated with the third register group) is three, it is selected as the current register group. What is executed is a register group to be executed, and the others are standby register groups. When executing the plate C, the third register group is selected as the current register group.

Even after the selection destination is switched, the operation of saving the register value group in the context memory is unnecessary. Even in the above configuration that does not include a context storage area, a plurality of programs are executed at high speed while being frequently switched every predetermined time, which is effective for parallel execution of pseudo real-time processing.
In the first embodiment, the context memory 200 is configured by SRAM. However, the context memory 200 may be DRAM, and is not limited to these memories. It may be an external storage device.

In the first embodiment, the management application is included in one plate. However, the management application may be included in a plurality of plates.
<Second Embodiment>
(1. Configuration)
The second embodiment will be described in detail with reference to the drawings.

FIG. 15 is a functional block diagram of the virtual multiprocessor 400 according to the second embodiment. Similar to the virtual multiprocessor 100 in the first embodiment, the virtual multiprocessor 400 is a processor that executes a plurality of programs in a pseudo-parallel manner.
The virtual multiprocessor 400 executes a plurality of programs in a pseudo-parallel manner by sequentially executing a program assigned to each of a plurality of time slots. Here, the time slot is a minimum program execution time frame when a program is executed in a time-sharing manner.

In the virtual multiprocessor 100 in the first embodiment, the plate itself, that is, the execution order of the program is defined. In the virtual multiprocessor 400 of the second embodiment, first, the order of the time slots is defined. Further, the present embodiment is different from the first embodiment in that a program candidate to be executed for each time slot is prepared.
More specifically, each time slot is associated with four or one program that is a candidate for allocation to the own time slot, and usually one of these programs is the target of the allocation. . In principle, the program assigned to each time slot is sequentially executed based on the prescribed time slot order.

The virtual multiprocessor 400 is different from the virtual multiprocessor 100 in the first embodiment in the contents of the processing when the allocation target program becomes inexecutable. The program to be executed as viewed from the processor side is referred to as a logical processor (hereinafter referred to as “LP”) for convenience.
FIG. 15 also shows control information such as the value of the program counter indicating the execution position of the program and the address indicating the storage position of the program and data, that is, the context memory 500 in which the context is stored. The context memory 500 is constituted by an SRAM and has a context storage area 501 in which contexts corresponding to the respective programs are stored.

The context storage area 501 is a predetermined storage area in the context memory 500, and stores context values corresponding to the respective programs. Further, FIG. 15 shows an oscillator 600 that generates a reference signal and a PLL 601 that generates a clock pulse to be supplied to the virtual multiprocessor 400 based on the reference signal.
In addition to these functional units, the following functional units not shown are related to the virtual multiprocessor 400. In other words, a program and data are stored, and a main memory made of DRAM and a cache memory for storing the above-mentioned program and data made of SRAM are connected to the virtual multiprocessor 400 via a bus.

  The virtual multiprocessor 400 includes a time allocation information storage register 402, a process execution unit 410, a process control unit 411, a register switching unit 412, a scheduling control unit 413, a first register group 414, and a second register group 415. A cycle counter 416, an external I / F 417, a DMA management unit 418, a request detection unit 419, a control register 420, a setting flag register 421, an LP state storage register 424, a processor state storage unit 425, A clock mask portion 427.

  The time allocation information storage register 402 stores information on time slots and programs. More specifically, this information defines the time slot program execution time frame and execution order, etc. 1) Time slot information, and 2) LP information for specifying candidate programs to be executed in each time slot 3) priority & mode information for limiting the range of program candidates, 4) idle option information for determining the contents of processing when no executable program candidate exists in the time slot, 5) Time option information for determining the contents of processing when a program being executed is interrupted.

These five types of information exist for each time slot, and are associated with each other in units of time slots. The first register group 414 and the second register group 415 are collections of registers for storing register values such as program counter values, addresses indicating program and data storage positions, which are context contents.
In accordance with an instruction from the scheduling control unit 413, the register switching unit 412 uses one of the first register group 414 and the second register group 415 when executing a program, that is, a current register. Select as a group. As in the first embodiment, this selection destination switching is referred to as register switching, and the register group that is not selected as the current register group is referred to as a standby register group.

  Incidentally, this register switching is sometimes called context switching. The process execution unit 410 includes a CPU for executing a program, and executes the above-described register switching, that is, based on the context stored in the current register group when the current register group is selected. The location of the program and data necessary for executing the program is specified, and the DMA management unit 418 is instructed to acquire the program and data necessary for executing the program.

Then, when data necessary for executing the program is acquired, the process executing unit 410 starts executing the program according to an instruction from the process control unit 411.
In addition, the process execution unit 410 outputs a wait code indicating that the execution of the program is interrupted to the process control unit 411 when the process cannot be continued during the execution of the program.

  The CPU described above is driven in synchronization with the clock pulse output from the PLL 601 via the clock mask unit 427. When this clock pulse is interrupted, program execution is also stopped. The LP status storage register 424 is a register for storing program status information indicating the status and attribute of each program and time slot setting information indicating the setting contents of each time slot.

  More specifically, the time slot setting information includes an ID (hereinafter referred to as “TS_ID”) for specifying the time slot and a code indicating the attribute of the time slot. Here, as a time slot attribute code, when the time slot is a time-driven type time slot prepared for executing a program based on the principle that it is executed on a regular basis, “TD” Further, “ED” is shown in the case of an event-driven time slot prepared for non-stationary program execution that is executed only when an event occurs.

  In other words, a time-driven time slot can be an execution target even if no event occurs, but an event-driven time slot cannot be an execution target unless an event occurs. The above-mentioned program status information includes an ID value that identifies a program, a code that identifies the program status, a code that indicates the attribute of the program, and a timing at which the program wakes up or recovers (hereinafter referred to as “wakeup timing”). .) Is shown.

There are six codes that specify the state of the program: waiting, ready, running, suspended-waiting, suspended-ready, and non-existent. Among these, “ready” and “running” indicate that the program can be executed at present. In particular, “running” indicates that the program is currently being executed.
“Waiting” and “suspended-waiting” indicate that the program cannot be executed at present.

Non-existent indicates that the program is not currently required to be executed. That is, the programs in the waiting, suspended-waiting, and non-existent states are outside the target range for program execution scheduling.
Further, when the program cannot be executed during the program execution and these codes transit to suspended-waiting, the TS_ID value of the time slot assigned at that time is attached to these codes.

  These codes transition to suspended-ready when the program can be executed, but remain with the above-described TS_ID value until the program is executed. As a code indicating the attribute of the program, “TD” is used when the program is a program whose principle is to be executed on a regular basis, and the program is executed only when an event occurs. In some cases, “ED” is indicated.

  As a code indicating the wake-up timing, a program that stores and executes a context after a register group that is a standby register group is released when a program execution request is generated, that is, a program with less processing time restrictions In the case of “n”, “n” is indicated, and in the case of a program that needs to be executed immediately until the context already stored in the standby register group is replaced, the code “e” is indicated.

  The control register 420 is a register for storing information for specifying the current time slot to be executed and the next time slot to be executed. More specifically, the control register 420 sets the current address value indicating the location where the time slot information corresponding to the time slot currently being executed is stored, and the next time slot to be executed. The next address value indicating the location where the corresponding time slot information is stored is stored.

  In the virtual multiprocessor 400, 16 time slots are set, and accordingly, there are 16 timeslot information. Of the 16 time slots, only four time slots are normally used for program execution. The time slot information is stored in the time allocation information storage register 402 so that the address values of the time slot information corresponding to the four time slots take consecutive values.

The control register 420 also stores the value of the start address having the smallest value and the value of the end address having the largest value among the above-described consecutive address values. Each time slot information includes a TS_ID value (any one of 0 to 15) for specifying each time slot.
The smaller the value of TS_ID, the smaller the value of the address where the time slot information is stored in the time allocation information storage register 402. TS_ID values from 0 to 3 are associated with the four time slots normally used for program execution. That is, time slot information indicating TS_ID value 0 is stored in the above-mentioned head address, and time slot information indicating TS_ID value 3 is stored in the above-mentioned end address. Yes.

  Each of the above four time slots has a superiority or inferiority relationship, and the time slot (TS_ID = 0) specified by the time slot information stored at the head address has the highest priority, and the address of the address toward the end address The higher the value, the lower the priority of the time slot stored at that address. The priority of this time slot indicates the degree to which real-time processing is required. In particular, in the time slot specified by the time slot information (TS_ID = 3) stored in the end address, real-time processing is guaranteed. do not do.

The processor state storage unit 425 is a register that stores information related to the state of the currently executing program. This information includes 1) a value of a switching prohibition flag indicating whether or not switching by the register switching unit 412 is currently prohibited, and 2) a common indicating whether or not a common interrupt process described later is currently being executed. It consists of the value of the interrupt flag.
When the switching is prohibited and the common interrupt is generated, the value of each flag is 1, and otherwise, the value is 0. The setting flag register 421 is a register for storing setting information regarding a program. More specifically, the setting information is a set of flags prepared for each program (hereinafter referred to as “setting flag group”), and the contents indicated by the values of the flags of these setting flag groups are as follows: For example, the type of unique interrupt processing request or event processing request that can be accepted by the own program.

  The request detection unit 419 includes a set of flags prepared for each program (hereinafter referred to as “unique flag group”) and a set of flags prepared for each program (hereinafter referred to as “common flag group”). Said). Each flag of this unique flag group has a one-to-one correspondence with each flag of the setting flag group stored in the setting flag register 421, and the bit string length of the bit data constituting the unique flag group is the setting flag group. Are the same as the bit string length of the bit data that constitutes, and the same bit position from the beginning indicates the value for the same item.

Some of these flags have information related to an item indicated by each flag, for example, related information such as an ID for specifying a program corresponding to the item. The request detection unit 419 updates the values of the unique flag group and the common flag group described above based on the arrangement and value of the bit data of the external signal received from the external I / F 417.
That is, the request detection unit 419 converts the received external signal into an understandable data format. The request detection unit 419 determines the external signal based on the updated value of each flag of the common flag group and the result of collating the value of the setting flag group in the setting flag register 421 with the value of the unique flag group. Know the contents.

Such processing is called external signal decoding processing for convenience. The contents of the external signal are roughly classified into two types: an interrupt processing request and an event processing request. The interrupt processing request further includes a specific interrupt processing request and a common interrupt processing request.
Here, the specific interrupt process request is a process execution request that can be executed only in a specific program, and only the specific program needs to execute the specific interrupt process.

The common interrupt processing request is an execution request for processing that can be executed in all programs, and these programs need to execute the common interrupt processing in common.
The above-described common flag group indicates the contents of the common interrupt processing request. These interrupt processes are executed by jumping from an executable program to a subroutine program. An event processing request is an execution request for a program that is in an inexecutable state or a program that is not currently required to be executed because an event that can be executed or an event that requires execution has occurred. .

  More specifically, the request detection unit 419 determines whether the received external signal indicates a specific interrupt processing request, a common interrupt processing request, or an event processing request by executing the above-described external signal decoding processing. When the determination result is a unique interrupt processing request, the request detection unit 419 identifies an ID (hereinafter, referred to as “unique P_ID”) that identifies a program that is an interrupt destination of the specific interrupt processing based on the related information described above. Also, an ID (hereinafter referred to as “unique SP_ID”) for specifying a subroutine program for executing the unique interrupt process is acquired.

If the determination result is a common interrupt processing request, the request detection unit 419 uses the above-described related information to identify an ID (hereinafter, “common”) that identifies a subroutine program that executes the common interrupt processing from the above external signal. SP_ID ").
If the determination result is an event processing request, the request detection unit 419 uses the above-described related information to identify an ID (hereinafter referred to as “event P_ID”) that identifies the program requested to be executed from the above external signal. .)

The request detection unit 419 outputs the acquired IDs to the scheduling control unit 413 in accordance with the acquisition described above.
In addition, when the request detection unit 419 receives from the scheduling control unit 413 that the execution of the processing corresponding to the above-described specific interrupt processing request, common interrupt processing request, and event processing request has been completed, Change the flag value to the default value.

  Further, when the determination result is an event processing request, the request detection unit 419 refers to the LP state storage register 424 prior to the output of the event P_ID described above to the scheduling control unit 413. At this time, if the attribute of the program specified by the event P_ID indicates “ED”, that is, if the program is an event-driven program that is executed non-stationarily, the request detection unit 419 will be described later. The P_ID is output to the scheduling control unit 413 only when the P_ID indicating the program having the program attribute “ED” has not been output to the scheduling control unit 413 from the latest reception time of the cycle head signal to the present. It shall be.

  The request detection unit 419 stores the P_ID for those for which the P_ID could not be output as a result of the above processing, and outputs it to the scheduling control unit 413 when the next cycle head signal is received. . The scheduling control unit 413 performs program execution scheduling within a program execution time frame for one time slot, and executes processing for returning the context to the standby register group (hereinafter referred to as “return processing”). A process for register switching (hereinafter referred to as “register switching process”) is performed, and a process for saving a context from the standby register group onto the context memory 500 (hereinafter referred to as “save process”) is performed. Has the function of (1-1. Scheduling) First, the above-described scheduling will be described.

  Scheduling consists of 1) time-driven scheduling, which is execution of routine processing, and 2) event-driven scheduling, which is scheduling of execution of programs that are not currently scheduled, and programs during program execution. There are three types of scheduling: 3) Abandoned scheduling.

As a preliminary process of these three scheduling and register switching processes, the scheduling control unit 413 includes (1) a target time slot search process, (2) a target TS allocation program search process, (3) a priority & mode information search process, (4) Perform idle option information search processing and (5) Time option information search processing.
(1-1-1. Target Time Slot Search Process)
The target time slot search process will be described below.

The scheduling control unit 413 selects one of the target addresses (hereinafter referred to as “object”) among the current address value, the next address value, the start address value, and the end address value stored in the control register 420. With reference to the value of “address”), the value of TS_ID in the time slot information stored in the target address in the time allocation information storage register 402 is referred to, and the time slot (hereinafter referred to as “target TS”). In addition, the program execution time frame assigned to this time slot, that is, the value of the basic cycle is obtained.
(1-1-2. Target TS allocation program search process)
The target TS allocation program search process will be described below.

The scheduling control unit 413 refers to the LP information associated with the target TS, identifies the four programs indicated by the LP information, and further assigns priorities (from 0 to 3) associated with each of these programs. Either)
(1-1-3. Priority & Mode Information Search Process) The priority & mode information search process will be described below.

The scheduling control unit 413 refers to the priority & mode information associated with the target TS, indicates which of 0 to 3 is indicated as the priority, and which of the Index mode and the Level mode is the mode. Know what is shown. The above-described index mode and level mode are setting information that defines how to assign a program to a time slot. When the index mode is indicated in the priority & mode information, the time is set for only one program. Attempts to assign to a slot, and if Level mode is indicated in the priority & mode information, only programs having a priority higher than the specified priority will be assigned to a time slot. It will be.
(1-1-4. Idle option information search process)
Hereinafter, idle option information retrieval processing will be described.

The scheduling control unit 413 refers to the idle option information associated with the target TS as the idle option information search process, and determines which of “SWITCH” and “MICRO-SLEEP” is indicated.
(1-1-5. Time option information search process)
The scheduling control unit 413 refers to the contents of the time option information associated with the target TS as the time option information search process, and any one of “LP_SWITCH”, “TS_SWITCH”, and “MICRO-SLEEP” is indicated. Is determined.
(1-2. Time-driven scheduling)
Hereinafter, time-driven scheduling will be described.

Time-driven scheduling is scheduling related to normal program execution. As long as event-driven scheduling and abandonment scheduling, which will be described later, are not executed, the scheduling control unit 413 executes time-driven scheduling and performs return processing, register switching processing, and save processing based on this.
The scheduling control unit 413 performs the following scheduling process as time-driven scheduling.
(1-2-1. Scheduling process)
Hereinafter, the scheduling process will be described. The scheduling control unit 413 performs the target time slot search process described above using the next address as the target address, specifies the target TS (hereinafter referred to as “next TS”), and then determines the target described above. A TS allocation program search process is performed to identify four programs associated with the next TS, and the priority associated with each of these programs is grasped.

  Next, the scheduling control unit 413 executes the priority & mode information search process described above to search for the contents of the priority & mode information associated with the next TS, that is, the priority and mode. To do. When the retrieved mode is the Level mode, the scheduling control unit 413 assigns all the programs associated with values less than or equal to the retrieved priority value to the above-described target TS (hereinafter, referred to as “program candidates”). "Candidate program").

  When the retrieved mode is the Index mode, the scheduling control unit 413 sets one program associated with the priority value retrieved by the priority & mode information retrieval process as the above candidate program. Further, the scheduling control unit 413 refers to the program state information corresponding to each candidate program in the LP state storage register 424, and detects whether each candidate program is executable.

More specifically, when the program status information of the candidate program indicates “ready”, the scheduling control unit 413 determines that the program is executable, and sets the program as a candidate for allocation to the next TS described above. To enable. A candidate program validated in this way is referred to as a valid candidate program.
When there are a plurality of valid candidate programs for one next TS, the scheduling control unit 413 assigns the valid candidate program associated with the lowest priority value to this next TS. set to target.

In addition, when there is one valid candidate program for one next TS, the scheduling control unit 413 sets the valid candidate program as an allocation target to this next TS.
As the valid candidate program is assigned to the next TS, the scheduling control unit 413 associates the ID for identifying the valid candidate program with the time slot information of the next TS. Furthermore, the scheduling control unit 413 deletes the ID that identifies the valid candidate program from the time slot information when the execution of the valid candidate program is completed.

  If there is no valid candidate program for one next TS, the scheduling control unit 413 performs subsequent processing based on the content of information obtained by performing idle option information search processing. Determine the contents. More specifically, when the content of the above-described information indicates “MICRO-SLEEP”, the scheduling control unit 413 does not set any program to be allocated to the next TS.

A time slot to which no program is assigned in this way is called an empty time slot.
When the content of the above information indicates “SWITCH”, the scheduling control unit 413 adds the value of the next address to 1 (however, only when the next address is the termination address, Value) is a new next address, and the above scheduling process is repeated.

After performing the time-driven scheduling as described above, the scheduling control unit 413 performs a return process, a register switching process, and a save process.
(1-3. Event Driven Scheduling) Event driven scheduling will be described below. Event-driven scheduling is scheduling that is executed in place of the time-driven scheduling when a request to execute the following program that is currently not subject to scheduling occurs.

  The above-mentioned program in which an execution request has occurred is a program having an ED attribute that has transitioned from a waiting state to ready, and a program that has a TD or ED attribute and is suspended. -The program has been suspended-ready from the waiting or running state. Note that the scheduling control unit 413 determines whether or not the above-described program execution request is generated immediately before the time-driven scheduling is performed.

When the scheduling control unit 413 receives the event P_ID from the request detection unit 419, the scheduling control unit 413 identifies the program by the received event P_ID, refers to the LP state storage register 424, and determines the status of the program, the value of TS_ID, the attribute of the program, The wake-up timing is grasped, and the following processing is performed according to the grasped contents.
(1-3-1. Recovery event processing)
The scheduling control unit 413 sets the current program state specified by the event P_ID in the LP state storage register 424 to “ready” when the state of the specific program indicates waiting, the attribute indicates “TD”, and the wake-up timing indicates “n”. Transition.

The scheduling control unit 413 performs a recovery process, a register switching process, and a saving process that are performed after time-driven scheduling after performing such a recovery event process.
(1-3-2. Emergency recovery event processing)
When the state of the specific program indicates suspended-waiting, the attribute indicates “TD”, and the wakeup timing indicates “e”, the scheduling control unit 413 changes the state of the specific program to suspended-ready.

Then, the scheduling control unit 413 specifies a time slot (hereinafter referred to as “specific TS”) from the value of TS_ID attached to the code indicating the state of this specific program, and the above-mentioned specific program is assigned to this specific TS. assign. After performing such an emergency recovery event process, the scheduling control unit 413 performs an emergency return process described later, and performs an emergency register switch process described below instead of the register switch process performed after time-driven scheduling. carry out.
(1-3-3. Event wake-up process) When the state of the specific program is suspended-waiting, the attribute is “TD”, and the wake-up timing is “n”, it is specified by the event P_ID in the LP state storage register 424. Transition the current program state to suspended-ready.

  Furthermore, when the status of the specific program is waiting or suspended-waiting, the attribute is “ED”, and the wake-up timing indicates “n”, the scheduling control unit 413 indicates that the status of the program specified by the received event P_ID is waiting. If so, change it to ready. If suspended-waiting, change it to suspended-ready. In addition, when the emergency register switching process at the wakeup timing “e” performed after event-driven scheduling occurs, the scheduling control unit 413 changes the state of the program being executed from running regardless of the attribute. Change to suspended-ready.

When this event wake-up process is performed, the scheduling control unit 413 performs an early return process, which will be described later, instead of the return process performed after time-driven scheduling, and is triggered by the arrival of the count value 0 signal as a trigger. Perform the switching process. Such event processing is called event wake-up processing.
(1-3-4. Emergency event wake-up process) When the status of the specific program is waiting or suspended-waiting, the attribute is “ED”, and the wake-up timing is “e”, the scheduling control unit 413 displays the specific program If the status is waiting, change it to ready, and if it is suspended-waiting, change it to suspended-ready.

When this emergency event wake-up process is performed, the scheduling control unit 413 performs an emergency return process, which will be described later, instead of a return process performed after time-driven scheduling, and a register switching process performed after time-driven scheduling Instead, an emergency register switching process, which will be described later, is performed. Such event processing is called emergency event wake-up processing.
(1-4. Abandonment scheduling)
Abandonment scheduling performed when the scheduling control unit 413 receives a wait code from the processing execution unit 410 via the processing control unit 411 or when receiving a cache miss signal described later from the DMA management unit 418 will be described.

  The above-described wait code is a code indicating that the time allocated to the running program is abandoned when the running program cannot be continued. This wait code includes “vmp_wait And “vmp_sus”. The “vmp_wait” code is a code issued by the process execution unit 410 when the above-described abandonment time is expected to be relatively long, and the “vmp_sus” code may be relatively short. This code is issued by the process execution unit 410 when expected.

  When the scheduling control unit 413 receives the “vmp_wait” code, the “vmp_sus” code, and the cache miss signal from the process execution unit 410 via the process control unit 411, the scheduling control unit 413 stores the execution status stored in the LP state storage register 424. Update the program state. More specifically, when the “vmp_wait” code is received, the scheduling control unit 413 changes the state of the program being executed from running to waiting.

Further, when the “vmp_sus” code is received or the cache miss signal is received, the scheduling control unit 413 changes the state of the program being executed from running to suspended-waiting. Then, the scheduling control unit 413 performs the time option information search process described above using the current address as the target address.
When the received wait code is “vmp_sus”, the scheduling control unit 413 performs an emergency register switching process described later, performs a save process, and further performs a control register value update process described later regardless of the time option information. carry out.

Further, even when the received wait code is “vmp_wait” and the content of the time option information indicates “TS_SWITCH”, the scheduling control unit 413 performs an emergency register switching process described later, as described above, The saving process is performed, and further a control register value updating process described later is performed.
In the standby register group immediately before the emergency register switching process is performed, the return process by time-driven scheduling or the early return process after the event wake-up process performed by event-driven scheduling is performed.

  In addition, when the received wait code is “vmp_wait” and the content of the time option information indicates “LP_SWITCH”, the scheduling control unit 413 has a valid candidate program in the time slot currently being executed. If there is a valid candidate program, the register value of the context corresponding to the program having the highest priority among the valid candidate programs (or the program when there is one valid candidate program) Is stored in the standby register group, that is, recovery is performed.

Thereafter, the scheduling control unit 413 performs an emergency register switching process, which will be described later, and performs a save process.
In addition, when there is no valid candidate program, and when the content of the time option information indicates “MICRO-SLEEP”, the scheduling control unit 413 does not involve updating the register values in the current register group in the process execution unit 410. The processing control unit 411 is instructed to execute a later-described NOP which is a program execution, and the following processing is performed.

  That is, the scheduling control unit 413 immediately starts outputting the mask signal to the clock mask unit 427, and further refers to the contents of the context stored in the standby register group, and is necessary for executing the program corresponding to this context. The DMA management unit 418 is instructed to acquire the value of the address of the memory where the correct data is stored and to write the data stored at this address to the cache memory.

Further, the scheduling control unit 413 stops the output of the mask signal to the clock mask unit 427 when register switching or emergency register switching is performed next time. When the scheduling control unit 413 receives a count value 0 signal from the cycle counter 416, the scheduling control unit 413 performs a register switching process and a saving process, which will be described later.
Next, processing related to restoration, such as restoration processing, emergency restoration processing, and early restoration processing, will be described.
(1-5-1. Return processing)
The return processing is processing for storing the register value in the standby register group, which is performed by the scheduling control unit 413 after the time-driven scheduling is performed.

When the standby register group is released, that is, when the saving is completed, the scheduling control unit 413 converts the register value of the program context allocated by the above time-driven scheduling into the above-described standby register group. The DMA management unit 418 is instructed to store.
(1-5-2. Emergency return processing)
The emergency return process is a case where, as a result of performing event-driven scheduling, when the wake-up timing of the specific program described above indicates “e”, the register value executed by the scheduling control unit 413 is stored in the standby register group. Process.

  The scheduling control unit 413 saves the register value stored in the standby register group and immediately corresponds to the specific program when the execution of the emergency recovery event process or emergency event wake-up process described above is completed as the emergency return process. The DMA management unit 418 is instructed to store the register value of the context in the above-described standby register group, that is, to perform an urgent return.

Note that the above-described saving and restoring can be executed in units of registers, not in register groups. By performing saving and restoring in sequence for each register, these saving and restoration are performed in a pseudo-parallel manner. Will be implemented.
(1-5-3. Early return processing)
The early return process is a process in which event-driven scheduling is performed, and when the wake-up timing of the specific program described above indicates “n”, the register value executed by the scheduling control unit 413 is stored in the standby register group. Process.

  As an early return process, the scheduling control unit 413 immediately stores the register value of the context corresponding to the specific program in the above-described standby register group when the standby register group is released, that is, when the saving is completed. Instructs the DMA management unit 418. Note that the scheduling control unit 413 initializes the register values of the standby register group prior to the above-described storage, similarly to the emergency return processing.

Subsequently, processing related to register switching such as register switching processing and emergency register switching processing will be described.
(1-6-1. Register switching processing)
When the scheduling control unit 413 receives a count value 0 signal from the cycle counter 416, the scheduling control unit 413 performs basic cycle adjustment processing described later, and performs register switching so as to perform register switching after performing switching timing confirmation processing described later. The unit 412 is instructed.

  Further, when the scheduling control unit 413 receives a notification that the register switching is completed from the register switching unit 412, the scheduling control unit 413 outputs the value of the basic cycle to the cycle counter 416, and further, a real-time storage process described later and a control described later. Perform register value update processing. At this time, if the time slot that is the execution target is the empty time slot described above, the scheduling control unit 413 outputs the basic cycle value to the cycle counter 416, and the process execution unit 410 receives the NOP. The processing control unit 411 is instructed to be executed, the mask signal output to the clock mask unit 427 is started, and the contents of the context stored in the standby register group are referred to, and the program corresponding to this context The DMA management unit 418 is instructed to acquire the value of the address of the memory in which the data necessary for the execution is stored and to write the data stored at this address to the cache memory.

The scheduling control unit 413 stops outputting the mask signal to the clock mask unit 427 when register switching or emergency register switching is performed next time.
(1-6-1-1. Basic cycle adjustment process)
Hereinafter, the basic cycle adjustment process will be described.
The scheduling control unit 413 refers to the LP state storage register 424 immediately before register switching, and determines whether or not the state of the program corresponding to the register value group stored in the standby register group is suspended-ready. In the case of suspended-ready, a later-described actual count value is acquired from a later-described remaining cycle value storage area in the standby register group.

Then, at the next program execution, the scheduling control unit 413 replaces the regular basic cycle indicated in the time slot information of the time slot to which this program is assigned with this actual count value by executing this program. Time, that is, the basic cycle of the time slot to which this program is assigned.
Furthermore, when the TS_ID value of this time slot is 3, that is, when the time slot does not guarantee real-time processing, the scheduling control unit 413 acquires the time lag value in the time slot information in which the TS_ID value indicates 3. Then, a value obtained by subtracting the time lag value from the above basic cycle value is used as a new basic cycle at the next program execution, and the time lag value in the time slot information is updated to zero.

When the scheduling control unit 413 receives a notification of the start of program execution from the processing control unit 411, the scheduling control unit 413 outputs the basic cycle value obtained as described above to the cycle counter 416.
(1-6-1-2. Switching timing confirmation processing)
Hereinafter, the switching timing confirmation process will be described.

  When executing a program in a time-sharing manner, the execution of the program cannot be terminated at an arbitrary time due to, for example, shared resources used for executing the program. That is, register switching cannot be performed at an arbitrary time. For this reason, the scheduling control unit 413 first requests the processing control unit 411 to end the program, ends the program at a point where the execution of the program can be ended, and checks whether register switching is possible. .

More specifically, after the above request, the scheduling control unit 413 refers to the value of the switching prohibition flag and the value of the common interrupt flag in the processor state storage unit 425, and sets the value of the switching prohibition flag and the common interrupt flag. When the value is 0, it is possible to switch the register, and when the value of the switching prohibition flag and the value of the common interrupt flag are 1, it is determined that the register cannot be switched.
(1-6-1-3. Real-time storage processing)
The real time storage process will be described below.

  When the scheduling control unit 413 instructs the register switching unit 412 to perform register switching, the scheduling control unit 413 acquires the count value of the cycle counter 416 at that time, and this count value (hereinafter referred to as “actual count value”). Takes a positive value and receives the “vmp_sus” code that triggers the register switching described above, this actual count value is set to the register group that becomes the standby register group as a result of the register switching. Write to a predetermined area (hereinafter referred to as “residual cycle value storage area”).

In this way, the actual count value of the program that has finished executing is attached to the context of this program, and is stored in the context memory 500 as the context is saved. The actual count value at the time of program execution can be acquired.
Further, when the actual count value takes a negative value, or when the actual count value takes a positive value and the “vmp_wait” code that triggers the register switching is received, the scheduling control unit 413 performs a target time slot search process using the end address as a target address, specifies the storage location of the time slot information of the specified time slot (TS_ID = 3), and is stored in this time slot information. The time lag value is updated by adding the actual count value from the time lag value.

Note that, for the reason described in the description of the switching timing confirmation process described above, the switching timing cannot be strictly matched with the basic cycle of the time slot. The value takes a negative value, and the actual count value is less than the basic cycle of the time slot to be executed, for example, when register switching is performed by interrupting program execution. Therefore, it takes a positive value.
(1-6-1-4. Control register value update processing)
Hereinafter, the control register value update processing will be described.

The control register value update process is a data update in the control register 420 that is executed in accordance with the following scheduling. The implementation of the above-mentioned scheduling means that 1) implementation of time-driven scheduling and 2) implementation of abandonment scheduling when the content of the time option information indicates “TS_SWITCH”.
The scheduling control unit 413 sets the current address value as a new current address value and a value obtained by adding 1 to the next address value (provided that the next address is a terminal address only if the next address is a terminal address). Address value) is set as a new next address, and accordingly, the current address value and the next address value stored in the control register 420 are updated.

Also, the scheduling control unit 413 outputs a cycle start signal to the request detection unit 419 when the current address value is shifted from the end address value to the start address value.
(1-6-2. Emergency register switching process)
Hereinafter, the emergency register switching process will be described.

  In the abandon scheduling time option process, the scheduling control unit 413 completes the emergency return process when the content of the time option information indicates “TS_SWITCH” and after the emergency recovery event process and the emergency event wake-up process during event-driven scheduling. Sometimes, the register switching unit 412 is instructed to perform the above-described basic cycle adjustment processing and further perform the above-described switching timing confirmation processing and then perform register switching.

When the scheduling control unit 413 receives a notification that the register switching has been completed from the register switching unit 412, the scheduling control unit 413 outputs the basic cycle value to the cycle counter 416, and further performs the above-described real-time storage processing.
(1-7-1. Saving process)
When the scheduling control unit 413 receives a notification that the register switching is completed from the register switching unit 412, the scheduling control unit 413 displays the register value of the context stored in the register group that becomes the standby register group by this register switching. The DMA management unit 418 is instructed to overwrite the saved storage area on the context memory 500, that is, to save.

Note that, immediately before the above-described register switching is performed, the above-described saving is performed even when the time slot that is the execution target is the empty time slot described above.
(1-8-1. Specific interrupt processing)
When the scheduling control unit 413 receives the unique P_ID and the unique SP_ID from the request detection unit 419, the scheduling control unit 413 performs the following processing.

  That is, the scheduling control unit 413 refers to the LP state storage register 424 and determines whether or not the program specified by the received unique P_ID is currently being executed. Via the unit 411, the process execution unit 410 is instructed to jump to the subroutine program specified by the received unique SP_ID and execute the process.

If the program identified by the received unique P_ID is not currently being executed, the scheduling control unit 413 identifies a program that is an interrupt destination of this subroutine program by referring to the flag in the request detection unit 419. When this specified program is executed, the process execution unit 410 is instructed to jump to this subroutine program via the process control unit 411 and execute the process.
(1-8-2. Common interrupt processing)
Further, when the scheduling control unit 413 receives the common SP_ID from the request detection unit 419, the scheduling control unit 413 immediately jumps to the subroutine program specified by the common SP_ID received by the processing execution unit 410 via the processing control unit 411 and performs processing. When it is instructed to execute and a notification of execution start of the subroutine program is received from the processing control unit 411, the cycle counter 416 is instructed to interrupt the countdown.

  When the scheduling control unit 413 receives a notification indicating that the execution of the subroutine program specified by the common SP_ID is completed from the processing control unit 411, the scheduling control unit 413 instructs the cycle counter 416 to restart the countdown. Is output. As described above, the scheduling control unit 413 has a function of executing various processes.

  The process control unit 411 has a function of managing the execution status of the program in the process execution unit 410, monitors the program execution status of the process execution unit 410, and starts and ends the program execution in the process execution unit 410; Understand the start timing and end timing of interrupt processing. The process control unit 411 notifies the scheduling control unit 413 that these timings have arrived each time these timings arrive.

  When the process control unit 411 receives a wait code from the process execution unit 410, the process control unit 411 outputs the wait code to the scheduling control unit 413. Furthermore, the process control unit 411 sets the value of the switching prohibition flag in the processor state storage unit 425 to 1 (default value is 0) when the program execution in the process execution unit 410 cannot be interrupted, and the process execution unit In 410, while the subroutine program specified by the common SP_ID is being executed, the value of the common interrupt flag in the processor state storage unit 425 is set to 1 (the default value is 0).

  Further, when the processing control unit 411 receives a register switching prohibition command from the processing execution unit 410, the processing control unit 411 sets the value of the switching prohibition flag in the processor state storage unit 425 to 1, and from the processing execution unit 410, the register switching prohibition release instruction Is received, the value of the switching prohibition flag is set to zero. In addition, when receiving an instruction to execute NOP from the scheduling control unit 413, the process control unit 411 causes the process execution unit 410 to perform NOP execution.

The DMA management unit 418 is a functional unit that smoothly performs and manages DMA transfer, and performs DMA transfer based on requests from the respective functional units such as the processing execution unit 410 and the scheduling control unit 413.
Further, when the DMA transfer requested by each functional unit is completed, the DMA management unit 418 outputs a signal indicating the fact (hereinafter referred to as “transfer completion signal”) to the functional unit and the scheduling control unit 413. When a cache miss occurs in response to a request from the processing execution unit 410 and a program and data are acquired from the cache memory, a signal indicating that a cache miss has occurred (hereinafter referred to as “cache miss signal”). ) Is output to the scheduling control unit 413.

  The external I / F 417 is an interface connected to an external device such as an external processor, and outputs a signal received from the outside to the scheduling control unit 413 and the request detection unit 419. The cycle counter 416 includes a clock counter, and when receiving a basic cycle value from the scheduling control unit 413, the cycle counter 416 starts counting down using this value as an initial value of the counter.

The cycle counter 416 decrements one by one every clock from the initial value described above, and when the value becomes 0, when the value becomes 0, a signal (hereinafter referred to as “count”) indicating the fact to the scheduling control unit 413. "Value 0 signal") is output.
Further, the cycle counter 416 interrupts and restarts the countdown based on an instruction from the scheduling control unit 413, and further outputs an actual count value that is a counter value at the instructed time point to the scheduling control unit 413.

The clock mask unit 427 has a function of blocking the signal path of the clock pulse to the processing execution unit 410 while receiving the mask signal from the scheduling control unit 413.
(2. Data) FIG. 16 is a diagram showing the contents of information stored in the time allocation information storage register 402 and the LP state storage register 424.
The time allocation information storage register 402 stores 1) time slot information, 2) LP information, 3) priority & mode information, 4) idle option information, and 5) time option information. These pieces of information are prepared for each time slot and are associated with each other.
(2-1-1. Time Slot Information) The time slot information includes a TS_ID value for specifying a time slot and a basic cycle value.

The time slot information with a TS_ID value of 3 further includes a time lag value.
When scheduling is performed by the scheduling control unit 413, the ID of this program is associated with the value of TS_ID of the time slot to which the program is assigned.
(2-1-2. LP information) The LP information stores information about programs that are candidates for assignment to time slots.

The attributes and number of programs that are candidates for assignment to one time slot differ depending on the attributes of the assignment time slot. That is, a program having the TD attribute is always assigned to a time slot having the TD attribute.
Also, four candidate programs having the TD attribute are prepared for each time slot having the TD attribute.

On the other hand, a program having the ED attribute is always assigned to a time slot having the ED attribute.
Further, only one candidate program having the ED attribute is prepared for each time slot having the ED attribute. Each LP information is associated with time slot information corresponding to the above-mentioned time slot of the assignment destination.

  The LP information includes a combination of an ID value for specifying a program, a value indicating a priority, and an address value on the context memory 500 in which a context corresponding to the program is stored as an allocation candidate. As many programs as are stored. The value indicating the priority is one of 0, 1, 2, and 3, and is set so that the priorities of the programs that are candidates for allocation do not overlap.

Note that the value indicating the priority when the number of allocation candidate programs is one is zero.
(2-1-3. Priority & Mode information)
The priority & mode information stores information related to the designation of programs that are candidates for assignment to time slots.

That is, the priority & mode information stores one of 0, 1, 2, and 3 indicating the priority, and the code “I” or “L” indicating the mode. Here, the code “I” indicates the Index mode, and the code “L” indicates the Level mode. By changing the contents of the priority & mode information, the range of valid candidate programs changes, so that the execution frequency of each candidate program can be brought close to a design-preferable value.
(2-1-4. Idle option information)
The idle option information stores information for determining the program execution operation when all the programs to be assigned to the time slots are in an inexecutable state.

That is, in the idle option information, a code “MICRO-SLEEP” indicating power saving or a code “SWITCH” indicating highly efficient program execution is stored.
(2-1-5. Time option information)
The time option information stores information for determining the program execution operation after the interruption when the program being executed is interrupted.

  That is, in the time option information, when a running program is interrupted, another executable program associated with the time slot to which this program belongs is assigned to the time slot instead of this program. A code “LP_SWITCH”, a code “TS_SWITCH” indicating that the next time slot is to be executed, or a code “MICRO-SLEEP” indicating power saving is stored.

The LP status storage register 424 stores 1) program status information and 2) time slot setting information.
(2-2. Program status information)
The program status information stores, for each program, an ID for identifying the program, a code indicating the program status, a program attribute, and a code indicating the timing to wake up or recover the program.

  There are six codes indicating the program state: waiting, suspended-waiting, ready, suspended-ready, running, and nonexistent. The waiting code indicates that the execution time of the program is currently abandoned and the program is executed in the program execution time frame of the normal time slot at the next program execution, and the suspended-waiting code is currently It is shown that the execution time of the program is abandoned, and the time (maximum 1 slot) that is not used after being abandoned is used as the program execution time at the next program execution.

The ready code indicates that the program is currently executable, and the suspended-ready code indicates that the program that has been the suspended-waiting code is currently executable.
In addition, when the program execution time is abandoned, when the state transits to a waiting code, a suspended-waiting code, and a suspended-ready code, these codes were assigned to when the abandonment occurred. The value of TS_ID of the time slot is attached.

Since the value of TS_ID is not cleared until it is executed, it may be added to the ready code and the suspended-ready code. The running code indicates that the program is currently in an executable state and is being executed. The nonexistent code indicates that the program is currently outside the scheduling target range.
Here, “outside the scope of scheduling” means a state of a program that cannot be a candidate program at the present time. Incidentally, a candidate program that is in a waiting or suspended-waiting state is excluded from candidate scheduling. Note that the program recovery described above means that the program with the “TD” attribute has changed from the waiting state to the ready state, or that the program with the “TD” attribute has the timing “e” described above from the suspended-waiting state. ”Means suspended-ready.

  The wake-up of the program means that the program with the “TD” attribute is suspended-ready at the timing “n” described above from the suspended-waiting state, or the program with the “ED” attribute is waiting or It means that it has changed from the suspended-waiting state to the ready or suspended-ready state, respectively. It should be noted that the timing for waking up or recovering such a program is generically called a wake-up timing in this embodiment as described above.

  When the event occurs, the code indicating the attribute of the program falls within the scope of the candidate scheduling, and the event that is assigned to the time slot and executed in the event-driven scheduling regardless of the predetermined order determined by the time-driven scheduling When an event occurs with the code “ED” indicating that it is a driven type program, it will fall within the candidate scheduling target range, but it will be assigned to a time slot and executed after waiting for a predetermined order by time-driven scheduling There is a code “TD” indicating that the program is a time-driven program.

That is, an ED attribute program transitions from a waiting or suspended-waiting state to ready or suspended-ready, respectively, and is assigned to a time slot by event-driven scheduling, while a TD attribute program transitions from waiting to ready, Assigned to time slots by time-driven scheduling.
However, as an exception, even for time-driven programs, if an event occurs, it is within the scope of candidate scheduling, and in event-driven scheduling, it is assigned to a time slot regardless of the predetermined order determined by time-driven scheduling. May be executed. That is, this exception is a case where a time-driven program transitions from a suspended-waiting state to a suspended-ready and is allocated to a time slot by event-driven scheduling.

  The code indicating the wake-up timing is a code indicating that it is necessary to execute the program urgently without waiting until the count value 0 signal is received even if the context that has already been stored in the standby register group is deleted. There is a code “n” indicating that “e” and the program is to be executed after the storage in the standby register group is completed and the count value 0 signal is received after the saving process is completed from the standby register group.

The setting flag register 421 stores a setting flag group prepared for each program. This set flag group is for specifying the contents of interrupts and events allowed by each program, and is the same as the set flag group described in the first embodiment except that it is prepared for each program. Therefore, detailed description is omitted here.
As shown in FIG. 15, the request detection unit 419 stores an LP unique flag group and one common flag group prepared for each program. The LP unique flag group is information related to a unique interrupt, and indicates what kind of unique interrupt execution request is currently generated for which program. This LP specific flag group apparently exists for each program, but the actual state is one bit string data, and each flag exists in the bit position corresponding to the program that allows the interrupt and the content of the specific interrupt. Yes.

That is, when an interrupt of the contents is permitted in a certain program, the value of the LP specific flag (default value is 0) existing in the bit position corresponding to the contents of the program and the interrupt is 1. Since the data structure is the same as the completion notification flag described in the first embodiment, detailed description thereof is omitted here.
The common flag group is a collection of flags indicating whether or not a common interrupt execution request is generated. Here, the execution request for the common interrupt means an execution request for a subroutine program that can be executed in any program. The actual state of the common flag group is one bit string data, and there is a bit position specific to the subroutine program to be interrupted and executed.

That is, when there is a subroutine program in which a common interrupt request has occurred, the value of the flag at the bit position corresponding to the subroutine program is 1 (the default value is 0). The processor state storage unit 425 stores the value of the switching prohibition flag and the value of the common interrupt flag.
The switch prohibition flag indicates, for example, that a shared resource is being accessed during program execution, and that it is currently impossible to perform register switch because the program cannot be interrupted immediately. While it cannot be executed, it takes a value of 1 (default value is 0). The value of the switch prohibition flag can be rewritten by an instruction issued by the program being executed.

The common interrupt flag indicates that a common interrupt process is currently being executed, and takes a value of 1 (default value is 0) while the common interrupt process is being executed.
(3. Operation)
Hereinafter, a process for realizing efficient program execution when a virtual multiprocessor 400 executes a program in a pseudo-parallel manner by one processor will be described.

  FIG. 17 is a flowchart showing processing executed in the virtual multiprocessor 400. The process execution unit 410 starts executing the program based on an instruction from the process control unit 411 (step S100). In parallel with this program execution, the scheduling control unit 413 performs a saving process for register values stored in the standby register group (step S101), and the request detection unit 419 receives from the external I / F 417. Based on the external signal, it is determined whether an event processing request has occurred (step S102).

  If an event processing request has occurred, the request detection unit 419 outputs the event P_ID to the scheduling control unit 413. The scheduling control unit 413 performs event-driven scheduling based on the event P_ID (step S103). Note that the content of the process performed after the event-driven scheduling is performed differs depending on the result of the event-driven scheduling.

  When an event processing request has not occurred, the scheduling control unit 413 sets the target TS as the next TS (step S104), performs time-driven scheduling (step S105), and further performs return processing (step S106). Then, the request detection unit 419 determines whether or not an interrupt processing request has occurred (step S107), and when an interrupt processing request has occurred, the unique P_ID, the unique SP_ID, and the common, depending on the type of interrupt. SP_ID and the like are output to the scheduling control unit 413.

  When receiving these IDs, the scheduling control unit 413 executes interrupt processing (step S108). On the other hand, when an interrupt processing request has not occurred, the scheduling control unit 413 determines whether or not the program execution time has been abandoned or a cache miss has occurred based on the wait code and the cache miss signal (step S109). If these have occurred, abandonment scheduling is performed (step S110).

  Note that the content of the processing performed after the abandonment scheduling is performed differs depending on the execution result of the abandonment scheduling. On the other hand, if the abandonment of the program execution time or the cache miss has not occurred, the scheduling control unit 413 ends the program execution in the process execution unit 410 when receiving the count value 0 signal from the cycle counter 416 (step S111). After executing the register switching process (step S112), the process returns to step S100 where the process execution unit 410 starts program execution.

FIG. 18 is a flowchart showing the contents of time-driven scheduling performed by the scheduling control unit 413. First, the operation when the target TS is the next TS will be described. The scheduling control unit 413 performs the target time slot search process following the process of step S104 in FIG. 18A (step S120).
More specifically, the scheduling control unit 413 refers to the time slot information stored in the next address in the time allocation information storage register 402, identifies the next TS by TS_ID that identifies the time slot, and further Get the value of the basic cycle assigned to the time slot. Then, the scheduling control unit 413 performs a target TS allocation program search process (step S121).

More specifically, the scheduling control unit 413 refers to the LP information associated with the next TS, identifies the candidate program indicated by this LP information, and further assigns the priority associated with each of these programs. To figure out. Then, the scheduling control unit 413 performs priority & mode information search processing (step S122).
More specifically, the scheduling control unit 413 refers to the priority & mode information associated with the next TS, indicates which one of 0 to 3 is indicated as the priority, and further indicates the Index mode as the mode. And grasp which of the Level mode is shown.

Also, the scheduling control unit 413 performs idle option information search processing (step S123).
More specifically, the scheduling control unit 413 refers to idle option information associated with the next TS, and determines which of “SWITCH” and “MICRO-SLEEP” is indicated. Subsequently, the scheduling control unit 413 performs scheduling processing (step S124).

  More specifically, the scheduling control unit 413 identifies four programs associated with the next TS obtained by the target time slot search process, and associates them with each of these programs by the target TS allocation program search process. Understand the priorities that have been assigned. Then, the scheduling control unit 413 selects candidate programs from the above four programs based on the priority and mode obtained by the priority & mode information search process.

  Further, the scheduling control unit 413 refers to the program state information corresponding to each candidate program in the LP state storage register 424, detects whether each candidate program can be executed, and determines whether or not each candidate program can be executed. Is elected. At this time, when there are a plurality of valid candidate programs, the valid candidate program associated with the smallest priority value is set as the allocation target to the next TS.

  If there is no valid candidate program, the scheduling control unit 413 determines the content of subsequent processing based on the content of information obtained by performing the idle option information search processing. That is, when the content of the above information indicates “MICRO-SLEEP”, the scheduling control unit 413 does not set any program to be assigned to the next TS.

In this case, the scheduling control unit 413 causes the process execution unit 410 to execute NOP during the period when the next TS is an execution target, and causes the clock mask unit 427 to block the supply of the clock pulse to the process execution unit 410.
When the content of the above information indicates “SWITCH”, the scheduling control unit 413 adds the value of the next address to 1 (however, only when the next address is the termination address, Value) is set as a new next address, and the scheduling process of steps S120 to S124 is repeatedly performed.

When the above processing ends, the process proceeds to step S106 described above for determining whether or not an interrupt processing request has occurred. The operation when the target TS is the current TS will be described later. FIG. 19 is a flowchart showing the contents of event-driven scheduling performed by the scheduling control unit 413.
The scheduling control unit 413 specifies a program based on the event P-ID received from the request detection unit 419.

In addition, when the program being executed is interrupted by switching the emergency register by event-driven scheduling, the scheduling control unit 413 specifies the interrupted program (step S130).
Further, the scheduling control unit 413 refers to the LP state storage register 424 to determine the attribute, state, and wake-up timing of this program. Then, the scheduling control unit 413 determines whether or not any of the following (1) to (3) is satisfied (step S131).
(1) The attribute of the program is ED.
(2) The attribute of the program is TD, the program state is suspended-waiting, and the wake-up timing is “n”.
(3) The emergency register was switched by the event-driven scheduling for the program that was in the running state.

  If the result of this determination is not applicable, that is, “No”, the scheduling control unit 413 refers to the LP state storage register 424 to determine whether or not the wake-up timing of this program is “e”. If it is not “e”, that is, if it is “n”, recovery event processing is performed. More specifically, the scheduling control unit 413 changes the status of this program indicated in the LP status storage register 424 to “ready” if it is waiting.

Thereafter, the process proceeds to step S104 described above in which time-driven scheduling is performed.
When the determination result in step S132 is “e”, the scheduling control unit 413 performs the emergency recovery event process described above (step S134), and performs the emergency return process described above (step S134). S135) Further, after performing the emergency register switching process described above (step S136), the process proceeds to the above-described step S100.

  Further, in the above-described step S131, if the result of determination is applicable, that is, if “Yes”, the scheduling control unit 413 refers to the LP state storage register 424, and the wake-up timing of this program is “e”. If it is not “e”, ie, “n”, the event wake-up process described above is performed (step S141), and the early return process described above is performed. (Step S142), the process proceeds to Step S107 described above.

  In the determination in step S137, when the wake-up timing is “e”, the scheduling control unit 413 performs the emergency event wake-up process described above (step S138), and performs the emergency return process described above. (Step S139), and after performing the emergency register switching process described above (step S140), the process proceeds to step S100 described above.

FIG. 20 is a flowchart showing the contents of the interrupt process performed in step S108 described above. The scheduling control unit 413 determines whether a request for common interrupt processing is generated based on the unique P_ID, the unique SP_ID, and the common SP_ID received from the request detection unit 419 (step S150).
When a request for common interrupt processing occurs, that is, when a common SP_ID is received from the request detection unit 419, the scheduling control unit 413 performs a cycle counter while the subroutine program specified by this common SP_ID is being executed. When the countdown at 416 is interrupted (steps S151 to S152), the request for the common interrupt process is not generated and the request for the specific interrupt process is generated, that is, the request detection unit 419 generates the unique P_ID and the unique When the SP_ID is received, the scheduling control unit 413 does nothing particularly about the countdown in the cycle counter 416 while the subroutine program specified by the unique SP_ID is being executed (step S153). Step S154).

  After the above processing is executed, the process proceeds to step S109 described above. FIG. 21 is a flowchart showing the contents of abandonment scheduling performed in step S110 described above. The scheduling control unit 413 determines whether or not a cache miss signal has been received from the DMA management unit 418 (step S160). If the cache miss signal has been received, the scheduling control unit 413 changes the program state of the program being executed to suspended-waiting. (Step S161) The time option information search process described above is performed (Step S162).

  If the cache miss signal has not been received, the scheduling control unit 413 further determines whether or not the “vmp_sus” code has been received (step S163). If the “vmp_sus” code has been received, The program state of the program is changed to suspended-waiting (step S161), and the time option information search process described above is performed (step S162).

In the determination in step S163 described above, if the “vmp_sus” code is not received, the “vmp_wait” code is inevitably received, so the scheduling control unit 413 changes the program state of the program being executed to waiting ( In step S166), the time option information search process described above is performed (step S162).
The scheduling control unit 413 recognizes the contents of the time option information by executing this time option information search process. Then, the scheduling control unit 413 determines whether or not the content of the time option information indicates “MICRO-SLEEP”. (Step S165) When the content of the time option information is “MICRO-SLEEP”, the processing control unit In step S166, the process execution unit 410 performs nop via step 411, and the process proceeds to step S102 described above.

When the content of the time option information is not “MICRO-SLEEP”, the scheduling control unit 413 further determines whether the content of the time option information indicates “TS_SWITCH”. A register switching process is performed (step S168), and the process proceeds to the above-described step S100.
Further, when the content of the time option information does not indicate “TS_SWITCH”, the content of the time option information inevitably becomes “LP_SWITCH”, and therefore the scheduling control unit 413 sets the target TS as the current TS ( In step S169), the time-driven scheduling described above is performed (step S170).

Here, the contents of the time-driven scheduling performed in step S170 will be described with the difference from the contents of the time-driven scheduling performed in step S105. There are the following two differences in the contents of the above two time-driven scheduling.
That is, in the time-driven scheduling performed in step S170, the target TS is the current TS, not the next TS, and the result of the scheduling process is that the NOP is independent of the idle option information when there is no valid candidate program. The point is to move to execution. More specifically, following the process of step S169 in FIG. 18B, the scheduling control unit 413 performs a target time slot search process (step S120).

  That is, the scheduling control unit 413 refers to the time slot information stored at the current address in the time allocation information storage register 402, identifies the current TS by the TS-ID that identifies the time slot, and further, this time slot. Get the value of basic cycle assigned to. Then, the scheduling control unit 413 performs a target TS allocation program search process (step S121), and executes a priority & mode information search process (step S122).

  Subsequently, the scheduling control unit 413 performs an idle option information search process (step S123) and performs a scheduling process (step S124). More specifically, the scheduling control unit 413 identifies four programs associated with the current TS obtained by the target time slot search process, and associates them with each of these programs by the target TS allocation program search process. Understand the priorities that have been assigned.

  Then, the scheduling control unit 413 selects candidate programs from the above four programs based on the priority and mode obtained by the priority & mode information search process. Further, the scheduling control unit 413 refers to the program state information corresponding to each candidate program in the LP state storage register 424, detects whether each candidate program can be executed, and determines whether or not each candidate program can be executed. Is elected.

At this time, when there are a plurality of valid candidate programs, the valid candidate program associated with the smallest priority value is set as the allocation target to the current TS. If no valid candidate program exists, it is stored that there is no valid candidate program regardless of the acquired idle option.
The above processing is the time-driven scheduling in step S170 in which the target TS is the current TS. After executing such time-driven scheduling, the scheduling control unit 413 determines whether there is a valid candidate program (step S171).

If there is no valid candidate program, the scheduling control unit 413 causes the process execution unit 410 to execute nop via the process control unit 411 (step S166), and during the nop execution, the clock mask unit 427 causes the process execution unit 410 to execute. Is instructed to cut off the clock supply to the terminal, and the process proceeds to step S102 described above.
As a result of this instruction, the supply of the clock to the process execution unit 410 is cut off. On the other hand, when there is a valid candidate program, a return process is performed (step S172), an emergency register switching process is performed (step S168), and the process proceeds to the above-described step S100.
(4. Program Execution Status when Processor is Driven) The program execution status when the virtual multiprocessor 400 is driven will be described below.
(4-1. Basic program execution state)
The virtual multiprocessor 400 executes a program based on a plurality of time slots and a program assigned to each time slot, as described above.

  FIG. 22 is a diagram for explaining this time slot. Hereinafter, for convenience, each time slot is denoted as TSn (n is an integer from 0 to 15), and the value of n is unique to each time slot. Sixteen time slots are prepared for setting, and four of these time slots (TS0 to TS3) are time-driven time slots used for normal scheduling.

  That is, one program assigned to each time slot from TS0 to TS3 is sequentially executed, and when the execution of the program assigned to the time slot of TS3 is completed, the program is assigned to the time slot of TS0. It will be executed from the program. The time slots from TS0 to TS2 are program execution time slots that are premised on real-time processing for video and audio.

  TS3 (TS_ID = 3) is a time slot for program execution that does not assume real-time processing. Other time slots (TS4 to TS15) are event-driven time slots that wake up when an event occurs. As shown in FIG. 22A, each time slot is associated with a basic cycle value, and a time corresponding to the basic cycle value is a program execution time frame.

  As shown in FIG. 22 (b), the switching timing cannot be made exactly the same as the basic cycle of the time slot, and the switching is usually over several cycles. In the virtual multiprocessor 400, by executing the basic cycle adjustment process described above, in the time slots from TS0 to TS3, the time exceeding the execution time frame is subtracted from the execution time frame of the time slot of TS3, and the execution time Make sure you don't fail.

Further, in the virtual multiprocessor 400, when the program execution time assigned to the program to be executed is abandoned, it is determined that the contents of the measures for efficient program execution or power saving are determined. There are two types of information: option information and idle option information.
(4-2. Program execution state based on time option information when abandoned) As described above, the time option information indicates that this program cannot be executed during program execution, and the execution time of this program is abandoned. This is information about a time slot that determines the contents of program execution thereafter.

FIG. 23 is a diagram for explaining a program execution state based on time option information when the program execution time is abandoned, that is, a program execution state by time option information search processing. Hereinafter, for convenience, each program is referred to as LPm (m is an integer from 0 to 31), and the value of m is specific to each program.
As shown in FIG. 23A, when there are valid candidate programs in the time-driven time slots TS0, TS1, TS2, and TS3, the programs are sequentially executed within the execution time frame of each time slot. . Here, LP0 is assigned to TS0, LP1 is assigned to TS1, LP2 is assigned to TS2, and LP3 is assigned to TS3.

  As shown in FIG. 23B, during execution of LP1 in the execution time frame of TS1, the program execution time is abandoned by using the “vmp_wait” code output by the process execution unit 410 as a trigger, and this TS1 When the time option information indicates “LP_SWITCH”, the program is executed as follows by executing the processing in each functional unit described above.

  That is, LP4, which is an effective candidate program that is associated with the same TS1 and can be executed, is the highest priority candidate program, instead of LP1, until the execution time frame of TS1 is used up. Executed. At this time, the register value of the context corresponding to LP2 stored in the standby register group is once discarded, and the register value of the context corresponding to LP4 is stored.

  It takes time t2 to perform such destruction and return of LP4 and start execution of LP4. Normally, t2 is a time corresponding to approximately 30 cycles of pulse output by the cycle counter 416. By the way, when there is no valid candidate program in TS1, it is no longer possible to execute the program in this time slot. In such a case, the scheduling control unit 413 indicates that the time option information of TS1 described later is “MICRO-SLEEP”. It is assumed that the program execution is controlled to be the same as the program execution in the case where

Since there is no valid candidate program, a time slot such as TS1 that is out of the execution target range is called a sleeping time slot. When the above program execution time is abandoned and the time option information of this TS1 indicates “TS_SWITCH”, the program is executed as follows.
That is, as shown in FIG. 23C, register switching is performed quickly, and LP2 assigned to the next TS2 is moved up and executed. At this time, since LP2 is already stored in the standby register group, LP2 is executed promptly.

When the above program execution time is abandoned and the time option information of this TS1 indicates “MICRO-SLEEP”, the execution time frame of this TS1 is set as shown in FIG. Until it is used up, execution of a program having no meaning unrelated to the program that is originally executed, that is, nop execution is performed.
In addition, while the above-mentioned nop is being executed, the output of the clock to the process execution unit 410 is cut off, and as a result, the driving power is reduced.
(4-3. Program Execution State Based on Idle Option Information at Abandonment) As described above, the idle option information is the contents of program execution when there is no valid candidate program in a certain time slot. Information about the time slot to be determined.

FIGS. 24A, 24B, and 24C are diagrams for explaining the state of program execution based on idle option information when there is no valid candidate program in the time-driven time slot. FIG. 24A shows a program execution situation when there is at least one effective candidate program in each time-driven time slot.
Based on such a situation, the following describes the program execution when there is no valid candidate program in TS1. When there is no valid candidate program in TS1 and the idle option information of TS1 indicates “SWITCH”, the processing in each functional unit described above is executed, so that FIG. As shown in (b), LP2 assigned to TS2 is executed instead of TS1.

If there is no valid candidate program in TS1 and the idle option information of TS1 indicates “MICRO-SLEEP”, execution of TS1 is executed as shown in FIG. Nop is executed until the time frame is used up. In addition, while the above-mentioned nop is being executed, the output of the clock pulse to the process execution unit 410, that is, the CPU is cut off, and as a result, the driving power is reduced.
(4-4. Program Execution State when Wait State is Cleared) The program being executed becomes suspended-waiting (suspended-waiting) triggered by vmp_sus code output.

In addition, when the program is interrupted by another program with the emergency register switching, the program being executed becomes an executable suspended state (suspended-ready). A time slot assigned during execution of these programs is called an interrupt time slot, and the P_ID of the program is stored in association with TS_ID as described above.
The above-described suspended program that cannot be executed becomes a valid candidate program when the wait state is resolved.

A program interrupted by another program becomes a valid candidate program when it becomes an executable interrupted state. Hereinafter, a situation will be described in which a program that has been interrupted becomes a valid candidate program and is assigned to an interrupt time slot and execution is resumed from the middle of the time slot.
FIGS. 25A and 25B are diagrams for explaining the execution status of the program in such a situation. FIG. 25A shows that among the four time slots from TS0 to TS3, TS3 is already a suspended time slot, and is assigned to TS0 using the “vmp_sus” code output from the processing execution unit 410 as a trigger. The execution status of the program when the existing LP0 is no longer valid and TS0 newly becomes an interruption time slot is shown.

At this time, in TS0, the time t3 corresponding to the set execution time frame is not used up. When the “vmp_sus” code is received, the scheduling control unit 413 updates the program state of LP0 to suspended-waiting, and stores the remaining time t4 that is not used in the execution time frame as an actual count value in the context.
Then, as shown in FIG. 25A, only TS1 and TS2 are repeatedly executed. FIG. 25 (b) shows that a wait state is resolved in LP0 assigned to TS0 that has become a suspended time slot, that is, an unexecutable suspended state (suspended-waiting) is resolved, and the LP state storage register In 424, the execution status of the program in the case where the wake-up timing of LP0 indicates “n”, that is, the normal wake-up timing is shown.

In this case, as shown in FIG. 25B, the scheduling control unit 413 updates the program state of LP0 to suspended-ready when the non-executable suspended state is resolved, but immediately executes LP0. Instead of waiting for the count value 0 signal, control is performed so that LP0 is executed at a timing at which the program execution in the other TS is not interrupted.
As a result, the register value already stored in the standby register group is used at the time when the non-executable interruption state is resolved, and this storage is not wasted. At this time, the scheduling control unit 413 performs control so that LP0 is executed only for the time t4 corresponding to the actual count value stored in the context.

Note that LP0 is executed by event-driven scheduling. Subsequently, LP0 assigned to TS0 that is the execution target by normal time-driven scheduling is executed for t3.
Hereinafter, in the above-described case, when the wake-up timing of LP0 in the LP state storage register 424 indicates “e”, the program execution state when the wait is resolved, that is, when the inexecutable interrupted state is resolved explain.
(4-5. Program Execution State at Urgent Return Event Occurrence) FIG. 26 (a) shows the same as in FIG. 25 (a), among the four time slots TS0 to TS3, TS3 has already been suspended. The execution status of the program when LP0 assigned to TS0 becomes invalid and TS0 becomes a suspended time slot is triggered by the output of the “vmp_sus” code from the processing execution unit 410. Show.

At this time, in TS0, the set execution time frame t5 is not completely used up.
Similarly to FIG. 25A, when the “vmp_sus” code is received, the scheduling control unit 413 updates the program state of LP0 to suspended-waiting, and remains unused t6 within the execution time frame. Is stored in the context as the actual count value.

FIG. 26B shows a state in which a wait is canceled in LP0 assigned to TS0 that has become a sleeping time slot, that is, an unexecutable interrupted state is resolved, and LP0 wake-up timing in LP status storage register 424 "E", that is, the execution status of the program in the case where it indicates that the user wakes up urgently.
In this case, as shown in FIG. 26 (b), the scheduling control unit 413 updates the program state of LP0 to suspended-ready when the cancellation of the wait, that is, the cancellation of the inexecutable suspended state occurs, Attempt to execute LP0 immediately. Here, the above-mentioned immediate means program execution with overhead (t2) required for return processing, register switching, and the like.

  More specifically, the scheduling control unit 413 discards the register value already stored in the standby register group at the time when the cancellation of the wait, that is, the cancellation of the non-executable interruption state occurs, An emergency return process of storing the register value of the context corresponding to LP0 in the register group is executed, an emergency register switching process is executed, and LP0 is immediately executed for the time t6 described above, and the program state of LP1 is suspended- Update to ready, and the remaining time t7 not used in the execution time frame of TS1 is stored in the context of LP1 as an actual count value.

  In the register group that has become the standby register group by executing the register switching process described above, the register value of the context corresponding to LP1 that has been executed so far exists, but the scheduling control unit 413 uses the register value of this LP1. The data is saved, and the return process is executed along with the execution of LP0. After the execution of LP0 is completed, the register switching process is executed, and LP1 is immediately executed for the time t7 described above.

The LP1 is also executed by event-driven scheduling. Specifically, the execution is resumed by an event wake-up process (wake-up timing “n”).
(4-6. Program Execution State When Event Processing Request Occurs) When no event processing request occurs, TS0, TS1, TS2, and TS3 are sequentially executed as shown in FIG. The programs LP0, LP1, LP2, and LP3 assigned to the slots are sequentially executed.

  In FIG. 27B, on the assumption of the above-described state, an event processing request for executing LP4 of TS4 that is a time slot for an event is generated, and the wake-up timing of LP4 is “n” in LP state storage register 424. That is, the execution status of the program in the case of indicating to wake up normally is shown. In this case, as shown in FIG. 27B, the scheduling control unit 413 updates the program state of LP4 from waiting to ready when an event processing request occurs, but does not immediately execute LP4. The register group that is the current register group when the event processing request is generated becomes the standby register group, and when this register group is released, the register value of the context corresponding to LP4 is stored in this register group. When this register group becomes the current register group, LP4 is executed.

  Thereby, when an event processing request is generated, the register values already stored in the standby register group are used, and this storage is not wasted. FIG. 27C shows an event processing request for executing LP4 of TS4 which is a time slot for an event, and the wakeup timing of LP4 is “e” in the LP state storage register 424, that is, wake up urgently. The execution status of the program in the case where this is indicated.

  In this case, as shown in FIG. 27C, the scheduling control unit 413 updates the LP4 program state to ready when an event processing request occurs, and immediately executes the LP4 at t2 described above. Try to. More specifically, the scheduling control unit 413 discards the register value already stored in the standby register group at the time when the event processing request occurs, and registers the context register value corresponding to LP4 in this standby register group. , Execute the emergency register switching process, immediately execute LP4, update the program state of LP1 whose execution is suspended to suspended-ready, and the time remaining unused in the execution time frame of TS1, That is, the actual count value is stored in the context of LP1.

  The register group that has become the standby register group by executing the register switching process described above has a context register value corresponding to LP1 that has been executed so far, and the scheduling control unit 413 temporarily saves this register value. Then, this register value is restored to the standby register group again, and after the execution of LP4 is completed, the register switching process is performed immediately, and control is performed so that LP1 is executed for the remaining time immediately without being used.

The LP1 is also executed by event-driven scheduling. Specifically, the execution is resumed by an event wake-up process (wake-up timing “n”).
(4-7. Program Execution Situation When Common Interrupt Processing Request Occurs) FIGS. 28A and 28B are diagrams for explaining the program execution situation when a common interrupt processing request occurs.

  As shown in FIG. 28A, when no common interrupt processing request is generated, four time slots from TS0 to TS3 are sequentially executed time slots, and LP0 and LP1 assigned to these time slots, respectively. , LP2 and LP3 are sequentially executed. When a common interrupt processing request is generated during execution of LP2 in TS2, as shown in FIG. 28B, the scheduling control unit 413 jumps to this common interrupt processing dedicated subroutine during execution of the LP2 program and performs common interrupt processing. After this common interrupt processing is completed, the program returns to LP2 to execute the program.

At this time, the scheduling control unit 413 performs control so that the program execution time in the above subroutine is not included in the execution time of the interrupted LP2. More specifically, the scheduling control unit 413 stops the countdown in the cycle counter 416 while the common interrupt process is being executed in the above-described subroutine.
As a result, a time obtained by adding the time t10 during which the program is executed in the above-described subroutine to the execution time frame t9 of TS2 is the execution time of LP2. In this way, the execution time of the common interrupt process is not included in the original execution time of the interrupted LP2, even though all programs need to execute the common interrupt process. This is to correct the unfairness that the execution time is reduced by the program assigned to this time slot by consuming the execution time frame of one interrupted time slot.
(4-8. Program execution status when a specific interrupt processing request occurs)
FIGS. 29A, 29B, and 29C are diagrams for explaining the program execution status when a specific interrupt processing request is generated.

  As shown in FIG. 29A, when a specific interrupt processing request is not generated, four time slots from TS0 to TS3 are sequentially executed time slots, and LP0 and LP1 assigned to these time slots, respectively. , LP2 and LP3 are sequentially executed. As shown in FIG. 29 (b), when a unique interrupt processing request corresponding to LP3 is generated during execution of LP2 in TS2, the scheduling control unit 413 is dedicated to this unique interrupt processing the next time LP3 is executed. The subroutine jumps to execute the unique interrupt process, and after the unique interrupt process is completed, the program returns to LP3 to execute the program.

At this time, the scheduling control unit 413 includes the program execution time in the subroutine dedicated to the specific interrupt processing in the execution time of the interrupted LP3. That is, the scheduling control unit 413 does not stop the countdown in the cycle counter 416 while the unique interrupt process is being executed in the above-described subroutine.
Thus, the reason for including the execution time of the specific interrupt process corresponding to LP3 in the original execution time of the interrupted LP3 is that only LP3 needs to execute this specific interrupt process, This is because even if the execution time of the intrinsic interrupt processing is consumed from the execution time of the necessary program, unfairness between the programs regarding the execution time as in the case of the common interrupt processing does not occur.

Also, as shown in FIG. 29 (c), when a specific interrupt processing request corresponding to LP3 occurs during execution of LP3 in TS3, the scheduling control unit 413 immediately jumps to this specific interrupt processing dedicated subroutine to execute a specific interrupt. After the process is executed and this unique interrupt process is completed, the program returns to LP3 to execute the program.
Also at this time, as described above, the scheduling control unit 413 includes the program execution time in the subroutine for executing the specific interrupt process in the execution time of the interrupted LP3. As described above, according to the second embodiment, even when a plurality of programs are executed in a pseudo-parallel manner in one virtual multiprocessor 400, context saving, determination, and restoration are performed in parallel with program execution. Therefore, the time required for saving, determining, and returning the context does not intervene in the execution time of the program, so that the task can be executed efficiently.

  In addition, since multiple programs are prepared for each time slot, even if one program cannot be executed, another program can be executed instead of that program, and the execution time of the program becomes effective. Can be used. Further, when the program cannot be executed, the power consumption can be reduced by stopping the driving while the process execution unit 410 is executing NOP during the execution time of the program.

  In the present embodiment, the scheduling control unit 413 includes the program execution time in the subroutine for executing the specific interrupt process in the execution time of the interrupted program. However, the present invention is not limited to this. Also good. Here, as shown in FIG. 30 (a), when the unique interrupt processing has not occurred, four time slots from TS0 to TS3 are sequentially executed time slots, and are assigned to each of these time slots. Assume that LP0, LP1, LP2, and LP3 are sequentially executed.

  When the programs from LP0 to LP3 assigned to each time slot are executed, the program execution of the first round is completed. As shown in FIG. 30B, when the unique interrupt process corresponding to LP2 occurs during the execution of LP2 in the k-th cycle, the scheduling control unit 413 is only in this case in the unique interrupt process execution subroutine. The program execution time t13 is not included in the execution time of the interrupted program (LP).

  That is, the scheduling control unit 413 stops the countdown in the cycle counter 416 during the time t13 during which the program is executed in the inherent interrupt process execution subroutine. Then, as shown in FIG. 30C, when the LP2 assigned to TS2 is executed in the order of k + 1, the scheduling control unit 413 performs the above described program execution time from the execution time frame t12 of TS2. LP2 is executed for the time obtained by subtracting t13.

More specifically, the scheduling control unit 413 outputs a value corresponding to the time obtained by subtracting t13 from the above-described t12 to the cycle counter 416 instead of the basic cycle value output to the cycle counter 416. In the k + 2th round, normal execution as shown in FIG.
Further, in this embodiment, as shown in FIG. 31A, while the clock mask unit 427 receives the mask signal from the scheduling control unit 413, the signal path of the clock pulse to the processing execution unit 410 is blocked. As a result, the power consumption of the processing execution unit 410 is reduced, but the present invention is not limited to this, and the following may be adopted.

That is, as shown in FIG. 31B, the power control unit 430 arranged on the power supply path to the processing execution unit 410 receives a power control signal instead of the above mask signal from the scheduling control unit 413. During this time, the power consumption in the processing execution unit 410 may be reduced to 0 by cutting off the power supply path.
Further, as shown in FIG. 31C, a frequency dividing unit 431 including a frequency divider arranged on the signal path of the clock pulse between the oscillator 600 and the processing execution unit 410 includes a scheduling control unit 413. While receiving a frequency-divided signal instead of the mask signal described above, for example, by dividing by 4, the drive frequency of the processing execution unit 410 may be lowered to reduce power consumption.

  Further, as shown in FIG. 31D, a frequency dividing unit 431 including a frequency divider arranged on a signal path of a clock pulse between the oscillator 600 and the virtual multiprocessor 400 is a scheduling control unit 413. While receiving a frequency-divided signal in place of the mask signal described above, the frequency of this clock pulse is divided by 4, for example, to reduce the drive frequency of the processing execution unit 410 and reduce power consumption. Good.

At this time, the cycle counter 416 includes a multiplication unit 433 including a multiplier in addition to the normal processing unit 432 that performs the conventional function, and the frequency of the clock pulse is multiplied by, for example, four times, and the above-described distribution. The countdown may be performed by canceling the influence of the lap. Of course, the above-mentioned frequency division and multiplication values are not limited to four.
Further, in the second embodiment, when the request detection unit 419 tries to output the event P_ID, the number of output times of the event P_ID stored in a period retroactive to the past by a predetermined time from the present is stored in advance. When the predetermined threshold value is exceeded, the above output is delayed so that the number of output times is equal to or less than the threshold value, but the output number exceeds the threshold value. The output of the event P_ID may be canceled, that is, the event processing request may be ignored.

  In the second embodiment, the scheduling control unit 413 instructs the DMA management unit 418 to write the data necessary for executing the program corresponding to the context stored in the standby register group to the cache memory. Alternatively, the execution of garbage collection may be instructed to the function unit that executes garbage collection.

  In the second embodiment, when a state of two or more programs newly becomes ready or suspended-ready at a certain point in time, that is, within an event-driven scheduling candidate, that is, within a scheduling target range. However, when there are multiple programs, which program is executed first is not described, but based on the priority assigned to the program, the program with the highest priority is executed first. It is good.

For example, when the priority is higher as the value of the program ID is smaller, the program having the smaller program ID is selected as the execution target first.
In the second embodiment, the description has been made on the assumption that the number of programs (LP) exceeds the number of register groups. However, the present invention is not limited to this, and the number of programs is less than or equal to the number of register groups. There may be.

  In this case, the context memory 500 may not be provided, and the saving and restoring steps are not necessary. When the number of programs is two, LP0 is associated with the first register group, and LP1 is associated with the second register group. For example, when executing LP0, the scheduling control unit 413 selects the first register group as the current register group without performing the operation of restoring the register value group from the context memory.

Even if the number of programs and register groups is three, what is selected as the current register group is the execution target register group, and the others are standby register groups. Here, LP2 is assumed to be associated with the third register group. When executing LP2, the third register group is selected as the current register group.
Even after the selection destination is switched, the operation of saving the register value group in the context memory is unnecessary.

  In addition, the context memory 500 is configured by SRAM. However, the context memory 500 may be DRAM, and is not limited to these memories, and may be a register accessed at high speed or an external storage device accessed at low speed. Good.

2 is a functional block diagram of a virtual multiprocessor 100 in the first embodiment. FIG. It is a figure which shows the data structure of the table stored in the context memory, and context. It is a figure explaining each flag of a completion notification flag group and a setting flag group. It is a figure which shows the relationship between a task and a plate. It is a flowchart which shows the process implemented in a virtual multiprocessor. It is a flowchart which shows a flag determination process. It is a figure explaining the process implemented in a virtual multiprocessor in time series. It is a figure which shows the data structure of the table which shows an execution order using a pointer. It is a figure which shows the plate execution condition in time series when implementing flag determination processing preferentially with respect to the context of the plate which is sleeping. It is a figure which shows the example which implements a flag determination process preferentially with respect to the context of the plate which slept late. It is a figure which shows the data structure of the execution order table by which the initial value of the count value was added to the context address. It is a functional block diagram of a cycle counter. It is a figure which shows the example which implements a 4-stage pipeline process. For the period from immediately after going to sleep until one plate is executed, the execution order of the sleeped plates is the first order, and the flow of plate execution in the case of preferentially executing the sleeped plates is shown in FIG. is there. It is a functional block diagram of the virtual multiprocessor in 2nd Embodiment. It is a figure which shows the content of the information stored in the time allocation information storage register and LP status storage register. It is a flowchart which shows the process implemented in the virtual multiprocessor in 2nd Embodiment. It is a flowchart which shows the content of the time driven scheduling implemented by the scheduling control part. It is a flowchart which shows the content of the event driven scheduling implemented by a scheduling control part. It is a flowchart which shows the content of the interruption process. It is a flowchart which shows the content of abandonment scheduling. (A) is a figure which shows the value of the basic cycle of each time slot. (B) is a figure explaining reexamination of the value of a basic cycle by basic cycle adjustment processing. (A) is a figure which shows the normal program execution state by which program execution time is not abandoned. (B) is a diagram showing a program execution state when the program execution time is abandoned and the time option information indicates “LP_SWITCH”. (C) is a diagram showing a program execution state when the program execution time is abandoned and the time option information of this LP1 indicates “TS_SWITCH”. (D) is a diagram showing a program execution state when the program execution time is abandoned and the time option information of this LP1 indicates “MICRO-SLEEP”. (A) is a figure explaining the condition of the program execution based on idle option information in case there is no effective candidate program in a time driven type time slot. (B) is a diagram showing a program execution state when there is no valid candidate program and the idle option information of this LP1 indicates “SWITCH”. (C) is a diagram showing a program execution state when there is no valid candidate program in TS1 and the idle option information of this LP1 indicates “MICRO-SLEEP”. (A) shows the execution status of the program when there is a sleeping time slot. (B) shows the execution status of the program when the wait state of the program assigned to the sleeping time slot is resolved and the wake-up timing of this program indicates “n”. (A) shows the execution status of the program when there is a sleeping time slot. (B) shows the execution state of the program when the wait state of the program assigned to the sleeping time slot is resolved and the wake-up timing of this program indicates “e”. (A) is a figure which shows a program execution state in case an event process request does not generate | occur | produce. (B) shows the execution status of the program when an event processing request is generated and the wake-up timing of the program executing the event processing indicates “n”. (C) shows the execution status of the program when an event processing request is generated and the wake-up timing of the program executing the event processing indicates “e”. (A) is a diagram showing a program execution state when a common interrupt processing request is not generated. (B) is a diagram showing a program execution state when a common interrupt processing request is generated. (A) is a figure which shows the program execution state in case the intrinsic | native interrupt process request has not generate | occur | produced. (B) is a diagram illustrating an execution state of the specific interrupt process when a program other than the program that executes the specific interrupt process is executed when a specific interrupt process request is generated. (C) is a diagram showing an execution state of the specific interrupt process when a program for executing the specific interrupt process is executed when a specific interrupt process request is generated. (A) is a figure which shows the program execution state in case the intrinsic | native interrupt process request has not generate | occur | produced. (B) is a diagram illustrating an execution state of the k-th unique interrupt process by a method other than the first and second embodiments when the unique interrupt process occurs in the k-th round. (C) is a diagram showing an execution state of the k + 1-th unique interrupt process by a method other than the first and second embodiments when the unique interrupt process occurs in the k-th round. (A) is a figure which shows the structure of the function part which reduces the power consumption in 2nd Embodiment. (B) is a figure which shows an example of a structure of the function part which reduces the power consumption by methods other than 2nd Embodiment. (C) is a figure which shows an example of a structure of the function part which reduces the power consumption by methods other than 2nd Embodiment. (D) is a figure which shows an example of a structure of the function part which reduces the power consumption by methods other than 2nd Embodiment. It is a functional block diagram of a conventional processor. It is a figure which shows the flow of the task execution in the conventional processor, and the condition of the input / output of the context between a register group and a context memory. 2 is a diagram illustrating a connection relationship between a virtual multiprocessor 100 and an external processor 30 in the first embodiment. FIG.

Explanation of symbols

10 main memory 30 external processor 100 virtual multiprocessor 110 processing execution unit 111 processing control unit 112 register switching unit 113 switching switching control unit 114 register group 115 register group 116 cycle counter 117 external I / F
118 DMA manager 119 Completion notification register 120 Control register 121 Setting flag register 200 Context memory 201 Context storage area 202 Execution order table storage area 301 Input / output unit 302 First memory 303 Second memory 304 Countdown unit 400 Virtual multiprocessor 402 Time allocation Information storage register 410 Processing execution unit 411 Processing control unit 412 Register switching unit 413 Scheduling control unit 414 Register group 415 Register group 416 Cycle counter 417 External I / F
418 DMA management unit 419 Request detection unit 420 Control register 421 Setting flag register 424 LP state storage register 425 Processor state storage unit 427 Clock mask unit 430 Power control unit 431 Multiplication unit 432 Normal processing unit 433 Dividing unit 500 Context memory 501 Context memory 501 Region 600 Oscillator 601 PLL
700 Bus 701 External processor processing request signal line 702 External processor processing completion signal line

Claims (21)

A processor that sequentially executes a program corresponding to each of these register value groups using a plurality of register value groups stored in a memory,
A selection destination switching means for selecting a plurality of register groups and any one of the plurality of register groups as an execution target register group as a basis for program execution, and switching the selection destination at predetermined time intervals;
Returning means for returning the register value group to one register group that is not selected among the plurality of register groups each time the switching is performed;
Each time the switching is performed, prior to the return, each register value in the register group targeted for the return is saved by overwriting the register value group in the memory corresponding to the register value. Evacuation means to perform,
Program execution means for specifying a program by a register value group including a program counter value in the execution target register group each time the switching is performed, and executing the specified program;
Order information obtaining means for obtaining order information for specifying a time slot serving as an execution time frame of the program, which is determined in order to allocate time for occupying the program execution means,
The predetermined time is specified by the count value based on table information in which a plurality of count values are stored in association with each program through the time slot according to a program having a desired processing time. Time to be
Furthermore, there are a plurality of candidate register value groups associated with the priority order of the return candidates,
The return means refers to the order information, and identifies the current time slot to be executed and the next time slot to be executed in order to periodically switch the time slots in a predetermined order. Then, referring to the time allocation information that associates the count value and a plurality of candidate register value groups with a time slot,
The execution time frame of the program assigned to the specified time slot is obtained, and the return target is selected from among a plurality of candidate register value groups assigned to the specified time slot based on the priority order. And determine the register value group to implement the return,
The program execution means starts the execution when the switching is performed ,
Further, the processor is characterized in that the predetermined time is determined for each time slot to be a predetermined ratio with respect to the total time for the program execution means to execute the specified program . The order information is identification information unique to each register value group is a table arranged in a predetermined order, the order is according to claim 1, wherein the shown by the order of the sequence of the identification information Processor. The sequence information includes one or more pieces of the same identification information in the array, and the number of the same identification information in the array is unique to each program corresponding to the register value group specified by each identification information. 3. A processor according to claim 2, characterized in that: The plurality of programs includes a management program for determining whether the table needs to be changed and changing the table, and identification information for specifying the location of a register value group corresponding to the management program in the array 4. The processor of claim 3 , wherein there is only one. The predetermined time is a time unique to each of the plurality of programs, and each identification information is added with time information indicating the unique time of the program corresponding to the register value group specified by the identification information. and has the management program, according to claim 4 in which the sum of the specific time indicated by the time information added to each identification information which comprises carrying out the change to be within the predetermined ratio The processor described. When the program execution unit determines that the table needs to be changed during the execution of the management program, the program execution unit generates a dummy table in which the change has been made to the table, and the dummy table, the table, 6. The processor according to claim 5, wherein the change is performed by exchanging. The plurality of programs includes a video processing program for executing video processing, and the number of pieces of identification information for specifying the location of the register value group corresponding to the video processing program in the array is higher than that of other programs. 4. The processor according to claim 3, wherein the number of processors is large. The identification information is an address value indicating an area in which a register value group is stored, and the return means specifies the location of the register value group to be returned by the address value and performs the return. The processor according to claim 3 . The order information is a table in which each identification information unique to each register value group is attached with a pointer pointing to other identification information, and the order is indicated by tracing the pointer. 3. A processor according to claim 2, characterized in that:   2. The processor according to claim 1, wherein the plurality of register groups are two, and the selection destination switching unit alternately performs the switching for the two register groups. The program execution unit executes N stages of pipeline processing, and the save unit executes the save after (N−1) clocks from the time when the selection destination is switched. The processor of claim 10 .   The selection destination switching means determines the selection destination in a predetermined order from the plurality of register groups, performs the switching, and the return means returns register value groups from the plurality of register groups in a predetermined order. The processor according to claim 1, wherein the processor determines a destination and performs the return.   The return means copies the register value group stored in the memory and performs the return, and the program execution means changes a register value in the execution target register group as the program is executed. 2. The processor according to claim 1, wherein the save unit executes the save only when the change is made by the program execution unit. Each register of the plurality of register groups is attached with change information indicating whether or not the register value returned to the respective register has been changed, and the saving means can change the register based on the change information. 14. The processor according to claim 13 , wherein the saving is performed by writing only the registered register values to the locations in the memory where the values before the register values are changed are stored. 15. The processor according to claim 14 , wherein the change information is a 1-bit flag. In the table information, specific information for specifying any of the plurality of register value groups is associated with each count value,
The return target is specified each time the selection is made by the count value in the order based on the order of the register value group to be returned by the specific information,
The predetermined time from when the register group including the register value group restored by the specific information is selected as the execution target register group until the other register group is selected as the execution target register group is used for the restoration. 3. The processor according to claim 2, wherein the time is indicated by a count value associated with the specific information.   The processor according to claim 1, wherein the predetermined time is unique to each of the plurality of time slots. Furthermore, a plurality of caches for storing execution data necessary for program execution,
With the return by the return means, referring to the register value group that has been returned, execution data specifying means for specifying execution data of a program corresponding to the register value group,
2. The processor according to claim 1, further comprising cache writing means for writing the specified execution data into any one of the plurality of caches not used for program execution. A program execution method for executing a program in a processor including a plurality of register groups and using a plurality of register value groups stored in a memory and sequentially executing a program corresponding to each of these register value groups,
A selection destination switching step of selecting any one of the plurality of register groups as an execution target register group based on program execution, and switching the selection destination at predetermined time intervals;
A return step of returning the register value group to one register group that is not selected among the plurality of register groups each time the switching is performed;
Each time the switching is performed, prior to the return, each register value in the register group targeted for the return is saved by overwriting the register value group in the memory corresponding to the register value. Evacuation step to
A program execution step of specifying a program by a register value group including a program counter value in the execution target register group each time the switching is performed, and executing the specified program;
An order information obtaining step for obtaining order information for specifying a time slot serving as an execution time frame of the program, which is defined in order to allocate time for occupying the program execution step;
The predetermined time is specified by the count value based on table information in which a plurality of count values are stored in association with each program through the time slot according to a program having a desired processing time. Time to be
Furthermore, there are a plurality of candidate register value groups associated with the priority order of the return candidates,
The returning step refers to the order information, and identifies the current time slot to be executed and the next time slot to be executed in order to periodically switch the time slots in a predetermined order. Thereafter, referring to time allocation information in which the count value and a plurality of candidate register value groups are associated with a time slot, an execution time frame of a program assigned to the specified time slot is acquired, and the specified time Among the plurality of candidate register value groups assigned to the slot, based on the priority order, determine the register value group to be restored, and perform the restoration,
The program execution step starts the execution when the switching is performed ,
The program execution method characterized in that the predetermined time is determined for each time slot to be a predetermined ratio with respect to the total time for executing the program specified in the program execution step . A processor that sequentially executes a program corresponding to each register value group using a plurality of register value groups,
A plurality of register groups storing each of the register value groups;
Selection destination switching means for selecting any one of the plurality of register groups as an execution target register group based on program execution and switching the selection destination every predetermined time;
Program execution means for specifying a program by a register value group including a program counter value in the execution target register group each time the switching is performed, and executing the specified program;
Order information obtaining means for obtaining order information for specifying a time slot serving as an execution time frame of the program, which is determined in order to allocate time for occupying the program execution means,
The predetermined time is specified by the count value based on table information in which a plurality of count values are stored in association with each program through the time slot according to a program having a desired processing time. Time to be
Furthermore, there are a plurality of candidate register value groups associated with the priority order of the return candidates,
The return means refers to the order information, and identifies the current time slot to be executed and the next time slot to be executed in order to periodically switch the time slots in a predetermined order. Thereafter, referring to time allocation information in which the count value and a plurality of candidate register value groups are associated with a time slot, an execution time frame of a program assigned to the specified time slot is acquired, and the specified time Among the plurality of candidate register value groups assigned to the slot, based on the priority order, determine the register value group to be restored, and perform the restoration,
The program execution means starts the execution when the switching is performed ,
The processor according to claim 1, wherein the predetermined time is determined for each time slot to be a predetermined ratio with respect to a total time for executing the program specified by the program execution means . A program execution method for executing a program in a processor including a plurality of register groups and using a plurality of register value groups to sequentially execute a program corresponding to each of these register value groups,
A selection destination switching step of selecting any one of the plurality of register groups as an execution target register group as a basis for program execution, and switching the selection destination at predetermined time intervals;
A program execution step of specifying a program by a register value group including a program counter value in the execution target register group each time the switching is performed, and executing the specified program;
An order information obtaining step for obtaining order information for specifying a time slot serving as an execution time frame of the program, which is defined in order to allocate time for occupying the program execution step;
The predetermined time is specified by the count value based on table information in which a plurality of count values are stored in association with each program through the time slot according to a program having a desired processing time. Time to be
Furthermore, there are a plurality of candidate register value groups associated with the priority order of the return candidates,
The returning step refers to the order information, and identifies the current time slot to be executed and the next time slot to be executed in order to periodically switch the time slots in a predetermined order. Thereafter, referring to time allocation information in which the count value and a plurality of candidate register value groups are associated with a time slot, an execution time frame of a program assigned to the specified time slot is acquired, and the specified time Among the plurality of candidate register value groups assigned to the slot, based on the priority order, determine the register value group to be restored, and perform the restoration,
The program execution step starts the execution when the switching is performed ,
The program execution method characterized in that the predetermined time is determined for each time slot to be a predetermined ratio with respect to the total time for executing the program specified in the program execution step .

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